2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 static int ath_max_4ms_framelen[4][32] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
107 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
118 list_add_tail(&tid->list, &ac->tid_q);
124 list_add_tail(&ac->list, &txq->axq_acq);
127 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129 struct ath_txq *txq = tid->ac->txq;
131 WARN_ON(!tid->paused);
133 spin_lock_bh(&txq->axq_lock);
136 if (skb_queue_empty(&tid->buf_q))
139 ath_tx_queue_tid(txq, tid);
140 ath_txq_schedule(sc, txq);
142 spin_unlock_bh(&txq->axq_lock);
145 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
149 sizeof(tx_info->rate_driver_data));
150 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
153 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
155 struct ath_txq *txq = tid->ac->txq;
158 struct list_head bf_head;
159 struct ath_tx_status ts;
160 struct ath_frame_info *fi;
162 INIT_LIST_HEAD(&bf_head);
164 memset(&ts, 0, sizeof(ts));
165 spin_lock_bh(&txq->axq_lock);
167 while ((skb = __skb_dequeue(&tid->buf_q))) {
168 fi = get_frame_info(skb);
171 spin_unlock_bh(&txq->axq_lock);
172 if (bf && fi->retries) {
173 list_add_tail(&bf->list, &bf_head);
174 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
175 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
177 ath_tx_send_normal(sc, txq, NULL, skb);
179 spin_lock_bh(&txq->axq_lock);
182 spin_unlock_bh(&txq->axq_lock);
185 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
190 index = ATH_BA_INDEX(tid->seq_start, seqno);
191 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
193 __clear_bit(cindex, tid->tx_buf);
195 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
196 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
197 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
201 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
206 index = ATH_BA_INDEX(tid->seq_start, seqno);
207 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
208 __set_bit(cindex, tid->tx_buf);
210 if (index >= ((tid->baw_tail - tid->baw_head) &
211 (ATH_TID_MAX_BUFS - 1))) {
212 tid->baw_tail = cindex;
213 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
223 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
224 struct ath_atx_tid *tid)
229 struct list_head bf_head;
230 struct ath_tx_status ts;
231 struct ath_frame_info *fi;
233 memset(&ts, 0, sizeof(ts));
234 INIT_LIST_HEAD(&bf_head);
236 while ((skb = __skb_dequeue(&tid->buf_q))) {
237 fi = get_frame_info(skb);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
243 spin_lock(&txq->axq_lock);
247 list_add_tail(&bf->list, &bf_head);
250 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
252 spin_unlock(&txq->axq_lock);
253 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
254 spin_lock(&txq->axq_lock);
257 tid->seq_next = tid->seq_start;
258 tid->baw_tail = tid->baw_head;
261 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
264 struct ath_frame_info *fi = get_frame_info(skb);
265 struct ath_buf *bf = fi->bf;
266 struct ieee80211_hdr *hdr;
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
274 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
275 sizeof(*hdr), DMA_TO_DEVICE);
278 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
280 struct ath_buf *bf = NULL;
282 spin_lock_bh(&sc->tx.txbuflock);
284 if (unlikely(list_empty(&sc->tx.txbuf))) {
285 spin_unlock_bh(&sc->tx.txbuflock);
289 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
292 spin_unlock_bh(&sc->tx.txbuflock);
297 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
299 spin_lock_bh(&sc->tx.txbuflock);
300 list_add_tail(&bf->list, &sc->tx.txbuf);
301 spin_unlock_bh(&sc->tx.txbuflock);
304 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
308 tbf = ath_tx_get_buffer(sc);
312 ATH_TXBUF_RESET(tbf);
314 tbf->bf_mpdu = bf->bf_mpdu;
315 tbf->bf_buf_addr = bf->bf_buf_addr;
316 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
317 tbf->bf_state = bf->bf_state;
322 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
323 struct ath_tx_status *ts, int txok,
324 int *nframes, int *nbad)
326 struct ath_frame_info *fi;
328 u32 ba[WME_BA_BMP_SIZE >> 5];
335 isaggr = bf_isaggr(bf);
337 seq_st = ts->ts_seqnum;
338 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
342 fi = get_frame_info(bf->bf_mpdu);
343 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
346 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
354 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
355 struct ath_buf *bf, struct list_head *bf_q,
356 struct ath_tx_status *ts, int txok, bool retry)
358 struct ath_node *an = NULL;
360 struct ieee80211_sta *sta;
361 struct ieee80211_hw *hw = sc->hw;
362 struct ieee80211_hdr *hdr;
363 struct ieee80211_tx_info *tx_info;
364 struct ath_atx_tid *tid = NULL;
365 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
366 struct list_head bf_head;
367 struct sk_buff_head bf_pending;
368 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
369 u32 ba[WME_BA_BMP_SIZE >> 5];
370 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
371 bool rc_update = true;
372 struct ieee80211_tx_rate rates[4];
373 struct ath_frame_info *fi;
378 hdr = (struct ieee80211_hdr *)skb->data;
380 tx_info = IEEE80211_SKB_CB(skb);
382 memcpy(rates, tx_info->control.rates, sizeof(rates));
386 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
390 INIT_LIST_HEAD(&bf_head);
392 bf_next = bf->bf_next;
394 if (!bf->bf_stale || bf_next != NULL)
395 list_move_tail(&bf->list, &bf_head);
397 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
405 an = (struct ath_node *)sta->drv_priv;
406 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
407 tid = ATH_AN_2_TID(an, tidno);
410 * The hardware occasionally sends a tx status for the wrong TID.
411 * In this case, the BA status cannot be considered valid and all
412 * subframes need to be retransmitted
414 if (tidno != ts->tid)
417 isaggr = bf_isaggr(bf);
418 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
420 if (isaggr && txok) {
421 if (ts->ts_flags & ATH9K_TX_BA) {
422 seq_st = ts->ts_seqnum;
423 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
426 * AR5416 can become deaf/mute when BA
427 * issue happens. Chip needs to be reset.
428 * But AP code may have sychronization issues
429 * when perform internal reset in this routine.
430 * Only enable reset in STA mode for now.
432 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
437 __skb_queue_head_init(&bf_pending);
439 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
441 u16 seqno = bf->bf_state.seqno;
443 txfail = txpending = sendbar = 0;
444 bf_next = bf->bf_next;
447 tx_info = IEEE80211_SKB_CB(skb);
448 fi = get_frame_info(skb);
450 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
451 /* transmit completion, subframe is
452 * acked by block ack */
454 } else if (!isaggr && txok) {
455 /* transmit completion */
458 if ((tid->state & AGGR_CLEANUP) || !retry) {
460 * cleanup in progress, just fail
461 * the un-acked sub-frames
464 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
465 if (txok || !an->sleeping)
466 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
477 * Make sure the last desc is reclaimed if it
478 * not a holding desc.
480 INIT_LIST_HEAD(&bf_head);
481 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
482 bf_next != NULL || !bf_last->bf_stale)
483 list_move_tail(&bf->list, &bf_head);
485 if (!txpending || (tid->state & AGGR_CLEANUP)) {
487 * complete the acked-ones/xretried ones; update
490 spin_lock_bh(&txq->axq_lock);
491 ath_tx_update_baw(sc, tid, seqno);
492 spin_unlock_bh(&txq->axq_lock);
494 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
495 memcpy(tx_info->control.rates, rates, sizeof(rates));
496 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
500 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
503 /* retry the un-acked ones */
504 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
505 if (bf->bf_next == NULL && bf_last->bf_stale) {
508 tbf = ath_clone_txbuf(sc, bf_last);
510 * Update tx baw and complete the
511 * frame with failed status if we
515 spin_lock_bh(&txq->axq_lock);
516 ath_tx_update_baw(sc, tid, seqno);
517 spin_unlock_bh(&txq->axq_lock);
519 ath_tx_complete_buf(sc, bf, txq,
530 * Put this buffer to the temporary pending
531 * queue to retain ordering
533 __skb_queue_tail(&bf_pending, skb);
539 /* prepend un-acked frames to the beginning of the pending frame queue */
540 if (!skb_queue_empty(&bf_pending)) {
542 ieee80211_sta_set_buffered(sta, tid->tidno, true);
544 spin_lock_bh(&txq->axq_lock);
545 skb_queue_splice(&bf_pending, &tid->buf_q);
547 ath_tx_queue_tid(txq, tid);
549 if (ts->ts_status & ATH9K_TXERR_FILT)
550 tid->ac->clear_ps_filter = true;
552 spin_unlock_bh(&txq->axq_lock);
555 if (tid->state & AGGR_CLEANUP) {
556 ath_tx_flush_tid(sc, tid);
558 if (tid->baw_head == tid->baw_tail) {
559 tid->state &= ~AGGR_ADDBA_COMPLETE;
560 tid->state &= ~AGGR_CLEANUP;
567 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
568 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
572 static bool ath_lookup_legacy(struct ath_buf *bf)
575 struct ieee80211_tx_info *tx_info;
576 struct ieee80211_tx_rate *rates;
580 tx_info = IEEE80211_SKB_CB(skb);
581 rates = tx_info->control.rates;
583 for (i = 0; i < 4; i++) {
584 if (!rates[i].count || rates[i].idx < 0)
587 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
594 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
595 struct ath_atx_tid *tid)
598 struct ieee80211_tx_info *tx_info;
599 struct ieee80211_tx_rate *rates;
600 u32 max_4ms_framelen, frmlen;
601 u16 aggr_limit, legacy = 0;
605 tx_info = IEEE80211_SKB_CB(skb);
606 rates = tx_info->control.rates;
609 * Find the lowest frame length among the rate series that will have a
610 * 4ms transmit duration.
611 * TODO - TXOP limit needs to be considered.
613 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
615 for (i = 0; i < 4; i++) {
616 if (rates[i].count) {
618 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
623 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
628 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
631 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
632 max_4ms_framelen = min(max_4ms_framelen, frmlen);
637 * limit aggregate size by the minimum rate if rate selected is
638 * not a probe rate, if rate selected is a probe rate then
639 * avoid aggregation of this packet.
641 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
644 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
645 aggr_limit = min((max_4ms_framelen * 3) / 8,
646 (u32)ATH_AMPDU_LIMIT_MAX);
648 aggr_limit = min(max_4ms_framelen,
649 (u32)ATH_AMPDU_LIMIT_MAX);
652 * h/w can accept aggregates up to 16 bit lengths (65535).
653 * The IE, however can hold up to 65536, which shows up here
654 * as zero. Ignore 65536 since we are constrained by hw.
656 if (tid->an->maxampdu)
657 aggr_limit = min(aggr_limit, tid->an->maxampdu);
663 * Returns the number of delimiters to be added to
664 * meet the minimum required mpdudensity.
666 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
667 struct ath_buf *bf, u16 frmlen,
670 #define FIRST_DESC_NDELIMS 60
671 struct sk_buff *skb = bf->bf_mpdu;
672 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
673 u32 nsymbits, nsymbols;
676 int width, streams, half_gi, ndelim, mindelim;
677 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
679 /* Select standard number of delimiters based on frame length alone */
680 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
683 * If encryption enabled, hardware requires some more padding between
685 * TODO - this could be improved to be dependent on the rate.
686 * The hardware can keep up at lower rates, but not higher rates
688 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
689 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
690 ndelim += ATH_AGGR_ENCRYPTDELIM;
693 * Add delimiter when using RTS/CTS with aggregation
694 * and non enterprise AR9003 card
696 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
697 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
698 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
701 * Convert desired mpdu density from microeconds to bytes based
702 * on highest rate in rate series (i.e. first rate) to determine
703 * required minimum length for subframe. Take into account
704 * whether high rate is 20 or 40Mhz and half or full GI.
706 * If there is no mpdu density restriction, no further calculation
710 if (tid->an->mpdudensity == 0)
713 rix = tx_info->control.rates[0].idx;
714 flags = tx_info->control.rates[0].flags;
715 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
716 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
719 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
721 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
726 streams = HT_RC_2_STREAMS(rix);
727 nsymbits = bits_per_symbol[rix % 8][width] * streams;
728 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
730 if (frmlen < minlen) {
731 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
732 ndelim = max(mindelim, ndelim);
738 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
740 struct ath_atx_tid *tid,
741 struct list_head *bf_q,
744 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
745 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
746 int rl = 0, nframes = 0, ndelim, prev_al = 0;
747 u16 aggr_limit = 0, al = 0, bpad = 0,
748 al_delta, h_baw = tid->baw_size / 2;
749 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
750 struct ieee80211_tx_info *tx_info;
751 struct ath_frame_info *fi;
756 skb = skb_peek(&tid->buf_q);
757 fi = get_frame_info(skb);
760 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
765 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
766 seqno = bf->bf_state.seqno;
770 /* do not step over block-ack window */
771 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
772 status = ATH_AGGR_BAW_CLOSED;
777 aggr_limit = ath_lookup_rate(sc, bf, tid);
781 /* do not exceed aggregation limit */
782 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
785 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
786 ath_lookup_legacy(bf))) {
787 status = ATH_AGGR_LIMITED;
791 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
792 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
795 /* do not exceed subframe limit */
796 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
797 status = ATH_AGGR_LIMITED;
801 /* add padding for previous frame to aggregation length */
802 al += bpad + al_delta;
805 * Get the delimiters needed to meet the MPDU
806 * density for this node.
808 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
810 bpad = PADBYTES(al_delta) + (ndelim << 2);
815 /* link buffers of this frame to the aggregate */
817 ath_tx_addto_baw(sc, tid, seqno);
818 bf->bf_state.ndelim = ndelim;
820 __skb_unlink(skb, &tid->buf_q);
821 list_add_tail(&bf->list, bf_q);
823 bf_prev->bf_next = bf;
827 } while (!skb_queue_empty(&tid->buf_q));
837 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
838 * width - 0 for 20 MHz, 1 for 40 MHz
839 * half_gi - to use 4us v/s 3.6 us for symbol time
841 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
842 int width, int half_gi, bool shortPreamble)
844 u32 nbits, nsymbits, duration, nsymbols;
847 /* find number of symbols: PLCP + data */
848 streams = HT_RC_2_STREAMS(rix);
849 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
850 nsymbits = bits_per_symbol[rix % 8][width] * streams;
851 nsymbols = (nbits + nsymbits - 1) / nsymbits;
854 duration = SYMBOL_TIME(nsymbols);
856 duration = SYMBOL_TIME_HALFGI(nsymbols);
858 /* addup duration for legacy/ht training and signal fields */
859 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
864 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
865 struct ath_tx_info *info, int len)
867 struct ath_hw *ah = sc->sc_ah;
869 struct ieee80211_tx_info *tx_info;
870 struct ieee80211_tx_rate *rates;
871 const struct ieee80211_rate *rate;
872 struct ieee80211_hdr *hdr;
877 tx_info = IEEE80211_SKB_CB(skb);
878 rates = tx_info->control.rates;
879 hdr = (struct ieee80211_hdr *)skb->data;
881 /* set dur_update_en for l-sig computation except for PS-Poll frames */
882 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
885 * We check if Short Preamble is needed for the CTS rate by
886 * checking the BSS's global flag.
887 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
889 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
890 info->rtscts_rate = rate->hw_value;
891 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
892 info->rtscts_rate |= rate->hw_value_short;
894 for (i = 0; i < 4; i++) {
895 bool is_40, is_sgi, is_sp;
898 if (!rates[i].count || (rates[i].idx < 0))
902 info->rates[i].Tries = rates[i].count;
904 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
905 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
906 info->flags |= ATH9K_TXDESC_RTSENA;
907 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
908 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
909 info->flags |= ATH9K_TXDESC_CTSENA;
912 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
913 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
914 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
915 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
917 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
918 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
919 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
921 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
923 info->rates[i].Rate = rix | 0x80;
924 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
925 ah->txchainmask, info->rates[i].Rate);
926 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
927 is_40, is_sgi, is_sp);
928 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
929 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
934 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
935 !(rate->flags & IEEE80211_RATE_ERP_G))
936 phy = WLAN_RC_PHY_CCK;
938 phy = WLAN_RC_PHY_OFDM;
940 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
941 info->rates[i].Rate = rate->hw_value;
942 if (rate->hw_value_short) {
943 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
944 info->rates[i].Rate |= rate->hw_value_short;
949 if (bf->bf_state.bfs_paprd)
950 info->rates[i].ChSel = ah->txchainmask;
952 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
953 ah->txchainmask, info->rates[i].Rate);
955 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
956 phy, rate->bitrate * 100, len, rix, is_sp);
959 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
960 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
961 info->flags &= ~ATH9K_TXDESC_RTSENA;
963 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
964 if (info->flags & ATH9K_TXDESC_RTSENA)
965 info->flags &= ~ATH9K_TXDESC_CTSENA;
968 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
970 struct ieee80211_hdr *hdr;
971 enum ath9k_pkt_type htype;
974 hdr = (struct ieee80211_hdr *)skb->data;
975 fc = hdr->frame_control;
977 if (ieee80211_is_beacon(fc))
978 htype = ATH9K_PKT_TYPE_BEACON;
979 else if (ieee80211_is_probe_resp(fc))
980 htype = ATH9K_PKT_TYPE_PROBE_RESP;
981 else if (ieee80211_is_atim(fc))
982 htype = ATH9K_PKT_TYPE_ATIM;
983 else if (ieee80211_is_pspoll(fc))
984 htype = ATH9K_PKT_TYPE_PSPOLL;
986 htype = ATH9K_PKT_TYPE_NORMAL;
991 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
992 struct ath_txq *txq, int len)
994 struct ath_hw *ah = sc->sc_ah;
995 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
996 struct ath_buf *bf_first = bf;
997 struct ath_tx_info info;
998 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1000 memset(&info, 0, sizeof(info));
1001 info.is_first = true;
1002 info.is_last = true;
1003 info.txpower = MAX_RATE_POWER;
1004 info.qcu = txq->axq_qnum;
1006 info.flags = ATH9K_TXDESC_INTREQ;
1007 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1008 info.flags |= ATH9K_TXDESC_NOACK;
1009 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1010 info.flags |= ATH9K_TXDESC_LDPC;
1012 ath_buf_set_rate(sc, bf, &info, len);
1014 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1015 info.flags |= ATH9K_TXDESC_CLRDMASK;
1017 if (bf->bf_state.bfs_paprd)
1018 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1022 struct sk_buff *skb = bf->bf_mpdu;
1023 struct ath_frame_info *fi = get_frame_info(skb);
1025 info.type = get_hw_packet_type(skb);
1027 info.link = bf->bf_next->bf_daddr;
1031 info.buf_addr[0] = bf->bf_buf_addr;
1032 info.buf_len[0] = skb->len;
1033 info.pkt_len = fi->framelen;
1034 info.keyix = fi->keyix;
1035 info.keytype = fi->keytype;
1039 info.aggr = AGGR_BUF_FIRST;
1040 else if (!bf->bf_next)
1041 info.aggr = AGGR_BUF_LAST;
1043 info.aggr = AGGR_BUF_MIDDLE;
1045 info.ndelim = bf->bf_state.ndelim;
1046 info.aggr_len = len;
1049 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1054 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1055 struct ath_atx_tid *tid)
1058 enum ATH_AGGR_STATUS status;
1059 struct ieee80211_tx_info *tx_info;
1060 struct list_head bf_q;
1064 if (skb_queue_empty(&tid->buf_q))
1067 INIT_LIST_HEAD(&bf_q);
1069 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1072 * no frames picked up to be aggregated;
1073 * block-ack window is not open.
1075 if (list_empty(&bf_q))
1078 bf = list_first_entry(&bf_q, struct ath_buf, list);
1079 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1080 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1082 if (tid->ac->clear_ps_filter) {
1083 tid->ac->clear_ps_filter = false;
1084 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1086 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1089 /* if only one frame, send as non-aggregate */
1090 if (bf == bf->bf_lastbf) {
1091 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1092 bf->bf_state.bf_type = BUF_AMPDU;
1094 TX_STAT_INC(txq->axq_qnum, a_aggr);
1097 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1098 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1099 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1100 status != ATH_AGGR_BAW_CLOSED);
1103 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1106 struct ath_atx_tid *txtid;
1107 struct ath_node *an;
1109 an = (struct ath_node *)sta->drv_priv;
1110 txtid = ATH_AN_2_TID(an, tid);
1112 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1115 txtid->state |= AGGR_ADDBA_PROGRESS;
1116 txtid->paused = true;
1117 *ssn = txtid->seq_start = txtid->seq_next;
1119 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1120 txtid->baw_head = txtid->baw_tail = 0;
1125 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1127 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1128 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1129 struct ath_txq *txq = txtid->ac->txq;
1131 if (txtid->state & AGGR_CLEANUP)
1134 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1135 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1139 spin_lock_bh(&txq->axq_lock);
1140 txtid->paused = true;
1143 * If frames are still being transmitted for this TID, they will be
1144 * cleaned up during tx completion. To prevent race conditions, this
1145 * TID can only be reused after all in-progress subframes have been
1148 if (txtid->baw_head != txtid->baw_tail)
1149 txtid->state |= AGGR_CLEANUP;
1151 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1152 spin_unlock_bh(&txq->axq_lock);
1154 ath_tx_flush_tid(sc, txtid);
1157 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1158 struct ath_node *an)
1160 struct ath_atx_tid *tid;
1161 struct ath_atx_ac *ac;
1162 struct ath_txq *txq;
1166 for (tidno = 0, tid = &an->tid[tidno];
1167 tidno < WME_NUM_TID; tidno++, tid++) {
1175 spin_lock_bh(&txq->axq_lock);
1177 buffered = !skb_queue_empty(&tid->buf_q);
1180 list_del(&tid->list);
1184 list_del(&ac->list);
1187 spin_unlock_bh(&txq->axq_lock);
1189 ieee80211_sta_set_buffered(sta, tidno, buffered);
1193 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1195 struct ath_atx_tid *tid;
1196 struct ath_atx_ac *ac;
1197 struct ath_txq *txq;
1200 for (tidno = 0, tid = &an->tid[tidno];
1201 tidno < WME_NUM_TID; tidno++, tid++) {
1206 spin_lock_bh(&txq->axq_lock);
1207 ac->clear_ps_filter = true;
1209 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1210 ath_tx_queue_tid(txq, tid);
1211 ath_txq_schedule(sc, txq);
1214 spin_unlock_bh(&txq->axq_lock);
1218 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1220 struct ath_atx_tid *txtid;
1221 struct ath_node *an;
1223 an = (struct ath_node *)sta->drv_priv;
1225 if (sc->sc_flags & SC_OP_TXAGGR) {
1226 txtid = ATH_AN_2_TID(an, tid);
1228 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1229 txtid->state |= AGGR_ADDBA_COMPLETE;
1230 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1231 ath_tx_resume_tid(sc, txtid);
1235 /********************/
1236 /* Queue Management */
1237 /********************/
1239 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1240 struct ath_txq *txq)
1242 struct ath_atx_ac *ac, *ac_tmp;
1243 struct ath_atx_tid *tid, *tid_tmp;
1245 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1246 list_del(&ac->list);
1248 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1249 list_del(&tid->list);
1251 ath_tid_drain(sc, txq, tid);
1256 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1258 struct ath_hw *ah = sc->sc_ah;
1259 struct ath9k_tx_queue_info qi;
1260 static const int subtype_txq_to_hwq[] = {
1261 [WME_AC_BE] = ATH_TXQ_AC_BE,
1262 [WME_AC_BK] = ATH_TXQ_AC_BK,
1263 [WME_AC_VI] = ATH_TXQ_AC_VI,
1264 [WME_AC_VO] = ATH_TXQ_AC_VO,
1268 memset(&qi, 0, sizeof(qi));
1269 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1270 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1271 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1272 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1273 qi.tqi_physCompBuf = 0;
1276 * Enable interrupts only for EOL and DESC conditions.
1277 * We mark tx descriptors to receive a DESC interrupt
1278 * when a tx queue gets deep; otherwise waiting for the
1279 * EOL to reap descriptors. Note that this is done to
1280 * reduce interrupt load and this only defers reaping
1281 * descriptors, never transmitting frames. Aside from
1282 * reducing interrupts this also permits more concurrency.
1283 * The only potential downside is if the tx queue backs
1284 * up in which case the top half of the kernel may backup
1285 * due to a lack of tx descriptors.
1287 * The UAPSD queue is an exception, since we take a desc-
1288 * based intr on the EOSP frames.
1290 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1291 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1292 TXQ_FLAG_TXERRINT_ENABLE;
1294 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1295 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1297 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1298 TXQ_FLAG_TXDESCINT_ENABLE;
1300 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1301 if (axq_qnum == -1) {
1303 * NB: don't print a message, this happens
1304 * normally on parts with too few tx queues
1308 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1309 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1311 txq->axq_qnum = axq_qnum;
1312 txq->mac80211_qnum = -1;
1313 txq->axq_link = NULL;
1314 INIT_LIST_HEAD(&txq->axq_q);
1315 INIT_LIST_HEAD(&txq->axq_acq);
1316 spin_lock_init(&txq->axq_lock);
1318 txq->axq_ampdu_depth = 0;
1319 txq->axq_tx_inprogress = false;
1320 sc->tx.txqsetup |= 1<<axq_qnum;
1322 txq->txq_headidx = txq->txq_tailidx = 0;
1323 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1324 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1326 return &sc->tx.txq[axq_qnum];
1329 int ath_txq_update(struct ath_softc *sc, int qnum,
1330 struct ath9k_tx_queue_info *qinfo)
1332 struct ath_hw *ah = sc->sc_ah;
1334 struct ath9k_tx_queue_info qi;
1336 if (qnum == sc->beacon.beaconq) {
1338 * XXX: for beacon queue, we just save the parameter.
1339 * It will be picked up by ath_beaconq_config when
1342 sc->beacon.beacon_qi = *qinfo;
1346 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1348 ath9k_hw_get_txq_props(ah, qnum, &qi);
1349 qi.tqi_aifs = qinfo->tqi_aifs;
1350 qi.tqi_cwmin = qinfo->tqi_cwmin;
1351 qi.tqi_cwmax = qinfo->tqi_cwmax;
1352 qi.tqi_burstTime = qinfo->tqi_burstTime;
1353 qi.tqi_readyTime = qinfo->tqi_readyTime;
1355 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1356 ath_err(ath9k_hw_common(sc->sc_ah),
1357 "Unable to update hardware queue %u!\n", qnum);
1360 ath9k_hw_resettxqueue(ah, qnum);
1366 int ath_cabq_update(struct ath_softc *sc)
1368 struct ath9k_tx_queue_info qi;
1369 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1370 int qnum = sc->beacon.cabq->axq_qnum;
1372 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1374 * Ensure the readytime % is within the bounds.
1376 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1377 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1378 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1379 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1381 qi.tqi_readyTime = (cur_conf->beacon_interval *
1382 sc->config.cabqReadytime) / 100;
1383 ath_txq_update(sc, qnum, &qi);
1388 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1390 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1391 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1394 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1395 struct list_head *list, bool retry_tx)
1396 __releases(txq->axq_lock)
1397 __acquires(txq->axq_lock)
1399 struct ath_buf *bf, *lastbf;
1400 struct list_head bf_head;
1401 struct ath_tx_status ts;
1403 memset(&ts, 0, sizeof(ts));
1404 INIT_LIST_HEAD(&bf_head);
1406 while (!list_empty(list)) {
1407 bf = list_first_entry(list, struct ath_buf, list);
1410 list_del(&bf->list);
1412 ath_tx_return_buffer(sc, bf);
1416 lastbf = bf->bf_lastbf;
1417 list_cut_position(&bf_head, list, &lastbf->list);
1420 if (bf_is_ampdu_not_probing(bf))
1421 txq->axq_ampdu_depth--;
1423 spin_unlock_bh(&txq->axq_lock);
1425 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1428 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1429 spin_lock_bh(&txq->axq_lock);
1434 * Drain a given TX queue (could be Beacon or Data)
1436 * This assumes output has been stopped and
1437 * we do not need to block ath_tx_tasklet.
1439 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1441 spin_lock_bh(&txq->axq_lock);
1442 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1443 int idx = txq->txq_tailidx;
1445 while (!list_empty(&txq->txq_fifo[idx])) {
1446 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1449 INCR(idx, ATH_TXFIFO_DEPTH);
1451 txq->txq_tailidx = idx;
1454 txq->axq_link = NULL;
1455 txq->axq_tx_inprogress = false;
1456 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1458 /* flush any pending frames if aggregation is enabled */
1459 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1460 ath_txq_drain_pending_buffers(sc, txq);
1462 spin_unlock_bh(&txq->axq_lock);
1465 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1467 struct ath_hw *ah = sc->sc_ah;
1468 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1469 struct ath_txq *txq;
1473 if (sc->sc_flags & SC_OP_INVALID)
1476 ath9k_hw_abort_tx_dma(ah);
1478 /* Check if any queue remains active */
1479 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1480 if (!ATH_TXQ_SETUP(sc, i))
1483 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1488 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1490 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1491 if (!ATH_TXQ_SETUP(sc, i))
1495 * The caller will resume queues with ieee80211_wake_queues.
1496 * Mark the queue as not stopped to prevent ath_tx_complete
1497 * from waking the queue too early.
1499 txq = &sc->tx.txq[i];
1500 txq->stopped = false;
1501 ath_draintxq(sc, txq, retry_tx);
1507 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1509 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1510 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1513 /* For each axq_acq entry, for each tid, try to schedule packets
1514 * for transmit until ampdu_depth has reached min Q depth.
1516 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1518 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1519 struct ath_atx_tid *tid, *last_tid;
1521 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1522 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1525 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1526 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1528 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1529 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1530 list_del(&ac->list);
1533 while (!list_empty(&ac->tid_q)) {
1534 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1536 list_del(&tid->list);
1542 ath_tx_sched_aggr(sc, txq, tid);
1545 * add tid to round-robin queue if more frames
1546 * are pending for the tid
1548 if (!skb_queue_empty(&tid->buf_q))
1549 ath_tx_queue_tid(txq, tid);
1551 if (tid == last_tid ||
1552 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1556 if (!list_empty(&ac->tid_q)) {
1559 list_add_tail(&ac->list, &txq->axq_acq);
1563 if (ac == last_ac ||
1564 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1574 * Insert a chain of ath_buf (descriptors) on a txq and
1575 * assume the descriptors are already chained together by caller.
1577 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1578 struct list_head *head, bool internal)
1580 struct ath_hw *ah = sc->sc_ah;
1581 struct ath_common *common = ath9k_hw_common(ah);
1582 struct ath_buf *bf, *bf_last;
1583 bool puttxbuf = false;
1587 * Insert the frame on the outbound list and
1588 * pass it on to the hardware.
1591 if (list_empty(head))
1594 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1595 bf = list_first_entry(head, struct ath_buf, list);
1596 bf_last = list_entry(head->prev, struct ath_buf, list);
1598 ath_dbg(common, ATH_DBG_QUEUE,
1599 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1601 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1602 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1603 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1606 list_splice_tail_init(head, &txq->axq_q);
1608 if (txq->axq_link) {
1609 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1610 ath_dbg(common, ATH_DBG_XMIT,
1611 "link[%u] (%p)=%llx (%p)\n",
1612 txq->axq_qnum, txq->axq_link,
1613 ito64(bf->bf_daddr), bf->bf_desc);
1617 txq->axq_link = bf_last->bf_desc;
1621 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1622 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1623 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1624 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1628 TX_STAT_INC(txq->axq_qnum, txstart);
1629 ath9k_hw_txstart(ah, txq->axq_qnum);
1634 if (bf_is_ampdu_not_probing(bf))
1635 txq->axq_ampdu_depth++;
1639 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1640 struct sk_buff *skb, struct ath_tx_control *txctl)
1642 struct ath_frame_info *fi = get_frame_info(skb);
1643 struct list_head bf_head;
1647 * Do not queue to h/w when any of the following conditions is true:
1648 * - there are pending frames in software queue
1649 * - the TID is currently paused for ADDBA/BAR request
1650 * - seqno is not within block-ack window
1651 * - h/w queue depth exceeds low water mark
1653 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1654 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1655 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1657 * Add this frame to software queue for scheduling later
1660 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1661 __skb_queue_tail(&tid->buf_q, skb);
1662 if (!txctl->an || !txctl->an->sleeping)
1663 ath_tx_queue_tid(txctl->txq, tid);
1667 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1671 bf->bf_state.bf_type = BUF_AMPDU;
1672 INIT_LIST_HEAD(&bf_head);
1673 list_add(&bf->list, &bf_head);
1675 /* Add sub-frame to BAW */
1676 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1678 /* Queue to h/w without aggregation */
1679 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1681 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1682 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1685 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1686 struct ath_atx_tid *tid, struct sk_buff *skb)
1688 struct ath_frame_info *fi = get_frame_info(skb);
1689 struct list_head bf_head;
1694 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1699 INIT_LIST_HEAD(&bf_head);
1700 list_add_tail(&bf->list, &bf_head);
1701 bf->bf_state.bf_type = 0;
1703 /* update starting sequence number for subsequent ADDBA request */
1705 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1708 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1709 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1710 TX_STAT_INC(txq->axq_qnum, queued);
1713 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1716 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1717 struct ieee80211_sta *sta = tx_info->control.sta;
1718 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1719 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1720 struct ath_frame_info *fi = get_frame_info(skb);
1721 struct ath_node *an = NULL;
1722 enum ath9k_key_type keytype;
1724 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1727 an = (struct ath_node *) sta->drv_priv;
1729 memset(fi, 0, sizeof(*fi));
1731 fi->keyix = hw_key->hw_key_idx;
1732 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1733 fi->keyix = an->ps_key;
1735 fi->keyix = ATH9K_TXKEYIX_INVALID;
1736 fi->keytype = keytype;
1737 fi->framelen = framelen;
1740 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1742 struct ath_hw *ah = sc->sc_ah;
1743 struct ath9k_channel *curchan = ah->curchan;
1744 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1745 (curchan->channelFlags & CHANNEL_5GHZ) &&
1746 (chainmask == 0x7) && (rate < 0x90))
1753 * Assign a descriptor (and sequence number if necessary,
1754 * and map buffer for DMA. Frees skb on error
1756 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1757 struct ath_txq *txq,
1758 struct ath_atx_tid *tid,
1759 struct sk_buff *skb)
1761 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1762 struct ath_frame_info *fi = get_frame_info(skb);
1763 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1767 bf = ath_tx_get_buffer(sc);
1769 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1773 ATH_TXBUF_RESET(bf);
1776 seqno = tid->seq_next;
1777 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1778 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1779 bf->bf_state.seqno = seqno;
1784 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1785 skb->len, DMA_TO_DEVICE);
1786 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1788 bf->bf_buf_addr = 0;
1789 ath_err(ath9k_hw_common(sc->sc_ah),
1790 "dma_mapping_error() on TX\n");
1791 ath_tx_return_buffer(sc, bf);
1800 dev_kfree_skb_any(skb);
1804 /* FIXME: tx power */
1805 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1806 struct ath_tx_control *txctl)
1808 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1809 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1810 struct ath_atx_tid *tid = NULL;
1814 spin_lock_bh(&txctl->txq->axq_lock);
1815 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1816 ieee80211_is_data_qos(hdr->frame_control)) {
1817 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1818 IEEE80211_QOS_CTL_TID_MASK;
1819 tid = ATH_AN_2_TID(txctl->an, tidno);
1821 WARN_ON(tid->ac->txq != txctl->txq);
1824 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1826 * Try aggregation if it's a unicast data frame
1827 * and the destination is HT capable.
1829 ath_tx_send_ampdu(sc, tid, skb, txctl);
1831 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1835 bf->bf_state.bfs_paprd = txctl->paprd;
1838 bf->bf_state.bfs_paprd_timestamp = jiffies;
1840 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1844 spin_unlock_bh(&txctl->txq->axq_lock);
1847 /* Upon failure caller should free skb */
1848 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1849 struct ath_tx_control *txctl)
1851 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1852 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1853 struct ieee80211_sta *sta = info->control.sta;
1854 struct ieee80211_vif *vif = info->control.vif;
1855 struct ath_softc *sc = hw->priv;
1856 struct ath_txq *txq = txctl->txq;
1857 int padpos, padsize;
1858 int frmlen = skb->len + FCS_LEN;
1861 /* NOTE: sta can be NULL according to net/mac80211.h */
1863 txctl->an = (struct ath_node *)sta->drv_priv;
1865 if (info->control.hw_key)
1866 frmlen += info->control.hw_key->icv_len;
1869 * As a temporary workaround, assign seq# here; this will likely need
1870 * to be cleaned up to work better with Beacon transmission and virtual
1873 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1874 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1875 sc->tx.seq_no += 0x10;
1876 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1877 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1880 /* Add the padding after the header if this is not already done */
1881 padpos = ath9k_cmn_padpos(hdr->frame_control);
1882 padsize = padpos & 3;
1883 if (padsize && skb->len > padpos) {
1884 if (skb_headroom(skb) < padsize)
1887 skb_push(skb, padsize);
1888 memmove(skb->data, skb->data + padsize, padpos);
1889 hdr = (struct ieee80211_hdr *) skb->data;
1892 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1893 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1894 !ieee80211_is_data(hdr->frame_control))
1895 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1897 setup_frame_info(hw, skb, frmlen);
1900 * At this point, the vif, hw_key and sta pointers in the tx control
1901 * info are no longer valid (overwritten by the ath_frame_info data.
1904 q = skb_get_queue_mapping(skb);
1905 spin_lock_bh(&txq->axq_lock);
1906 if (txq == sc->tx.txq_map[q] &&
1907 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1908 ieee80211_stop_queue(sc->hw, q);
1911 spin_unlock_bh(&txq->axq_lock);
1913 ath_tx_start_dma(sc, skb, txctl);
1921 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1922 int tx_flags, struct ath_txq *txq)
1924 struct ieee80211_hw *hw = sc->hw;
1925 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1926 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1927 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1928 int q, padpos, padsize;
1930 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1932 if (tx_flags & ATH_TX_BAR)
1933 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1935 if (!(tx_flags & ATH_TX_ERROR))
1936 /* Frame was ACKed */
1937 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1939 padpos = ath9k_cmn_padpos(hdr->frame_control);
1940 padsize = padpos & 3;
1941 if (padsize && skb->len>padpos+padsize) {
1943 * Remove MAC header padding before giving the frame back to
1946 memmove(skb->data + padsize, skb->data, padpos);
1947 skb_pull(skb, padsize);
1950 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1951 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1952 ath_dbg(common, ATH_DBG_PS,
1953 "Going back to sleep after having received TX status (0x%lx)\n",
1954 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1956 PS_WAIT_FOR_PSPOLL_DATA |
1957 PS_WAIT_FOR_TX_ACK));
1960 q = skb_get_queue_mapping(skb);
1961 if (txq == sc->tx.txq_map[q]) {
1962 spin_lock_bh(&txq->axq_lock);
1963 if (WARN_ON(--txq->pending_frames < 0))
1964 txq->pending_frames = 0;
1966 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1967 ieee80211_wake_queue(sc->hw, q);
1970 spin_unlock_bh(&txq->axq_lock);
1973 ieee80211_tx_status(hw, skb);
1976 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1977 struct ath_txq *txq, struct list_head *bf_q,
1978 struct ath_tx_status *ts, int txok, int sendbar)
1980 struct sk_buff *skb = bf->bf_mpdu;
1981 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1982 unsigned long flags;
1986 tx_flags = ATH_TX_BAR;
1989 tx_flags |= ATH_TX_ERROR;
1991 if (ts->ts_status & ATH9K_TXERR_FILT)
1992 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1994 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1995 bf->bf_buf_addr = 0;
1997 if (bf->bf_state.bfs_paprd) {
1998 if (time_after(jiffies,
1999 bf->bf_state.bfs_paprd_timestamp +
2000 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2001 dev_kfree_skb_any(skb);
2003 complete(&sc->paprd_complete);
2005 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2006 ath_tx_complete(sc, skb, tx_flags, txq);
2008 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2009 * accidentally reference it later.
2014 * Return the list of ath_buf of this mpdu to free queue
2016 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2017 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2018 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2021 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2022 struct ath_tx_status *ts, int nframes, int nbad,
2025 struct sk_buff *skb = bf->bf_mpdu;
2026 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2027 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2028 struct ieee80211_hw *hw = sc->hw;
2029 struct ath_hw *ah = sc->sc_ah;
2033 tx_info->status.ack_signal = ts->ts_rssi;
2035 tx_rateindex = ts->ts_rateindex;
2036 WARN_ON(tx_rateindex >= hw->max_rates);
2038 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2039 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2041 BUG_ON(nbad > nframes);
2043 tx_info->status.ampdu_len = nframes;
2044 tx_info->status.ampdu_ack_len = nframes - nbad;
2046 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2047 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2049 * If an underrun error is seen assume it as an excessive
2050 * retry only if max frame trigger level has been reached
2051 * (2 KB for single stream, and 4 KB for dual stream).
2052 * Adjust the long retry as if the frame was tried
2053 * hw->max_rate_tries times to affect how rate control updates
2054 * PER for the failed rate.
2055 * In case of congestion on the bus penalizing this type of
2056 * underruns should help hardware actually transmit new frames
2057 * successfully by eventually preferring slower rates.
2058 * This itself should also alleviate congestion on the bus.
2060 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2061 ATH9K_TX_DELIM_UNDERRUN)) &&
2062 ieee80211_is_data(hdr->frame_control) &&
2063 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2064 tx_info->status.rates[tx_rateindex].count =
2068 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2069 tx_info->status.rates[i].count = 0;
2070 tx_info->status.rates[i].idx = -1;
2073 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2076 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2077 struct ath_tx_status *ts, struct ath_buf *bf,
2078 struct list_head *bf_head)
2079 __releases(txq->axq_lock)
2080 __acquires(txq->axq_lock)
2085 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2086 txq->axq_tx_inprogress = false;
2087 if (bf_is_ampdu_not_probing(bf))
2088 txq->axq_ampdu_depth--;
2090 spin_unlock_bh(&txq->axq_lock);
2092 if (!bf_isampdu(bf)) {
2093 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2094 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2096 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2098 spin_lock_bh(&txq->axq_lock);
2100 if (sc->sc_flags & SC_OP_TXAGGR)
2101 ath_txq_schedule(sc, txq);
2104 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2106 struct ath_hw *ah = sc->sc_ah;
2107 struct ath_common *common = ath9k_hw_common(ah);
2108 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2109 struct list_head bf_head;
2110 struct ath_desc *ds;
2111 struct ath_tx_status ts;
2114 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2115 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2118 spin_lock_bh(&txq->axq_lock);
2120 if (work_pending(&sc->hw_reset_work))
2123 if (list_empty(&txq->axq_q)) {
2124 txq->axq_link = NULL;
2125 if (sc->sc_flags & SC_OP_TXAGGR)
2126 ath_txq_schedule(sc, txq);
2129 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2132 * There is a race condition that a BH gets scheduled
2133 * after sw writes TxE and before hw re-load the last
2134 * descriptor to get the newly chained one.
2135 * Software must keep the last DONE descriptor as a
2136 * holding descriptor - software does so by marking
2137 * it with the STALE flag.
2142 if (list_is_last(&bf_held->list, &txq->axq_q))
2145 bf = list_entry(bf_held->list.next, struct ath_buf,
2149 lastbf = bf->bf_lastbf;
2150 ds = lastbf->bf_desc;
2152 memset(&ts, 0, sizeof(ts));
2153 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2154 if (status == -EINPROGRESS)
2157 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2160 * Remove ath_buf's of the same transmit unit from txq,
2161 * however leave the last descriptor back as the holding
2162 * descriptor for hw.
2164 lastbf->bf_stale = true;
2165 INIT_LIST_HEAD(&bf_head);
2166 if (!list_is_singular(&lastbf->list))
2167 list_cut_position(&bf_head,
2168 &txq->axq_q, lastbf->list.prev);
2171 list_del(&bf_held->list);
2172 ath_tx_return_buffer(sc, bf_held);
2175 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2177 spin_unlock_bh(&txq->axq_lock);
2180 static void ath_tx_complete_poll_work(struct work_struct *work)
2182 struct ath_softc *sc = container_of(work, struct ath_softc,
2183 tx_complete_work.work);
2184 struct ath_txq *txq;
2186 bool needreset = false;
2187 #ifdef CONFIG_ATH9K_DEBUGFS
2188 sc->tx_complete_poll_work_seen++;
2191 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2192 if (ATH_TXQ_SETUP(sc, i)) {
2193 txq = &sc->tx.txq[i];
2194 spin_lock_bh(&txq->axq_lock);
2195 if (txq->axq_depth) {
2196 if (txq->axq_tx_inprogress) {
2198 spin_unlock_bh(&txq->axq_lock);
2201 txq->axq_tx_inprogress = true;
2204 spin_unlock_bh(&txq->axq_lock);
2208 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2209 "tx hung, resetting the chip\n");
2210 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2211 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2214 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2215 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2220 void ath_tx_tasklet(struct ath_softc *sc)
2223 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2225 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2227 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2228 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2229 ath_tx_processq(sc, &sc->tx.txq[i]);
2233 void ath_tx_edma_tasklet(struct ath_softc *sc)
2235 struct ath_tx_status ts;
2236 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2237 struct ath_hw *ah = sc->sc_ah;
2238 struct ath_txq *txq;
2239 struct ath_buf *bf, *lastbf;
2240 struct list_head bf_head;
2244 if (work_pending(&sc->hw_reset_work))
2247 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2248 if (status == -EINPROGRESS)
2250 if (status == -EIO) {
2251 ath_dbg(common, ATH_DBG_XMIT,
2252 "Error processing tx status\n");
2256 /* Skip beacon completions */
2257 if (ts.qid == sc->beacon.beaconq)
2260 txq = &sc->tx.txq[ts.qid];
2262 spin_lock_bh(&txq->axq_lock);
2264 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2265 spin_unlock_bh(&txq->axq_lock);
2269 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2270 struct ath_buf, list);
2271 lastbf = bf->bf_lastbf;
2273 INIT_LIST_HEAD(&bf_head);
2274 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2277 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2278 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2280 if (!list_empty(&txq->axq_q)) {
2281 struct list_head bf_q;
2283 INIT_LIST_HEAD(&bf_q);
2284 txq->axq_link = NULL;
2285 list_splice_tail_init(&txq->axq_q, &bf_q);
2286 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2290 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2291 spin_unlock_bh(&txq->axq_lock);
2299 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2301 struct ath_descdma *dd = &sc->txsdma;
2302 u8 txs_len = sc->sc_ah->caps.txs_len;
2304 dd->dd_desc_len = size * txs_len;
2305 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2306 &dd->dd_desc_paddr, GFP_KERNEL);
2313 static int ath_tx_edma_init(struct ath_softc *sc)
2317 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2319 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2320 sc->txsdma.dd_desc_paddr,
2321 ATH_TXSTATUS_RING_SIZE);
2326 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2328 struct ath_descdma *dd = &sc->txsdma;
2330 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2334 int ath_tx_init(struct ath_softc *sc, int nbufs)
2336 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2339 spin_lock_init(&sc->tx.txbuflock);
2341 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2345 "Failed to allocate tx descriptors: %d\n", error);
2349 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2350 "beacon", ATH_BCBUF, 1, 1);
2353 "Failed to allocate beacon descriptors: %d\n", error);
2357 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2359 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2360 error = ath_tx_edma_init(sc);
2372 void ath_tx_cleanup(struct ath_softc *sc)
2374 if (sc->beacon.bdma.dd_desc_len != 0)
2375 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2377 if (sc->tx.txdma.dd_desc_len != 0)
2378 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2380 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2381 ath_tx_edma_cleanup(sc);
2384 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2386 struct ath_atx_tid *tid;
2387 struct ath_atx_ac *ac;
2390 for (tidno = 0, tid = &an->tid[tidno];
2391 tidno < WME_NUM_TID;
2395 tid->seq_start = tid->seq_next = 0;
2396 tid->baw_size = WME_MAX_BA;
2397 tid->baw_head = tid->baw_tail = 0;
2399 tid->paused = false;
2400 tid->state &= ~AGGR_CLEANUP;
2401 __skb_queue_head_init(&tid->buf_q);
2402 acno = TID_TO_WME_AC(tidno);
2403 tid->ac = &an->ac[acno];
2404 tid->state &= ~AGGR_ADDBA_COMPLETE;
2405 tid->state &= ~AGGR_ADDBA_PROGRESS;
2408 for (acno = 0, ac = &an->ac[acno];
2409 acno < WME_NUM_AC; acno++, ac++) {
2411 ac->txq = sc->tx.txq_map[acno];
2412 INIT_LIST_HEAD(&ac->tid_q);
2416 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2418 struct ath_atx_ac *ac;
2419 struct ath_atx_tid *tid;
2420 struct ath_txq *txq;
2423 for (tidno = 0, tid = &an->tid[tidno];
2424 tidno < WME_NUM_TID; tidno++, tid++) {
2429 spin_lock_bh(&txq->axq_lock);
2432 list_del(&tid->list);
2437 list_del(&ac->list);
2438 tid->ac->sched = false;
2441 ath_tid_drain(sc, txq, tid);
2442 tid->state &= ~AGGR_ADDBA_COMPLETE;
2443 tid->state &= ~AGGR_CLEANUP;
2445 spin_unlock_bh(&txq->axq_lock);