2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 #define OFDM_SIFS_TIME 16
37 static u16 bits_per_symbol[][2] = {
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid,
53 struct list_head *bf_head);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
60 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
61 struct ath_tx_status *ts, int txok);
62 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
63 int nbad, int txok, bool update_rc);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
74 static int ath_max_4ms_framelen[4][32] = {
76 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
77 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
78 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
79 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
82 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
83 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
84 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
85 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
88 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
89 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
90 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
91 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
94 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
95 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
96 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
97 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
101 /*********************/
102 /* Aggregation logic */
103 /*********************/
105 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
107 struct ath_atx_ac *ac = tid->ac;
116 list_add_tail(&tid->list, &ac->tid_q);
122 list_add_tail(&ac->list, &txq->axq_acq);
125 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
127 struct ath_txq *txq = tid->ac->txq;
129 WARN_ON(!tid->paused);
131 spin_lock_bh(&txq->axq_lock);
134 if (list_empty(&tid->buf_q))
137 ath_tx_queue_tid(txq, tid);
138 ath_txq_schedule(sc, txq);
140 spin_unlock_bh(&txq->axq_lock);
143 static u16 ath_frame_seqno(struct sk_buff *skb)
145 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
146 return le16_to_cpu(hdr->seq_ctrl) >> IEEE80211_SEQ_SEQ_SHIFT;
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = tid->ac->txq;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
156 INIT_LIST_HEAD(&bf_head);
158 memset(&ts, 0, sizeof(ts));
159 spin_lock_bh(&txq->axq_lock);
161 while (!list_empty(&tid->buf_q)) {
162 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
163 list_move_tail(&bf->list, &bf_head);
165 if (bf_isretried(bf)) {
166 ath_tx_update_baw(sc, tid, ath_frame_seqno(bf->bf_mpdu));
167 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
169 ath_tx_send_normal(sc, txq, tid, &bf_head);
173 spin_unlock_bh(&txq->axq_lock);
176 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
181 index = ATH_BA_INDEX(tid->seq_start, seqno);
182 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
184 __clear_bit(cindex, tid->tx_buf);
186 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
187 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
188 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
192 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 index = ATH_BA_INDEX(tid->seq_start, seqno);
198 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
199 __set_bit(cindex, tid->tx_buf);
201 if (index >= ((tid->baw_tail - tid->baw_head) &
202 (ATH_TID_MAX_BUFS - 1))) {
203 tid->baw_tail = cindex;
204 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
209 * TODO: For frame(s) that are in the retry state, we will reuse the
210 * sequence number(s) without setting the retry bit. The
211 * alternative is to give up on these and BAR the receiver's window
214 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
215 struct ath_atx_tid *tid)
219 struct list_head bf_head;
220 struct ath_tx_status ts;
223 memset(&ts, 0, sizeof(ts));
224 INIT_LIST_HEAD(&bf_head);
227 if (list_empty(&tid->buf_q))
230 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
231 list_move_tail(&bf->list, &bf_head);
233 bf_seqno = ath_frame_seqno(bf->bf_mpdu);
234 if (bf_isretried(bf))
235 ath_tx_update_baw(sc, tid, bf_seqno);
237 spin_unlock(&txq->axq_lock);
238 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
239 spin_lock(&txq->axq_lock);
242 tid->seq_next = tid->seq_start;
243 tid->baw_tail = tid->baw_head;
246 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
250 struct ieee80211_hdr *hdr;
252 bf->bf_state.bf_type |= BUF_RETRY;
254 TX_STAT_INC(txq->axq_qnum, a_retries);
257 hdr = (struct ieee80211_hdr *)skb->data;
258 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
261 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
263 struct ath_buf *bf = NULL;
265 spin_lock_bh(&sc->tx.txbuflock);
267 if (unlikely(list_empty(&sc->tx.txbuf))) {
268 spin_unlock_bh(&sc->tx.txbuflock);
272 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
275 spin_unlock_bh(&sc->tx.txbuflock);
280 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
282 spin_lock_bh(&sc->tx.txbuflock);
283 list_add_tail(&bf->list, &sc->tx.txbuf);
284 spin_unlock_bh(&sc->tx.txbuflock);
287 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
291 tbf = ath_tx_get_buffer(sc);
295 ATH_TXBUF_RESET(tbf);
297 tbf->aphy = bf->aphy;
298 tbf->bf_mpdu = bf->bf_mpdu;
299 tbf->bf_buf_addr = bf->bf_buf_addr;
300 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
301 tbf->bf_state = bf->bf_state;
306 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
307 struct ath_buf *bf, struct list_head *bf_q,
308 struct ath_tx_status *ts, int txok)
310 struct ath_node *an = NULL;
312 struct ieee80211_sta *sta;
313 struct ieee80211_hw *hw;
314 struct ieee80211_hdr *hdr;
315 struct ieee80211_tx_info *tx_info;
316 struct ath_atx_tid *tid = NULL;
317 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
318 struct list_head bf_head, bf_pending;
319 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
320 u32 ba[WME_BA_BMP_SIZE >> 5];
321 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
322 bool rc_update = true;
323 struct ieee80211_tx_rate rates[4];
329 hdr = (struct ieee80211_hdr *)skb->data;
331 tx_info = IEEE80211_SKB_CB(skb);
334 memcpy(rates, tx_info->control.rates, sizeof(rates));
335 nframes = bf->bf_nframes;
339 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
343 INIT_LIST_HEAD(&bf_head);
345 bf_next = bf->bf_next;
347 bf->bf_state.bf_type |= BUF_XRETRY;
348 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
349 !bf->bf_stale || bf_next != NULL)
350 list_move_tail(&bf->list, &bf_head);
352 ath_tx_rc_status(bf, ts, 1, 0, false);
353 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
361 an = (struct ath_node *)sta->drv_priv;
362 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
363 tid = ATH_AN_2_TID(an, tidno);
366 * The hardware occasionally sends a tx status for the wrong TID.
367 * In this case, the BA status cannot be considered valid and all
368 * subframes need to be retransmitted
370 if (tidno != ts->tid)
373 isaggr = bf_isaggr(bf);
374 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
376 if (isaggr && txok) {
377 if (ts->ts_flags & ATH9K_TX_BA) {
378 seq_st = ts->ts_seqnum;
379 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
382 * AR5416 can become deaf/mute when BA
383 * issue happens. Chip needs to be reset.
384 * But AP code may have sychronization issues
385 * when perform internal reset in this routine.
386 * Only enable reset in STA mode for now.
388 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
393 INIT_LIST_HEAD(&bf_pending);
394 INIT_LIST_HEAD(&bf_head);
396 nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
398 txfail = txpending = 0;
399 bf_next = bf->bf_next;
402 tx_info = IEEE80211_SKB_CB(skb);
403 bf_seqno = ath_frame_seqno(skb);
405 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf_seqno))) {
406 /* transmit completion, subframe is
407 * acked by block ack */
409 } else if (!isaggr && txok) {
410 /* transmit completion */
413 if (!(tid->state & AGGR_CLEANUP) &&
414 !bf_last->bf_tx_aborted) {
415 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
416 ath_tx_set_retry(sc, txq, bf);
419 bf->bf_state.bf_type |= BUF_XRETRY;
426 * cleanup in progress, just fail
427 * the un-acked sub-frames
433 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
436 * Make sure the last desc is reclaimed if it
437 * not a holding desc.
439 if (!bf_last->bf_stale)
440 list_move_tail(&bf->list, &bf_head);
442 INIT_LIST_HEAD(&bf_head);
444 BUG_ON(list_empty(bf_q));
445 list_move_tail(&bf->list, &bf_head);
448 if (!txpending || (tid->state & AGGR_CLEANUP)) {
450 * complete the acked-ones/xretried ones; update
453 spin_lock_bh(&txq->axq_lock);
454 ath_tx_update_baw(sc, tid, bf_seqno);
455 spin_unlock_bh(&txq->axq_lock);
457 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
458 memcpy(tx_info->control.rates, rates, sizeof(rates));
459 bf->bf_nframes = nframes;
460 ath_tx_rc_status(bf, ts, nbad, txok, true);
463 ath_tx_rc_status(bf, ts, nbad, txok, false);
466 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
469 /* retry the un-acked ones */
470 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
471 if (bf->bf_next == NULL && bf_last->bf_stale) {
474 tbf = ath_clone_txbuf(sc, bf_last);
476 * Update tx baw and complete the
477 * frame with failed status if we
481 spin_lock_bh(&txq->axq_lock);
482 ath_tx_update_baw(sc, tid,
484 spin_unlock_bh(&txq->axq_lock);
486 bf->bf_state.bf_type |=
488 ath_tx_rc_status(bf, ts, nbad,
490 ath_tx_complete_buf(sc, bf, txq,
496 ath9k_hw_cleartxdesc(sc->sc_ah,
498 list_add_tail(&tbf->list, &bf_head);
501 * Clear descriptor status words for
504 ath9k_hw_cleartxdesc(sc->sc_ah,
510 * Put this buffer to the temporary pending
511 * queue to retain ordering
513 list_splice_tail_init(&bf_head, &bf_pending);
519 /* prepend un-acked frames to the beginning of the pending frame queue */
520 if (!list_empty(&bf_pending)) {
521 spin_lock_bh(&txq->axq_lock);
522 list_splice(&bf_pending, &tid->buf_q);
523 ath_tx_queue_tid(txq, tid);
524 spin_unlock_bh(&txq->axq_lock);
527 if (tid->state & AGGR_CLEANUP) {
528 ath_tx_flush_tid(sc, tid);
530 if (tid->baw_head == tid->baw_tail) {
531 tid->state &= ~AGGR_ADDBA_COMPLETE;
532 tid->state &= ~AGGR_CLEANUP;
539 ath_reset(sc, false);
542 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
543 struct ath_atx_tid *tid)
546 struct ieee80211_tx_info *tx_info;
547 struct ieee80211_tx_rate *rates;
548 u32 max_4ms_framelen, frmlen;
549 u16 aggr_limit, legacy = 0;
553 tx_info = IEEE80211_SKB_CB(skb);
554 rates = tx_info->control.rates;
557 * Find the lowest frame length among the rate series that will have a
558 * 4ms transmit duration.
559 * TODO - TXOP limit needs to be considered.
561 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
563 for (i = 0; i < 4; i++) {
564 if (rates[i].count) {
566 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
571 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
576 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
579 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
580 max_4ms_framelen = min(max_4ms_framelen, frmlen);
585 * limit aggregate size by the minimum rate if rate selected is
586 * not a probe rate, if rate selected is a probe rate then
587 * avoid aggregation of this packet.
589 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
592 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
593 aggr_limit = min((max_4ms_framelen * 3) / 8,
594 (u32)ATH_AMPDU_LIMIT_MAX);
596 aggr_limit = min(max_4ms_framelen,
597 (u32)ATH_AMPDU_LIMIT_MAX);
600 * h/w can accept aggregates upto 16 bit lengths (65535).
601 * The IE, however can hold upto 65536, which shows up here
602 * as zero. Ignore 65536 since we are constrained by hw.
604 if (tid->an->maxampdu)
605 aggr_limit = min(aggr_limit, tid->an->maxampdu);
611 * Returns the number of delimiters to be added to
612 * meet the minimum required mpdudensity.
614 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
615 struct ath_buf *bf, u16 frmlen)
617 struct sk_buff *skb = bf->bf_mpdu;
618 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
619 u32 nsymbits, nsymbols;
622 int width, streams, half_gi, ndelim, mindelim;
624 /* Select standard number of delimiters based on frame length alone */
625 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
628 * If encryption enabled, hardware requires some more padding between
630 * TODO - this could be improved to be dependent on the rate.
631 * The hardware can keep up at lower rates, but not higher rates
633 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
634 ndelim += ATH_AGGR_ENCRYPTDELIM;
637 * Convert desired mpdu density from microeconds to bytes based
638 * on highest rate in rate series (i.e. first rate) to determine
639 * required minimum length for subframe. Take into account
640 * whether high rate is 20 or 40Mhz and half or full GI.
642 * If there is no mpdu density restriction, no further calculation
646 if (tid->an->mpdudensity == 0)
649 rix = tx_info->control.rates[0].idx;
650 flags = tx_info->control.rates[0].flags;
651 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
652 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
655 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
657 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
662 streams = HT_RC_2_STREAMS(rix);
663 nsymbits = bits_per_symbol[rix % 8][width] * streams;
664 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
666 if (frmlen < minlen) {
667 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
668 ndelim = max(mindelim, ndelim);
674 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
676 struct ath_atx_tid *tid,
677 struct list_head *bf_q)
679 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
680 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
681 int rl = 0, nframes = 0, ndelim, prev_al = 0;
682 u16 aggr_limit = 0, al = 0, bpad = 0,
683 al_delta, h_baw = tid->baw_size / 2;
684 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
685 struct ieee80211_tx_info *tx_info;
688 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
691 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
692 bf_seqno = ath_frame_seqno(bf->bf_mpdu);
694 /* do not step over block-ack window */
695 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf_seqno)) {
696 status = ATH_AGGR_BAW_CLOSED;
701 aggr_limit = ath_lookup_rate(sc, bf, tid);
705 /* do not exceed aggregation limit */
706 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
709 (aggr_limit < (al + bpad + al_delta + prev_al))) {
710 status = ATH_AGGR_LIMITED;
714 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
715 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
716 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
719 /* do not exceed subframe limit */
720 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
721 status = ATH_AGGR_LIMITED;
726 /* add padding for previous frame to aggregation length */
727 al += bpad + al_delta;
730 * Get the delimiters needed to meet the MPDU
731 * density for this node.
733 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
734 bpad = PADBYTES(al_delta) + (ndelim << 2);
737 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
739 /* link buffers of this frame to the aggregate */
740 if (!bf_isretried(bf))
741 ath_tx_addto_baw(sc, tid, bf_seqno);
742 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
743 list_move_tail(&bf->list, bf_q);
745 bf_prev->bf_next = bf;
746 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
751 } while (!list_empty(&tid->buf_q));
753 bf_first->bf_al = al;
754 bf_first->bf_nframes = nframes;
760 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
761 struct ath_atx_tid *tid)
764 enum ATH_AGGR_STATUS status;
765 struct list_head bf_q;
768 if (list_empty(&tid->buf_q))
771 INIT_LIST_HEAD(&bf_q);
773 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
776 * no frames picked up to be aggregated;
777 * block-ack window is not open.
779 if (list_empty(&bf_q))
782 bf = list_first_entry(&bf_q, struct ath_buf, list);
783 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
785 /* if only one frame, send as non-aggregate */
786 if (bf->bf_nframes == 1) {
787 bf->bf_state.bf_type &= ~BUF_AGGR;
788 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
789 ath_buf_set_rate(sc, bf);
790 ath_tx_txqaddbuf(sc, txq, &bf_q);
794 /* setup first desc of aggregate */
795 bf->bf_state.bf_type |= BUF_AGGR;
796 ath_buf_set_rate(sc, bf);
797 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
799 /* anchor last desc of aggregate */
800 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
802 ath_tx_txqaddbuf(sc, txq, &bf_q);
803 TX_STAT_INC(txq->axq_qnum, a_aggr);
805 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
806 status != ATH_AGGR_BAW_CLOSED);
809 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
812 struct ath_atx_tid *txtid;
815 an = (struct ath_node *)sta->drv_priv;
816 txtid = ATH_AN_2_TID(an, tid);
818 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
821 txtid->state |= AGGR_ADDBA_PROGRESS;
822 txtid->paused = true;
823 *ssn = txtid->seq_start;
828 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
830 struct ath_node *an = (struct ath_node *)sta->drv_priv;
831 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
832 struct ath_txq *txq = txtid->ac->txq;
834 if (txtid->state & AGGR_CLEANUP)
837 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
838 txtid->state &= ~AGGR_ADDBA_PROGRESS;
842 spin_lock_bh(&txq->axq_lock);
843 txtid->paused = true;
846 * If frames are still being transmitted for this TID, they will be
847 * cleaned up during tx completion. To prevent race conditions, this
848 * TID can only be reused after all in-progress subframes have been
851 if (txtid->baw_head != txtid->baw_tail)
852 txtid->state |= AGGR_CLEANUP;
854 txtid->state &= ~AGGR_ADDBA_COMPLETE;
855 spin_unlock_bh(&txq->axq_lock);
857 ath_tx_flush_tid(sc, txtid);
860 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
862 struct ath_atx_tid *txtid;
865 an = (struct ath_node *)sta->drv_priv;
867 if (sc->sc_flags & SC_OP_TXAGGR) {
868 txtid = ATH_AN_2_TID(an, tid);
870 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
871 txtid->state |= AGGR_ADDBA_COMPLETE;
872 txtid->state &= ~AGGR_ADDBA_PROGRESS;
873 ath_tx_resume_tid(sc, txtid);
877 /********************/
878 /* Queue Management */
879 /********************/
881 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
884 struct ath_atx_ac *ac, *ac_tmp;
885 struct ath_atx_tid *tid, *tid_tmp;
887 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
890 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
891 list_del(&tid->list);
893 ath_tid_drain(sc, txq, tid);
898 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
900 struct ath_hw *ah = sc->sc_ah;
901 struct ath_common *common = ath9k_hw_common(ah);
902 struct ath9k_tx_queue_info qi;
903 static const int subtype_txq_to_hwq[] = {
904 [WME_AC_BE] = ATH_TXQ_AC_BE,
905 [WME_AC_BK] = ATH_TXQ_AC_BK,
906 [WME_AC_VI] = ATH_TXQ_AC_VI,
907 [WME_AC_VO] = ATH_TXQ_AC_VO,
911 memset(&qi, 0, sizeof(qi));
912 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
913 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
914 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
915 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
916 qi.tqi_physCompBuf = 0;
919 * Enable interrupts only for EOL and DESC conditions.
920 * We mark tx descriptors to receive a DESC interrupt
921 * when a tx queue gets deep; otherwise waiting for the
922 * EOL to reap descriptors. Note that this is done to
923 * reduce interrupt load and this only defers reaping
924 * descriptors, never transmitting frames. Aside from
925 * reducing interrupts this also permits more concurrency.
926 * The only potential downside is if the tx queue backs
927 * up in which case the top half of the kernel may backup
928 * due to a lack of tx descriptors.
930 * The UAPSD queue is an exception, since we take a desc-
931 * based intr on the EOSP frames.
933 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
934 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
935 TXQ_FLAG_TXERRINT_ENABLE;
937 if (qtype == ATH9K_TX_QUEUE_UAPSD)
938 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
940 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
941 TXQ_FLAG_TXDESCINT_ENABLE;
943 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
946 * NB: don't print a message, this happens
947 * normally on parts with too few tx queues
951 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
952 ath_print(common, ATH_DBG_FATAL,
953 "qnum %u out of range, max %u!\n",
954 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
955 ath9k_hw_releasetxqueue(ah, qnum);
958 if (!ATH_TXQ_SETUP(sc, qnum)) {
959 struct ath_txq *txq = &sc->tx.txq[qnum];
961 txq->axq_qnum = qnum;
962 txq->axq_link = NULL;
963 INIT_LIST_HEAD(&txq->axq_q);
964 INIT_LIST_HEAD(&txq->axq_acq);
965 spin_lock_init(&txq->axq_lock);
967 txq->axq_tx_inprogress = false;
968 sc->tx.txqsetup |= 1<<qnum;
970 txq->txq_headidx = txq->txq_tailidx = 0;
971 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
972 INIT_LIST_HEAD(&txq->txq_fifo[i]);
973 INIT_LIST_HEAD(&txq->txq_fifo_pending);
975 return &sc->tx.txq[qnum];
978 int ath_txq_update(struct ath_softc *sc, int qnum,
979 struct ath9k_tx_queue_info *qinfo)
981 struct ath_hw *ah = sc->sc_ah;
983 struct ath9k_tx_queue_info qi;
985 if (qnum == sc->beacon.beaconq) {
987 * XXX: for beacon queue, we just save the parameter.
988 * It will be picked up by ath_beaconq_config when
991 sc->beacon.beacon_qi = *qinfo;
995 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
997 ath9k_hw_get_txq_props(ah, qnum, &qi);
998 qi.tqi_aifs = qinfo->tqi_aifs;
999 qi.tqi_cwmin = qinfo->tqi_cwmin;
1000 qi.tqi_cwmax = qinfo->tqi_cwmax;
1001 qi.tqi_burstTime = qinfo->tqi_burstTime;
1002 qi.tqi_readyTime = qinfo->tqi_readyTime;
1004 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1005 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1006 "Unable to update hardware queue %u!\n", qnum);
1009 ath9k_hw_resettxqueue(ah, qnum);
1015 int ath_cabq_update(struct ath_softc *sc)
1017 struct ath9k_tx_queue_info qi;
1018 int qnum = sc->beacon.cabq->axq_qnum;
1020 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1022 * Ensure the readytime % is within the bounds.
1024 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1025 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1026 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1027 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1029 qi.tqi_readyTime = (sc->beacon_interval *
1030 sc->config.cabqReadytime) / 100;
1031 ath_txq_update(sc, qnum, &qi);
1037 * Drain a given TX queue (could be Beacon or Data)
1039 * This assumes output has been stopped and
1040 * we do not need to block ath_tx_tasklet.
1042 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1044 struct ath_buf *bf, *lastbf;
1045 struct list_head bf_head;
1046 struct ath_tx_status ts;
1048 memset(&ts, 0, sizeof(ts));
1049 INIT_LIST_HEAD(&bf_head);
1052 spin_lock_bh(&txq->axq_lock);
1054 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1055 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1056 txq->txq_headidx = txq->txq_tailidx = 0;
1057 spin_unlock_bh(&txq->axq_lock);
1060 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1061 struct ath_buf, list);
1064 if (list_empty(&txq->axq_q)) {
1065 txq->axq_link = NULL;
1066 spin_unlock_bh(&txq->axq_lock);
1069 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1073 list_del(&bf->list);
1074 spin_unlock_bh(&txq->axq_lock);
1076 ath_tx_return_buffer(sc, bf);
1081 lastbf = bf->bf_lastbf;
1083 lastbf->bf_tx_aborted = true;
1085 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1086 list_cut_position(&bf_head,
1087 &txq->txq_fifo[txq->txq_tailidx],
1089 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1091 /* remove ath_buf's of the same mpdu from txq */
1092 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1097 spin_unlock_bh(&txq->axq_lock);
1100 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
1102 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1105 spin_lock_bh(&txq->axq_lock);
1106 txq->axq_tx_inprogress = false;
1107 spin_unlock_bh(&txq->axq_lock);
1109 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1110 spin_lock_bh(&txq->axq_lock);
1111 while (!list_empty(&txq->txq_fifo_pending)) {
1112 bf = list_first_entry(&txq->txq_fifo_pending,
1113 struct ath_buf, list);
1114 list_cut_position(&bf_head,
1115 &txq->txq_fifo_pending,
1116 &bf->bf_lastbf->list);
1117 spin_unlock_bh(&txq->axq_lock);
1120 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1123 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1125 spin_lock_bh(&txq->axq_lock);
1127 spin_unlock_bh(&txq->axq_lock);
1130 /* flush any pending frames if aggregation is enabled */
1131 if (sc->sc_flags & SC_OP_TXAGGR) {
1133 spin_lock_bh(&txq->axq_lock);
1134 ath_txq_drain_pending_buffers(sc, txq);
1135 spin_unlock_bh(&txq->axq_lock);
1140 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1142 struct ath_hw *ah = sc->sc_ah;
1143 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1144 struct ath_txq *txq;
1147 if (sc->sc_flags & SC_OP_INVALID)
1150 /* Stop beacon queue */
1151 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1153 /* Stop data queues */
1154 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1155 if (ATH_TXQ_SETUP(sc, i)) {
1156 txq = &sc->tx.txq[i];
1157 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1158 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1165 ath_print(common, ATH_DBG_FATAL,
1166 "Failed to stop TX DMA. Resetting hardware!\n");
1168 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1170 ath_print(common, ATH_DBG_FATAL,
1171 "Unable to reset hardware; reset status %d\n",
1175 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1176 if (ATH_TXQ_SETUP(sc, i))
1177 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1181 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1183 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1184 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1187 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1189 struct ath_atx_ac *ac;
1190 struct ath_atx_tid *tid;
1192 if (list_empty(&txq->axq_acq))
1195 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1196 list_del(&ac->list);
1200 if (list_empty(&ac->tid_q))
1203 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1204 list_del(&tid->list);
1210 ath_tx_sched_aggr(sc, txq, tid);
1213 * add tid to round-robin queue if more frames
1214 * are pending for the tid
1216 if (!list_empty(&tid->buf_q))
1217 ath_tx_queue_tid(txq, tid);
1220 } while (!list_empty(&ac->tid_q));
1222 if (!list_empty(&ac->tid_q)) {
1225 list_add_tail(&ac->list, &txq->axq_acq);
1235 * Insert a chain of ath_buf (descriptors) on a txq and
1236 * assume the descriptors are already chained together by caller.
1238 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1239 struct list_head *head)
1241 struct ath_hw *ah = sc->sc_ah;
1242 struct ath_common *common = ath9k_hw_common(ah);
1246 * Insert the frame on the outbound list and
1247 * pass it on to the hardware.
1250 if (list_empty(head))
1253 bf = list_first_entry(head, struct ath_buf, list);
1255 ath_print(common, ATH_DBG_QUEUE,
1256 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1258 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1259 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1260 list_splice_tail_init(head, &txq->txq_fifo_pending);
1263 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1264 ath_print(common, ATH_DBG_XMIT,
1265 "Initializing tx fifo %d which "
1268 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1269 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1270 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1271 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1272 ath_print(common, ATH_DBG_XMIT,
1273 "TXDP[%u] = %llx (%p)\n",
1274 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1276 list_splice_tail_init(head, &txq->axq_q);
1278 if (txq->axq_link == NULL) {
1279 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1280 ath_print(common, ATH_DBG_XMIT,
1281 "TXDP[%u] = %llx (%p)\n",
1282 txq->axq_qnum, ito64(bf->bf_daddr),
1285 *txq->axq_link = bf->bf_daddr;
1286 ath_print(common, ATH_DBG_XMIT,
1287 "link[%u] (%p)=%llx (%p)\n",
1288 txq->axq_qnum, txq->axq_link,
1289 ito64(bf->bf_daddr), bf->bf_desc);
1291 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1293 ath9k_hw_txstart(ah, txq->axq_qnum);
1298 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1299 struct list_head *bf_head,
1300 struct ath_tx_control *txctl)
1305 bf = list_first_entry(bf_head, struct ath_buf, list);
1306 bf->bf_state.bf_type |= BUF_AMPDU;
1307 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1308 bf_seqno = ath_frame_seqno(bf->bf_mpdu);
1311 * Do not queue to h/w when any of the following conditions is true:
1312 * - there are pending frames in software queue
1313 * - the TID is currently paused for ADDBA/BAR request
1314 * - seqno is not within block-ack window
1315 * - h/w queue depth exceeds low water mark
1317 if (!list_empty(&tid->buf_q) || tid->paused ||
1318 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf_seqno) ||
1319 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1321 * Add this frame to software queue for scheduling later
1324 list_move_tail(&bf->list, &tid->buf_q);
1325 ath_tx_queue_tid(txctl->txq, tid);
1329 /* Add sub-frame to BAW */
1330 if (!bf_isretried(bf))
1331 ath_tx_addto_baw(sc, tid, bf_seqno);
1333 /* Queue to h/w without aggregation */
1336 ath_buf_set_rate(sc, bf);
1337 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1340 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1341 struct ath_atx_tid *tid,
1342 struct list_head *bf_head)
1346 bf = list_first_entry(bf_head, struct ath_buf, list);
1347 bf->bf_state.bf_type &= ~BUF_AMPDU;
1349 /* update starting sequence number for subsequent ADDBA request */
1351 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1355 ath_buf_set_rate(sc, bf);
1356 ath_tx_txqaddbuf(sc, txq, bf_head);
1357 TX_STAT_INC(txq->axq_qnum, queued);
1360 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1362 struct ieee80211_hdr *hdr;
1363 enum ath9k_pkt_type htype;
1366 hdr = (struct ieee80211_hdr *)skb->data;
1367 fc = hdr->frame_control;
1369 if (ieee80211_is_beacon(fc))
1370 htype = ATH9K_PKT_TYPE_BEACON;
1371 else if (ieee80211_is_probe_resp(fc))
1372 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1373 else if (ieee80211_is_atim(fc))
1374 htype = ATH9K_PKT_TYPE_ATIM;
1375 else if (ieee80211_is_pspoll(fc))
1376 htype = ATH9K_PKT_TYPE_PSPOLL;
1378 htype = ATH9K_PKT_TYPE_NORMAL;
1383 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1386 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1387 struct ieee80211_hdr *hdr;
1388 struct ath_node *an;
1389 struct ath_atx_tid *tid;
1393 if (!tx_info->control.sta)
1396 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1397 hdr = (struct ieee80211_hdr *)skb->data;
1398 fc = hdr->frame_control;
1399 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1402 * Override seqno set by upper layer with the one
1403 * in tx aggregation state.
1405 tid = ATH_AN_2_TID(an, tidno);
1406 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1407 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1410 static int setup_tx_flags(struct sk_buff *skb)
1412 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1415 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1416 flags |= ATH9K_TXDESC_INTREQ;
1418 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1419 flags |= ATH9K_TXDESC_NOACK;
1421 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1422 flags |= ATH9K_TXDESC_LDPC;
1429 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1430 * width - 0 for 20 MHz, 1 for 40 MHz
1431 * half_gi - to use 4us v/s 3.6 us for symbol time
1433 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1434 int width, int half_gi, bool shortPreamble)
1436 u32 nbits, nsymbits, duration, nsymbols;
1437 int streams, pktlen;
1439 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1441 /* find number of symbols: PLCP + data */
1442 streams = HT_RC_2_STREAMS(rix);
1443 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1444 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1445 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1448 duration = SYMBOL_TIME(nsymbols);
1450 duration = SYMBOL_TIME_HALFGI(nsymbols);
1452 /* addup duration for legacy/ht training and signal fields */
1453 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1458 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1460 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1461 struct ath9k_11n_rate_series series[4];
1462 struct sk_buff *skb;
1463 struct ieee80211_tx_info *tx_info;
1464 struct ieee80211_tx_rate *rates;
1465 const struct ieee80211_rate *rate;
1466 struct ieee80211_hdr *hdr;
1468 u8 rix = 0, ctsrate = 0;
1471 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1474 tx_info = IEEE80211_SKB_CB(skb);
1475 rates = tx_info->control.rates;
1476 hdr = (struct ieee80211_hdr *)skb->data;
1477 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1480 * We check if Short Preamble is needed for the CTS rate by
1481 * checking the BSS's global flag.
1482 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1484 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1485 ctsrate = rate->hw_value;
1486 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1487 ctsrate |= rate->hw_value_short;
1489 for (i = 0; i < 4; i++) {
1490 bool is_40, is_sgi, is_sp;
1493 if (!rates[i].count || (rates[i].idx < 0))
1497 series[i].Tries = rates[i].count;
1498 series[i].ChSel = common->tx_chainmask;
1500 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1501 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1502 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1503 flags |= ATH9K_TXDESC_RTSENA;
1504 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1505 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1506 flags |= ATH9K_TXDESC_CTSENA;
1509 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1510 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1511 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1512 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1514 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1515 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1516 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1518 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1520 series[i].Rate = rix | 0x80;
1521 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1522 is_40, is_sgi, is_sp);
1523 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1524 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1529 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1530 !(rate->flags & IEEE80211_RATE_ERP_G))
1531 phy = WLAN_RC_PHY_CCK;
1533 phy = WLAN_RC_PHY_OFDM;
1535 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1536 series[i].Rate = rate->hw_value;
1537 if (rate->hw_value_short) {
1538 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1539 series[i].Rate |= rate->hw_value_short;
1544 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1545 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1548 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1549 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1550 flags &= ~ATH9K_TXDESC_RTSENA;
1552 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1553 if (flags & ATH9K_TXDESC_RTSENA)
1554 flags &= ~ATH9K_TXDESC_CTSENA;
1556 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1557 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1558 bf->bf_lastbf->bf_desc,
1559 !is_pspoll, ctsrate,
1560 0, series, 4, flags);
1562 if (sc->config.ath_aggr_prot && flags)
1563 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1566 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1567 struct sk_buff *skb)
1569 struct ath_wiphy *aphy = hw->priv;
1570 struct ath_softc *sc = aphy->sc;
1571 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1572 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1573 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1577 int padpos, padsize;
1579 bf = ath_tx_get_buffer(sc);
1581 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1585 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1586 fc = hdr->frame_control;
1588 ATH_TXBUF_RESET(bf);
1591 bf->bf_frmlen = skb->len + FCS_LEN;
1592 /* Remove the padding size from bf_frmlen, if any */
1593 padpos = ath9k_cmn_padpos(hdr->frame_control);
1594 padsize = padpos & 3;
1595 if (padsize && skb->len>padpos+padsize) {
1596 bf->bf_frmlen -= padsize;
1599 if (ieee80211_is_data_qos(fc) && conf_is_ht(&hw->conf)) {
1600 bf->bf_state.bf_type |= BUF_HT;
1601 if (sc->sc_flags & SC_OP_TXAGGR)
1602 assign_aggr_tid_seqno(skb, bf);
1605 bf->bf_flags = setup_tx_flags(skb);
1607 bf->bf_keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1608 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1609 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1610 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1612 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1617 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1618 skb->len, DMA_TO_DEVICE);
1619 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1621 bf->bf_buf_addr = 0;
1622 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1623 "dma_mapping_error() on TX\n");
1624 ath_tx_return_buffer(sc, bf);
1628 bf->bf_tx_aborted = false;
1633 /* FIXME: tx power */
1634 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1635 struct ath_tx_control *txctl)
1637 struct sk_buff *skb = bf->bf_mpdu;
1638 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1639 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1640 struct ath_node *an = NULL;
1641 struct list_head bf_head;
1642 struct ath_desc *ds;
1643 struct ath_atx_tid *tid;
1644 struct ath_hw *ah = sc->sc_ah;
1649 frm_type = get_hw_packet_type(skb);
1650 fc = hdr->frame_control;
1652 INIT_LIST_HEAD(&bf_head);
1653 list_add_tail(&bf->list, &bf_head);
1656 ath9k_hw_set_desc_link(ah, ds, 0);
1658 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1659 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1661 ath9k_hw_filltxdesc(ah, ds,
1662 skb->len, /* segment length */
1663 true, /* first segment */
1664 true, /* last segment */
1665 ds, /* first descriptor */
1667 txctl->txq->axq_qnum);
1669 spin_lock_bh(&txctl->txq->axq_lock);
1671 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1672 tx_info->control.sta) {
1673 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1674 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1675 IEEE80211_QOS_CTL_TID_MASK;
1676 tid = ATH_AN_2_TID(an, tidno);
1679 WARN_ON(tid->ac->txq != txctl->txq);
1680 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1682 * Try aggregation if it's a unicast data frame
1683 * and the destination is HT capable.
1685 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1688 * Send this frame as regular when ADDBA
1689 * exchange is neither complete nor pending.
1691 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1694 bf->bf_state.bfs_ftype = txctl->frame_type;
1695 bf->bf_state.bfs_paprd = txctl->paprd;
1697 if (bf->bf_state.bfs_paprd)
1698 ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
1701 bf->bf_state.bfs_paprd_timestamp = jiffies;
1703 ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head);
1706 spin_unlock_bh(&txctl->txq->axq_lock);
1709 /* Upon failure caller should free skb */
1710 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1711 struct ath_tx_control *txctl)
1713 struct ath_wiphy *aphy = hw->priv;
1714 struct ath_softc *sc = aphy->sc;
1715 struct ath_txq *txq = txctl->txq;
1719 bf = ath_tx_setup_buffer(hw, skb);
1723 q = skb_get_queue_mapping(skb);
1724 spin_lock_bh(&txq->axq_lock);
1725 if (txq == sc->tx.txq_map[q] &&
1726 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1727 ath_mac80211_stop_queue(sc, q);
1730 spin_unlock_bh(&txq->axq_lock);
1732 ath_tx_start_dma(sc, bf, txctl);
1737 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1739 struct ath_wiphy *aphy = hw->priv;
1740 struct ath_softc *sc = aphy->sc;
1741 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1742 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1743 int padpos, padsize;
1744 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1745 struct ath_tx_control txctl;
1747 memset(&txctl, 0, sizeof(struct ath_tx_control));
1750 * As a temporary workaround, assign seq# here; this will likely need
1751 * to be cleaned up to work better with Beacon transmission and virtual
1754 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1755 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1756 sc->tx.seq_no += 0x10;
1757 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1758 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1761 /* Add the padding after the header if this is not already done */
1762 padpos = ath9k_cmn_padpos(hdr->frame_control);
1763 padsize = padpos & 3;
1764 if (padsize && skb->len>padpos) {
1765 if (skb_headroom(skb) < padsize) {
1766 ath_print(common, ATH_DBG_XMIT,
1767 "TX CABQ padding failed\n");
1768 dev_kfree_skb_any(skb);
1771 skb_push(skb, padsize);
1772 memmove(skb->data, skb->data + padsize, padpos);
1775 txctl.txq = sc->beacon.cabq;
1777 ath_print(common, ATH_DBG_XMIT,
1778 "transmitting CABQ packet, skb: %p\n", skb);
1780 if (ath_tx_start(hw, skb, &txctl) != 0) {
1781 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1787 dev_kfree_skb_any(skb);
1794 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1795 struct ath_wiphy *aphy, int tx_flags, int ftype,
1796 struct ath_txq *txq)
1798 struct ieee80211_hw *hw = sc->hw;
1799 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1800 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1801 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1802 int q, padpos, padsize;
1804 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1809 if (tx_flags & ATH_TX_BAR)
1810 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1812 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1813 /* Frame was ACKed */
1814 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1817 padpos = ath9k_cmn_padpos(hdr->frame_control);
1818 padsize = padpos & 3;
1819 if (padsize && skb->len>padpos+padsize) {
1821 * Remove MAC header padding before giving the frame back to
1824 memmove(skb->data + padsize, skb->data, padpos);
1825 skb_pull(skb, padsize);
1828 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1829 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1830 ath_print(common, ATH_DBG_PS,
1831 "Going back to sleep after having "
1832 "received TX status (0x%lx)\n",
1833 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1835 PS_WAIT_FOR_PSPOLL_DATA |
1836 PS_WAIT_FOR_TX_ACK));
1839 if (unlikely(ftype))
1840 ath9k_tx_status(hw, skb, ftype);
1842 q = skb_get_queue_mapping(skb);
1843 if (txq == sc->tx.txq_map[q]) {
1844 spin_lock_bh(&txq->axq_lock);
1845 if (WARN_ON(--txq->pending_frames < 0))
1846 txq->pending_frames = 0;
1847 spin_unlock_bh(&txq->axq_lock);
1850 ieee80211_tx_status(hw, skb);
1854 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1855 struct ath_txq *txq, struct list_head *bf_q,
1856 struct ath_tx_status *ts, int txok, int sendbar)
1858 struct sk_buff *skb = bf->bf_mpdu;
1859 unsigned long flags;
1863 tx_flags = ATH_TX_BAR;
1866 tx_flags |= ATH_TX_ERROR;
1868 if (bf_isxretried(bf))
1869 tx_flags |= ATH_TX_XRETRY;
1872 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1873 bf->bf_buf_addr = 0;
1875 if (bf->bf_state.bfs_paprd) {
1876 if (time_after(jiffies,
1877 bf->bf_state.bfs_paprd_timestamp +
1878 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1879 dev_kfree_skb_any(skb);
1881 complete(&sc->paprd_complete);
1883 ath_debug_stat_tx(sc, bf, ts);
1884 ath_tx_complete(sc, skb, bf->aphy, tx_flags,
1885 bf->bf_state.bfs_ftype, txq);
1887 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1888 * accidentally reference it later.
1893 * Return the list of ath_buf of this mpdu to free queue
1895 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1896 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1897 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1900 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1901 struct ath_tx_status *ts, int txok)
1904 u32 ba[WME_BA_BMP_SIZE >> 5];
1909 if (bf->bf_lastbf->bf_tx_aborted)
1912 isaggr = bf_isaggr(bf);
1914 seq_st = ts->ts_seqnum;
1915 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
1919 ba_index = ATH_BA_INDEX(seq_st, ath_frame_seqno(bf->bf_mpdu));
1920 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1929 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1930 int nbad, int txok, bool update_rc)
1932 struct sk_buff *skb = bf->bf_mpdu;
1933 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1934 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1935 struct ieee80211_hw *hw = bf->aphy->hw;
1936 struct ath_softc *sc = bf->aphy->sc;
1937 struct ath_hw *ah = sc->sc_ah;
1941 tx_info->status.ack_signal = ts->ts_rssi;
1943 tx_rateindex = ts->ts_rateindex;
1944 WARN_ON(tx_rateindex >= hw->max_rates);
1946 if (ts->ts_status & ATH9K_TXERR_FILT)
1947 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1948 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1949 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1951 BUG_ON(nbad > bf->bf_nframes);
1953 tx_info->status.ampdu_len = bf->bf_nframes;
1954 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
1957 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1958 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1960 * If an underrun error is seen assume it as an excessive
1961 * retry only if max frame trigger level has been reached
1962 * (2 KB for single stream, and 4 KB for dual stream).
1963 * Adjust the long retry as if the frame was tried
1964 * hw->max_rate_tries times to affect how rate control updates
1965 * PER for the failed rate.
1966 * In case of congestion on the bus penalizing this type of
1967 * underruns should help hardware actually transmit new frames
1968 * successfully by eventually preferring slower rates.
1969 * This itself should also alleviate congestion on the bus.
1971 if (ieee80211_is_data(hdr->frame_control) &&
1972 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1973 ATH9K_TX_DELIM_UNDERRUN)) &&
1974 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1975 tx_info->status.rates[tx_rateindex].count =
1979 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1980 tx_info->status.rates[i].count = 0;
1981 tx_info->status.rates[i].idx = -1;
1984 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1987 static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum)
1989 struct ath_txq *txq;
1991 txq = sc->tx.txq_map[qnum];
1992 spin_lock_bh(&txq->axq_lock);
1993 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1994 if (ath_mac80211_start_queue(sc, qnum))
1997 spin_unlock_bh(&txq->axq_lock);
2000 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2002 struct ath_hw *ah = sc->sc_ah;
2003 struct ath_common *common = ath9k_hw_common(ah);
2004 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2005 struct list_head bf_head;
2006 struct ath_desc *ds;
2007 struct ath_tx_status ts;
2012 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2013 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2017 spin_lock_bh(&txq->axq_lock);
2018 if (list_empty(&txq->axq_q)) {
2019 txq->axq_link = NULL;
2020 spin_unlock_bh(&txq->axq_lock);
2023 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2026 * There is a race condition that a BH gets scheduled
2027 * after sw writes TxE and before hw re-load the last
2028 * descriptor to get the newly chained one.
2029 * Software must keep the last DONE descriptor as a
2030 * holding descriptor - software does so by marking
2031 * it with the STALE flag.
2036 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2037 spin_unlock_bh(&txq->axq_lock);
2040 bf = list_entry(bf_held->list.next,
2041 struct ath_buf, list);
2045 lastbf = bf->bf_lastbf;
2046 ds = lastbf->bf_desc;
2048 memset(&ts, 0, sizeof(ts));
2049 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2050 if (status == -EINPROGRESS) {
2051 spin_unlock_bh(&txq->axq_lock);
2056 * Remove ath_buf's of the same transmit unit from txq,
2057 * however leave the last descriptor back as the holding
2058 * descriptor for hw.
2060 lastbf->bf_stale = true;
2061 INIT_LIST_HEAD(&bf_head);
2062 if (!list_is_singular(&lastbf->list))
2063 list_cut_position(&bf_head,
2064 &txq->axq_q, lastbf->list.prev);
2067 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2068 txq->axq_tx_inprogress = false;
2070 list_del(&bf_held->list);
2071 spin_unlock_bh(&txq->axq_lock);
2074 ath_tx_return_buffer(sc, bf_held);
2076 if (!bf_isampdu(bf)) {
2078 * This frame is sent out as a single frame.
2079 * Use hardware retry status for this frame.
2081 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2082 bf->bf_state.bf_type |= BUF_XRETRY;
2083 ath_tx_rc_status(bf, &ts, txok ? 0 : 1, txok, true);
2086 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2089 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
2091 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2093 if (txq == sc->tx.txq_map[qnum])
2094 ath_wake_mac80211_queue(sc, qnum);
2096 spin_lock_bh(&txq->axq_lock);
2097 if (sc->sc_flags & SC_OP_TXAGGR)
2098 ath_txq_schedule(sc, txq);
2099 spin_unlock_bh(&txq->axq_lock);
2103 static void ath_tx_complete_poll_work(struct work_struct *work)
2105 struct ath_softc *sc = container_of(work, struct ath_softc,
2106 tx_complete_work.work);
2107 struct ath_txq *txq;
2109 bool needreset = false;
2111 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2112 if (ATH_TXQ_SETUP(sc, i)) {
2113 txq = &sc->tx.txq[i];
2114 spin_lock_bh(&txq->axq_lock);
2115 if (txq->axq_depth) {
2116 if (txq->axq_tx_inprogress) {
2118 spin_unlock_bh(&txq->axq_lock);
2121 txq->axq_tx_inprogress = true;
2124 spin_unlock_bh(&txq->axq_lock);
2128 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2129 "tx hung, resetting the chip\n");
2130 ath9k_ps_wakeup(sc);
2131 ath_reset(sc, true);
2132 ath9k_ps_restore(sc);
2135 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2136 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2141 void ath_tx_tasklet(struct ath_softc *sc)
2144 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2146 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2148 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2149 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2150 ath_tx_processq(sc, &sc->tx.txq[i]);
2154 void ath_tx_edma_tasklet(struct ath_softc *sc)
2156 struct ath_tx_status txs;
2157 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2158 struct ath_hw *ah = sc->sc_ah;
2159 struct ath_txq *txq;
2160 struct ath_buf *bf, *lastbf;
2161 struct list_head bf_head;
2167 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2168 if (status == -EINPROGRESS)
2170 if (status == -EIO) {
2171 ath_print(common, ATH_DBG_XMIT,
2172 "Error processing tx status\n");
2176 /* Skip beacon completions */
2177 if (txs.qid == sc->beacon.beaconq)
2180 txq = &sc->tx.txq[txs.qid];
2182 spin_lock_bh(&txq->axq_lock);
2183 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2184 spin_unlock_bh(&txq->axq_lock);
2188 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2189 struct ath_buf, list);
2190 lastbf = bf->bf_lastbf;
2192 INIT_LIST_HEAD(&bf_head);
2193 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2195 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2197 txq->axq_tx_inprogress = false;
2198 spin_unlock_bh(&txq->axq_lock);
2200 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2202 if (!bf_isampdu(bf)) {
2203 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2204 bf->bf_state.bf_type |= BUF_XRETRY;
2205 ath_tx_rc_status(bf, &txs, txok ? 0 : 1, txok, true);
2208 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2211 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
2213 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2216 if (txq == sc->tx.txq_map[qnum])
2217 ath_wake_mac80211_queue(sc, qnum);
2219 spin_lock_bh(&txq->axq_lock);
2220 if (!list_empty(&txq->txq_fifo_pending)) {
2221 INIT_LIST_HEAD(&bf_head);
2222 bf = list_first_entry(&txq->txq_fifo_pending,
2223 struct ath_buf, list);
2224 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2225 &bf->bf_lastbf->list);
2226 ath_tx_txqaddbuf(sc, txq, &bf_head);
2227 } else if (sc->sc_flags & SC_OP_TXAGGR)
2228 ath_txq_schedule(sc, txq);
2229 spin_unlock_bh(&txq->axq_lock);
2237 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2239 struct ath_descdma *dd = &sc->txsdma;
2240 u8 txs_len = sc->sc_ah->caps.txs_len;
2242 dd->dd_desc_len = size * txs_len;
2243 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2244 &dd->dd_desc_paddr, GFP_KERNEL);
2251 static int ath_tx_edma_init(struct ath_softc *sc)
2255 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2257 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2258 sc->txsdma.dd_desc_paddr,
2259 ATH_TXSTATUS_RING_SIZE);
2264 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2266 struct ath_descdma *dd = &sc->txsdma;
2268 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2272 int ath_tx_init(struct ath_softc *sc, int nbufs)
2274 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2277 spin_lock_init(&sc->tx.txbuflock);
2279 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2282 ath_print(common, ATH_DBG_FATAL,
2283 "Failed to allocate tx descriptors: %d\n", error);
2287 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2288 "beacon", ATH_BCBUF, 1, 1);
2290 ath_print(common, ATH_DBG_FATAL,
2291 "Failed to allocate beacon descriptors: %d\n", error);
2295 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2297 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2298 error = ath_tx_edma_init(sc);
2310 void ath_tx_cleanup(struct ath_softc *sc)
2312 if (sc->beacon.bdma.dd_desc_len != 0)
2313 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2315 if (sc->tx.txdma.dd_desc_len != 0)
2316 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2318 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2319 ath_tx_edma_cleanup(sc);
2322 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2324 struct ath_atx_tid *tid;
2325 struct ath_atx_ac *ac;
2328 for (tidno = 0, tid = &an->tid[tidno];
2329 tidno < WME_NUM_TID;
2333 tid->seq_start = tid->seq_next = 0;
2334 tid->baw_size = WME_MAX_BA;
2335 tid->baw_head = tid->baw_tail = 0;
2337 tid->paused = false;
2338 tid->state &= ~AGGR_CLEANUP;
2339 INIT_LIST_HEAD(&tid->buf_q);
2340 acno = TID_TO_WME_AC(tidno);
2341 tid->ac = &an->ac[acno];
2342 tid->state &= ~AGGR_ADDBA_COMPLETE;
2343 tid->state &= ~AGGR_ADDBA_PROGRESS;
2346 for (acno = 0, ac = &an->ac[acno];
2347 acno < WME_NUM_AC; acno++, ac++) {
2349 ac->txq = sc->tx.txq_map[acno];
2350 INIT_LIST_HEAD(&ac->tid_q);
2354 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2356 struct ath_atx_ac *ac;
2357 struct ath_atx_tid *tid;
2358 struct ath_txq *txq;
2361 for (tidno = 0, tid = &an->tid[tidno];
2362 tidno < WME_NUM_TID; tidno++, tid++) {
2367 spin_lock_bh(&txq->axq_lock);
2370 list_del(&tid->list);
2375 list_del(&ac->list);
2376 tid->ac->sched = false;
2379 ath_tid_drain(sc, txq, tid);
2380 tid->state &= ~AGGR_ADDBA_COMPLETE;
2381 tid->state &= ~AGGR_CLEANUP;
2383 spin_unlock_bh(&txq->axq_lock);