2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid,
52 struct list_head *bf_head);
53 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
54 struct ath_txq *txq, struct list_head *bf_q,
55 struct ath_tx_status *ts, int txok, int sendbar);
56 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
57 struct list_head *head, bool internal);
58 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
72 static int ath_max_4ms_framelen[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
105 struct ath_atx_ac *ac = tid->ac;
114 list_add_tail(&tid->list, &ac->tid_q);
120 list_add_tail(&ac->list, &txq->axq_acq);
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
125 struct ath_txq *txq = tid->ac->txq;
127 WARN_ON(!tid->paused);
129 spin_lock_bh(&txq->axq_lock);
132 if (list_empty(&tid->buf_q))
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
138 spin_unlock_bh(&txq->axq_lock);
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = tid->ac->txq;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
157 INIT_LIST_HEAD(&bf_head);
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
172 ath_tx_send_normal(sc, txq, NULL, &bf_head);
174 spin_lock_bh(&txq->axq_lock);
177 spin_unlock_bh(&txq->axq_lock);
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
188 __clear_bit(cindex, tid->tx_buf);
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
231 if (list_empty(&tid->buf_q))
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
237 fi = get_frame_info(bf->bf_mpdu);
239 ath_tx_update_baw(sc, tid, fi->seqno);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
266 struct ath_buf *bf = NULL;
268 spin_lock_bh(&sc->tx.txbuflock);
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
278 spin_unlock_bh(&sc->tx.txbuflock);
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
294 tbf = ath_tx_get_buffer(sc);
298 ATH_TXBUF_RESET(tbf);
300 tbf->bf_mpdu = bf->bf_mpdu;
301 tbf->bf_buf_addr = bf->bf_buf_addr;
302 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
303 tbf->bf_state = bf->bf_state;
308 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
309 struct ath_tx_status *ts, int txok,
310 int *nframes, int *nbad)
312 struct ath_frame_info *fi;
314 u32 ba[WME_BA_BMP_SIZE >> 5];
321 isaggr = bf_isaggr(bf);
323 seq_st = ts->ts_seqnum;
324 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
328 fi = get_frame_info(bf->bf_mpdu);
329 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
332 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
340 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
341 struct ath_buf *bf, struct list_head *bf_q,
342 struct ath_tx_status *ts, int txok, bool retry)
344 struct ath_node *an = NULL;
346 struct ieee80211_sta *sta;
347 struct ieee80211_hw *hw = sc->hw;
348 struct ieee80211_hdr *hdr;
349 struct ieee80211_tx_info *tx_info;
350 struct ath_atx_tid *tid = NULL;
351 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
352 struct list_head bf_head, bf_pending;
353 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
354 u32 ba[WME_BA_BMP_SIZE >> 5];
355 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
356 bool rc_update = true;
357 struct ieee80211_tx_rate rates[4];
358 struct ath_frame_info *fi;
364 hdr = (struct ieee80211_hdr *)skb->data;
366 tx_info = IEEE80211_SKB_CB(skb);
368 memcpy(rates, tx_info->control.rates, sizeof(rates));
372 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
376 INIT_LIST_HEAD(&bf_head);
378 bf_next = bf->bf_next;
380 bf->bf_state.bf_type |= BUF_XRETRY;
381 if (!bf->bf_stale || bf_next != NULL)
382 list_move_tail(&bf->list, &bf_head);
384 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
385 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
393 an = (struct ath_node *)sta->drv_priv;
394 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
395 tid = ATH_AN_2_TID(an, tidno);
398 * The hardware occasionally sends a tx status for the wrong TID.
399 * In this case, the BA status cannot be considered valid and all
400 * subframes need to be retransmitted
402 if (tidno != ts->tid)
405 isaggr = bf_isaggr(bf);
406 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
408 if (isaggr && txok) {
409 if (ts->ts_flags & ATH9K_TX_BA) {
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
414 * AR5416 can become deaf/mute when BA
415 * issue happens. Chip needs to be reset.
416 * But AP code may have sychronization issues
417 * when perform internal reset in this routine.
418 * Only enable reset in STA mode for now.
420 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
425 INIT_LIST_HEAD(&bf_pending);
426 INIT_LIST_HEAD(&bf_head);
428 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
430 txfail = txpending = sendbar = 0;
431 bf_next = bf->bf_next;
434 tx_info = IEEE80211_SKB_CB(skb);
435 fi = get_frame_info(skb);
437 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
438 /* transmit completion, subframe is
439 * acked by block ack */
441 } else if (!isaggr && txok) {
442 /* transmit completion */
445 if ((tid->state & AGGR_CLEANUP) || !retry) {
447 * cleanup in progress, just fail
448 * the un-acked sub-frames
451 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
452 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
454 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
459 bf->bf_state.bf_type |= BUF_XRETRY;
467 * Make sure the last desc is reclaimed if it
468 * not a holding desc.
470 if (!bf_last->bf_stale || bf_next != NULL)
471 list_move_tail(&bf->list, &bf_head);
473 INIT_LIST_HEAD(&bf_head);
475 if (!txpending || (tid->state & AGGR_CLEANUP)) {
477 * complete the acked-ones/xretried ones; update
480 spin_lock_bh(&txq->axq_lock);
481 ath_tx_update_baw(sc, tid, fi->seqno);
482 spin_unlock_bh(&txq->axq_lock);
484 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
485 memcpy(tx_info->control.rates, rates, sizeof(rates));
486 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
489 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
492 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
495 /* retry the un-acked ones */
496 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
497 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
498 if (bf->bf_next == NULL && bf_last->bf_stale) {
501 tbf = ath_clone_txbuf(sc, bf_last);
503 * Update tx baw and complete the
504 * frame with failed status if we
508 spin_lock_bh(&txq->axq_lock);
509 ath_tx_update_baw(sc, tid, fi->seqno);
510 spin_unlock_bh(&txq->axq_lock);
512 bf->bf_state.bf_type |=
514 ath_tx_rc_status(sc, bf, ts, nframes,
516 ath_tx_complete_buf(sc, bf, txq,
522 ath9k_hw_cleartxdesc(sc->sc_ah,
524 list_add_tail(&tbf->list, &bf_head);
527 * Clear descriptor status words for
530 ath9k_hw_cleartxdesc(sc->sc_ah,
536 * Put this buffer to the temporary pending
537 * queue to retain ordering
539 list_splice_tail_init(&bf_head, &bf_pending);
545 /* prepend un-acked frames to the beginning of the pending frame queue */
546 if (!list_empty(&bf_pending)) {
548 ieee80211_sta_set_tim(sta);
550 spin_lock_bh(&txq->axq_lock);
552 tid->ac->clear_ps_filter = true;
553 list_splice(&bf_pending, &tid->buf_q);
555 ath_tx_queue_tid(txq, tid);
556 spin_unlock_bh(&txq->axq_lock);
559 if (tid->state & AGGR_CLEANUP) {
560 ath_tx_flush_tid(sc, tid);
562 if (tid->baw_head == tid->baw_tail) {
563 tid->state &= ~AGGR_ADDBA_COMPLETE;
564 tid->state &= ~AGGR_CLEANUP;
571 ath_reset(sc, false);
574 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
575 struct ath_atx_tid *tid)
578 struct ieee80211_tx_info *tx_info;
579 struct ieee80211_tx_rate *rates;
580 u32 max_4ms_framelen, frmlen;
581 u16 aggr_limit, legacy = 0;
585 tx_info = IEEE80211_SKB_CB(skb);
586 rates = tx_info->control.rates;
589 * Find the lowest frame length among the rate series that will have a
590 * 4ms transmit duration.
591 * TODO - TXOP limit needs to be considered.
593 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
595 for (i = 0; i < 4; i++) {
596 if (rates[i].count) {
598 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
603 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
608 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
611 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
612 max_4ms_framelen = min(max_4ms_framelen, frmlen);
617 * limit aggregate size by the minimum rate if rate selected is
618 * not a probe rate, if rate selected is a probe rate then
619 * avoid aggregation of this packet.
621 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
624 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
625 aggr_limit = min((max_4ms_framelen * 3) / 8,
626 (u32)ATH_AMPDU_LIMIT_MAX);
628 aggr_limit = min(max_4ms_framelen,
629 (u32)ATH_AMPDU_LIMIT_MAX);
632 * h/w can accept aggregates up to 16 bit lengths (65535).
633 * The IE, however can hold up to 65536, which shows up here
634 * as zero. Ignore 65536 since we are constrained by hw.
636 if (tid->an->maxampdu)
637 aggr_limit = min(aggr_limit, tid->an->maxampdu);
643 * Returns the number of delimiters to be added to
644 * meet the minimum required mpdudensity.
646 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
647 struct ath_buf *bf, u16 frmlen)
649 struct sk_buff *skb = bf->bf_mpdu;
650 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
651 u32 nsymbits, nsymbols;
654 int width, streams, half_gi, ndelim, mindelim;
655 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
657 /* Select standard number of delimiters based on frame length alone */
658 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
661 * If encryption enabled, hardware requires some more padding between
663 * TODO - this could be improved to be dependent on the rate.
664 * The hardware can keep up at lower rates, but not higher rates
666 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
667 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
668 ndelim += ATH_AGGR_ENCRYPTDELIM;
671 * Convert desired mpdu density from microeconds to bytes based
672 * on highest rate in rate series (i.e. first rate) to determine
673 * required minimum length for subframe. Take into account
674 * whether high rate is 20 or 40Mhz and half or full GI.
676 * If there is no mpdu density restriction, no further calculation
680 if (tid->an->mpdudensity == 0)
683 rix = tx_info->control.rates[0].idx;
684 flags = tx_info->control.rates[0].flags;
685 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
686 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
689 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
691 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
696 streams = HT_RC_2_STREAMS(rix);
697 nsymbits = bits_per_symbol[rix % 8][width] * streams;
698 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
700 if (frmlen < minlen) {
701 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
702 ndelim = max(mindelim, ndelim);
708 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
710 struct ath_atx_tid *tid,
711 struct list_head *bf_q,
714 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
715 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
716 int rl = 0, nframes = 0, ndelim, prev_al = 0;
717 u16 aggr_limit = 0, al = 0, bpad = 0,
718 al_delta, h_baw = tid->baw_size / 2;
719 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
720 struct ieee80211_tx_info *tx_info;
721 struct ath_frame_info *fi;
723 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
726 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
727 fi = get_frame_info(bf->bf_mpdu);
729 /* do not step over block-ack window */
730 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
731 status = ATH_AGGR_BAW_CLOSED;
736 aggr_limit = ath_lookup_rate(sc, bf, tid);
740 /* do not exceed aggregation limit */
741 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
744 (aggr_limit < (al + bpad + al_delta + prev_al))) {
745 status = ATH_AGGR_LIMITED;
749 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
750 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
751 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
754 /* do not exceed subframe limit */
755 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
756 status = ATH_AGGR_LIMITED;
761 /* add padding for previous frame to aggregation length */
762 al += bpad + al_delta;
765 * Get the delimiters needed to meet the MPDU
766 * density for this node.
768 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
769 bpad = PADBYTES(al_delta) + (ndelim << 2);
772 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
774 /* link buffers of this frame to the aggregate */
776 ath_tx_addto_baw(sc, tid, fi->seqno);
777 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
778 list_move_tail(&bf->list, bf_q);
780 bf_prev->bf_next = bf;
781 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
786 } while (!list_empty(&tid->buf_q));
794 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
795 struct ath_atx_tid *tid)
798 enum ATH_AGGR_STATUS status;
799 struct ath_frame_info *fi;
800 struct list_head bf_q;
804 if (list_empty(&tid->buf_q))
807 INIT_LIST_HEAD(&bf_q);
809 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
812 * no frames picked up to be aggregated;
813 * block-ack window is not open.
815 if (list_empty(&bf_q))
818 bf = list_first_entry(&bf_q, struct ath_buf, list);
819 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
821 if (tid->ac->clear_ps_filter) {
822 tid->ac->clear_ps_filter = false;
823 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
826 /* if only one frame, send as non-aggregate */
827 if (bf == bf->bf_lastbf) {
828 fi = get_frame_info(bf->bf_mpdu);
830 bf->bf_state.bf_type &= ~BUF_AGGR;
831 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
832 ath_buf_set_rate(sc, bf, fi->framelen);
833 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
837 /* setup first desc of aggregate */
838 bf->bf_state.bf_type |= BUF_AGGR;
839 ath_buf_set_rate(sc, bf, aggr_len);
840 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
842 /* anchor last desc of aggregate */
843 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
845 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
846 TX_STAT_INC(txq->axq_qnum, a_aggr);
848 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
849 status != ATH_AGGR_BAW_CLOSED);
852 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
855 struct ath_atx_tid *txtid;
858 an = (struct ath_node *)sta->drv_priv;
859 txtid = ATH_AN_2_TID(an, tid);
861 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
864 txtid->state |= AGGR_ADDBA_PROGRESS;
865 txtid->paused = true;
866 *ssn = txtid->seq_start = txtid->seq_next;
868 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
869 txtid->baw_head = txtid->baw_tail = 0;
874 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
876 struct ath_node *an = (struct ath_node *)sta->drv_priv;
877 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
878 struct ath_txq *txq = txtid->ac->txq;
880 if (txtid->state & AGGR_CLEANUP)
883 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
884 txtid->state &= ~AGGR_ADDBA_PROGRESS;
888 spin_lock_bh(&txq->axq_lock);
889 txtid->paused = true;
892 * If frames are still being transmitted for this TID, they will be
893 * cleaned up during tx completion. To prevent race conditions, this
894 * TID can only be reused after all in-progress subframes have been
897 if (txtid->baw_head != txtid->baw_tail)
898 txtid->state |= AGGR_CLEANUP;
900 txtid->state &= ~AGGR_ADDBA_COMPLETE;
901 spin_unlock_bh(&txq->axq_lock);
903 ath_tx_flush_tid(sc, txtid);
906 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
908 struct ath_atx_tid *tid;
909 struct ath_atx_ac *ac;
911 bool buffered = false;
914 for (tidno = 0, tid = &an->tid[tidno];
915 tidno < WME_NUM_TID; tidno++, tid++) {
923 spin_lock_bh(&txq->axq_lock);
925 if (!list_empty(&tid->buf_q))
929 list_del(&tid->list);
936 spin_unlock_bh(&txq->axq_lock);
942 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
944 struct ath_atx_tid *tid;
945 struct ath_atx_ac *ac;
949 for (tidno = 0, tid = &an->tid[tidno];
950 tidno < WME_NUM_TID; tidno++, tid++) {
955 spin_lock_bh(&txq->axq_lock);
956 ac->clear_ps_filter = true;
958 if (!list_empty(&tid->buf_q) && !tid->paused) {
959 ath_tx_queue_tid(txq, tid);
960 ath_txq_schedule(sc, txq);
963 spin_unlock_bh(&txq->axq_lock);
967 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
969 struct ath_atx_tid *txtid;
972 an = (struct ath_node *)sta->drv_priv;
974 if (sc->sc_flags & SC_OP_TXAGGR) {
975 txtid = ATH_AN_2_TID(an, tid);
977 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
978 txtid->state |= AGGR_ADDBA_COMPLETE;
979 txtid->state &= ~AGGR_ADDBA_PROGRESS;
980 ath_tx_resume_tid(sc, txtid);
984 /********************/
985 /* Queue Management */
986 /********************/
988 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
991 struct ath_atx_ac *ac, *ac_tmp;
992 struct ath_atx_tid *tid, *tid_tmp;
994 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
997 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
998 list_del(&tid->list);
1000 ath_tid_drain(sc, txq, tid);
1005 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1007 struct ath_hw *ah = sc->sc_ah;
1008 struct ath_common *common = ath9k_hw_common(ah);
1009 struct ath9k_tx_queue_info qi;
1010 static const int subtype_txq_to_hwq[] = {
1011 [WME_AC_BE] = ATH_TXQ_AC_BE,
1012 [WME_AC_BK] = ATH_TXQ_AC_BK,
1013 [WME_AC_VI] = ATH_TXQ_AC_VI,
1014 [WME_AC_VO] = ATH_TXQ_AC_VO,
1018 memset(&qi, 0, sizeof(qi));
1019 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1020 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1021 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1022 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1023 qi.tqi_physCompBuf = 0;
1026 * Enable interrupts only for EOL and DESC conditions.
1027 * We mark tx descriptors to receive a DESC interrupt
1028 * when a tx queue gets deep; otherwise waiting for the
1029 * EOL to reap descriptors. Note that this is done to
1030 * reduce interrupt load and this only defers reaping
1031 * descriptors, never transmitting frames. Aside from
1032 * reducing interrupts this also permits more concurrency.
1033 * The only potential downside is if the tx queue backs
1034 * up in which case the top half of the kernel may backup
1035 * due to a lack of tx descriptors.
1037 * The UAPSD queue is an exception, since we take a desc-
1038 * based intr on the EOSP frames.
1040 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1041 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1042 TXQ_FLAG_TXERRINT_ENABLE;
1044 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1045 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1047 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1048 TXQ_FLAG_TXDESCINT_ENABLE;
1050 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1051 if (axq_qnum == -1) {
1053 * NB: don't print a message, this happens
1054 * normally on parts with too few tx queues
1058 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1059 ath_err(common, "qnum %u out of range, max %zu!\n",
1060 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1061 ath9k_hw_releasetxqueue(ah, axq_qnum);
1064 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1065 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1067 txq->axq_qnum = axq_qnum;
1068 txq->mac80211_qnum = -1;
1069 txq->axq_link = NULL;
1070 INIT_LIST_HEAD(&txq->axq_q);
1071 INIT_LIST_HEAD(&txq->axq_acq);
1072 spin_lock_init(&txq->axq_lock);
1074 txq->axq_ampdu_depth = 0;
1075 txq->axq_tx_inprogress = false;
1076 sc->tx.txqsetup |= 1<<axq_qnum;
1078 txq->txq_headidx = txq->txq_tailidx = 0;
1079 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1080 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1082 return &sc->tx.txq[axq_qnum];
1085 int ath_txq_update(struct ath_softc *sc, int qnum,
1086 struct ath9k_tx_queue_info *qinfo)
1088 struct ath_hw *ah = sc->sc_ah;
1090 struct ath9k_tx_queue_info qi;
1092 if (qnum == sc->beacon.beaconq) {
1094 * XXX: for beacon queue, we just save the parameter.
1095 * It will be picked up by ath_beaconq_config when
1098 sc->beacon.beacon_qi = *qinfo;
1102 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1104 ath9k_hw_get_txq_props(ah, qnum, &qi);
1105 qi.tqi_aifs = qinfo->tqi_aifs;
1106 qi.tqi_cwmin = qinfo->tqi_cwmin;
1107 qi.tqi_cwmax = qinfo->tqi_cwmax;
1108 qi.tqi_burstTime = qinfo->tqi_burstTime;
1109 qi.tqi_readyTime = qinfo->tqi_readyTime;
1111 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1112 ath_err(ath9k_hw_common(sc->sc_ah),
1113 "Unable to update hardware queue %u!\n", qnum);
1116 ath9k_hw_resettxqueue(ah, qnum);
1122 int ath_cabq_update(struct ath_softc *sc)
1124 struct ath9k_tx_queue_info qi;
1125 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1126 int qnum = sc->beacon.cabq->axq_qnum;
1128 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1130 * Ensure the readytime % is within the bounds.
1132 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1133 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1134 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1135 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1137 qi.tqi_readyTime = (cur_conf->beacon_interval *
1138 sc->config.cabqReadytime) / 100;
1139 ath_txq_update(sc, qnum, &qi);
1144 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1146 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1147 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1150 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1151 struct list_head *list, bool retry_tx)
1152 __releases(txq->axq_lock)
1153 __acquires(txq->axq_lock)
1155 struct ath_buf *bf, *lastbf;
1156 struct list_head bf_head;
1157 struct ath_tx_status ts;
1159 memset(&ts, 0, sizeof(ts));
1160 INIT_LIST_HEAD(&bf_head);
1162 while (!list_empty(list)) {
1163 bf = list_first_entry(list, struct ath_buf, list);
1166 list_del(&bf->list);
1168 ath_tx_return_buffer(sc, bf);
1172 lastbf = bf->bf_lastbf;
1173 list_cut_position(&bf_head, list, &lastbf->list);
1176 if (bf_is_ampdu_not_probing(bf))
1177 txq->axq_ampdu_depth--;
1179 spin_unlock_bh(&txq->axq_lock);
1181 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1184 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1185 spin_lock_bh(&txq->axq_lock);
1190 * Drain a given TX queue (could be Beacon or Data)
1192 * This assumes output has been stopped and
1193 * we do not need to block ath_tx_tasklet.
1195 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1197 spin_lock_bh(&txq->axq_lock);
1198 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1199 int idx = txq->txq_tailidx;
1201 while (!list_empty(&txq->txq_fifo[idx])) {
1202 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1205 INCR(idx, ATH_TXFIFO_DEPTH);
1207 txq->txq_tailidx = idx;
1210 txq->axq_link = NULL;
1211 txq->axq_tx_inprogress = false;
1212 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1214 /* flush any pending frames if aggregation is enabled */
1215 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1216 ath_txq_drain_pending_buffers(sc, txq);
1218 spin_unlock_bh(&txq->axq_lock);
1221 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1223 struct ath_hw *ah = sc->sc_ah;
1224 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1225 struct ath_txq *txq;
1228 if (sc->sc_flags & SC_OP_INVALID)
1231 ath9k_hw_abort_tx_dma(ah);
1233 /* Check if any queue remains active */
1234 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1235 if (!ATH_TXQ_SETUP(sc, i))
1238 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1242 ath_err(common, "Failed to stop TX DMA!\n");
1244 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1245 if (!ATH_TXQ_SETUP(sc, i))
1249 * The caller will resume queues with ieee80211_wake_queues.
1250 * Mark the queue as not stopped to prevent ath_tx_complete
1251 * from waking the queue too early.
1253 txq = &sc->tx.txq[i];
1254 txq->stopped = false;
1255 ath_draintxq(sc, txq, retry_tx);
1261 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1263 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1264 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1267 /* For each axq_acq entry, for each tid, try to schedule packets
1268 * for transmit until ampdu_depth has reached min Q depth.
1270 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1272 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1273 struct ath_atx_tid *tid, *last_tid;
1275 if (list_empty(&txq->axq_acq) ||
1276 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1279 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1280 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1282 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1283 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1284 list_del(&ac->list);
1287 while (!list_empty(&ac->tid_q)) {
1288 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1290 list_del(&tid->list);
1296 ath_tx_sched_aggr(sc, txq, tid);
1299 * add tid to round-robin queue if more frames
1300 * are pending for the tid
1302 if (!list_empty(&tid->buf_q))
1303 ath_tx_queue_tid(txq, tid);
1305 if (tid == last_tid ||
1306 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1310 if (!list_empty(&ac->tid_q)) {
1313 list_add_tail(&ac->list, &txq->axq_acq);
1317 if (ac == last_ac ||
1318 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1328 * Insert a chain of ath_buf (descriptors) on a txq and
1329 * assume the descriptors are already chained together by caller.
1331 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1332 struct list_head *head, bool internal)
1334 struct ath_hw *ah = sc->sc_ah;
1335 struct ath_common *common = ath9k_hw_common(ah);
1336 struct ath_buf *bf, *bf_last;
1337 bool puttxbuf = false;
1341 * Insert the frame on the outbound list and
1342 * pass it on to the hardware.
1345 if (list_empty(head))
1348 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1349 bf = list_first_entry(head, struct ath_buf, list);
1350 bf_last = list_entry(head->prev, struct ath_buf, list);
1352 ath_dbg(common, ATH_DBG_QUEUE,
1353 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1355 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1356 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1357 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1360 list_splice_tail_init(head, &txq->axq_q);
1362 if (txq->axq_link) {
1363 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1364 ath_dbg(common, ATH_DBG_XMIT,
1365 "link[%u] (%p)=%llx (%p)\n",
1366 txq->axq_qnum, txq->axq_link,
1367 ito64(bf->bf_daddr), bf->bf_desc);
1371 txq->axq_link = bf_last->bf_desc;
1375 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1376 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1377 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1378 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1382 TX_STAT_INC(txq->axq_qnum, txstart);
1383 ath9k_hw_txstart(ah, txq->axq_qnum);
1388 if (bf_is_ampdu_not_probing(bf))
1389 txq->axq_ampdu_depth++;
1393 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1394 struct ath_buf *bf, struct ath_tx_control *txctl)
1396 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1397 struct list_head bf_head;
1399 bf->bf_state.bf_type |= BUF_AMPDU;
1402 * Do not queue to h/w when any of the following conditions is true:
1403 * - there are pending frames in software queue
1404 * - the TID is currently paused for ADDBA/BAR request
1405 * - seqno is not within block-ack window
1406 * - h/w queue depth exceeds low water mark
1408 if (!list_empty(&tid->buf_q) || tid->paused ||
1409 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1410 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1412 * Add this frame to software queue for scheduling later
1415 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1416 list_add_tail(&bf->list, &tid->buf_q);
1417 if (!txctl->an || !txctl->an->sleeping)
1418 ath_tx_queue_tid(txctl->txq, tid);
1422 INIT_LIST_HEAD(&bf_head);
1423 list_add(&bf->list, &bf_head);
1425 /* Add sub-frame to BAW */
1427 ath_tx_addto_baw(sc, tid, fi->seqno);
1429 /* Queue to h/w without aggregation */
1430 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1432 ath_buf_set_rate(sc, bf, fi->framelen);
1433 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1436 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1437 struct ath_atx_tid *tid,
1438 struct list_head *bf_head)
1440 struct ath_frame_info *fi;
1443 bf = list_first_entry(bf_head, struct ath_buf, list);
1444 bf->bf_state.bf_type &= ~BUF_AMPDU;
1446 /* update starting sequence number for subsequent ADDBA request */
1448 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1451 fi = get_frame_info(bf->bf_mpdu);
1452 ath_buf_set_rate(sc, bf, fi->framelen);
1453 ath_tx_txqaddbuf(sc, txq, bf_head, false);
1454 TX_STAT_INC(txq->axq_qnum, queued);
1457 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1459 struct ieee80211_hdr *hdr;
1460 enum ath9k_pkt_type htype;
1463 hdr = (struct ieee80211_hdr *)skb->data;
1464 fc = hdr->frame_control;
1466 if (ieee80211_is_beacon(fc))
1467 htype = ATH9K_PKT_TYPE_BEACON;
1468 else if (ieee80211_is_probe_resp(fc))
1469 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1470 else if (ieee80211_is_atim(fc))
1471 htype = ATH9K_PKT_TYPE_ATIM;
1472 else if (ieee80211_is_pspoll(fc))
1473 htype = ATH9K_PKT_TYPE_PSPOLL;
1475 htype = ATH9K_PKT_TYPE_NORMAL;
1480 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1483 struct ath_softc *sc = hw->priv;
1484 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1485 struct ieee80211_sta *sta = tx_info->control.sta;
1486 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1487 struct ieee80211_hdr *hdr;
1488 struct ath_frame_info *fi = get_frame_info(skb);
1489 struct ath_node *an = NULL;
1490 struct ath_atx_tid *tid;
1491 enum ath9k_key_type keytype;
1495 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1498 an = (struct ath_node *) sta->drv_priv;
1500 hdr = (struct ieee80211_hdr *)skb->data;
1501 if (an && ieee80211_is_data_qos(hdr->frame_control) &&
1502 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1504 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1507 * Override seqno set by upper layer with the one
1508 * in tx aggregation state.
1510 tid = ATH_AN_2_TID(an, tidno);
1511 seqno = tid->seq_next;
1512 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1513 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1516 memset(fi, 0, sizeof(*fi));
1518 fi->keyix = hw_key->hw_key_idx;
1519 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1520 fi->keyix = an->ps_key;
1522 fi->keyix = ATH9K_TXKEYIX_INVALID;
1523 fi->keytype = keytype;
1524 fi->framelen = framelen;
1528 static int setup_tx_flags(struct sk_buff *skb)
1530 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1533 flags |= ATH9K_TXDESC_INTREQ;
1535 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1536 flags |= ATH9K_TXDESC_NOACK;
1538 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1539 flags |= ATH9K_TXDESC_LDPC;
1546 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1547 * width - 0 for 20 MHz, 1 for 40 MHz
1548 * half_gi - to use 4us v/s 3.6 us for symbol time
1550 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1551 int width, int half_gi, bool shortPreamble)
1553 u32 nbits, nsymbits, duration, nsymbols;
1556 /* find number of symbols: PLCP + data */
1557 streams = HT_RC_2_STREAMS(rix);
1558 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1559 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1560 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1563 duration = SYMBOL_TIME(nsymbols);
1565 duration = SYMBOL_TIME_HALFGI(nsymbols);
1567 /* addup duration for legacy/ht training and signal fields */
1568 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1573 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1575 struct ath_hw *ah = sc->sc_ah;
1576 struct ath9k_channel *curchan = ah->curchan;
1577 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1578 (curchan->channelFlags & CHANNEL_5GHZ) &&
1579 (chainmask == 0x7) && (rate < 0x90))
1585 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1587 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1588 struct ath9k_11n_rate_series series[4];
1589 struct sk_buff *skb;
1590 struct ieee80211_tx_info *tx_info;
1591 struct ieee80211_tx_rate *rates;
1592 const struct ieee80211_rate *rate;
1593 struct ieee80211_hdr *hdr;
1595 u8 rix = 0, ctsrate = 0;
1598 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1601 tx_info = IEEE80211_SKB_CB(skb);
1602 rates = tx_info->control.rates;
1603 hdr = (struct ieee80211_hdr *)skb->data;
1604 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1607 * We check if Short Preamble is needed for the CTS rate by
1608 * checking the BSS's global flag.
1609 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1611 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1612 ctsrate = rate->hw_value;
1613 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1614 ctsrate |= rate->hw_value_short;
1616 for (i = 0; i < 4; i++) {
1617 bool is_40, is_sgi, is_sp;
1620 if (!rates[i].count || (rates[i].idx < 0))
1624 series[i].Tries = rates[i].count;
1626 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1627 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1628 flags |= ATH9K_TXDESC_RTSENA;
1629 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1630 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1631 flags |= ATH9K_TXDESC_CTSENA;
1634 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1635 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1636 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1637 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1639 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1640 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1641 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1643 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1645 series[i].Rate = rix | 0x80;
1646 series[i].ChSel = ath_txchainmask_reduction(sc,
1647 common->tx_chainmask, series[i].Rate);
1648 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1649 is_40, is_sgi, is_sp);
1650 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1651 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1656 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1657 !(rate->flags & IEEE80211_RATE_ERP_G))
1658 phy = WLAN_RC_PHY_CCK;
1660 phy = WLAN_RC_PHY_OFDM;
1662 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1663 series[i].Rate = rate->hw_value;
1664 if (rate->hw_value_short) {
1665 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1666 series[i].Rate |= rate->hw_value_short;
1671 if (bf->bf_state.bfs_paprd)
1672 series[i].ChSel = common->tx_chainmask;
1674 series[i].ChSel = ath_txchainmask_reduction(sc,
1675 common->tx_chainmask, series[i].Rate);
1677 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1678 phy, rate->bitrate * 100, len, rix, is_sp);
1681 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1682 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1683 flags &= ~ATH9K_TXDESC_RTSENA;
1685 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1686 if (flags & ATH9K_TXDESC_RTSENA)
1687 flags &= ~ATH9K_TXDESC_CTSENA;
1689 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1690 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1691 bf->bf_lastbf->bf_desc,
1692 !is_pspoll, ctsrate,
1693 0, series, 4, flags);
1697 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1698 struct ath_txq *txq,
1699 struct sk_buff *skb)
1701 struct ath_softc *sc = hw->priv;
1702 struct ath_hw *ah = sc->sc_ah;
1703 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1704 struct ath_frame_info *fi = get_frame_info(skb);
1706 struct ath_desc *ds;
1709 bf = ath_tx_get_buffer(sc);
1711 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1715 ATH_TXBUF_RESET(bf);
1717 bf->bf_flags = setup_tx_flags(skb);
1720 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1721 skb->len, DMA_TO_DEVICE);
1722 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1724 bf->bf_buf_addr = 0;
1725 ath_err(ath9k_hw_common(sc->sc_ah),
1726 "dma_mapping_error() on TX\n");
1727 ath_tx_return_buffer(sc, bf);
1731 frm_type = get_hw_packet_type(skb);
1734 ath9k_hw_set_desc_link(ah, ds, 0);
1736 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1737 fi->keyix, fi->keytype, bf->bf_flags);
1739 ath9k_hw_filltxdesc(ah, ds,
1740 skb->len, /* segment length */
1741 true, /* first segment */
1742 true, /* last segment */
1743 ds, /* first descriptor */
1751 /* FIXME: tx power */
1752 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1753 struct ath_tx_control *txctl)
1755 struct sk_buff *skb = bf->bf_mpdu;
1756 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1757 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1758 struct list_head bf_head;
1759 struct ath_atx_tid *tid = NULL;
1762 spin_lock_bh(&txctl->txq->axq_lock);
1763 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1764 ieee80211_is_data_qos(hdr->frame_control)) {
1765 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1766 IEEE80211_QOS_CTL_TID_MASK;
1767 tid = ATH_AN_2_TID(txctl->an, tidno);
1769 WARN_ON(tid->ac->txq != txctl->txq);
1772 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1774 * Try aggregation if it's a unicast data frame
1775 * and the destination is HT capable.
1777 ath_tx_send_ampdu(sc, tid, bf, txctl);
1779 INIT_LIST_HEAD(&bf_head);
1780 list_add_tail(&bf->list, &bf_head);
1782 bf->bf_state.bfs_paprd = txctl->paprd;
1784 if (bf->bf_state.bfs_paprd)
1785 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1786 bf->bf_state.bfs_paprd);
1789 bf->bf_state.bfs_paprd_timestamp = jiffies;
1791 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1792 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1794 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1797 spin_unlock_bh(&txctl->txq->axq_lock);
1800 /* Upon failure caller should free skb */
1801 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1802 struct ath_tx_control *txctl)
1804 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1805 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1806 struct ieee80211_sta *sta = info->control.sta;
1807 struct ieee80211_vif *vif = info->control.vif;
1808 struct ath_softc *sc = hw->priv;
1809 struct ath_txq *txq = txctl->txq;
1811 int padpos, padsize;
1812 int frmlen = skb->len + FCS_LEN;
1815 /* NOTE: sta can be NULL according to net/mac80211.h */
1817 txctl->an = (struct ath_node *)sta->drv_priv;
1819 if (info->control.hw_key)
1820 frmlen += info->control.hw_key->icv_len;
1823 * As a temporary workaround, assign seq# here; this will likely need
1824 * to be cleaned up to work better with Beacon transmission and virtual
1827 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1828 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1829 sc->tx.seq_no += 0x10;
1830 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1831 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1834 /* Add the padding after the header if this is not already done */
1835 padpos = ath9k_cmn_padpos(hdr->frame_control);
1836 padsize = padpos & 3;
1837 if (padsize && skb->len > padpos) {
1838 if (skb_headroom(skb) < padsize)
1841 skb_push(skb, padsize);
1842 memmove(skb->data, skb->data + padsize, padpos);
1845 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1846 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1847 !ieee80211_is_data(hdr->frame_control))
1848 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1850 setup_frame_info(hw, skb, frmlen);
1853 * At this point, the vif, hw_key and sta pointers in the tx control
1854 * info are no longer valid (overwritten by the ath_frame_info data.
1857 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1861 q = skb_get_queue_mapping(skb);
1862 spin_lock_bh(&txq->axq_lock);
1863 if (txq == sc->tx.txq_map[q] &&
1864 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1865 ieee80211_stop_queue(sc->hw, q);
1868 spin_unlock_bh(&txq->axq_lock);
1870 ath_tx_start_dma(sc, bf, txctl);
1879 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1880 int tx_flags, struct ath_txq *txq)
1882 struct ieee80211_hw *hw = sc->hw;
1883 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1884 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1885 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1886 int q, padpos, padsize;
1888 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1890 if (tx_flags & ATH_TX_BAR)
1891 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1893 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1894 /* Frame was ACKed */
1895 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1898 padpos = ath9k_cmn_padpos(hdr->frame_control);
1899 padsize = padpos & 3;
1900 if (padsize && skb->len>padpos+padsize) {
1902 * Remove MAC header padding before giving the frame back to
1905 memmove(skb->data + padsize, skb->data, padpos);
1906 skb_pull(skb, padsize);
1909 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1910 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1911 ath_dbg(common, ATH_DBG_PS,
1912 "Going back to sleep after having received TX status (0x%lx)\n",
1913 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1915 PS_WAIT_FOR_PSPOLL_DATA |
1916 PS_WAIT_FOR_TX_ACK));
1919 q = skb_get_queue_mapping(skb);
1920 if (txq == sc->tx.txq_map[q]) {
1921 spin_lock_bh(&txq->axq_lock);
1922 if (WARN_ON(--txq->pending_frames < 0))
1923 txq->pending_frames = 0;
1925 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1926 ieee80211_wake_queue(sc->hw, q);
1929 spin_unlock_bh(&txq->axq_lock);
1932 ieee80211_tx_status(hw, skb);
1935 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1936 struct ath_txq *txq, struct list_head *bf_q,
1937 struct ath_tx_status *ts, int txok, int sendbar)
1939 struct sk_buff *skb = bf->bf_mpdu;
1940 unsigned long flags;
1944 tx_flags = ATH_TX_BAR;
1947 tx_flags |= ATH_TX_ERROR;
1949 if (bf_isxretried(bf))
1950 tx_flags |= ATH_TX_XRETRY;
1953 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1954 bf->bf_buf_addr = 0;
1956 if (bf->bf_state.bfs_paprd) {
1957 if (time_after(jiffies,
1958 bf->bf_state.bfs_paprd_timestamp +
1959 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1960 dev_kfree_skb_any(skb);
1962 complete(&sc->paprd_complete);
1964 ath_debug_stat_tx(sc, bf, ts, txq);
1965 ath_tx_complete(sc, skb, tx_flags, txq);
1967 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1968 * accidentally reference it later.
1973 * Return the list of ath_buf of this mpdu to free queue
1975 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1976 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1977 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1980 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1981 struct ath_tx_status *ts, int nframes, int nbad,
1982 int txok, bool update_rc)
1984 struct sk_buff *skb = bf->bf_mpdu;
1985 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1986 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1987 struct ieee80211_hw *hw = sc->hw;
1988 struct ath_hw *ah = sc->sc_ah;
1992 tx_info->status.ack_signal = ts->ts_rssi;
1994 tx_rateindex = ts->ts_rateindex;
1995 WARN_ON(tx_rateindex >= hw->max_rates);
1997 if (ts->ts_status & ATH9K_TXERR_FILT)
1998 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1999 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
2000 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2002 BUG_ON(nbad > nframes);
2004 tx_info->status.ampdu_len = nframes;
2005 tx_info->status.ampdu_ack_len = nframes - nbad;
2008 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2009 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2011 * If an underrun error is seen assume it as an excessive
2012 * retry only if max frame trigger level has been reached
2013 * (2 KB for single stream, and 4 KB for dual stream).
2014 * Adjust the long retry as if the frame was tried
2015 * hw->max_rate_tries times to affect how rate control updates
2016 * PER for the failed rate.
2017 * In case of congestion on the bus penalizing this type of
2018 * underruns should help hardware actually transmit new frames
2019 * successfully by eventually preferring slower rates.
2020 * This itself should also alleviate congestion on the bus.
2022 if (ieee80211_is_data(hdr->frame_control) &&
2023 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2024 ATH9K_TX_DELIM_UNDERRUN)) &&
2025 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2026 tx_info->status.rates[tx_rateindex].count =
2030 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2031 tx_info->status.rates[i].count = 0;
2032 tx_info->status.rates[i].idx = -1;
2035 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2038 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2039 struct ath_tx_status *ts, struct ath_buf *bf,
2040 struct list_head *bf_head)
2041 __releases(txq->axq_lock)
2042 __acquires(txq->axq_lock)
2047 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2048 txq->axq_tx_inprogress = false;
2049 if (bf_is_ampdu_not_probing(bf))
2050 txq->axq_ampdu_depth--;
2052 spin_unlock_bh(&txq->axq_lock);
2054 if (!bf_isampdu(bf)) {
2056 * This frame is sent out as a single frame.
2057 * Use hardware retry status for this frame.
2059 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2060 bf->bf_state.bf_type |= BUF_XRETRY;
2061 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2062 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2064 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2066 spin_lock_bh(&txq->axq_lock);
2068 if (sc->sc_flags & SC_OP_TXAGGR)
2069 ath_txq_schedule(sc, txq);
2072 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2074 struct ath_hw *ah = sc->sc_ah;
2075 struct ath_common *common = ath9k_hw_common(ah);
2076 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2077 struct list_head bf_head;
2078 struct ath_desc *ds;
2079 struct ath_tx_status ts;
2082 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2083 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2086 spin_lock_bh(&txq->axq_lock);
2088 if (list_empty(&txq->axq_q)) {
2089 txq->axq_link = NULL;
2090 if (sc->sc_flags & SC_OP_TXAGGR)
2091 ath_txq_schedule(sc, txq);
2094 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2097 * There is a race condition that a BH gets scheduled
2098 * after sw writes TxE and before hw re-load the last
2099 * descriptor to get the newly chained one.
2100 * Software must keep the last DONE descriptor as a
2101 * holding descriptor - software does so by marking
2102 * it with the STALE flag.
2107 if (list_is_last(&bf_held->list, &txq->axq_q))
2110 bf = list_entry(bf_held->list.next, struct ath_buf,
2114 lastbf = bf->bf_lastbf;
2115 ds = lastbf->bf_desc;
2117 memset(&ts, 0, sizeof(ts));
2118 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2119 if (status == -EINPROGRESS)
2122 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2125 * Remove ath_buf's of the same transmit unit from txq,
2126 * however leave the last descriptor back as the holding
2127 * descriptor for hw.
2129 lastbf->bf_stale = true;
2130 INIT_LIST_HEAD(&bf_head);
2131 if (!list_is_singular(&lastbf->list))
2132 list_cut_position(&bf_head,
2133 &txq->axq_q, lastbf->list.prev);
2136 list_del(&bf_held->list);
2137 ath_tx_return_buffer(sc, bf_held);
2140 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2142 spin_unlock_bh(&txq->axq_lock);
2145 static void ath_tx_complete_poll_work(struct work_struct *work)
2147 struct ath_softc *sc = container_of(work, struct ath_softc,
2148 tx_complete_work.work);
2149 struct ath_txq *txq;
2151 bool needreset = false;
2152 #ifdef CONFIG_ATH9K_DEBUGFS
2153 sc->tx_complete_poll_work_seen++;
2156 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2157 if (ATH_TXQ_SETUP(sc, i)) {
2158 txq = &sc->tx.txq[i];
2159 spin_lock_bh(&txq->axq_lock);
2160 if (txq->axq_depth) {
2161 if (txq->axq_tx_inprogress) {
2163 spin_unlock_bh(&txq->axq_lock);
2166 txq->axq_tx_inprogress = true;
2169 spin_unlock_bh(&txq->axq_lock);
2173 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2174 "tx hung, resetting the chip\n");
2175 spin_lock_bh(&sc->sc_pcu_lock);
2176 ath_reset(sc, true);
2177 spin_unlock_bh(&sc->sc_pcu_lock);
2180 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2181 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2186 void ath_tx_tasklet(struct ath_softc *sc)
2189 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2191 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2193 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2194 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2195 ath_tx_processq(sc, &sc->tx.txq[i]);
2199 void ath_tx_edma_tasklet(struct ath_softc *sc)
2201 struct ath_tx_status ts;
2202 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2203 struct ath_hw *ah = sc->sc_ah;
2204 struct ath_txq *txq;
2205 struct ath_buf *bf, *lastbf;
2206 struct list_head bf_head;
2210 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2211 if (status == -EINPROGRESS)
2213 if (status == -EIO) {
2214 ath_dbg(common, ATH_DBG_XMIT,
2215 "Error processing tx status\n");
2219 /* Skip beacon completions */
2220 if (ts.qid == sc->beacon.beaconq)
2223 txq = &sc->tx.txq[ts.qid];
2225 spin_lock_bh(&txq->axq_lock);
2227 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2228 spin_unlock_bh(&txq->axq_lock);
2232 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2233 struct ath_buf, list);
2234 lastbf = bf->bf_lastbf;
2236 INIT_LIST_HEAD(&bf_head);
2237 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2240 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2241 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2243 if (!list_empty(&txq->axq_q)) {
2244 struct list_head bf_q;
2246 INIT_LIST_HEAD(&bf_q);
2247 txq->axq_link = NULL;
2248 list_splice_tail_init(&txq->axq_q, &bf_q);
2249 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2253 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2254 spin_unlock_bh(&txq->axq_lock);
2262 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2264 struct ath_descdma *dd = &sc->txsdma;
2265 u8 txs_len = sc->sc_ah->caps.txs_len;
2267 dd->dd_desc_len = size * txs_len;
2268 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2269 &dd->dd_desc_paddr, GFP_KERNEL);
2276 static int ath_tx_edma_init(struct ath_softc *sc)
2280 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2282 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2283 sc->txsdma.dd_desc_paddr,
2284 ATH_TXSTATUS_RING_SIZE);
2289 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2291 struct ath_descdma *dd = &sc->txsdma;
2293 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2297 int ath_tx_init(struct ath_softc *sc, int nbufs)
2299 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2302 spin_lock_init(&sc->tx.txbuflock);
2304 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2308 "Failed to allocate tx descriptors: %d\n", error);
2312 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2313 "beacon", ATH_BCBUF, 1, 1);
2316 "Failed to allocate beacon descriptors: %d\n", error);
2320 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2322 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2323 error = ath_tx_edma_init(sc);
2335 void ath_tx_cleanup(struct ath_softc *sc)
2337 if (sc->beacon.bdma.dd_desc_len != 0)
2338 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2340 if (sc->tx.txdma.dd_desc_len != 0)
2341 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2343 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2344 ath_tx_edma_cleanup(sc);
2347 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2349 struct ath_atx_tid *tid;
2350 struct ath_atx_ac *ac;
2353 for (tidno = 0, tid = &an->tid[tidno];
2354 tidno < WME_NUM_TID;
2358 tid->seq_start = tid->seq_next = 0;
2359 tid->baw_size = WME_MAX_BA;
2360 tid->baw_head = tid->baw_tail = 0;
2362 tid->paused = false;
2363 tid->state &= ~AGGR_CLEANUP;
2364 INIT_LIST_HEAD(&tid->buf_q);
2365 acno = TID_TO_WME_AC(tidno);
2366 tid->ac = &an->ac[acno];
2367 tid->state &= ~AGGR_ADDBA_COMPLETE;
2368 tid->state &= ~AGGR_ADDBA_PROGRESS;
2371 for (acno = 0, ac = &an->ac[acno];
2372 acno < WME_NUM_AC; acno++, ac++) {
2374 ac->txq = sc->tx.txq_map[acno];
2375 INIT_LIST_HEAD(&ac->tid_q);
2379 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2381 struct ath_atx_ac *ac;
2382 struct ath_atx_tid *tid;
2383 struct ath_txq *txq;
2386 for (tidno = 0, tid = &an->tid[tidno];
2387 tidno < WME_NUM_TID; tidno++, tid++) {
2392 spin_lock_bh(&txq->axq_lock);
2395 list_del(&tid->list);
2400 list_del(&ac->list);
2401 tid->ac->sched = false;
2404 ath_tid_drain(sc, txq, tid);
2405 tid->state &= ~AGGR_ADDBA_COMPLETE;
2406 tid->state &= ~AGGR_CLEANUP;
2408 spin_unlock_bh(&txq->axq_lock);