2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
85 spin_lock_bh(&txq->axq_lock);
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
91 spin_unlock_bh(&txq->axq_lock);
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
97 struct sk_buff_head q;
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
138 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
139 seqno << IEEE80211_SEQ_SEQ_SHIFT);
142 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
145 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
146 ARRAY_SIZE(bf->rates));
149 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
154 q = skb_get_queue_mapping(skb);
155 if (txq == sc->tx.uapsdq)
156 txq = sc->tx.txq_map[q];
158 if (txq != sc->tx.txq_map[q])
161 if (WARN_ON(--txq->pending_frames < 0))
162 txq->pending_frames = 0;
165 txq->pending_frames < sc->tx.txq_max_pending[q]) {
166 ieee80211_wake_queue(sc->hw, q);
167 txq->stopped = false;
171 static struct ath_atx_tid *
172 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
174 struct ieee80211_hdr *hdr;
177 hdr = (struct ieee80211_hdr *) skb->data;
178 if (ieee80211_is_data_qos(hdr->frame_control))
179 tidno = ieee80211_get_qos_ctl(hdr)[0];
181 tidno &= IEEE80211_QOS_CTL_TID_MASK;
182 return ATH_AN_2_TID(an, tidno);
185 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
187 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
190 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 skb = __skb_dequeue(&tid->retry_q);
196 skb = __skb_dequeue(&tid->buf_q);
202 * ath_tx_tid_change_state:
203 * - clears a-mpdu flag of previous session
204 * - force sequence number allocation to fix next BlockAck Window
207 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
209 struct ath_txq *txq = tid->ac->txq;
210 struct ieee80211_tx_info *tx_info;
211 struct sk_buff *skb, *tskb;
213 struct ath_frame_info *fi;
215 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
216 fi = get_frame_info(skb);
219 tx_info = IEEE80211_SKB_CB(skb);
220 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
225 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
227 __skb_unlink(skb, &tid->buf_q);
228 ath_txq_skb_done(sc, txq, skb);
229 ieee80211_free_txskb(sc->hw, skb);
236 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
238 struct ath_txq *txq = tid->ac->txq;
241 struct list_head bf_head;
242 struct ath_tx_status ts;
243 struct ath_frame_info *fi;
244 bool sendbar = false;
246 INIT_LIST_HEAD(&bf_head);
248 memset(&ts, 0, sizeof(ts));
250 while ((skb = __skb_dequeue(&tid->retry_q))) {
251 fi = get_frame_info(skb);
254 ath_txq_skb_done(sc, txq, skb);
255 ieee80211_free_txskb(sc->hw, skb);
259 if (fi->baw_tracked) {
260 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
264 list_add_tail(&bf->list, &bf_head);
265 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
269 ath_txq_unlock(sc, txq);
270 ath_send_bar(tid, tid->seq_start);
271 ath_txq_lock(sc, txq);
275 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
280 index = ATH_BA_INDEX(tid->seq_start, seqno);
281 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
283 __clear_bit(cindex, tid->tx_buf);
285 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
286 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
287 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
288 if (tid->bar_index >= 0)
293 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
296 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
297 u16 seqno = bf->bf_state.seqno;
300 index = ATH_BA_INDEX(tid->seq_start, seqno);
301 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
302 __set_bit(cindex, tid->tx_buf);
305 if (index >= ((tid->baw_tail - tid->baw_head) &
306 (ATH_TID_MAX_BUFS - 1))) {
307 tid->baw_tail = cindex;
308 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
313 * TODO: For frame(s) that are in the retry state, we will reuse the
314 * sequence number(s) without setting the retry bit. The
315 * alternative is to give up on these and BAR the receiver's window
318 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
319 struct ath_atx_tid *tid)
324 struct list_head bf_head;
325 struct ath_tx_status ts;
326 struct ath_frame_info *fi;
328 memset(&ts, 0, sizeof(ts));
329 INIT_LIST_HEAD(&bf_head);
331 while ((skb = ath_tid_dequeue(tid))) {
332 fi = get_frame_info(skb);
336 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
340 list_add_tail(&bf->list, &bf_head);
342 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
343 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
346 tid->seq_next = tid->seq_start;
347 tid->baw_tail = tid->baw_head;
351 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
352 struct sk_buff *skb, int count)
354 struct ath_frame_info *fi = get_frame_info(skb);
355 struct ath_buf *bf = fi->bf;
356 struct ieee80211_hdr *hdr;
357 int prev = fi->retries;
359 TX_STAT_INC(txq->axq_qnum, a_retries);
360 fi->retries += count;
365 hdr = (struct ieee80211_hdr *)skb->data;
366 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
367 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
368 sizeof(*hdr), DMA_TO_DEVICE);
371 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
373 struct ath_buf *bf = NULL;
375 spin_lock_bh(&sc->tx.txbuflock);
377 if (unlikely(list_empty(&sc->tx.txbuf))) {
378 spin_unlock_bh(&sc->tx.txbuflock);
382 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
385 spin_unlock_bh(&sc->tx.txbuflock);
390 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
392 spin_lock_bh(&sc->tx.txbuflock);
393 list_add_tail(&bf->list, &sc->tx.txbuf);
394 spin_unlock_bh(&sc->tx.txbuflock);
397 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
401 tbf = ath_tx_get_buffer(sc);
405 ATH_TXBUF_RESET(tbf);
407 tbf->bf_mpdu = bf->bf_mpdu;
408 tbf->bf_buf_addr = bf->bf_buf_addr;
409 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
410 tbf->bf_state = bf->bf_state;
415 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
416 struct ath_tx_status *ts, int txok,
417 int *nframes, int *nbad)
419 struct ath_frame_info *fi;
421 u32 ba[WME_BA_BMP_SIZE >> 5];
428 isaggr = bf_isaggr(bf);
430 seq_st = ts->ts_seqnum;
431 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
435 fi = get_frame_info(bf->bf_mpdu);
436 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
439 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
447 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
448 struct ath_buf *bf, struct list_head *bf_q,
449 struct ath_tx_status *ts, int txok)
451 struct ath_node *an = NULL;
453 struct ieee80211_sta *sta;
454 struct ieee80211_hw *hw = sc->hw;
455 struct ieee80211_hdr *hdr;
456 struct ieee80211_tx_info *tx_info;
457 struct ath_atx_tid *tid = NULL;
458 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
459 struct list_head bf_head;
460 struct sk_buff_head bf_pending;
461 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
462 u32 ba[WME_BA_BMP_SIZE >> 5];
463 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
464 bool rc_update = true, isba;
465 struct ieee80211_tx_rate rates[4];
466 struct ath_frame_info *fi;
468 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
473 hdr = (struct ieee80211_hdr *)skb->data;
475 tx_info = IEEE80211_SKB_CB(skb);
477 memcpy(rates, bf->rates, sizeof(rates));
479 retries = ts->ts_longretry + 1;
480 for (i = 0; i < ts->ts_rateindex; i++)
481 retries += rates[i].count;
485 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
489 INIT_LIST_HEAD(&bf_head);
491 bf_next = bf->bf_next;
493 if (!bf->bf_stale || bf_next != NULL)
494 list_move_tail(&bf->list, &bf_head);
496 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
503 an = (struct ath_node *)sta->drv_priv;
504 tid = ath_get_skb_tid(sc, an, skb);
505 seq_first = tid->seq_start;
506 isba = ts->ts_flags & ATH9K_TX_BA;
509 * The hardware occasionally sends a tx status for the wrong TID.
510 * In this case, the BA status cannot be considered valid and all
511 * subframes need to be retransmitted
513 * Only BlockAcks have a TID and therefore normal Acks cannot be
516 if (isba && tid->tidno != ts->tid)
519 isaggr = bf_isaggr(bf);
520 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
522 if (isaggr && txok) {
523 if (ts->ts_flags & ATH9K_TX_BA) {
524 seq_st = ts->ts_seqnum;
525 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
528 * AR5416 can become deaf/mute when BA
529 * issue happens. Chip needs to be reset.
530 * But AP code may have sychronization issues
531 * when perform internal reset in this routine.
532 * Only enable reset in STA mode for now.
534 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
539 __skb_queue_head_init(&bf_pending);
541 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
543 u16 seqno = bf->bf_state.seqno;
545 txfail = txpending = sendbar = 0;
546 bf_next = bf->bf_next;
549 tx_info = IEEE80211_SKB_CB(skb);
550 fi = get_frame_info(skb);
552 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
555 * Outside of the current BlockAck window,
556 * maybe part of a previous session
559 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
560 /* transmit completion, subframe is
561 * acked by block ack */
563 } else if (!isaggr && txok) {
564 /* transmit completion */
568 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
569 if (txok || !an->sleeping)
570 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
577 bar_index = max_t(int, bar_index,
578 ATH_BA_INDEX(seq_first, seqno));
582 * Make sure the last desc is reclaimed if it
583 * not a holding desc.
585 INIT_LIST_HEAD(&bf_head);
586 if (bf_next != NULL || !bf_last->bf_stale)
587 list_move_tail(&bf->list, &bf_head);
591 * complete the acked-ones/xretried ones; update
594 ath_tx_update_baw(sc, tid, seqno);
596 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
597 memcpy(tx_info->control.rates, rates, sizeof(rates));
598 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
602 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
605 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
606 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
607 ieee80211_sta_eosp(sta);
609 /* retry the un-acked ones */
610 if (bf->bf_next == NULL && bf_last->bf_stale) {
613 tbf = ath_clone_txbuf(sc, bf_last);
615 * Update tx baw and complete the
616 * frame with failed status if we
620 ath_tx_update_baw(sc, tid, seqno);
622 ath_tx_complete_buf(sc, bf, txq,
624 bar_index = max_t(int, bar_index,
625 ATH_BA_INDEX(seq_first, seqno));
633 * Put this buffer to the temporary pending
634 * queue to retain ordering
636 __skb_queue_tail(&bf_pending, skb);
642 /* prepend un-acked frames to the beginning of the pending frame queue */
643 if (!skb_queue_empty(&bf_pending)) {
645 ieee80211_sta_set_buffered(sta, tid->tidno, true);
647 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
649 ath_tx_queue_tid(txq, tid);
651 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
652 tid->ac->clear_ps_filter = true;
656 if (bar_index >= 0) {
657 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
659 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
660 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
662 ath_txq_unlock(sc, txq);
663 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
664 ath_txq_lock(sc, txq);
670 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
673 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
675 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
676 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
679 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
680 struct ath_tx_status *ts, struct ath_buf *bf,
681 struct list_head *bf_head)
683 struct ieee80211_tx_info *info;
686 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
687 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
688 txq->axq_tx_inprogress = false;
691 if (bf_is_ampdu_not_probing(bf))
692 txq->axq_ampdu_depth--;
694 if (!bf_isampdu(bf)) {
696 info = IEEE80211_SKB_CB(bf->bf_mpdu);
697 memcpy(info->control.rates, bf->rates,
698 sizeof(info->control.rates));
699 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
701 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
703 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
706 ath_txq_schedule(sc, txq);
709 static bool ath_lookup_legacy(struct ath_buf *bf)
712 struct ieee80211_tx_info *tx_info;
713 struct ieee80211_tx_rate *rates;
717 tx_info = IEEE80211_SKB_CB(skb);
718 rates = tx_info->control.rates;
720 for (i = 0; i < 4; i++) {
721 if (!rates[i].count || rates[i].idx < 0)
724 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
731 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
732 struct ath_atx_tid *tid)
735 struct ieee80211_tx_info *tx_info;
736 struct ieee80211_tx_rate *rates;
737 u32 max_4ms_framelen, frmlen;
738 u16 aggr_limit, bt_aggr_limit, legacy = 0;
739 int q = tid->ac->txq->mac80211_qnum;
743 tx_info = IEEE80211_SKB_CB(skb);
747 * Find the lowest frame length among the rate series that will have a
748 * 4ms (or TXOP limited) transmit duration.
750 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
752 for (i = 0; i < 4; i++) {
758 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
763 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
768 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
771 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
772 max_4ms_framelen = min(max_4ms_framelen, frmlen);
776 * limit aggregate size by the minimum rate if rate selected is
777 * not a probe rate, if rate selected is a probe rate then
778 * avoid aggregation of this packet.
780 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
783 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
786 * Override the default aggregation limit for BTCOEX.
788 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
790 aggr_limit = bt_aggr_limit;
793 * h/w can accept aggregates up to 16 bit lengths (65535).
794 * The IE, however can hold up to 65536, which shows up here
795 * as zero. Ignore 65536 since we are constrained by hw.
797 if (tid->an->maxampdu)
798 aggr_limit = min(aggr_limit, tid->an->maxampdu);
804 * Returns the number of delimiters to be added to
805 * meet the minimum required mpdudensity.
807 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
808 struct ath_buf *bf, u16 frmlen,
811 #define FIRST_DESC_NDELIMS 60
812 u32 nsymbits, nsymbols;
815 int width, streams, half_gi, ndelim, mindelim;
816 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
818 /* Select standard number of delimiters based on frame length alone */
819 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
822 * If encryption enabled, hardware requires some more padding between
824 * TODO - this could be improved to be dependent on the rate.
825 * The hardware can keep up at lower rates, but not higher rates
827 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
828 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
829 ndelim += ATH_AGGR_ENCRYPTDELIM;
832 * Add delimiter when using RTS/CTS with aggregation
833 * and non enterprise AR9003 card
835 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
836 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
837 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
840 * Convert desired mpdu density from microeconds to bytes based
841 * on highest rate in rate series (i.e. first rate) to determine
842 * required minimum length for subframe. Take into account
843 * whether high rate is 20 or 40Mhz and half or full GI.
845 * If there is no mpdu density restriction, no further calculation
849 if (tid->an->mpdudensity == 0)
852 rix = bf->rates[0].idx;
853 flags = bf->rates[0].flags;
854 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
855 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
858 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
860 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
865 streams = HT_RC_2_STREAMS(rix);
866 nsymbits = bits_per_symbol[rix % 8][width] * streams;
867 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
869 if (frmlen < minlen) {
870 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
871 ndelim = max(mindelim, ndelim);
877 static struct ath_buf *
878 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
879 struct ath_atx_tid *tid, struct sk_buff_head **q)
881 struct ieee80211_tx_info *tx_info;
882 struct ath_frame_info *fi;
889 if (skb_queue_empty(*q))
896 fi = get_frame_info(skb);
899 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
902 __skb_unlink(skb, *q);
903 ath_txq_skb_done(sc, txq, skb);
904 ieee80211_free_txskb(sc->hw, skb);
911 tx_info = IEEE80211_SKB_CB(skb);
912 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
913 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
914 bf->bf_state.bf_type = 0;
918 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
919 seqno = bf->bf_state.seqno;
921 /* do not step over block-ack window */
922 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
925 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
926 struct ath_tx_status ts = {};
927 struct list_head bf_head;
929 INIT_LIST_HEAD(&bf_head);
930 list_add(&bf->list, &bf_head);
931 __skb_unlink(skb, *q);
932 ath_tx_update_baw(sc, tid, seqno);
933 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
944 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
945 struct ath_atx_tid *tid, struct list_head *bf_q,
946 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
949 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
950 struct ath_buf *bf = bf_first, *bf_prev = NULL;
951 int nframes = 0, ndelim;
952 u16 aggr_limit = 0, al = 0, bpad = 0,
953 al_delta, h_baw = tid->baw_size / 2;
954 struct ieee80211_tx_info *tx_info;
955 struct ath_frame_info *fi;
960 aggr_limit = ath_lookup_rate(sc, bf, tid);
964 fi = get_frame_info(skb);
966 /* do not exceed aggregation limit */
967 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
969 if (aggr_limit < al + bpad + al_delta ||
970 ath_lookup_legacy(bf) || nframes >= h_baw)
973 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
974 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
975 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
979 /* add padding for previous frame to aggregation length */
980 al += bpad + al_delta;
983 * Get the delimiters needed to meet the MPDU
984 * density for this node.
986 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
988 bpad = PADBYTES(al_delta) + (ndelim << 2);
993 /* link buffers of this frame to the aggregate */
994 if (!fi->baw_tracked)
995 ath_tx_addto_baw(sc, tid, bf);
996 bf->bf_state.ndelim = ndelim;
998 __skb_unlink(skb, tid_q);
999 list_add_tail(&bf->list, bf_q);
1001 bf_prev->bf_next = bf;
1005 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1010 } while (ath_tid_has_buffered(tid));
1013 bf->bf_lastbf = bf_prev;
1015 if (bf == bf_prev) {
1016 al = get_frame_info(bf->bf_mpdu)->framelen;
1017 bf->bf_state.bf_type = BUF_AMPDU;
1019 TX_STAT_INC(txq->axq_qnum, a_aggr);
1030 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1031 * width - 0 for 20 MHz, 1 for 40 MHz
1032 * half_gi - to use 4us v/s 3.6 us for symbol time
1034 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1035 int width, int half_gi, bool shortPreamble)
1037 u32 nbits, nsymbits, duration, nsymbols;
1040 /* find number of symbols: PLCP + data */
1041 streams = HT_RC_2_STREAMS(rix);
1042 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1043 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1044 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1047 duration = SYMBOL_TIME(nsymbols);
1049 duration = SYMBOL_TIME_HALFGI(nsymbols);
1051 /* addup duration for legacy/ht training and signal fields */
1052 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1057 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1059 int streams = HT_RC_2_STREAMS(mcs);
1063 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1064 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1065 bits -= OFDM_PLCP_BITS;
1067 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1074 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1076 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1079 /* 4ms is the default (and maximum) duration */
1080 if (!txop || txop > 4096)
1083 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1084 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1085 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1086 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1087 for (mcs = 0; mcs < 32; mcs++) {
1088 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1089 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1090 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1091 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1095 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1096 struct ath_tx_info *info, int len, bool rts)
1098 struct ath_hw *ah = sc->sc_ah;
1099 struct sk_buff *skb;
1100 struct ieee80211_tx_info *tx_info;
1101 struct ieee80211_tx_rate *rates;
1102 const struct ieee80211_rate *rate;
1103 struct ieee80211_hdr *hdr;
1104 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1105 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1110 tx_info = IEEE80211_SKB_CB(skb);
1112 hdr = (struct ieee80211_hdr *)skb->data;
1114 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1115 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1116 info->rtscts_rate = fi->rtscts_rate;
1118 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1119 bool is_40, is_sgi, is_sp;
1122 if (!rates[i].count || (rates[i].idx < 0))
1126 info->rates[i].Tries = rates[i].count;
1129 * Handle RTS threshold for unaggregated HT frames.
1131 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1132 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1133 unlikely(rts_thresh != (u32) -1)) {
1134 if (!rts_thresh || (len > rts_thresh))
1138 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1139 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1140 info->flags |= ATH9K_TXDESC_RTSENA;
1141 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1143 info->flags |= ATH9K_TXDESC_CTSENA;
1146 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1147 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1148 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1149 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1151 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1152 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1153 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1155 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1157 info->rates[i].Rate = rix | 0x80;
1158 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1159 ah->txchainmask, info->rates[i].Rate);
1160 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1161 is_40, is_sgi, is_sp);
1162 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1163 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1168 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1169 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1170 !(rate->flags & IEEE80211_RATE_ERP_G))
1171 phy = WLAN_RC_PHY_CCK;
1173 phy = WLAN_RC_PHY_OFDM;
1175 info->rates[i].Rate = rate->hw_value;
1176 if (rate->hw_value_short) {
1177 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1178 info->rates[i].Rate |= rate->hw_value_short;
1183 if (bf->bf_state.bfs_paprd)
1184 info->rates[i].ChSel = ah->txchainmask;
1186 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1187 ah->txchainmask, info->rates[i].Rate);
1189 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1190 phy, rate->bitrate * 100, len, rix, is_sp);
1193 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1194 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1195 info->flags &= ~ATH9K_TXDESC_RTSENA;
1197 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1198 if (info->flags & ATH9K_TXDESC_RTSENA)
1199 info->flags &= ~ATH9K_TXDESC_CTSENA;
1202 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1204 struct ieee80211_hdr *hdr;
1205 enum ath9k_pkt_type htype;
1208 hdr = (struct ieee80211_hdr *)skb->data;
1209 fc = hdr->frame_control;
1211 if (ieee80211_is_beacon(fc))
1212 htype = ATH9K_PKT_TYPE_BEACON;
1213 else if (ieee80211_is_probe_resp(fc))
1214 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1215 else if (ieee80211_is_atim(fc))
1216 htype = ATH9K_PKT_TYPE_ATIM;
1217 else if (ieee80211_is_pspoll(fc))
1218 htype = ATH9K_PKT_TYPE_PSPOLL;
1220 htype = ATH9K_PKT_TYPE_NORMAL;
1225 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1226 struct ath_txq *txq, int len)
1228 struct ath_hw *ah = sc->sc_ah;
1229 struct ath_buf *bf_first = NULL;
1230 struct ath_tx_info info;
1231 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1234 memset(&info, 0, sizeof(info));
1235 info.is_first = true;
1236 info.is_last = true;
1237 info.txpower = MAX_RATE_POWER;
1238 info.qcu = txq->axq_qnum;
1241 struct sk_buff *skb = bf->bf_mpdu;
1242 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1243 struct ath_frame_info *fi = get_frame_info(skb);
1244 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1246 info.type = get_hw_packet_type(skb);
1248 info.link = bf->bf_next->bf_daddr;
1255 info.flags = ATH9K_TXDESC_INTREQ;
1256 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1257 txq == sc->tx.uapsdq)
1258 info.flags |= ATH9K_TXDESC_CLRDMASK;
1260 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1261 info.flags |= ATH9K_TXDESC_NOACK;
1262 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1263 info.flags |= ATH9K_TXDESC_LDPC;
1265 if (bf->bf_state.bfs_paprd)
1266 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1267 ATH9K_TXDESC_PAPRD_S;
1270 * mac80211 doesn't handle RTS threshold for HT because
1271 * the decision has to be taken based on AMPDU length
1272 * and aggregation is done entirely inside ath9k.
1273 * Set the RTS/CTS flag for the first subframe based
1276 if (aggr && (bf == bf_first) &&
1277 unlikely(rts_thresh != (u32) -1)) {
1279 * "len" is the size of the entire AMPDU.
1281 if (!rts_thresh || (len > rts_thresh))
1284 ath_buf_set_rate(sc, bf, &info, len, rts);
1287 info.buf_addr[0] = bf->bf_buf_addr;
1288 info.buf_len[0] = skb->len;
1289 info.pkt_len = fi->framelen;
1290 info.keyix = fi->keyix;
1291 info.keytype = fi->keytype;
1295 info.aggr = AGGR_BUF_FIRST;
1296 else if (bf == bf_first->bf_lastbf)
1297 info.aggr = AGGR_BUF_LAST;
1299 info.aggr = AGGR_BUF_MIDDLE;
1301 info.ndelim = bf->bf_state.ndelim;
1302 info.aggr_len = len;
1305 if (bf == bf_first->bf_lastbf)
1308 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1314 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1315 struct ath_atx_tid *tid, struct list_head *bf_q,
1316 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1318 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1319 struct sk_buff *skb;
1323 struct ieee80211_tx_info *tx_info;
1327 __skb_unlink(skb, tid_q);
1328 list_add_tail(&bf->list, bf_q);
1330 bf_prev->bf_next = bf;
1336 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1340 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1341 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1344 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1348 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1349 struct ath_atx_tid *tid, bool *stop)
1352 struct ieee80211_tx_info *tx_info;
1353 struct sk_buff_head *tid_q;
1354 struct list_head bf_q;
1356 bool aggr, last = true;
1358 if (!ath_tid_has_buffered(tid))
1361 INIT_LIST_HEAD(&bf_q);
1363 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1367 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1368 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1369 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1370 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1375 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1377 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1380 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1382 if (list_empty(&bf_q))
1385 if (tid->ac->clear_ps_filter) {
1386 tid->ac->clear_ps_filter = false;
1387 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1390 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1391 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1395 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1398 struct ath_atx_tid *txtid;
1399 struct ath_node *an;
1402 an = (struct ath_node *)sta->drv_priv;
1403 txtid = ATH_AN_2_TID(an, tid);
1405 /* update ampdu factor/density, they may have changed. This may happen
1406 * in HT IBSS when a beacon with HT-info is received after the station
1407 * has already been added.
1409 if (sta->ht_cap.ht_supported) {
1410 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1411 sta->ht_cap.ampdu_factor);
1412 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1413 an->mpdudensity = density;
1416 /* force sequence number allocation for pending frames */
1417 ath_tx_tid_change_state(sc, txtid);
1419 txtid->active = true;
1420 txtid->paused = true;
1421 *ssn = txtid->seq_start = txtid->seq_next;
1422 txtid->bar_index = -1;
1424 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1425 txtid->baw_head = txtid->baw_tail = 0;
1430 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1432 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1433 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1434 struct ath_txq *txq = txtid->ac->txq;
1436 ath_txq_lock(sc, txq);
1437 txtid->active = false;
1438 txtid->paused = false;
1439 ath_tx_flush_tid(sc, txtid);
1440 ath_tx_tid_change_state(sc, txtid);
1441 ath_txq_unlock_complete(sc, txq);
1444 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1445 struct ath_node *an)
1447 struct ath_atx_tid *tid;
1448 struct ath_atx_ac *ac;
1449 struct ath_txq *txq;
1453 for (tidno = 0, tid = &an->tid[tidno];
1454 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1462 ath_txq_lock(sc, txq);
1464 buffered = ath_tid_has_buffered(tid);
1467 list_del(&tid->list);
1471 list_del(&ac->list);
1474 ath_txq_unlock(sc, txq);
1476 ieee80211_sta_set_buffered(sta, tidno, buffered);
1480 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1482 struct ath_atx_tid *tid;
1483 struct ath_atx_ac *ac;
1484 struct ath_txq *txq;
1487 for (tidno = 0, tid = &an->tid[tidno];
1488 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1493 ath_txq_lock(sc, txq);
1494 ac->clear_ps_filter = true;
1496 if (!tid->paused && ath_tid_has_buffered(tid)) {
1497 ath_tx_queue_tid(txq, tid);
1498 ath_txq_schedule(sc, txq);
1501 ath_txq_unlock_complete(sc, txq);
1505 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1508 struct ath_atx_tid *tid;
1509 struct ath_node *an;
1510 struct ath_txq *txq;
1512 an = (struct ath_node *)sta->drv_priv;
1513 tid = ATH_AN_2_TID(an, tidno);
1516 ath_txq_lock(sc, txq);
1518 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1519 tid->paused = false;
1521 if (ath_tid_has_buffered(tid)) {
1522 ath_tx_queue_tid(txq, tid);
1523 ath_txq_schedule(sc, txq);
1526 ath_txq_unlock_complete(sc, txq);
1529 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1530 struct ieee80211_sta *sta,
1531 u16 tids, int nframes,
1532 enum ieee80211_frame_release_type reason,
1535 struct ath_softc *sc = hw->priv;
1536 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1537 struct ath_txq *txq = sc->tx.uapsdq;
1538 struct ieee80211_tx_info *info;
1539 struct list_head bf_q;
1540 struct ath_buf *bf_tail = NULL, *bf;
1541 struct sk_buff_head *tid_q;
1545 INIT_LIST_HEAD(&bf_q);
1546 for (i = 0; tids && nframes; i++, tids >>= 1) {
1547 struct ath_atx_tid *tid;
1552 tid = ATH_AN_2_TID(an, i);
1556 ath_txq_lock(sc, tid->ac->txq);
1557 while (nframes > 0) {
1558 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1562 __skb_unlink(bf->bf_mpdu, tid_q);
1563 list_add_tail(&bf->list, &bf_q);
1564 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1565 ath_tx_addto_baw(sc, tid, bf);
1566 bf->bf_state.bf_type &= ~BUF_AGGR;
1568 bf_tail->bf_next = bf;
1573 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1575 if (!ath_tid_has_buffered(tid))
1576 ieee80211_sta_set_buffered(an->sta, i, false);
1578 ath_txq_unlock_complete(sc, tid->ac->txq);
1581 if (list_empty(&bf_q))
1584 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1585 info->flags |= IEEE80211_TX_STATUS_EOSP;
1587 bf = list_first_entry(&bf_q, struct ath_buf, list);
1588 ath_txq_lock(sc, txq);
1589 ath_tx_fill_desc(sc, bf, txq, 0);
1590 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1591 ath_txq_unlock(sc, txq);
1594 /********************/
1595 /* Queue Management */
1596 /********************/
1598 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1600 struct ath_hw *ah = sc->sc_ah;
1601 struct ath9k_tx_queue_info qi;
1602 static const int subtype_txq_to_hwq[] = {
1603 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1604 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1605 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1606 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1610 memset(&qi, 0, sizeof(qi));
1611 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1612 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1613 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1614 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1615 qi.tqi_physCompBuf = 0;
1618 * Enable interrupts only for EOL and DESC conditions.
1619 * We mark tx descriptors to receive a DESC interrupt
1620 * when a tx queue gets deep; otherwise waiting for the
1621 * EOL to reap descriptors. Note that this is done to
1622 * reduce interrupt load and this only defers reaping
1623 * descriptors, never transmitting frames. Aside from
1624 * reducing interrupts this also permits more concurrency.
1625 * The only potential downside is if the tx queue backs
1626 * up in which case the top half of the kernel may backup
1627 * due to a lack of tx descriptors.
1629 * The UAPSD queue is an exception, since we take a desc-
1630 * based intr on the EOSP frames.
1632 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1633 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1635 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1636 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1638 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1639 TXQ_FLAG_TXDESCINT_ENABLE;
1641 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1642 if (axq_qnum == -1) {
1644 * NB: don't print a message, this happens
1645 * normally on parts with too few tx queues
1649 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1650 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1652 txq->axq_qnum = axq_qnum;
1653 txq->mac80211_qnum = -1;
1654 txq->axq_link = NULL;
1655 __skb_queue_head_init(&txq->complete_q);
1656 INIT_LIST_HEAD(&txq->axq_q);
1657 INIT_LIST_HEAD(&txq->axq_acq);
1658 spin_lock_init(&txq->axq_lock);
1660 txq->axq_ampdu_depth = 0;
1661 txq->axq_tx_inprogress = false;
1662 sc->tx.txqsetup |= 1<<axq_qnum;
1664 txq->txq_headidx = txq->txq_tailidx = 0;
1665 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1666 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1668 return &sc->tx.txq[axq_qnum];
1671 int ath_txq_update(struct ath_softc *sc, int qnum,
1672 struct ath9k_tx_queue_info *qinfo)
1674 struct ath_hw *ah = sc->sc_ah;
1676 struct ath9k_tx_queue_info qi;
1678 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1680 ath9k_hw_get_txq_props(ah, qnum, &qi);
1681 qi.tqi_aifs = qinfo->tqi_aifs;
1682 qi.tqi_cwmin = qinfo->tqi_cwmin;
1683 qi.tqi_cwmax = qinfo->tqi_cwmax;
1684 qi.tqi_burstTime = qinfo->tqi_burstTime;
1685 qi.tqi_readyTime = qinfo->tqi_readyTime;
1687 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1688 ath_err(ath9k_hw_common(sc->sc_ah),
1689 "Unable to update hardware queue %u!\n", qnum);
1692 ath9k_hw_resettxqueue(ah, qnum);
1698 int ath_cabq_update(struct ath_softc *sc)
1700 struct ath9k_tx_queue_info qi;
1701 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1702 int qnum = sc->beacon.cabq->axq_qnum;
1704 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1706 * Ensure the readytime % is within the bounds.
1708 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1709 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1710 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1711 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1713 qi.tqi_readyTime = (cur_conf->beacon_interval *
1714 sc->config.cabqReadytime) / 100;
1715 ath_txq_update(sc, qnum, &qi);
1720 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1721 struct list_head *list)
1723 struct ath_buf *bf, *lastbf;
1724 struct list_head bf_head;
1725 struct ath_tx_status ts;
1727 memset(&ts, 0, sizeof(ts));
1728 ts.ts_status = ATH9K_TX_FLUSH;
1729 INIT_LIST_HEAD(&bf_head);
1731 while (!list_empty(list)) {
1732 bf = list_first_entry(list, struct ath_buf, list);
1735 list_del(&bf->list);
1737 ath_tx_return_buffer(sc, bf);
1741 lastbf = bf->bf_lastbf;
1742 list_cut_position(&bf_head, list, &lastbf->list);
1743 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1748 * Drain a given TX queue (could be Beacon or Data)
1750 * This assumes output has been stopped and
1751 * we do not need to block ath_tx_tasklet.
1753 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1755 ath_txq_lock(sc, txq);
1757 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1758 int idx = txq->txq_tailidx;
1760 while (!list_empty(&txq->txq_fifo[idx])) {
1761 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1763 INCR(idx, ATH_TXFIFO_DEPTH);
1765 txq->txq_tailidx = idx;
1768 txq->axq_link = NULL;
1769 txq->axq_tx_inprogress = false;
1770 ath_drain_txq_list(sc, txq, &txq->axq_q);
1772 ath_txq_unlock_complete(sc, txq);
1775 bool ath_drain_all_txq(struct ath_softc *sc)
1777 struct ath_hw *ah = sc->sc_ah;
1778 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1779 struct ath_txq *txq;
1783 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1786 ath9k_hw_abort_tx_dma(ah);
1788 /* Check if any queue remains active */
1789 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1790 if (!ATH_TXQ_SETUP(sc, i))
1793 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1798 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1800 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1801 if (!ATH_TXQ_SETUP(sc, i))
1805 * The caller will resume queues with ieee80211_wake_queues.
1806 * Mark the queue as not stopped to prevent ath_tx_complete
1807 * from waking the queue too early.
1809 txq = &sc->tx.txq[i];
1810 txq->stopped = false;
1811 ath_draintxq(sc, txq);
1817 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1819 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1820 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1823 /* For each axq_acq entry, for each tid, try to schedule packets
1824 * for transmit until ampdu_depth has reached min Q depth.
1826 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1828 struct ath_atx_ac *ac, *last_ac;
1829 struct ath_atx_tid *tid, *last_tid;
1832 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1833 list_empty(&txq->axq_acq))
1838 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1839 while (!list_empty(&txq->axq_acq)) {
1842 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1843 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1844 list_del(&ac->list);
1847 while (!list_empty(&ac->tid_q)) {
1849 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1851 list_del(&tid->list);
1857 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1861 * add tid to round-robin queue if more frames
1862 * are pending for the tid
1864 if (ath_tid_has_buffered(tid))
1865 ath_tx_queue_tid(txq, tid);
1867 if (stop || tid == last_tid)
1871 if (!list_empty(&ac->tid_q) && !ac->sched) {
1873 list_add_tail(&ac->list, &txq->axq_acq);
1879 if (ac == last_ac) {
1884 last_ac = list_entry(txq->axq_acq.prev,
1885 struct ath_atx_ac, list);
1897 * Insert a chain of ath_buf (descriptors) on a txq and
1898 * assume the descriptors are already chained together by caller.
1900 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1901 struct list_head *head, bool internal)
1903 struct ath_hw *ah = sc->sc_ah;
1904 struct ath_common *common = ath9k_hw_common(ah);
1905 struct ath_buf *bf, *bf_last;
1906 bool puttxbuf = false;
1910 * Insert the frame on the outbound list and
1911 * pass it on to the hardware.
1914 if (list_empty(head))
1917 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1918 bf = list_first_entry(head, struct ath_buf, list);
1919 bf_last = list_entry(head->prev, struct ath_buf, list);
1921 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1922 txq->axq_qnum, txq->axq_depth);
1924 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1925 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1926 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1929 list_splice_tail_init(head, &txq->axq_q);
1931 if (txq->axq_link) {
1932 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1933 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1934 txq->axq_qnum, txq->axq_link,
1935 ito64(bf->bf_daddr), bf->bf_desc);
1939 txq->axq_link = bf_last->bf_desc;
1943 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1944 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1945 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1946 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1950 TX_STAT_INC(txq->axq_qnum, txstart);
1951 ath9k_hw_txstart(ah, txq->axq_qnum);
1957 if (bf_is_ampdu_not_probing(bf))
1958 txq->axq_ampdu_depth++;
1960 bf = bf->bf_lastbf->bf_next;
1965 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1966 struct ath_atx_tid *tid, struct sk_buff *skb)
1968 struct ath_frame_info *fi = get_frame_info(skb);
1969 struct list_head bf_head;
1974 INIT_LIST_HEAD(&bf_head);
1975 list_add_tail(&bf->list, &bf_head);
1976 bf->bf_state.bf_type = 0;
1980 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1981 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1982 TX_STAT_INC(txq->axq_qnum, queued);
1985 static void setup_frame_info(struct ieee80211_hw *hw,
1986 struct ieee80211_sta *sta,
1987 struct sk_buff *skb,
1990 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1991 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1992 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1993 const struct ieee80211_rate *rate;
1994 struct ath_frame_info *fi = get_frame_info(skb);
1995 struct ath_node *an = NULL;
1996 enum ath9k_key_type keytype;
1997 bool short_preamble = false;
2000 * We check if Short Preamble is needed for the CTS rate by
2001 * checking the BSS's global flag.
2002 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2004 if (tx_info->control.vif &&
2005 tx_info->control.vif->bss_conf.use_short_preamble)
2006 short_preamble = true;
2008 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2009 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2012 an = (struct ath_node *) sta->drv_priv;
2014 memset(fi, 0, sizeof(*fi));
2016 fi->keyix = hw_key->hw_key_idx;
2017 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2018 fi->keyix = an->ps_key;
2020 fi->keyix = ATH9K_TXKEYIX_INVALID;
2021 fi->keytype = keytype;
2022 fi->framelen = framelen;
2023 fi->rtscts_rate = rate->hw_value;
2025 fi->rtscts_rate |= rate->hw_value_short;
2028 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2030 struct ath_hw *ah = sc->sc_ah;
2031 struct ath9k_channel *curchan = ah->curchan;
2033 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2034 (curchan->channelFlags & CHANNEL_5GHZ) &&
2035 (chainmask == 0x7) && (rate < 0x90))
2037 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2045 * Assign a descriptor (and sequence number if necessary,
2046 * and map buffer for DMA. Frees skb on error
2048 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2049 struct ath_txq *txq,
2050 struct ath_atx_tid *tid,
2051 struct sk_buff *skb)
2053 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2054 struct ath_frame_info *fi = get_frame_info(skb);
2055 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2060 bf = ath_tx_get_buffer(sc);
2062 ath_dbg(common, XMIT, "TX buffers are full\n");
2066 ATH_TXBUF_RESET(bf);
2069 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2070 seqno = tid->seq_next;
2071 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2074 hdr->seq_ctrl |= cpu_to_le16(fragno);
2076 if (!ieee80211_has_morefrags(hdr->frame_control))
2077 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2079 bf->bf_state.seqno = seqno;
2084 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2085 skb->len, DMA_TO_DEVICE);
2086 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2088 bf->bf_buf_addr = 0;
2089 ath_err(ath9k_hw_common(sc->sc_ah),
2090 "dma_mapping_error() on TX\n");
2091 ath_tx_return_buffer(sc, bf);
2100 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2101 struct ath_tx_control *txctl)
2103 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2104 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2105 struct ieee80211_sta *sta = txctl->sta;
2106 struct ieee80211_vif *vif = info->control.vif;
2107 struct ath_softc *sc = hw->priv;
2108 int frmlen = skb->len + FCS_LEN;
2109 int padpos, padsize;
2111 /* NOTE: sta can be NULL according to net/mac80211.h */
2113 txctl->an = (struct ath_node *)sta->drv_priv;
2115 if (info->control.hw_key)
2116 frmlen += info->control.hw_key->icv_len;
2119 * As a temporary workaround, assign seq# here; this will likely need
2120 * to be cleaned up to work better with Beacon transmission and virtual
2123 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2124 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2125 sc->tx.seq_no += 0x10;
2126 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2127 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2130 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2131 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2132 !ieee80211_is_data(hdr->frame_control))
2133 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2135 /* Add the padding after the header if this is not already done */
2136 padpos = ieee80211_hdrlen(hdr->frame_control);
2137 padsize = padpos & 3;
2138 if (padsize && skb->len > padpos) {
2139 if (skb_headroom(skb) < padsize)
2142 skb_push(skb, padsize);
2143 memmove(skb->data, skb->data + padsize, padpos);
2146 setup_frame_info(hw, sta, skb, frmlen);
2151 /* Upon failure caller should free skb */
2152 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2153 struct ath_tx_control *txctl)
2155 struct ieee80211_hdr *hdr;
2156 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2157 struct ieee80211_sta *sta = txctl->sta;
2158 struct ieee80211_vif *vif = info->control.vif;
2159 struct ath_softc *sc = hw->priv;
2160 struct ath_txq *txq = txctl->txq;
2161 struct ath_atx_tid *tid = NULL;
2166 ret = ath_tx_prepare(hw, skb, txctl);
2170 hdr = (struct ieee80211_hdr *) skb->data;
2172 * At this point, the vif, hw_key and sta pointers in the tx control
2173 * info are no longer valid (overwritten by the ath_frame_info data.
2176 q = skb_get_queue_mapping(skb);
2178 ath_txq_lock(sc, txq);
2179 if (txq == sc->tx.txq_map[q] &&
2180 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2182 ieee80211_stop_queue(sc->hw, q);
2183 txq->stopped = true;
2186 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2187 ath_txq_unlock(sc, txq);
2188 txq = sc->tx.uapsdq;
2189 ath_txq_lock(sc, txq);
2190 } else if (txctl->an &&
2191 ieee80211_is_data_present(hdr->frame_control)) {
2192 tid = ath_get_skb_tid(sc, txctl->an, skb);
2194 WARN_ON(tid->ac->txq != txctl->txq);
2196 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2197 tid->ac->clear_ps_filter = true;
2200 * Add this frame to software queue for scheduling later
2203 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2204 __skb_queue_tail(&tid->buf_q, skb);
2205 if (!txctl->an->sleeping)
2206 ath_tx_queue_tid(txq, tid);
2208 ath_txq_schedule(sc, txq);
2212 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2214 ath_txq_skb_done(sc, txq, skb);
2216 dev_kfree_skb_any(skb);
2218 ieee80211_free_txskb(sc->hw, skb);
2222 bf->bf_state.bfs_paprd = txctl->paprd;
2225 bf->bf_state.bfs_paprd_timestamp = jiffies;
2227 ath_set_rates(vif, sta, bf);
2228 ath_tx_send_normal(sc, txq, tid, skb);
2231 ath_txq_unlock(sc, txq);
2236 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2237 struct sk_buff *skb)
2239 struct ath_softc *sc = hw->priv;
2240 struct ath_tx_control txctl = {
2241 .txq = sc->beacon.cabq
2243 struct ath_tx_info info = {};
2244 struct ieee80211_hdr *hdr;
2245 struct ath_buf *bf_tail = NULL;
2252 sc->cur_beacon_conf.beacon_interval * 1000 *
2253 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2256 struct ath_frame_info *fi = get_frame_info(skb);
2258 if (ath_tx_prepare(hw, skb, &txctl))
2261 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2266 ath_set_rates(vif, NULL, bf);
2267 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2268 duration += info.rates[0].PktDuration;
2270 bf_tail->bf_next = bf;
2272 list_add_tail(&bf->list, &bf_q);
2276 if (duration > max_duration)
2279 skb = ieee80211_get_buffered_bc(hw, vif);
2283 ieee80211_free_txskb(hw, skb);
2285 if (list_empty(&bf_q))
2288 bf = list_first_entry(&bf_q, struct ath_buf, list);
2289 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2291 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2292 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2293 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2294 sizeof(*hdr), DMA_TO_DEVICE);
2297 ath_txq_lock(sc, txctl.txq);
2298 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2299 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2300 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2301 ath_txq_unlock(sc, txctl.txq);
2308 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2309 int tx_flags, struct ath_txq *txq)
2311 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2312 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2313 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2314 int padpos, padsize;
2315 unsigned long flags;
2317 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2319 if (sc->sc_ah->caldata)
2320 sc->sc_ah->caldata->paprd_packet_sent = true;
2322 if (!(tx_flags & ATH_TX_ERROR))
2323 /* Frame was ACKed */
2324 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2326 padpos = ieee80211_hdrlen(hdr->frame_control);
2327 padsize = padpos & 3;
2328 if (padsize && skb->len>padpos+padsize) {
2330 * Remove MAC header padding before giving the frame back to
2333 memmove(skb->data + padsize, skb->data, padpos);
2334 skb_pull(skb, padsize);
2337 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2338 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2339 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2341 "Going back to sleep after having received TX status (0x%lx)\n",
2342 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2344 PS_WAIT_FOR_PSPOLL_DATA |
2345 PS_WAIT_FOR_TX_ACK));
2347 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2349 __skb_queue_tail(&txq->complete_q, skb);
2350 ath_txq_skb_done(sc, txq, skb);
2353 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2354 struct ath_txq *txq, struct list_head *bf_q,
2355 struct ath_tx_status *ts, int txok)
2357 struct sk_buff *skb = bf->bf_mpdu;
2358 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2359 unsigned long flags;
2363 tx_flags |= ATH_TX_ERROR;
2365 if (ts->ts_status & ATH9K_TXERR_FILT)
2366 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2368 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2369 bf->bf_buf_addr = 0;
2371 if (bf->bf_state.bfs_paprd) {
2372 if (time_after(jiffies,
2373 bf->bf_state.bfs_paprd_timestamp +
2374 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2375 dev_kfree_skb_any(skb);
2377 complete(&sc->paprd_complete);
2379 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2380 ath_tx_complete(sc, skb, tx_flags, txq);
2382 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2383 * accidentally reference it later.
2388 * Return the list of ath_buf of this mpdu to free queue
2390 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2391 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2392 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2395 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2396 struct ath_tx_status *ts, int nframes, int nbad,
2399 struct sk_buff *skb = bf->bf_mpdu;
2400 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2401 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2402 struct ieee80211_hw *hw = sc->hw;
2403 struct ath_hw *ah = sc->sc_ah;
2407 tx_info->status.ack_signal = ts->ts_rssi;
2409 tx_rateindex = ts->ts_rateindex;
2410 WARN_ON(tx_rateindex >= hw->max_rates);
2412 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2413 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2415 BUG_ON(nbad > nframes);
2417 tx_info->status.ampdu_len = nframes;
2418 tx_info->status.ampdu_ack_len = nframes - nbad;
2420 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2421 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2423 * If an underrun error is seen assume it as an excessive
2424 * retry only if max frame trigger level has been reached
2425 * (2 KB for single stream, and 4 KB for dual stream).
2426 * Adjust the long retry as if the frame was tried
2427 * hw->max_rate_tries times to affect how rate control updates
2428 * PER for the failed rate.
2429 * In case of congestion on the bus penalizing this type of
2430 * underruns should help hardware actually transmit new frames
2431 * successfully by eventually preferring slower rates.
2432 * This itself should also alleviate congestion on the bus.
2434 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2435 ATH9K_TX_DELIM_UNDERRUN)) &&
2436 ieee80211_is_data(hdr->frame_control) &&
2437 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2438 tx_info->status.rates[tx_rateindex].count =
2442 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2443 tx_info->status.rates[i].count = 0;
2444 tx_info->status.rates[i].idx = -1;
2447 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2450 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2452 struct ath_hw *ah = sc->sc_ah;
2453 struct ath_common *common = ath9k_hw_common(ah);
2454 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2455 struct list_head bf_head;
2456 struct ath_desc *ds;
2457 struct ath_tx_status ts;
2460 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2461 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2464 ath_txq_lock(sc, txq);
2466 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2469 if (list_empty(&txq->axq_q)) {
2470 txq->axq_link = NULL;
2471 ath_txq_schedule(sc, txq);
2474 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2477 * There is a race condition that a BH gets scheduled
2478 * after sw writes TxE and before hw re-load the last
2479 * descriptor to get the newly chained one.
2480 * Software must keep the last DONE descriptor as a
2481 * holding descriptor - software does so by marking
2482 * it with the STALE flag.
2487 if (list_is_last(&bf_held->list, &txq->axq_q))
2490 bf = list_entry(bf_held->list.next, struct ath_buf,
2494 lastbf = bf->bf_lastbf;
2495 ds = lastbf->bf_desc;
2497 memset(&ts, 0, sizeof(ts));
2498 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2499 if (status == -EINPROGRESS)
2502 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2505 * Remove ath_buf's of the same transmit unit from txq,
2506 * however leave the last descriptor back as the holding
2507 * descriptor for hw.
2509 lastbf->bf_stale = true;
2510 INIT_LIST_HEAD(&bf_head);
2511 if (!list_is_singular(&lastbf->list))
2512 list_cut_position(&bf_head,
2513 &txq->axq_q, lastbf->list.prev);
2516 list_del(&bf_held->list);
2517 ath_tx_return_buffer(sc, bf_held);
2520 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2522 ath_txq_unlock_complete(sc, txq);
2525 void ath_tx_tasklet(struct ath_softc *sc)
2527 struct ath_hw *ah = sc->sc_ah;
2528 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2531 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2532 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2533 ath_tx_processq(sc, &sc->tx.txq[i]);
2537 void ath_tx_edma_tasklet(struct ath_softc *sc)
2539 struct ath_tx_status ts;
2540 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2541 struct ath_hw *ah = sc->sc_ah;
2542 struct ath_txq *txq;
2543 struct ath_buf *bf, *lastbf;
2544 struct list_head bf_head;
2545 struct list_head *fifo_list;
2549 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2552 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2553 if (status == -EINPROGRESS)
2555 if (status == -EIO) {
2556 ath_dbg(common, XMIT, "Error processing tx status\n");
2560 /* Process beacon completions separately */
2561 if (ts.qid == sc->beacon.beaconq) {
2562 sc->beacon.tx_processed = true;
2563 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2567 txq = &sc->tx.txq[ts.qid];
2569 ath_txq_lock(sc, txq);
2571 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2573 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2574 if (list_empty(fifo_list)) {
2575 ath_txq_unlock(sc, txq);
2579 bf = list_first_entry(fifo_list, struct ath_buf, list);
2581 list_del(&bf->list);
2582 ath_tx_return_buffer(sc, bf);
2583 bf = list_first_entry(fifo_list, struct ath_buf, list);
2586 lastbf = bf->bf_lastbf;
2588 INIT_LIST_HEAD(&bf_head);
2589 if (list_is_last(&lastbf->list, fifo_list)) {
2590 list_splice_tail_init(fifo_list, &bf_head);
2591 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2593 if (!list_empty(&txq->axq_q)) {
2594 struct list_head bf_q;
2596 INIT_LIST_HEAD(&bf_q);
2597 txq->axq_link = NULL;
2598 list_splice_tail_init(&txq->axq_q, &bf_q);
2599 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2602 lastbf->bf_stale = true;
2604 list_cut_position(&bf_head, fifo_list,
2608 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2609 ath_txq_unlock_complete(sc, txq);
2617 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2619 struct ath_descdma *dd = &sc->txsdma;
2620 u8 txs_len = sc->sc_ah->caps.txs_len;
2622 dd->dd_desc_len = size * txs_len;
2623 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2624 &dd->dd_desc_paddr, GFP_KERNEL);
2631 static int ath_tx_edma_init(struct ath_softc *sc)
2635 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2637 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2638 sc->txsdma.dd_desc_paddr,
2639 ATH_TXSTATUS_RING_SIZE);
2644 int ath_tx_init(struct ath_softc *sc, int nbufs)
2646 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2649 spin_lock_init(&sc->tx.txbuflock);
2651 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2655 "Failed to allocate tx descriptors: %d\n", error);
2659 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2660 "beacon", ATH_BCBUF, 1, 1);
2663 "Failed to allocate beacon descriptors: %d\n", error);
2667 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2669 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2670 error = ath_tx_edma_init(sc);
2675 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2677 struct ath_atx_tid *tid;
2678 struct ath_atx_ac *ac;
2681 for (tidno = 0, tid = &an->tid[tidno];
2682 tidno < IEEE80211_NUM_TIDS;
2686 tid->seq_start = tid->seq_next = 0;
2687 tid->baw_size = WME_MAX_BA;
2688 tid->baw_head = tid->baw_tail = 0;
2690 tid->paused = false;
2691 tid->active = false;
2692 __skb_queue_head_init(&tid->buf_q);
2693 __skb_queue_head_init(&tid->retry_q);
2694 acno = TID_TO_WME_AC(tidno);
2695 tid->ac = &an->ac[acno];
2698 for (acno = 0, ac = &an->ac[acno];
2699 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2701 ac->clear_ps_filter = true;
2702 ac->txq = sc->tx.txq_map[acno];
2703 INIT_LIST_HEAD(&ac->tid_q);
2707 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2709 struct ath_atx_ac *ac;
2710 struct ath_atx_tid *tid;
2711 struct ath_txq *txq;
2714 for (tidno = 0, tid = &an->tid[tidno];
2715 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2720 ath_txq_lock(sc, txq);
2723 list_del(&tid->list);
2728 list_del(&ac->list);
2729 tid->ac->sched = false;
2732 ath_tid_drain(sc, txq, tid);
2733 tid->active = false;
2735 ath_txq_unlock(sc, txq);