drivers/net/wireless/ath/wil6210/interrupt.c

   1 /*
   2  * Copyright (c) 2012 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/interrupt.h>
  18
  19 #include "wil6210.h"
  20
  21 /**
  22  * Theory of operation:
  23  *
  24  * There is ISR pseudo-cause register,
  25  * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
  26  * Its bits represents OR'ed bits from 3 real ISR registers:
  27  * TX, RX, and MISC.
  28  *
  29  * Registers may be configured to either "write 1 to clear" or
  30  * "clear on read" mode
  31  *
  32  * When handling interrupt, one have to mask/unmask interrupts for the
  33  * real ISR registers, or hardware may malfunction.
  34  *
  35  */
  36
  37 #define WIL6210_IRQ_DISABLE     (0xFFFFFFFFUL)
  38 #define WIL6210_IMC_RX          BIT_DMA_EP_RX_ICR_RX_DONE
  39 #define WIL6210_IMC_TX          (BIT_DMA_EP_TX_ICR_TX_DONE | \
  40                                 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
  41 #define WIL6210_IMC_MISC        (ISR_MISC_FW_READY | \
  42                                  ISR_MISC_MBOX_EVT | \
  43                                  ISR_MISC_FW_ERROR)
  44
  45 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
  46                                         BIT_DMA_PSEUDO_CAUSE_TX | \
  47                                         BIT_DMA_PSEUDO_CAUSE_MISC))
  48
  49 #if defined(CONFIG_WIL6210_ISR_COR)
  50 /* configure to Clear-On-Read mode */
  51 #define WIL_ICR_ICC_VALUE       (0xFFFFFFFFUL)
  52
  53 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  54 {
  55
  56 }
  57 #else /* defined(CONFIG_WIL6210_ISR_COR) */
  58 /* configure to Write-1-to-Clear mode */
  59 #define WIL_ICR_ICC_VALUE       (0UL)
  60
  61 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  62 {
  63         iowrite32(x, addr);
  64 }
  65 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
  66
  67 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
  68 {
  69         u32 x = ioread32(addr);
  70
  71         wil_icr_clear(x, addr);
  72
  73         return x;
  74 }
  75
  76 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
  77 {
  78         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  79                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
  80                   offsetof(struct RGF_ICR, IMS));
  81 }
  82
  83 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
  84 {
  85         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  86                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
  87                   offsetof(struct RGF_ICR, IMS));
  88 }
  89
  90 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
  91 {
  92         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  93                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
  94                   offsetof(struct RGF_ICR, IMS));
  95 }
  96
  97 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
  98 {
  99         wil_dbg_IRQ(wil, "%s()\n", __func__);
 100
 101         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
 102                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 103
 104         clear_bit(wil_status_irqen, &wil->status);
 105 }
 106
 107 static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
 108 {
 109         iowrite32(WIL6210_IMC_TX, wil->csr +
 110                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
 111                   offsetof(struct RGF_ICR, IMC));
 112 }
 113
 114 static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
 115 {
 116         iowrite32(WIL6210_IMC_RX, wil->csr +
 117                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
 118                   offsetof(struct RGF_ICR, IMC));
 119 }
 120
 121 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
 122 {
 123         iowrite32(WIL6210_IMC_MISC, wil->csr +
 124                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 125                   offsetof(struct RGF_ICR, IMC));
 126 }
 127
 128 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
 129 {
 130         wil_dbg_IRQ(wil, "%s()\n", __func__);
 131
 132         set_bit(wil_status_irqen, &wil->status);
 133
 134         iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
 135                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 136 }
 137
 138 void wil6210_disable_irq(struct wil6210_priv *wil)
 139 {
 140         wil_dbg_IRQ(wil, "%s()\n", __func__);
 141
 142         wil6210_mask_irq_tx(wil);
 143         wil6210_mask_irq_rx(wil);
 144         wil6210_mask_irq_misc(wil);
 145         wil6210_mask_irq_pseudo(wil);
 146 }
 147
 148 void wil6210_enable_irq(struct wil6210_priv *wil)
 149 {
 150         wil_dbg_IRQ(wil, "%s()\n", __func__);
 151
 152         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 153                   offsetof(struct RGF_ICR, ICC));
 154         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 155                   offsetof(struct RGF_ICR, ICC));
 156         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 157                   offsetof(struct RGF_ICR, ICC));
 158
 159         wil6210_unmask_irq_pseudo(wil);
 160         wil6210_unmask_irq_tx(wil);
 161         wil6210_unmask_irq_rx(wil);
 162         wil6210_unmask_irq_misc(wil);
 163 }
 164
 165 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
 166 {
 167         struct wil6210_priv *wil = cookie;
 168         u32 isr = wil_ioread32_and_clear(wil->csr +
 169                                          HOSTADDR(RGF_DMA_EP_RX_ICR) +
 170                                          offsetof(struct RGF_ICR, ICR));
 171
 172         wil_dbg_IRQ(wil, "ISR RX 0x%08x\n", isr);
 173
 174         if (!isr) {
 175                 wil_err(wil, "spurious IRQ: RX\n");
 176                 return IRQ_NONE;
 177         }
 178
 179         wil6210_mask_irq_rx(wil);
 180
 181         if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
 182                 wil_dbg_IRQ(wil, "RX done\n");
 183                 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
 184                 wil_rx_handle(wil);
 185         }
 186
 187         if (isr)
 188                 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
 189
 190         wil6210_unmask_irq_rx(wil);
 191
 192         return IRQ_HANDLED;
 193 }
 194
 195 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
 196 {
 197         struct wil6210_priv *wil = cookie;
 198         u32 isr = wil_ioread32_and_clear(wil->csr +
 199                                          HOSTADDR(RGF_DMA_EP_TX_ICR) +
 200                                          offsetof(struct RGF_ICR, ICR));
 201
 202         wil_dbg_IRQ(wil, "ISR TX 0x%08x\n", isr);
 203
 204         if (!isr) {
 205                 wil_err(wil, "spurious IRQ: TX\n");
 206                 return IRQ_NONE;
 207         }
 208
 209         wil6210_mask_irq_tx(wil);
 210
 211         if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
 212                 uint i;
 213                 wil_dbg_IRQ(wil, "TX done\n");
 214                 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
 215                 for (i = 0; i < 24; i++) {
 216                         u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
 217                         if (isr & mask) {
 218                                 isr &= ~mask;
 219                                 wil_dbg_IRQ(wil, "TX done(%i)\n", i);
 220                                 wil_tx_complete(wil, i);
 221                         }
 222                 }
 223         }
 224
 225         if (isr)
 226                 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
 227
 228         wil6210_unmask_irq_tx(wil);
 229
 230         return IRQ_HANDLED;
 231 }
 232
 233 static void wil_notify_fw_error(struct wil6210_priv *wil)
 234 {
 235         struct device *dev = &wil_to_ndev(wil)->dev;
 236         char *envp[3] = {
 237                 [0] = "SOURCE=wil6210",
 238                 [1] = "EVENT=FW_ERROR",
 239                 [2] = NULL,
 240         };
 241         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
 242 }
 243
 244 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
 245 {
 246         struct wil6210_priv *wil = cookie;
 247         u32 isr = wil_ioread32_and_clear(wil->csr +
 248                                          HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 249                                          offsetof(struct RGF_ICR, ICR));
 250
 251         wil_dbg_IRQ(wil, "ISR MISC 0x%08x\n", isr);
 252
 253         if (!isr) {
 254                 wil_err(wil, "spurious IRQ: MISC\n");
 255                 return IRQ_NONE;
 256         }
 257
 258         wil6210_mask_irq_misc(wil);
 259
 260         if (isr & ISR_MISC_FW_ERROR) {
 261                 wil_dbg_IRQ(wil, "IRQ: Firmware error\n");
 262                 clear_bit(wil_status_fwready, &wil->status);
 263                 wil_notify_fw_error(wil);
 264                 isr &= ~ISR_MISC_FW_ERROR;
 265         }
 266
 267         if (isr & ISR_MISC_FW_READY) {
 268                 wil_dbg_IRQ(wil, "IRQ: FW ready\n");
 269                 /**
 270                  * Actual FW ready indicated by the
 271                  * WMI_FW_READY_EVENTID
 272                  */
 273                 isr &= ~ISR_MISC_FW_READY;
 274         }
 275
 276         wil->isr_misc = isr;
 277
 278         if (isr) {
 279                 return IRQ_WAKE_THREAD;
 280         } else {
 281                 wil6210_unmask_irq_misc(wil);
 282                 return IRQ_HANDLED;
 283         }
 284 }
 285
 286 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
 287 {
 288         struct wil6210_priv *wil = cookie;
 289         u32 isr = wil->isr_misc;
 290
 291         wil_dbg_IRQ(wil, "Thread ISR MISC 0x%08x\n", isr);
 292
 293         if (isr & ISR_MISC_MBOX_EVT) {
 294                 wil_dbg_IRQ(wil, "MBOX event\n");
 295                 wmi_recv_cmd(wil);
 296                 isr &= ~ISR_MISC_MBOX_EVT;
 297         }
 298
 299         if (isr)
 300                 wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
 301
 302         wil->isr_misc = 0;
 303
 304         wil6210_unmask_irq_misc(wil);
 305
 306         return IRQ_HANDLED;
 307 }
 308
 309 /**
 310  * thread IRQ handler
 311  */
 312 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
 313 {
 314         struct wil6210_priv *wil = cookie;
 315
 316         wil_dbg_IRQ(wil, "Thread IRQ\n");
 317         /* Discover real IRQ cause */
 318         if (wil->isr_misc)
 319                 wil6210_irq_misc_thread(irq, cookie);
 320
 321         wil6210_unmask_irq_pseudo(wil);
 322
 323         return IRQ_HANDLED;
 324 }
 325
 326 /* DEBUG
 327  * There is subtle bug in hardware that causes IRQ to raise when it should be
 328  * masked. It is quite rare and hard to debug.
 329  *
 330  * Catch irq issue if it happens and print all I can.
 331  */
 332 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
 333 {
 334         if (!test_bit(wil_status_irqen, &wil->status)) {
 335                 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
 336                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 337                                 offsetof(struct RGF_ICR, ICM));
 338                 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
 339                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 340                                 offsetof(struct RGF_ICR, ICR));
 341                 u32 imv_rx = ioread32(wil->csr +
 342                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 343                                 offsetof(struct RGF_ICR, IMV));
 344                 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
 345                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 346                                 offsetof(struct RGF_ICR, ICM));
 347                 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
 348                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 349                                 offsetof(struct RGF_ICR, ICR));
 350                 u32 imv_tx = ioread32(wil->csr +
 351                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 352                                 offsetof(struct RGF_ICR, IMV));
 353                 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
 354                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 355                                 offsetof(struct RGF_ICR, ICM));
 356                 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
 357                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 358                                 offsetof(struct RGF_ICR, ICR));
 359                 u32 imv_misc = ioread32(wil->csr +
 360                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 361                                 offsetof(struct RGF_ICR, IMV));
 362                 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
 363                                 "Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 364                                 "Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 365                                 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
 366                                 pseudo_cause,
 367                                 icm_rx, icr_rx, imv_rx,
 368                                 icm_tx, icr_tx, imv_tx,
 369                                 icm_misc, icr_misc, imv_misc);
 370
 371                 return -EINVAL;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
 378 {
 379         irqreturn_t rc = IRQ_HANDLED;
 380         struct wil6210_priv *wil = cookie;
 381         u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
 382
 383         /**
 384          * pseudo_cause is Clear-On-Read, no need to ACK
 385          */
 386         if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
 387                 return IRQ_NONE;
 388
 389         /* FIXME: IRQ mask debug */
 390         if (wil6210_debug_irq_mask(wil, pseudo_cause))
 391                 return IRQ_NONE;
 392
 393         wil6210_mask_irq_pseudo(wil);
 394
 395         /* Discover real IRQ cause
 396          * There are 2 possible phases for every IRQ:
 397          * - hard IRQ handler called right here
 398          * - threaded handler called later
 399          *
 400          * Hard IRQ handler reads and clears ISR.
 401          *
 402          * If threaded handler requested, hard IRQ handler
 403          * returns IRQ_WAKE_THREAD and saves ISR register value
 404          * for the threaded handler use.
 405          *
 406          * voting for wake thread - need at least 1 vote
 407          */
 408         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
 409             (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
 410                 rc = IRQ_WAKE_THREAD;
 411
 412         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
 413             (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
 414                 rc = IRQ_WAKE_THREAD;
 415
 416         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
 417             (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
 418                 rc = IRQ_WAKE_THREAD;
 419
 420         /* if thread is requested, it will unmask IRQ */
 421         if (rc != IRQ_WAKE_THREAD)
 422                 wil6210_unmask_irq_pseudo(wil);
 423
 424         wil_dbg_IRQ(wil, "Hard IRQ 0x%08x\n", pseudo_cause);
 425
 426         return rc;
 427 }
 428
 429 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
 430 {
 431         int rc;
 432         /*
 433          * IRQ's are in the following order:
 434          * - Tx
 435          * - Rx
 436          * - Misc
 437          */
 438
 439         rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
 440                          WIL_NAME"_tx", wil);
 441         if (rc)
 442                 return rc;
 443
 444         rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
 445                          WIL_NAME"_rx", wil);
 446         if (rc)
 447                 goto free0;
 448
 449         rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
 450                                   wil6210_irq_misc_thread,
 451                                   IRQF_SHARED, WIL_NAME"_misc", wil);
 452         if (rc)
 453                 goto free1;
 454
 455         return 0;
 456         /* error branch */
 457 free1:
 458         free_irq(irq + 1, wil);
 459 free0:
 460         free_irq(irq, wil);
 461
 462         return rc;
 463 }
 464
 465 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
 466 {
 467         int rc;
 468         if (wil->n_msi == 3)
 469                 rc = wil6210_request_3msi(wil, irq);
 470         else
 471                 rc = request_threaded_irq(irq, wil6210_hardirq,
 472                                           wil6210_thread_irq,
 473                                           wil->n_msi ? 0 : IRQF_SHARED,
 474                                           WIL_NAME, wil);
 475         if (rc)
 476                 return rc;
 477
 478         wil6210_enable_irq(wil);
 479
 480         return 0;
 481 }
 482
 483 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
 484 {
 485         wil6210_disable_irq(wil);
 486         free_irq(irq, wil);
 487         if (wil->n_msi == 3) {
 488                 free_irq(irq + 1, wil);
 489                 free_irq(irq + 2, wil);
 490         }
 491 }