2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef WIL6210_TXRX_H
18 #define WIL6210_TXRX_H
20 #define BUF_SW_OWNED (1)
21 #define BUF_HW_OWNED (0)
23 /* size of max. Rx packet */
24 #define RX_BUF_LEN (2048)
25 #define TX_BUF_LEN (2048)
26 /* how many bytes to reserve for rtap header? */
27 #define WIL6210_RTAP_SIZE (128)
31 * Tx descriptor - MAC part
33 * bit 0.. 9 : lifetime_expiry_value:10
34 * bit 10 : interrup_en:1
35 * bit 11 : status_en:1
36 * bit 12..13 : txss_override:2
37 * bit 14 : timestamp_insertion:1
38 * bit 15 : duration_preserve:1
39 * bit 16..21 : reserved0:6
40 * bit 22..26 : mcs_index:5
42 * bit 28..29 : reserved1:2
43 * bit 30 : reserved2:1
44 * bit 31 : sn_preserved:1
46 * bit 0.. 3 : pkt_mode:4
47 * bit 4 : pkt_mode_en:1
48 * bit 5.. 7 : reserved0:3
49 * bit 8..13 : reserved1:6
50 * bit 14 : reserved2:1
51 * bit 15 : ack_policy_en:1
52 * bit 16..19 : dst_index:4
53 * bit 20 : dst_index_en:1
54 * bit 21..22 : ack_policy:2
55 * bit 23 : lifetime_en:1
56 * bit 24..30 : max_retry:7
57 * bit 31 : max_retry_en:1
59 * bit 0.. 7 : num_of_descriptors:8
60 * bit 8..17 : reserved:10
61 * bit 18..19 : l2_translation_type:2
62 * bit 20 : snap_hdr_insertion_en:1
63 * bit 21 : vlan_removal_en:1
64 * bit 22..31 : reserved0:10
66 * bit 0.. 31: ucode_cmd:32
74 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
75 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
76 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
78 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
79 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
80 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
82 #define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
83 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
84 #define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
86 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
87 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
88 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
90 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
91 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
92 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
94 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
95 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
96 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
98 #define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
99 #define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
100 #define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
102 #define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
103 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
104 #define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
106 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
107 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
108 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
111 #define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
112 #define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
113 #define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
115 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
116 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
117 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
119 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
120 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
121 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
123 #define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
124 #define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
125 #define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
127 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
128 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
129 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
131 #define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
132 #define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
133 #define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
135 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
136 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
137 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
139 #define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
140 #define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
141 #define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
143 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
144 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
145 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
148 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
149 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
150 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
152 #define MAC_CFG_DESC_TX_2_RESERVED_POS 8
153 #define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
154 #define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
156 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
157 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
158 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
160 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
161 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
162 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
164 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
165 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
166 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
169 #define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
170 #define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
171 #define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
174 #define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
175 #define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
176 #define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
178 #define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
179 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
180 #define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
182 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
183 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
184 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
186 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
187 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
188 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
190 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
191 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
192 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
194 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
195 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
196 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
198 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
199 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
200 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
202 #define DMA_CFG_DESC_TX_0_QID_POS 16
203 #define DMA_CFG_DESC_TX_0_QID_LEN 5
204 #define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
206 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
207 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
208 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
210 #define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
211 #define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
212 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000
215 #define TX_DMA_STATUS_DU BIT(0)
217 struct vring_tx_dma {
222 u8 b11; /* 0..6: mac_length; 7:ip_version */
223 u8 error; /* 0..2: err; 3..7: reserved; */
224 u8 status; /* 0: used; 1..7; reserved */
229 * Rx descriptor - MAC part
231 * bit 0.. 3 : tid:4 The QoS (b3-0) TID Field
232 * bit 4.. 6 : connection_id:3 :The Source index that was found during
233 * Parsing the TA. This field is used to define the source of the packet
235 * bit 8.. 9 : mac_id:2 : The MAC virtual Ring number (always zero)
236 * bit 10..11 : frame_type:2 : The FC Control (b3-2) - MPDU Type
237 * (management, data, control and extension)
238 * bit 12..15 : frame_subtype:4 : The FC Control (b7-4) - Frame Subtype
239 * bit 16..27 : seq_number:12 The received Sequence number field
240 * bit 28..31 : extended:4 extended subtype
242 * bit 0.. 3 : reserved
243 * bit 4.. 5 : key_id:2
244 * bit 6 : decrypt_bypass:1
246 * bit 8.. 9 : ds_bits:2
247 * bit 10 : a_msdu_present:1 from qos header
248 * bit 11 : a_msdu_type:1 from qos header
249 * bit 12 : a_mpdu:1 part of AMPDU aggregation
250 * bit 13 : broadcast:1
251 * bit 14 : mutlicast:1
252 * bit 15 : reserved:1
253 * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
256 * bit 25..28 : mic_icr:4
257 * bit 29..31 : reserved:3
259 * bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received
260 * bit 3 : fc_protocol_ver:1 The FC Control (b0) - Protocol Version
261 * bit 4 : fc_order:1 The FC Control (b15) -Order
262 * bit 5.. 7 : qos_ack_policy:3 The QoS (b6-5) ack policy Field
263 * bit 8 : esop:1 The QoS (b4) ESOP field
264 * bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
265 * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
266 * bit 15 : qos_ac_constraint:1
267 * bit 16..31 : pn_15_0:16 low 2 bytes of PN
269 * bit 0..31 : pn_47_16:32 high 4 bytes of PN
271 struct vring_rx_mac {
280 * Rx descriptor - DMA part
282 * bit 0.. 7 : l4_length:8 layer 4 length
283 * bit 8.. 9 : reserved:2
284 * bit 10 : cmd_dma_it:1
285 * bit 11..15 : reserved:5
286 * bit 16..29 : phy_info_length:14
287 * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
289 * bit 0..31 : addr_low:32 The payload buffer low address
291 * bit 0..15 : addr_high:16 The payload buffer high address
292 * bit 16..23 : ip_length:8
293 * bit 24..30 : mac_length:7
294 * bit 31 : ip_version:1
302 * bit 4 : l3_identified:1
303 * bit 5 : l4_identified:1
304 * bit 6 : phy_info_included:1
310 #define RX_DMA_D0_CMD_DMA_IT BIT(10)
312 #define RX_DMA_STATUS_DU BIT(0)
313 #define RX_DMA_STATUS_ERROR BIT(2)
314 #define RX_DMA_STATUS_PHY_INFO BIT(6)
316 struct vring_rx_dma {
327 struct vring_tx_desc {
328 struct vring_tx_mac mac;
329 struct vring_tx_dma dma;
332 struct vring_rx_desc {
333 struct vring_rx_mac mac;
334 struct vring_rx_dma dma;
338 struct vring_tx_desc tx;
339 struct vring_rx_desc rx;
342 static inline int wil_rxdesc_phy_length(volatile struct vring_rx_desc *d)
344 return WIL_GET_BITS(d->dma.d0, 16, 29);
347 static inline int wil_rxdesc_mcs(volatile struct vring_rx_desc *d)
349 return WIL_GET_BITS(d->mac.d1, 21, 24);
352 static inline int wil_rxdesc_ds_bits(volatile struct vring_rx_desc *d)
354 return WIL_GET_BITS(d->mac.d1, 8, 9);
357 static inline int wil_rxdesc_ftype(volatile struct vring_rx_desc *d)
359 return WIL_GET_BITS(d->mac.d0, 10, 11);
362 #endif /* WIL6210_TXRX_H */