2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
99 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
102 static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
141 static struct ieee80211_rate ath5k_rates[] = {
143 .hw_value = ATH5K_RATE_CODE_1M, },
145 .hw_value = ATH5K_RATE_CODE_2M,
146 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149 .hw_value = ATH5K_RATE_CODE_5_5M,
150 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 .hw_value = ATH5K_RATE_CODE_11M,
154 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_6M,
160 .hw_value = ATH5K_RATE_CODE_9M,
163 .hw_value = ATH5K_RATE_CODE_12M,
166 .hw_value = ATH5K_RATE_CODE_18M,
169 .hw_value = ATH5K_RATE_CODE_24M,
172 .hw_value = ATH5K_RATE_CODE_36M,
175 .hw_value = ATH5K_RATE_CODE_48M,
178 .hw_value = ATH5K_RATE_CODE_54M,
184 * Prototypes - PCI stack related functions
186 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
187 const struct pci_device_id *id);
188 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
190 static int ath5k_pci_suspend(struct pci_dev *pdev,
192 static int ath5k_pci_resume(struct pci_dev *pdev);
194 #define ath5k_pci_suspend NULL
195 #define ath5k_pci_resume NULL
196 #endif /* CONFIG_PM */
198 static struct pci_driver ath5k_pci_driver = {
200 .id_table = ath5k_pci_id_table,
201 .probe = ath5k_pci_probe,
202 .remove = __devexit_p(ath5k_pci_remove),
203 .suspend = ath5k_pci_suspend,
204 .resume = ath5k_pci_resume,
210 * Prototypes - MAC 802.11 stack related functions
212 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
213 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
214 static int ath5k_reset_wake(struct ath5k_softc *sc);
215 static int ath5k_start(struct ieee80211_hw *hw);
216 static void ath5k_stop(struct ieee80211_hw *hw);
217 static int ath5k_add_interface(struct ieee80211_hw *hw,
218 struct ieee80211_if_init_conf *conf);
219 static void ath5k_remove_interface(struct ieee80211_hw *hw,
220 struct ieee80211_if_init_conf *conf);
221 static int ath5k_config(struct ieee80211_hw *hw,
222 struct ieee80211_conf *conf);
223 static int ath5k_config_interface(struct ieee80211_hw *hw,
224 struct ieee80211_vif *vif,
225 struct ieee80211_if_conf *conf);
226 static void ath5k_configure_filter(struct ieee80211_hw *hw,
227 unsigned int changed_flags,
228 unsigned int *new_flags,
229 int mc_count, struct dev_mc_list *mclist);
230 static int ath5k_set_key(struct ieee80211_hw *hw,
231 enum set_key_cmd cmd,
232 const u8 *local_addr, const u8 *addr,
233 struct ieee80211_key_conf *key);
234 static int ath5k_get_stats(struct ieee80211_hw *hw,
235 struct ieee80211_low_level_stats *stats);
236 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
237 struct ieee80211_tx_queue_stats *stats);
238 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
239 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
240 static int ath5k_beacon_update(struct ieee80211_hw *hw,
241 struct sk_buff *skb);
243 static struct ieee80211_ops ath5k_hw_ops = {
245 .start = ath5k_start,
247 .add_interface = ath5k_add_interface,
248 .remove_interface = ath5k_remove_interface,
249 .config = ath5k_config,
250 .config_interface = ath5k_config_interface,
251 .configure_filter = ath5k_configure_filter,
252 .set_key = ath5k_set_key,
253 .get_stats = ath5k_get_stats,
255 .get_tx_stats = ath5k_get_tx_stats,
256 .get_tsf = ath5k_get_tsf,
257 .reset_tsf = ath5k_reset_tsf,
261 * Prototypes - Internal functions
264 static int ath5k_attach(struct pci_dev *pdev,
265 struct ieee80211_hw *hw);
266 static void ath5k_detach(struct pci_dev *pdev,
267 struct ieee80211_hw *hw);
268 /* Channel/mode setup */
269 static inline short ath5k_ieee2mhz(short chan);
270 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
271 struct ieee80211_channel *channels,
274 static int ath5k_setup_bands(struct ieee80211_hw *hw);
275 static int ath5k_chan_set(struct ath5k_softc *sc,
276 struct ieee80211_channel *chan);
277 static void ath5k_setcurmode(struct ath5k_softc *sc,
279 static void ath5k_mode_setup(struct ath5k_softc *sc);
281 /* Descriptor setup */
282 static int ath5k_desc_alloc(struct ath5k_softc *sc,
283 struct pci_dev *pdev);
284 static void ath5k_desc_free(struct ath5k_softc *sc,
285 struct pci_dev *pdev);
287 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
288 struct ath5k_buf *bf);
289 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
290 struct ath5k_buf *bf);
291 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
292 struct ath5k_buf *bf)
297 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
299 dev_kfree_skb_any(bf->skb);
304 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
305 int qtype, int subtype);
306 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
307 static int ath5k_beaconq_config(struct ath5k_softc *sc);
308 static void ath5k_txq_drainq(struct ath5k_softc *sc,
309 struct ath5k_txq *txq);
310 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
311 static void ath5k_txq_release(struct ath5k_softc *sc);
313 static int ath5k_rx_start(struct ath5k_softc *sc);
314 static void ath5k_rx_stop(struct ath5k_softc *sc);
315 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
316 struct ath5k_desc *ds,
318 struct ath5k_rx_status *rs);
319 static void ath5k_tasklet_rx(unsigned long data);
321 static void ath5k_tx_processq(struct ath5k_softc *sc,
322 struct ath5k_txq *txq);
323 static void ath5k_tasklet_tx(unsigned long data);
324 /* Beacon handling */
325 static int ath5k_beacon_setup(struct ath5k_softc *sc,
326 struct ath5k_buf *bf);
327 static void ath5k_beacon_send(struct ath5k_softc *sc);
328 static void ath5k_beacon_config(struct ath5k_softc *sc);
329 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
331 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
333 u64 tsf = ath5k_hw_get_tsf64(ah);
335 if ((tsf & 0x7fff) < rstamp)
338 return (tsf & ~0x7fff) | rstamp;
341 /* Interrupt handling */
342 static int ath5k_init(struct ath5k_softc *sc);
343 static int ath5k_stop_locked(struct ath5k_softc *sc);
344 static int ath5k_stop_hw(struct ath5k_softc *sc);
345 static irqreturn_t ath5k_intr(int irq, void *dev_id);
346 static void ath5k_tasklet_reset(unsigned long data);
348 static void ath5k_calibrate(unsigned long data);
350 static int ath5k_init_leds(struct ath5k_softc *sc);
351 static void ath5k_led_enable(struct ath5k_softc *sc);
352 static void ath5k_led_off(struct ath5k_softc *sc);
353 static void ath5k_unregister_leds(struct ath5k_softc *sc);
356 * Module init/exit functions
365 ret = pci_register_driver(&ath5k_pci_driver);
367 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
377 pci_unregister_driver(&ath5k_pci_driver);
379 ath5k_debug_finish();
382 module_init(init_ath5k_pci);
383 module_exit(exit_ath5k_pci);
386 /********************\
387 * PCI Initialization *
388 \********************/
391 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
393 const char *name = "xxxxx";
396 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
397 if (srev_names[i].sr_type != type)
399 if ((val & 0xff) < srev_names[i + 1].sr_val) {
400 name = srev_names[i].sr_name;
409 ath5k_pci_probe(struct pci_dev *pdev,
410 const struct pci_device_id *id)
413 struct ath5k_softc *sc;
414 struct ieee80211_hw *hw;
418 ret = pci_enable_device(pdev);
420 dev_err(&pdev->dev, "can't enable device\n");
424 /* XXX 32-bit addressing only */
425 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
427 dev_err(&pdev->dev, "32-bit DMA not available\n");
432 * Cache line size is used to size and align various
433 * structures used to communicate with the hardware.
435 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
438 * Linux 2.4.18 (at least) writes the cache line size
439 * register as a 16-bit wide register which is wrong.
440 * We must have this setup properly for rx buffer
441 * DMA to work so force a reasonable value here if it
444 csz = L1_CACHE_BYTES / sizeof(u32);
445 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
448 * The default setting of latency timer yields poor results,
449 * set it to the value used by other systems. It may be worth
450 * tweaking this setting more.
452 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
454 /* Enable bus mastering */
455 pci_set_master(pdev);
458 * Disable the RETRY_TIMEOUT register (0x41) to keep
459 * PCI Tx retries from interfering with C3 CPU state.
461 pci_write_config_byte(pdev, 0x41, 0);
463 ret = pci_request_region(pdev, 0, "ath5k");
465 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
469 mem = pci_iomap(pdev, 0, 0);
471 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
477 * Allocate hw (mac80211 main struct)
478 * and hw->priv (driver private data)
480 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
482 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
487 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
489 /* Initialize driver private data */
490 SET_IEEE80211_DEV(hw, &pdev->dev);
491 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
492 IEEE80211_HW_SIGNAL_DBM |
493 IEEE80211_HW_NOISE_DBM;
495 hw->wiphy->interface_modes =
496 BIT(NL80211_IFTYPE_STATION) |
497 BIT(NL80211_IFTYPE_ADHOC) |
498 BIT(NL80211_IFTYPE_MESH_POINT);
500 hw->extra_tx_headroom = 2;
501 hw->channel_change_time = 5000;
506 ath5k_debug_init_device(sc);
509 * Mark the device as detached to avoid processing
510 * interrupts until setup is complete.
512 __set_bit(ATH_STAT_INVALID, sc->status);
514 sc->iobase = mem; /* So we can unmap it on detach */
515 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
516 sc->opmode = NL80211_IFTYPE_STATION;
517 mutex_init(&sc->lock);
518 spin_lock_init(&sc->rxbuflock);
519 spin_lock_init(&sc->txbuflock);
520 spin_lock_init(&sc->block);
522 /* Set private data */
523 pci_set_drvdata(pdev, hw);
525 /* Setup interrupt handler */
526 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
528 ATH5K_ERR(sc, "request_irq failed\n");
532 /* Initialize device */
533 sc->ah = ath5k_hw_attach(sc, id->driver_data);
534 if (IS_ERR(sc->ah)) {
535 ret = PTR_ERR(sc->ah);
539 /* Finish private driver data initialization */
540 ret = ath5k_attach(pdev, hw);
544 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
545 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
547 sc->ah->ah_phy_revision);
549 if (!sc->ah->ah_single_chip) {
550 /* Single chip radio (!RF5111) */
551 if (sc->ah->ah_radio_5ghz_revision &&
552 !sc->ah->ah_radio_2ghz_revision) {
553 /* No 5GHz support -> report 2GHz radio */
554 if (!test_bit(AR5K_MODE_11A,
555 sc->ah->ah_capabilities.cap_mode)) {
556 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
557 ath5k_chip_name(AR5K_VERSION_RAD,
558 sc->ah->ah_radio_5ghz_revision),
559 sc->ah->ah_radio_5ghz_revision);
560 /* No 2GHz support (5110 and some
561 * 5Ghz only cards) -> report 5Ghz radio */
562 } else if (!test_bit(AR5K_MODE_11B,
563 sc->ah->ah_capabilities.cap_mode)) {
564 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
565 ath5k_chip_name(AR5K_VERSION_RAD,
566 sc->ah->ah_radio_5ghz_revision),
567 sc->ah->ah_radio_5ghz_revision);
568 /* Multiband radio */
570 ATH5K_INFO(sc, "RF%s multiband radio found"
572 ath5k_chip_name(AR5K_VERSION_RAD,
573 sc->ah->ah_radio_5ghz_revision),
574 sc->ah->ah_radio_5ghz_revision);
577 /* Multi chip radio (RF5111 - RF2111) ->
578 * report both 2GHz/5GHz radios */
579 else if (sc->ah->ah_radio_5ghz_revision &&
580 sc->ah->ah_radio_2ghz_revision){
581 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
582 ath5k_chip_name(AR5K_VERSION_RAD,
583 sc->ah->ah_radio_5ghz_revision),
584 sc->ah->ah_radio_5ghz_revision);
585 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_2ghz_revision),
588 sc->ah->ah_radio_2ghz_revision);
593 /* ready to process interrupts */
594 __clear_bit(ATH_STAT_INVALID, sc->status);
598 ath5k_hw_detach(sc->ah);
600 free_irq(pdev->irq, sc);
602 ieee80211_free_hw(hw);
604 pci_iounmap(pdev, mem);
606 pci_release_region(pdev, 0);
608 pci_disable_device(pdev);
613 static void __devexit
614 ath5k_pci_remove(struct pci_dev *pdev)
616 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
617 struct ath5k_softc *sc = hw->priv;
619 ath5k_debug_finish_device(sc);
620 ath5k_detach(pdev, hw);
621 ath5k_hw_detach(sc->ah);
622 free_irq(pdev->irq, sc);
623 pci_iounmap(pdev, sc->iobase);
624 pci_release_region(pdev, 0);
625 pci_disable_device(pdev);
626 ieee80211_free_hw(hw);
631 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
633 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
634 struct ath5k_softc *sc = hw->priv;
640 free_irq(pdev->irq, sc);
641 pci_save_state(pdev);
642 pci_disable_device(pdev);
643 pci_set_power_state(pdev, PCI_D3hot);
649 ath5k_pci_resume(struct pci_dev *pdev)
651 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
652 struct ath5k_softc *sc = hw->priv;
653 struct ath5k_hw *ah = sc->ah;
656 pci_restore_state(pdev);
658 err = pci_enable_device(pdev);
663 * Suspend/Resume resets the PCI configuration space, so we have to
664 * re-disable the RETRY_TIMEOUT register (0x41) to keep
665 * PCI Tx retries from interfering with C3 CPU state
667 pci_write_config_byte(pdev, 0x41, 0);
669 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
671 ATH5K_ERR(sc, "request_irq failed\n");
675 err = ath5k_init(sc);
678 ath5k_led_enable(sc);
681 * Reset the key cache since some parts do not
682 * reset the contents on initial power up or resume.
684 * FIXME: This may need to be revisited when mac80211 becomes
685 * aware of suspend/resume.
687 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
688 ath5k_hw_reset_key(ah, i);
692 free_irq(pdev->irq, sc);
694 pci_disable_device(pdev);
697 #endif /* CONFIG_PM */
700 /***********************\
701 * Driver Initialization *
702 \***********************/
705 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
707 struct ath5k_softc *sc = hw->priv;
708 struct ath5k_hw *ah = sc->ah;
713 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
716 * Check if the MAC has multi-rate retry support.
717 * We do this by trying to setup a fake extended
718 * descriptor. MAC's that don't have support will
719 * return false w/o doing anything. MAC's that do
720 * support it will return true w/o doing anything.
722 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
726 __set_bit(ATH_STAT_MRRETRY, sc->status);
729 * Reset the key cache since some parts do not
730 * reset the contents on initial power up.
732 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
733 ath5k_hw_reset_key(ah, i);
736 * Collect the channel list. The 802.11 layer
737 * is resposible for filtering this list based
738 * on settings like the phy mode and regulatory
739 * domain restrictions.
741 ret = ath5k_setup_bands(hw);
743 ATH5K_ERR(sc, "can't get channels\n");
747 /* NB: setup here so ath5k_rate_update is happy */
748 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
749 ath5k_setcurmode(sc, AR5K_MODE_11A);
751 ath5k_setcurmode(sc, AR5K_MODE_11B);
754 * Allocate tx+rx descriptors and populate the lists.
756 ret = ath5k_desc_alloc(sc, pdev);
758 ATH5K_ERR(sc, "can't allocate descriptors\n");
763 * Allocate hardware transmit queues: one queue for
764 * beacon frames and one data queue for each QoS
765 * priority. Note that hw functions handle reseting
766 * these queues at the needed time.
768 ret = ath5k_beaconq_setup(ah);
770 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
775 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
776 if (IS_ERR(sc->txq)) {
777 ATH5K_ERR(sc, "can't setup xmit queue\n");
778 ret = PTR_ERR(sc->txq);
782 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
783 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
784 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
785 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
787 ath5k_hw_get_lladdr(ah, mac);
788 SET_IEEE80211_PERM_ADDR(hw, mac);
789 /* All MAC address bits matter for ACKs */
790 memset(sc->bssidmask, 0xff, ETH_ALEN);
791 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
793 ret = ieee80211_register_hw(hw);
795 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
803 ath5k_txq_release(sc);
805 ath5k_hw_release_tx_queue(ah, sc->bhalq);
807 ath5k_desc_free(sc, pdev);
813 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
815 struct ath5k_softc *sc = hw->priv;
818 * NB: the order of these is important:
819 * o call the 802.11 layer before detaching ath5k_hw to
820 * insure callbacks into the driver to delete global
821 * key cache entries can be handled
822 * o reclaim the tx queue data structures after calling
823 * the 802.11 layer as we'll get called back to reclaim
824 * node state and potentially want to use them
825 * o to cleanup the tx queues the hal is called, so detach
827 * XXX: ??? detach ath5k_hw ???
828 * Other than that, it's straightforward...
830 ieee80211_unregister_hw(hw);
831 ath5k_desc_free(sc, pdev);
832 ath5k_txq_release(sc);
833 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
834 ath5k_unregister_leds(sc);
837 * NB: can't reclaim these until after ieee80211_ifdetach
838 * returns because we'll get called back to reclaim node
839 * state and potentially want to use them.
846 /********************\
847 * Channel/mode setup *
848 \********************/
851 * Convert IEEE channel number to MHz frequency.
854 ath5k_ieee2mhz(short chan)
856 if (chan <= 14 || chan >= 27)
857 return ieee80211chan2mhz(chan);
859 return 2212 + chan * 20;
863 ath5k_copy_channels(struct ath5k_hw *ah,
864 struct ieee80211_channel *channels,
868 unsigned int i, count, size, chfreq, freq, ch;
870 if (!test_bit(mode, ah->ah_modes))
875 case AR5K_MODE_11A_TURBO:
876 /* 1..220, but 2GHz frequencies are filtered by check_channel */
878 chfreq = CHANNEL_5GHZ;
882 case AR5K_MODE_11G_TURBO:
884 chfreq = CHANNEL_2GHZ;
887 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
891 for (i = 0, count = 0; i < size && max > 0; i++) {
893 freq = ath5k_ieee2mhz(ch);
895 /* Check if channel is supported by the chipset */
896 if (!ath5k_channel_ok(ah, freq, chfreq))
899 /* Write channel info and increment counter */
900 channels[count].center_freq = freq;
901 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
902 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
906 channels[count].hw_value = chfreq | CHANNEL_OFDM;
908 case AR5K_MODE_11A_TURBO:
909 case AR5K_MODE_11G_TURBO:
910 channels[count].hw_value = chfreq |
911 CHANNEL_OFDM | CHANNEL_TURBO;
914 channels[count].hw_value = CHANNEL_B;
925 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
929 for (i = 0; i < AR5K_MAX_RATES; i++)
930 sc->rate_idx[b->band][i] = -1;
932 for (i = 0; i < b->n_bitrates; i++) {
933 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
934 if (b->bitrates[i].hw_value_short)
935 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
940 ath5k_setup_bands(struct ieee80211_hw *hw)
942 struct ath5k_softc *sc = hw->priv;
943 struct ath5k_hw *ah = sc->ah;
944 struct ieee80211_supported_band *sband;
945 int max_c, count_c = 0;
948 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
949 max_c = ARRAY_SIZE(sc->channels);
952 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
953 sband->band = IEEE80211_BAND_2GHZ;
954 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
956 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
958 memcpy(sband->bitrates, &ath5k_rates[0],
959 sizeof(struct ieee80211_rate) * 12);
960 sband->n_bitrates = 12;
962 sband->channels = sc->channels;
963 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
964 AR5K_MODE_11G, max_c);
966 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
967 count_c = sband->n_channels;
969 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
971 memcpy(sband->bitrates, &ath5k_rates[0],
972 sizeof(struct ieee80211_rate) * 4);
973 sband->n_bitrates = 4;
975 /* 5211 only supports B rates and uses 4bit rate codes
976 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
979 if (ah->ah_version == AR5K_AR5211) {
980 for (i = 0; i < 4; i++) {
981 sband->bitrates[i].hw_value =
982 sband->bitrates[i].hw_value & 0xF;
983 sband->bitrates[i].hw_value_short =
984 sband->bitrates[i].hw_value_short & 0xF;
988 sband->channels = sc->channels;
989 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
990 AR5K_MODE_11B, max_c);
992 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
993 count_c = sband->n_channels;
996 ath5k_setup_rate_idx(sc, sband);
998 /* 5GHz band, A mode */
999 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1000 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1001 sband->band = IEEE80211_BAND_5GHZ;
1002 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1004 memcpy(sband->bitrates, &ath5k_rates[4],
1005 sizeof(struct ieee80211_rate) * 8);
1006 sband->n_bitrates = 8;
1008 sband->channels = &sc->channels[count_c];
1009 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1010 AR5K_MODE_11A, max_c);
1012 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1014 ath5k_setup_rate_idx(sc, sband);
1016 ath5k_debug_dump_bands(sc);
1022 * Set/change channels. If the channel is really being changed,
1023 * it's done by reseting the chip. To accomplish this we must
1024 * first cleanup any pending DMA, then restart stuff after a la
1028 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1030 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1031 sc->curchan->center_freq, chan->center_freq);
1033 if (chan->center_freq != sc->curchan->center_freq ||
1034 chan->hw_value != sc->curchan->hw_value) {
1037 sc->curband = &sc->sbands[chan->band];
1040 * To switch channels clear any pending DMA operations;
1041 * wait long enough for the RX fifo to drain, reset the
1042 * hardware at the new frequency, and then re-enable
1043 * the relevant bits of the h/w.
1045 return ath5k_reset(sc, true, true);
1052 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1056 if (mode == AR5K_MODE_11A) {
1057 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1059 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1064 ath5k_mode_setup(struct ath5k_softc *sc)
1066 struct ath5k_hw *ah = sc->ah;
1069 /* configure rx filter */
1070 rfilt = sc->filter_flags;
1071 ath5k_hw_set_rx_filter(ah, rfilt);
1073 if (ath5k_hw_hasbssidmask(ah))
1074 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1076 /* configure operational mode */
1077 ath5k_hw_set_opmode(ah);
1079 ath5k_hw_set_mcast_filter(ah, 0, 0);
1080 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1084 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1086 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1087 return sc->rate_idx[sc->curband->band][hw_rix];
1095 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1097 struct ath5k_hw *ah = sc->ah;
1098 struct sk_buff *skb = bf->skb;
1099 struct ath5k_desc *ds;
1101 if (likely(skb == NULL)) {
1105 * Allocate buffer with headroom_needed space for the
1106 * fake physical layer header at the start.
1108 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1109 if (unlikely(skb == NULL)) {
1110 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1111 sc->rxbufsize + sc->cachelsz - 1);
1115 * Cache-line-align. This is important (for the
1116 * 5210 at least) as not doing so causes bogus data
1119 off = ((unsigned long)skb->data) % sc->cachelsz;
1121 skb_reserve(skb, sc->cachelsz - off);
1124 bf->skbaddr = pci_map_single(sc->pdev,
1125 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1126 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1127 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1135 * Setup descriptors. For receive we always terminate
1136 * the descriptor list with a self-linked entry so we'll
1137 * not get overrun under high load (as can happen with a
1138 * 5212 when ANI processing enables PHY error frames).
1140 * To insure the last descriptor is self-linked we create
1141 * each descriptor as self-linked and add it to the end. As
1142 * each additional descriptor is added the previous self-linked
1143 * entry is ``fixed'' naturally. This should be safe even
1144 * if DMA is happening. When processing RX interrupts we
1145 * never remove/process the last, self-linked, entry on the
1146 * descriptor list. This insures the hardware always has
1147 * someplace to write a new frame.
1150 ds->ds_link = bf->daddr; /* link to self */
1151 ds->ds_data = bf->skbaddr;
1152 ah->ah_setup_rx_desc(ah, ds,
1153 skb_tailroom(skb), /* buffer size */
1156 if (sc->rxlink != NULL)
1157 *sc->rxlink = bf->daddr;
1158 sc->rxlink = &ds->ds_link;
1163 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1165 struct ath5k_hw *ah = sc->ah;
1166 struct ath5k_txq *txq = sc->txq;
1167 struct ath5k_desc *ds = bf->desc;
1168 struct sk_buff *skb = bf->skb;
1169 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1170 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1173 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1175 /* XXX endianness */
1176 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1179 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1180 flags |= AR5K_TXDESC_NOACK;
1184 if (info->control.hw_key) {
1185 keyidx = info->control.hw_key->hw_key_idx;
1186 pktlen += info->control.icv_len;
1188 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1189 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1190 (sc->power_level * 2),
1191 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1192 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1197 ds->ds_data = bf->skbaddr;
1199 spin_lock_bh(&txq->lock);
1200 list_add_tail(&bf->list, &txq->q);
1201 sc->tx_stats[txq->qnum].len++;
1202 if (txq->link == NULL) /* is this first packet? */
1203 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1204 else /* no, so only link it */
1205 *txq->link = bf->daddr;
1207 txq->link = &ds->ds_link;
1208 ath5k_hw_start_tx_dma(ah, txq->qnum);
1210 spin_unlock_bh(&txq->lock);
1214 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1218 /*******************\
1219 * Descriptors setup *
1220 \*******************/
1223 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1225 struct ath5k_desc *ds;
1226 struct ath5k_buf *bf;
1231 /* allocate descriptors */
1232 sc->desc_len = sizeof(struct ath5k_desc) *
1233 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1234 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1235 if (sc->desc == NULL) {
1236 ATH5K_ERR(sc, "can't allocate descriptors\n");
1241 da = sc->desc_daddr;
1242 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1243 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1245 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1246 sizeof(struct ath5k_buf), GFP_KERNEL);
1248 ATH5K_ERR(sc, "can't allocate bufptr\n");
1254 INIT_LIST_HEAD(&sc->rxbuf);
1255 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1258 list_add_tail(&bf->list, &sc->rxbuf);
1261 INIT_LIST_HEAD(&sc->txbuf);
1262 sc->txbuf_len = ATH_TXBUF;
1263 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1264 da += sizeof(*ds)) {
1267 list_add_tail(&bf->list, &sc->txbuf);
1277 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1284 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1286 struct ath5k_buf *bf;
1288 ath5k_txbuf_free(sc, sc->bbuf);
1289 list_for_each_entry(bf, &sc->txbuf, list)
1290 ath5k_txbuf_free(sc, bf);
1291 list_for_each_entry(bf, &sc->rxbuf, list)
1292 ath5k_txbuf_free(sc, bf);
1294 /* Free memory associated with all descriptors */
1295 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1309 static struct ath5k_txq *
1310 ath5k_txq_setup(struct ath5k_softc *sc,
1311 int qtype, int subtype)
1313 struct ath5k_hw *ah = sc->ah;
1314 struct ath5k_txq *txq;
1315 struct ath5k_txq_info qi = {
1316 .tqi_subtype = subtype,
1317 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1318 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1319 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1324 * Enable interrupts only for EOL and DESC conditions.
1325 * We mark tx descriptors to receive a DESC interrupt
1326 * when a tx queue gets deep; otherwise waiting for the
1327 * EOL to reap descriptors. Note that this is done to
1328 * reduce interrupt load and this only defers reaping
1329 * descriptors, never transmitting frames. Aside from
1330 * reducing interrupts this also permits more concurrency.
1331 * The only potential downside is if the tx queue backs
1332 * up in which case the top half of the kernel may backup
1333 * due to a lack of tx descriptors.
1335 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1336 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1337 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1340 * NB: don't print a message, this happens
1341 * normally on parts with too few tx queues
1343 return ERR_PTR(qnum);
1345 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1346 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1347 qnum, ARRAY_SIZE(sc->txqs));
1348 ath5k_hw_release_tx_queue(ah, qnum);
1349 return ERR_PTR(-EINVAL);
1351 txq = &sc->txqs[qnum];
1355 INIT_LIST_HEAD(&txq->q);
1356 spin_lock_init(&txq->lock);
1359 return &sc->txqs[qnum];
1363 ath5k_beaconq_setup(struct ath5k_hw *ah)
1365 struct ath5k_txq_info qi = {
1366 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1367 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1368 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1369 /* NB: for dynamic turbo, don't enable any other interrupts */
1370 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1373 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1377 ath5k_beaconq_config(struct ath5k_softc *sc)
1379 struct ath5k_hw *ah = sc->ah;
1380 struct ath5k_txq_info qi;
1383 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1386 if (sc->opmode == NL80211_IFTYPE_AP ||
1387 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1389 * Always burst out beacon and CAB traffic
1390 * (aifs = cwmin = cwmax = 0)
1395 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1397 * Adhoc mode; backoff between 0 and (2 * cw_min).
1401 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1404 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1405 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1406 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1408 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1410 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1411 "hardware queue!\n", __func__);
1415 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1419 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1421 struct ath5k_buf *bf, *bf0;
1424 * NB: this assumes output has been stopped and
1425 * we do not need to block ath5k_tx_tasklet
1427 spin_lock_bh(&txq->lock);
1428 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1429 ath5k_debug_printtxbuf(sc, bf);
1431 ath5k_txbuf_free(sc, bf);
1433 spin_lock_bh(&sc->txbuflock);
1434 sc->tx_stats[txq->qnum].len--;
1435 list_move_tail(&bf->list, &sc->txbuf);
1437 spin_unlock_bh(&sc->txbuflock);
1440 spin_unlock_bh(&txq->lock);
1444 * Drain the transmit queues and reclaim resources.
1447 ath5k_txq_cleanup(struct ath5k_softc *sc)
1449 struct ath5k_hw *ah = sc->ah;
1452 /* XXX return value */
1453 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1454 /* don't touch the hardware if marked invalid */
1455 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1456 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1457 ath5k_hw_get_txdp(ah, sc->bhalq));
1458 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1459 if (sc->txqs[i].setup) {
1460 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1461 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1464 ath5k_hw_get_txdp(ah,
1469 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1471 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1472 if (sc->txqs[i].setup)
1473 ath5k_txq_drainq(sc, &sc->txqs[i]);
1477 ath5k_txq_release(struct ath5k_softc *sc)
1479 struct ath5k_txq *txq = sc->txqs;
1482 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1484 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1497 * Enable the receive h/w following a reset.
1500 ath5k_rx_start(struct ath5k_softc *sc)
1502 struct ath5k_hw *ah = sc->ah;
1503 struct ath5k_buf *bf;
1506 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1508 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1509 sc->cachelsz, sc->rxbufsize);
1513 spin_lock_bh(&sc->rxbuflock);
1514 list_for_each_entry(bf, &sc->rxbuf, list) {
1515 ret = ath5k_rxbuf_setup(sc, bf);
1517 spin_unlock_bh(&sc->rxbuflock);
1521 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1522 spin_unlock_bh(&sc->rxbuflock);
1524 ath5k_hw_set_rxdp(ah, bf->daddr);
1525 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1526 ath5k_mode_setup(sc); /* set filters, etc. */
1527 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1535 * Disable the receive h/w in preparation for a reset.
1538 ath5k_rx_stop(struct ath5k_softc *sc)
1540 struct ath5k_hw *ah = sc->ah;
1542 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1543 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1544 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1546 ath5k_debug_printrxbuffs(sc, ah);
1548 sc->rxlink = NULL; /* just in case */
1552 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1553 struct sk_buff *skb, struct ath5k_rx_status *rs)
1555 struct ieee80211_hdr *hdr = (void *)skb->data;
1556 unsigned int keyix, hlen;
1558 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1559 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1560 return RX_FLAG_DECRYPTED;
1562 /* Apparently when a default key is used to decrypt the packet
1563 the hw does not set the index used to decrypt. In such cases
1564 get the index from the packet. */
1565 hlen = ieee80211_hdrlen(hdr->frame_control);
1566 if (ieee80211_has_protected(hdr->frame_control) &&
1567 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1568 skb->len >= hlen + 4) {
1569 keyix = skb->data[hlen + 3] >> 6;
1571 if (test_bit(keyix, sc->keymap))
1572 return RX_FLAG_DECRYPTED;
1580 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1581 struct ieee80211_rx_status *rxs)
1585 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1587 if (ieee80211_is_beacon(mgmt->frame_control) &&
1588 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1589 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1591 * Received an IBSS beacon with the same BSSID. Hardware *must*
1592 * have updated the local TSF. We have to work around various
1593 * hardware bugs, though...
1595 tsf = ath5k_hw_get_tsf64(sc->ah);
1596 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1597 hw_tu = TSF_TO_TU(tsf);
1599 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1600 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1601 (unsigned long long)bc_tstamp,
1602 (unsigned long long)rxs->mactime,
1603 (unsigned long long)(rxs->mactime - bc_tstamp),
1604 (unsigned long long)tsf);
1607 * Sometimes the HW will give us a wrong tstamp in the rx
1608 * status, causing the timestamp extension to go wrong.
1609 * (This seems to happen especially with beacon frames bigger
1610 * than 78 byte (incl. FCS))
1611 * But we know that the receive timestamp must be later than the
1612 * timestamp of the beacon since HW must have synced to that.
1614 * NOTE: here we assume mactime to be after the frame was
1615 * received, not like mac80211 which defines it at the start.
1617 if (bc_tstamp > rxs->mactime) {
1618 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1619 "fixing mactime from %llx to %llx\n",
1620 (unsigned long long)rxs->mactime,
1621 (unsigned long long)tsf);
1626 * Local TSF might have moved higher than our beacon timers,
1627 * in that case we have to update them to continue sending
1628 * beacons. This also takes care of synchronizing beacon sending
1629 * times with other stations.
1631 if (hw_tu >= sc->nexttbtt)
1632 ath5k_beacon_update_timers(sc, bc_tstamp);
1638 ath5k_tasklet_rx(unsigned long data)
1640 struct ieee80211_rx_status rxs = {};
1641 struct ath5k_rx_status rs = {};
1642 struct sk_buff *skb;
1643 struct ath5k_softc *sc = (void *)data;
1644 struct ath5k_buf *bf, *bf_last;
1645 struct ath5k_desc *ds;
1650 spin_lock(&sc->rxbuflock);
1651 if (list_empty(&sc->rxbuf)) {
1652 ATH5K_WARN(sc, "empty rx buf pool\n");
1655 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1659 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1660 BUG_ON(bf->skb == NULL);
1665 * last buffer must not be freed to ensure proper hardware
1666 * function. When the hardware finishes also a packet next to
1667 * it, we are sure, it doesn't use it anymore and we can go on.
1672 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1673 struct ath5k_buf, list);
1674 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1679 /* skip the overwritten one (even status is martian) */
1683 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1684 if (unlikely(ret == -EINPROGRESS))
1686 else if (unlikely(ret)) {
1687 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1688 spin_unlock(&sc->rxbuflock);
1692 if (unlikely(rs.rs_more)) {
1693 ATH5K_WARN(sc, "unsupported jumbo\n");
1697 if (unlikely(rs.rs_status)) {
1698 if (rs.rs_status & AR5K_RXERR_PHY)
1700 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1702 * Decrypt error. If the error occurred
1703 * because there was no hardware key, then
1704 * let the frame through so the upper layers
1705 * can process it. This is necessary for 5210
1706 * parts which have no way to setup a ``clear''
1709 * XXX do key cache faulting
1711 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1712 !(rs.rs_status & AR5K_RXERR_CRC))
1715 if (rs.rs_status & AR5K_RXERR_MIC) {
1716 rxs.flag |= RX_FLAG_MMIC_ERROR;
1720 /* let crypto-error packets fall through in MNTR */
1722 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1723 sc->opmode != NL80211_IFTYPE_MONITOR)
1727 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1728 PCI_DMA_FROMDEVICE);
1731 skb_put(skb, rs.rs_datalen);
1734 * the hardware adds a padding to 4 byte boundaries between
1735 * the header and the payload data if the header length is
1736 * not multiples of 4 - remove it
1738 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1741 memmove(skb->data + pad, skb->data, hdrlen);
1746 * always extend the mac timestamp, since this information is
1747 * also needed for proper IBSS merging.
1749 * XXX: it might be too late to do it here, since rs_tstamp is
1750 * 15bit only. that means TSF extension has to be done within
1751 * 32768usec (about 32ms). it might be necessary to move this to
1752 * the interrupt handler, like it is done in madwifi.
1754 * Unfortunately we don't know when the hardware takes the rx
1755 * timestamp (beginning of phy frame, data frame, end of rx?).
1756 * The only thing we know is that it is hardware specific...
1757 * On AR5213 it seems the rx timestamp is at the end of the
1758 * frame, but i'm not sure.
1760 * NOTE: mac80211 defines mactime at the beginning of the first
1761 * data symbol. Since we don't have any time references it's
1762 * impossible to comply to that. This affects IBSS merge only
1763 * right now, so it's not too bad...
1765 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1766 rxs.flag |= RX_FLAG_TSFT;
1768 rxs.freq = sc->curchan->center_freq;
1769 rxs.band = sc->curband->band;
1771 rxs.noise = sc->ah->ah_noise_floor;
1772 rxs.signal = rxs.noise + rs.rs_rssi;
1773 rxs.qual = rs.rs_rssi * 100 / 64;
1775 rxs.antenna = rs.rs_antenna;
1776 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1777 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1779 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1780 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1781 rxs.flag |= RX_FLAG_SHORTPRE;
1783 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1785 /* check beacons in IBSS mode */
1786 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1787 ath5k_check_ibss_tsf(sc, skb, &rxs);
1789 __ieee80211_rx(sc->hw, skb, &rxs);
1791 list_move_tail(&bf->list, &sc->rxbuf);
1792 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1794 spin_unlock(&sc->rxbuflock);
1805 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1807 struct ath5k_tx_status ts = {};
1808 struct ath5k_buf *bf, *bf0;
1809 struct ath5k_desc *ds;
1810 struct sk_buff *skb;
1811 struct ieee80211_tx_info *info;
1814 spin_lock(&txq->lock);
1815 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1818 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1819 if (unlikely(ret == -EINPROGRESS))
1821 else if (unlikely(ret)) {
1822 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1828 info = IEEE80211_SKB_CB(skb);
1831 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1834 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1835 if (unlikely(ts.ts_status)) {
1836 sc->ll_stats.dot11ACKFailureCount++;
1837 if (ts.ts_status & AR5K_TXERR_XRETRY)
1838 info->status.excessive_retries = 1;
1839 else if (ts.ts_status & AR5K_TXERR_FILT)
1840 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1842 info->flags |= IEEE80211_TX_STAT_ACK;
1843 info->status.ack_signal = ts.ts_rssi;
1846 ieee80211_tx_status(sc->hw, skb);
1847 sc->tx_stats[txq->qnum].count++;
1849 spin_lock(&sc->txbuflock);
1850 sc->tx_stats[txq->qnum].len--;
1851 list_move_tail(&bf->list, &sc->txbuf);
1853 spin_unlock(&sc->txbuflock);
1855 if (likely(list_empty(&txq->q)))
1857 spin_unlock(&txq->lock);
1858 if (sc->txbuf_len > ATH_TXBUF / 5)
1859 ieee80211_wake_queues(sc->hw);
1863 ath5k_tasklet_tx(unsigned long data)
1865 struct ath5k_softc *sc = (void *)data;
1867 ath5k_tx_processq(sc, sc->txq);
1876 * Setup the beacon frame for transmit.
1879 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1881 struct sk_buff *skb = bf->skb;
1882 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1883 struct ath5k_hw *ah = sc->ah;
1884 struct ath5k_desc *ds;
1885 int ret, antenna = 0;
1888 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1890 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1891 "skbaddr %llx\n", skb, skb->data, skb->len,
1892 (unsigned long long)bf->skbaddr);
1893 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1894 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1900 flags = AR5K_TXDESC_NOACK;
1901 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1902 ds->ds_link = bf->daddr; /* self-linked */
1903 flags |= AR5K_TXDESC_VEOL;
1905 * Let hardware handle antenna switching if txantenna is not set
1910 * Switch antenna every 4 beacons if txantenna is not set
1911 * XXX assumes two antennas
1914 antenna = sc->bsent & 4 ? 2 : 1;
1917 ds->ds_data = bf->skbaddr;
1918 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1919 ieee80211_get_hdrlen_from_skb(skb),
1920 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1921 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1922 1, AR5K_TXKEYIX_INVALID,
1923 antenna, flags, 0, 0);
1929 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1934 * Transmit a beacon frame at SWBA. Dynamic updates to the
1935 * frame contents are done as needed and the slot time is
1936 * also adjusted based on current state.
1938 * this is usually called from interrupt context (ath5k_intr())
1939 * but also from ath5k_beacon_config() in IBSS mode which in turn
1940 * can be called from a tasklet and user context
1943 ath5k_beacon_send(struct ath5k_softc *sc)
1945 struct ath5k_buf *bf = sc->bbuf;
1946 struct ath5k_hw *ah = sc->ah;
1948 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1950 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1951 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1952 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1956 * Check if the previous beacon has gone out. If
1957 * not don't don't try to post another, skip this
1958 * period and wait for the next. Missed beacons
1959 * indicate a problem and should not occur. If we
1960 * miss too many consecutive beacons reset the device.
1962 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1964 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1965 "missed %u consecutive beacons\n", sc->bmisscount);
1966 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1967 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1968 "stuck beacon time (%u missed)\n",
1970 tasklet_schedule(&sc->restq);
1974 if (unlikely(sc->bmisscount != 0)) {
1975 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1976 "resume beacon xmit after %u misses\n",
1982 * Stop any current dma and put the new frame on the queue.
1983 * This should never fail since we check above that no frames
1984 * are still pending on the queue.
1986 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1987 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1988 /* NB: hw still stops DMA, so proceed */
1991 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1992 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1993 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1994 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2001 * ath5k_beacon_update_timers - update beacon timers
2003 * @sc: struct ath5k_softc pointer we are operating on
2004 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2005 * beacon timer update based on the current HW TSF.
2007 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2008 * of a received beacon or the current local hardware TSF and write it to the
2009 * beacon timer registers.
2011 * This is called in a variety of situations, e.g. when a beacon is received,
2012 * when a TSF update has been detected, but also when an new IBSS is created or
2013 * when we otherwise know we have to update the timers, but we keep it in this
2014 * function to have it all together in one place.
2017 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2019 struct ath5k_hw *ah = sc->ah;
2020 u32 nexttbtt, intval, hw_tu, bc_tu;
2023 intval = sc->bintval & AR5K_BEACON_PERIOD;
2024 if (WARN_ON(!intval))
2027 /* beacon TSF converted to TU */
2028 bc_tu = TSF_TO_TU(bc_tsf);
2030 /* current TSF converted to TU */
2031 hw_tsf = ath5k_hw_get_tsf64(ah);
2032 hw_tu = TSF_TO_TU(hw_tsf);
2035 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2038 * no beacons received, called internally.
2039 * just need to refresh timers based on HW TSF.
2041 nexttbtt = roundup(hw_tu + FUDGE, intval);
2042 } else if (bc_tsf == 0) {
2044 * no beacon received, probably called by ath5k_reset_tsf().
2045 * reset TSF to start with 0.
2048 intval |= AR5K_BEACON_RESET_TSF;
2049 } else if (bc_tsf > hw_tsf) {
2051 * beacon received, SW merge happend but HW TSF not yet updated.
2052 * not possible to reconfigure timers yet, but next time we
2053 * receive a beacon with the same BSSID, the hardware will
2054 * automatically update the TSF and then we need to reconfigure
2057 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2058 "need to wait for HW TSF sync\n");
2062 * most important case for beacon synchronization between STA.
2064 * beacon received and HW TSF has been already updated by HW.
2065 * update next TBTT based on the TSF of the beacon, but make
2066 * sure it is ahead of our local TSF timer.
2068 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2072 sc->nexttbtt = nexttbtt;
2074 intval |= AR5K_BEACON_ENA;
2075 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2078 * debugging output last in order to preserve the time critical aspect
2082 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2083 "reconfigured timers based on HW TSF\n");
2084 else if (bc_tsf == 0)
2085 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2086 "reset HW TSF and timers\n");
2088 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2089 "updated timers based on beacon TSF\n");
2091 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2092 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2093 (unsigned long long) bc_tsf,
2094 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2095 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2096 intval & AR5K_BEACON_PERIOD,
2097 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2098 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2103 * ath5k_beacon_config - Configure the beacon queues and interrupts
2105 * @sc: struct ath5k_softc pointer we are operating on
2107 * When operating in station mode we want to receive a BMISS interrupt when we
2108 * stop seeing beacons from the AP we've associated with so we can look for
2109 * another AP to associate with.
2111 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2112 * interrupts to detect TSF updates only.
2114 * AP mode is missing.
2117 ath5k_beacon_config(struct ath5k_softc *sc)
2119 struct ath5k_hw *ah = sc->ah;
2121 ath5k_hw_set_imr(ah, 0);
2123 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2125 if (sc->opmode == NL80211_IFTYPE_STATION) {
2126 sc->imask |= AR5K_INT_BMISS;
2127 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2129 * In IBSS mode we use a self-linked tx descriptor and let the
2130 * hardware send the beacons automatically. We have to load it
2132 * We use the SWBA interrupt only to keep track of the beacon
2133 * timers in order to detect automatic TSF updates.
2135 ath5k_beaconq_config(sc);
2137 sc->imask |= AR5K_INT_SWBA;
2139 if (ath5k_hw_hasveol(ah)) {
2140 spin_lock(&sc->block);
2141 ath5k_beacon_send(sc);
2142 spin_unlock(&sc->block);
2147 ath5k_hw_set_imr(ah, sc->imask);
2151 /********************\
2152 * Interrupt handling *
2153 \********************/
2156 ath5k_init(struct ath5k_softc *sc)
2160 mutex_lock(&sc->lock);
2162 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2165 * Stop anything previously setup. This is safe
2166 * no matter this is the first time through or not.
2168 ath5k_stop_locked(sc);
2171 * The basic interface to setting the hardware in a good
2172 * state is ``reset''. On return the hardware is known to
2173 * be powered up and with interrupts disabled. This must
2174 * be followed by initialization of the appropriate bits
2175 * and then setup of the interrupt mask.
2177 sc->curchan = sc->hw->conf.channel;
2178 sc->curband = &sc->sbands[sc->curchan->band];
2179 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2180 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2182 ret = ath5k_reset(sc, false, false);
2186 /* Set ack to be sent at low bit-rates */
2187 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2189 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2190 msecs_to_jiffies(ath5k_calinterval * 1000)));
2195 mutex_unlock(&sc->lock);
2200 ath5k_stop_locked(struct ath5k_softc *sc)
2202 struct ath5k_hw *ah = sc->ah;
2204 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2205 test_bit(ATH_STAT_INVALID, sc->status));
2208 * Shutdown the hardware and driver:
2209 * stop output from above
2210 * disable interrupts
2212 * turn off the radio
2213 * clear transmit machinery
2214 * clear receive machinery
2215 * drain and release tx queues
2216 * reclaim beacon resources
2217 * power down hardware
2219 * Note that some of this work is not possible if the
2220 * hardware is gone (invalid).
2222 ieee80211_stop_queues(sc->hw);
2224 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2226 ath5k_hw_set_imr(ah, 0);
2227 synchronize_irq(sc->pdev->irq);
2229 ath5k_txq_cleanup(sc);
2230 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2232 ath5k_hw_phy_disable(ah);
2240 * Stop the device, grabbing the top-level lock to protect
2241 * against concurrent entry through ath5k_init (which can happen
2242 * if another thread does a system call and the thread doing the
2243 * stop is preempted).
2246 ath5k_stop_hw(struct ath5k_softc *sc)
2250 mutex_lock(&sc->lock);
2251 ret = ath5k_stop_locked(sc);
2252 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2254 * Set the chip in full sleep mode. Note that we are
2255 * careful to do this only when bringing the interface
2256 * completely to a stop. When the chip is in this state
2257 * it must be carefully woken up or references to
2258 * registers in the PCI clock domain may freeze the bus
2259 * (and system). This varies by chip and is mostly an
2260 * issue with newer parts that go to sleep more quickly.
2262 if (sc->ah->ah_mac_srev >= 0x78) {
2265 * don't put newer MAC revisions > 7.8 to sleep because
2266 * of the above mentioned problems
2268 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2269 "not putting device to sleep\n");
2271 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2272 "putting device to full sleep\n");
2273 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2276 ath5k_txbuf_free(sc, sc->bbuf);
2278 mutex_unlock(&sc->lock);
2280 del_timer_sync(&sc->calib_tim);
2281 tasklet_kill(&sc->rxtq);
2282 tasklet_kill(&sc->txtq);
2283 tasklet_kill(&sc->restq);
2289 ath5k_intr(int irq, void *dev_id)
2291 struct ath5k_softc *sc = dev_id;
2292 struct ath5k_hw *ah = sc->ah;
2293 enum ath5k_int status;
2294 unsigned int counter = 1000;
2296 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2297 !ath5k_hw_is_intr_pending(ah)))
2302 * Figure out the reason(s) for the interrupt. Note
2303 * that get_isr returns a pseudo-ISR that may include
2304 * bits we haven't explicitly enabled so we mask the
2305 * value to insure we only process bits we requested.
2307 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2308 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2310 status &= sc->imask; /* discard unasked for bits */
2311 if (unlikely(status & AR5K_INT_FATAL)) {
2313 * Fatal errors are unrecoverable.
2314 * Typically these are caused by DMA errors.
2316 tasklet_schedule(&sc->restq);
2317 } else if (unlikely(status & AR5K_INT_RXORN)) {
2318 tasklet_schedule(&sc->restq);
2320 if (status & AR5K_INT_SWBA) {
2322 * Software beacon alert--time to send a beacon.
2323 * Handle beacon transmission directly; deferring
2324 * this is too slow to meet timing constraints
2327 * In IBSS mode we use this interrupt just to
2328 * keep track of the next TBTT (target beacon
2329 * transmission time) in order to detect wether
2330 * automatic TSF updates happened.
2332 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2333 /* XXX: only if VEOL suppported */
2334 u64 tsf = ath5k_hw_get_tsf64(ah);
2335 sc->nexttbtt += sc->bintval;
2336 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2337 "SWBA nexttbtt: %x hw_tu: %x "
2341 (unsigned long long) tsf);
2343 spin_lock(&sc->block);
2344 ath5k_beacon_send(sc);
2345 spin_unlock(&sc->block);
2348 if (status & AR5K_INT_RXEOL) {
2350 * NB: the hardware should re-read the link when
2351 * RXE bit is written, but it doesn't work at
2352 * least on older hardware revs.
2356 if (status & AR5K_INT_TXURN) {
2357 /* bump tx trigger level */
2358 ath5k_hw_update_tx_triglevel(ah, true);
2360 if (status & AR5K_INT_RX)
2361 tasklet_schedule(&sc->rxtq);
2362 if (status & AR5K_INT_TX)
2363 tasklet_schedule(&sc->txtq);
2364 if (status & AR5K_INT_BMISS) {
2366 if (status & AR5K_INT_MIB) {
2368 * These stats are also used for ANI i think
2369 * so how about updating them more often ?
2371 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2374 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2376 if (unlikely(!counter))
2377 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2383 ath5k_tasklet_reset(unsigned long data)
2385 struct ath5k_softc *sc = (void *)data;
2387 ath5k_reset_wake(sc);
2391 * Periodically recalibrate the PHY to account
2392 * for temperature/environment changes.
2395 ath5k_calibrate(unsigned long data)
2397 struct ath5k_softc *sc = (void *)data;
2398 struct ath5k_hw *ah = sc->ah;
2400 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2401 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2402 sc->curchan->hw_value);
2404 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2406 * Rfgain is out of bounds, reset the chip
2407 * to load new gain values.
2409 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2410 ath5k_reset_wake(sc);
2412 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2413 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2414 ieee80211_frequency_to_channel(
2415 sc->curchan->center_freq));
2417 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2418 msecs_to_jiffies(ath5k_calinterval * 1000)));
2428 ath5k_led_enable(struct ath5k_softc *sc)
2430 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2431 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2437 ath5k_led_on(struct ath5k_softc *sc)
2439 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2441 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2445 ath5k_led_off(struct ath5k_softc *sc)
2447 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2449 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2453 ath5k_led_brightness_set(struct led_classdev *led_dev,
2454 enum led_brightness brightness)
2456 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2459 if (brightness == LED_OFF)
2460 ath5k_led_off(led->sc);
2462 ath5k_led_on(led->sc);
2466 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2467 const char *name, char *trigger)
2472 strncpy(led->name, name, sizeof(led->name));
2473 led->led_dev.name = led->name;
2474 led->led_dev.default_trigger = trigger;
2475 led->led_dev.brightness_set = ath5k_led_brightness_set;
2477 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2480 ATH5K_WARN(sc, "could not register LED %s\n", name);
2487 ath5k_unregister_led(struct ath5k_led *led)
2491 led_classdev_unregister(&led->led_dev);
2492 ath5k_led_off(led->sc);
2497 ath5k_unregister_leds(struct ath5k_softc *sc)
2499 ath5k_unregister_led(&sc->rx_led);
2500 ath5k_unregister_led(&sc->tx_led);
2505 ath5k_init_leds(struct ath5k_softc *sc)
2508 struct ieee80211_hw *hw = sc->hw;
2509 struct pci_dev *pdev = sc->pdev;
2510 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2513 * Auto-enable soft led processing for IBM cards and for
2514 * 5211 minipci cards.
2516 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2517 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2518 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2520 sc->led_on = 0; /* active low */
2522 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2523 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2524 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2526 sc->led_on = 1; /* active high */
2528 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2531 ath5k_led_enable(sc);
2533 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2534 ret = ath5k_register_led(sc, &sc->rx_led, name,
2535 ieee80211_get_rx_led_name(hw));
2539 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2540 ret = ath5k_register_led(sc, &sc->tx_led, name,
2541 ieee80211_get_tx_led_name(hw));
2547 /********************\
2548 * Mac80211 functions *
2549 \********************/
2552 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2554 struct ath5k_softc *sc = hw->priv;
2555 struct ath5k_buf *bf;
2556 unsigned long flags;
2560 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2562 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2563 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2566 * the hardware expects the header padded to 4 byte boundaries
2567 * if this is not the case we add the padding after the header
2569 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2572 if (skb_headroom(skb) < pad) {
2573 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2574 " headroom to pad %d\n", hdrlen, pad);
2578 memmove(skb->data, skb->data+pad, hdrlen);
2581 spin_lock_irqsave(&sc->txbuflock, flags);
2582 if (list_empty(&sc->txbuf)) {
2583 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2584 spin_unlock_irqrestore(&sc->txbuflock, flags);
2585 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2588 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2589 list_del(&bf->list);
2591 if (list_empty(&sc->txbuf))
2592 ieee80211_stop_queues(hw);
2593 spin_unlock_irqrestore(&sc->txbuflock, flags);
2597 if (ath5k_txbuf_setup(sc, bf)) {
2599 spin_lock_irqsave(&sc->txbuflock, flags);
2600 list_add_tail(&bf->list, &sc->txbuf);
2602 spin_unlock_irqrestore(&sc->txbuflock, flags);
2603 dev_kfree_skb_any(skb);
2611 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2613 struct ath5k_hw *ah = sc->ah;
2616 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2619 ath5k_hw_set_imr(ah, 0);
2620 ath5k_txq_cleanup(sc);
2623 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2625 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2630 * This is needed only to setup initial state
2631 * but it's best done after a reset.
2633 ath5k_hw_set_txpower_limit(sc->ah, 0);
2635 ret = ath5k_rx_start(sc);
2637 ATH5K_ERR(sc, "can't start recv logic\n");
2642 * Change channels and update the h/w rate map if we're switching;
2643 * e.g. 11a to 11b/g.
2645 * We may be doing a reset in response to an ioctl that changes the
2646 * channel so update any state that might change as a result.
2650 /* ath5k_chan_change(sc, c); */
2652 ath5k_beacon_config(sc);
2653 /* intrs are enabled by ath5k_beacon_config */
2661 ath5k_reset_wake(struct ath5k_softc *sc)
2665 ret = ath5k_reset(sc, true, true);
2667 ieee80211_wake_queues(sc->hw);
2672 static int ath5k_start(struct ieee80211_hw *hw)
2674 return ath5k_init(hw->priv);
2677 static void ath5k_stop(struct ieee80211_hw *hw)
2679 ath5k_stop_hw(hw->priv);
2682 static int ath5k_add_interface(struct ieee80211_hw *hw,
2683 struct ieee80211_if_init_conf *conf)
2685 struct ath5k_softc *sc = hw->priv;
2688 mutex_lock(&sc->lock);
2694 sc->vif = conf->vif;
2696 switch (conf->type) {
2697 case NL80211_IFTYPE_STATION:
2698 case NL80211_IFTYPE_ADHOC:
2699 case NL80211_IFTYPE_MONITOR:
2700 sc->opmode = conf->type;
2707 /* Set to a reasonable value. Note that this will
2708 * be set to mac80211's value at ath5k_config(). */
2713 mutex_unlock(&sc->lock);
2718 ath5k_remove_interface(struct ieee80211_hw *hw,
2719 struct ieee80211_if_init_conf *conf)
2721 struct ath5k_softc *sc = hw->priv;
2723 mutex_lock(&sc->lock);
2724 if (sc->vif != conf->vif)
2729 mutex_unlock(&sc->lock);
2733 * TODO: Phy disable/diversity etc
2736 ath5k_config(struct ieee80211_hw *hw,
2737 struct ieee80211_conf *conf)
2739 struct ath5k_softc *sc = hw->priv;
2741 sc->bintval = conf->beacon_int;
2742 sc->power_level = conf->power_level;
2744 return ath5k_chan_set(sc, conf->channel);
2748 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2749 struct ieee80211_if_conf *conf)
2751 struct ath5k_softc *sc = hw->priv;
2752 struct ath5k_hw *ah = sc->ah;
2755 mutex_lock(&sc->lock);
2756 if (sc->vif != vif) {
2761 /* Cache for later use during resets */
2762 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2763 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2764 * a clean way of letting us retrieve this yet. */
2765 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2769 if (conf->changed & IEEE80211_IFCC_BEACON &&
2770 vif->type == NL80211_IFTYPE_ADHOC) {
2771 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2776 /* call old handler for now */
2777 ath5k_beacon_update(hw, beacon);
2780 mutex_unlock(&sc->lock);
2782 return ath5k_reset_wake(sc);
2784 mutex_unlock(&sc->lock);
2788 #define SUPPORTED_FIF_FLAGS \
2789 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2790 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2791 FIF_BCN_PRBRESP_PROMISC
2793 * o always accept unicast, broadcast, and multicast traffic
2794 * o multicast traffic for all BSSIDs will be enabled if mac80211
2796 * o maintain current state of phy ofdm or phy cck error reception.
2797 * If the hardware detects any of these type of errors then
2798 * ath5k_hw_get_rx_filter() will pass to us the respective
2799 * hardware filters to be able to receive these type of frames.
2800 * o probe request frames are accepted only when operating in
2801 * hostap, adhoc, or monitor modes
2802 * o enable promiscuous mode according to the interface state
2804 * - when operating in adhoc mode so the 802.11 layer creates
2805 * node table entries for peers,
2806 * - when operating in station mode for collecting rssi data when
2807 * the station is otherwise quiet, or
2810 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2811 unsigned int changed_flags,
2812 unsigned int *new_flags,
2813 int mc_count, struct dev_mc_list *mclist)
2815 struct ath5k_softc *sc = hw->priv;
2816 struct ath5k_hw *ah = sc->ah;
2817 u32 mfilt[2], val, rfilt;
2824 /* Only deal with supported flags */
2825 changed_flags &= SUPPORTED_FIF_FLAGS;
2826 *new_flags &= SUPPORTED_FIF_FLAGS;
2828 /* If HW detects any phy or radar errors, leave those filters on.
2829 * Also, always enable Unicast, Broadcasts and Multicast
2830 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2831 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2832 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2833 AR5K_RX_FILTER_MCAST);
2835 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2836 if (*new_flags & FIF_PROMISC_IN_BSS) {
2837 rfilt |= AR5K_RX_FILTER_PROM;
2838 __set_bit(ATH_STAT_PROMISC, sc->status);
2841 __clear_bit(ATH_STAT_PROMISC, sc->status);
2844 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2845 if (*new_flags & FIF_ALLMULTI) {
2849 for (i = 0; i < mc_count; i++) {
2852 /* calculate XOR of eight 6-bit values */
2853 val = get_unaligned_le32(mclist->dmi_addr + 0);
2854 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2855 val = get_unaligned_le32(mclist->dmi_addr + 3);
2856 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2858 mfilt[pos / 32] |= (1 << (pos % 32));
2859 /* XXX: we might be able to just do this instead,
2860 * but not sure, needs testing, if we do use this we'd
2861 * neet to inform below to not reset the mcast */
2862 /* ath5k_hw_set_mcast_filterindex(ah,
2863 * mclist->dmi_addr[5]); */
2864 mclist = mclist->next;
2868 /* This is the best we can do */
2869 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2870 rfilt |= AR5K_RX_FILTER_PHYERR;
2872 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2873 * and probes for any BSSID, this needs testing */
2874 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2875 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2877 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2878 * set we should only pass on control frames for this
2879 * station. This needs testing. I believe right now this
2880 * enables *all* control frames, which is OK.. but
2881 * but we should see if we can improve on granularity */
2882 if (*new_flags & FIF_CONTROL)
2883 rfilt |= AR5K_RX_FILTER_CONTROL;
2885 /* Additional settings per mode -- this is per ath5k */
2887 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2889 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2890 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2891 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2892 if (sc->opmode != NL80211_IFTYPE_STATION)
2893 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2894 if (sc->opmode != NL80211_IFTYPE_AP &&
2895 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2896 test_bit(ATH_STAT_PROMISC, sc->status))
2897 rfilt |= AR5K_RX_FILTER_PROM;
2898 if (sc->opmode == NL80211_IFTYPE_STATION ||
2899 sc->opmode == NL80211_IFTYPE_ADHOC) {
2900 rfilt |= AR5K_RX_FILTER_BEACON;
2904 ath5k_hw_set_rx_filter(ah,rfilt);
2906 /* Set multicast bits */
2907 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2908 /* Set the cached hw filter flags, this will alter actually
2910 sc->filter_flags = rfilt;
2914 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2915 const u8 *local_addr, const u8 *addr,
2916 struct ieee80211_key_conf *key)
2918 struct ath5k_softc *sc = hw->priv;
2923 /* XXX: fix hardware encryption, its not working. For now
2924 * allow software encryption */
2934 mutex_lock(&sc->lock);
2938 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2940 ATH5K_ERR(sc, "can't set the key\n");
2943 __set_bit(key->keyidx, sc->keymap);
2944 key->hw_key_idx = key->keyidx;
2947 ath5k_hw_reset_key(sc->ah, key->keyidx);
2948 __clear_bit(key->keyidx, sc->keymap);
2957 mutex_unlock(&sc->lock);
2962 ath5k_get_stats(struct ieee80211_hw *hw,
2963 struct ieee80211_low_level_stats *stats)
2965 struct ath5k_softc *sc = hw->priv;
2966 struct ath5k_hw *ah = sc->ah;
2969 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2971 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2977 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2978 struct ieee80211_tx_queue_stats *stats)
2980 struct ath5k_softc *sc = hw->priv;
2982 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2988 ath5k_get_tsf(struct ieee80211_hw *hw)
2990 struct ath5k_softc *sc = hw->priv;
2992 return ath5k_hw_get_tsf64(sc->ah);
2996 ath5k_reset_tsf(struct ieee80211_hw *hw)
2998 struct ath5k_softc *sc = hw->priv;
3001 * in IBSS mode we need to update the beacon timers too.
3002 * this will also reset the TSF if we call it with 0
3004 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3005 ath5k_beacon_update_timers(sc, 0);
3007 ath5k_hw_reset_tsf(sc->ah);
3011 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3013 struct ath5k_softc *sc = hw->priv;
3014 unsigned long flags;
3017 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3019 if (sc->opmode != NL80211_IFTYPE_ADHOC) {
3024 spin_lock_irqsave(&sc->block, flags);
3025 ath5k_txbuf_free(sc, sc->bbuf);
3026 sc->bbuf->skb = skb;
3027 ret = ath5k_beacon_setup(sc, sc->bbuf);
3029 sc->bbuf->skb = NULL;
3030 spin_unlock_irqrestore(&sc->block, flags);
3032 ath5k_beacon_config(sc);