2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
52 /* Macro to expand scalars to 64-bit objects */
54 #define ito64(x) (sizeof(x) == 8) ? \
55 (((unsigned long long int)(x)) & (0xff)) : \
57 (((unsigned long long int)(x)) & 0xffff) : \
58 ((sizeof(x) == 32) ? \
59 (((unsigned long long int)(x)) & 0xffffffff) : \
60 (unsigned long long int)(x))
62 /* increment with wrap-around */
63 #define INCR(_l, _sz) do { \
65 (_l) &= ((_sz) - 1); \
68 /* decrement with wrap-around */
69 #define DECR(_l, _sz) do { \
71 (_l) &= ((_sz) - 1); \
74 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
76 #define ASSERT(exp) do { \
77 if (unlikely(!(exp))) { \
83 #define memzero(_buf, _len) memset(_buf, 0, _len)
85 #define get_dma_mem_context(var, field) (&((var)->field))
86 #define copy_dma_mem_context(dst, src) (*dst = *src)
88 #define ATH9K_BH_STATUS_INTACT 0
89 #define ATH9K_BH_STATUS_CHANGE 1
91 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
93 static inline unsigned long get_timestamp(void)
95 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
98 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
105 ATH_DBG_RESET = 0x00000001,
106 ATH_DBG_PHY_IO = 0x00000002,
107 ATH_DBG_REG_IO = 0x00000004,
108 ATH_DBG_QUEUE = 0x00000008,
109 ATH_DBG_EEPROM = 0x00000010,
110 ATH_DBG_NF_CAL = 0x00000020,
111 ATH_DBG_CALIBRATE = 0x00000040,
112 ATH_DBG_CHANNEL = 0x00000080,
113 ATH_DBG_INTERRUPT = 0x00000100,
114 ATH_DBG_REGULATORY = 0x00000200,
115 ATH_DBG_ANI = 0x00000400,
116 ATH_DBG_POWER_MGMT = 0x00000800,
117 ATH_DBG_XMIT = 0x00001000,
118 ATH_DBG_BEACON = 0x00002000,
119 ATH_DBG_RATE = 0x00004000,
120 ATH_DBG_CONFIG = 0x00008000,
121 ATH_DBG_KEYCACHE = 0x00010000,
122 ATH_DBG_AGGR = 0x00020000,
123 ATH_DBG_FATAL = 0x00040000,
124 ATH_DBG_ANY = 0xffffffff
127 #define DBG_DEFAULT (ATH_DBG_FATAL)
129 #define DPRINTF(sc, _m, _fmt, ...) do { \
130 if (sc->sc_debug & (_m)) \
131 printk(_fmt , ##__VA_ARGS__); \
134 /***************************/
135 /* Load-time Configuration */
136 /***************************/
138 /* Per-instance load-time (note: NOT run-time) configurations
139 * for Atheros Device */
143 u16 txpowlimit_override;
144 u8 cabqReadytime; /* Cabq Readytime % */
145 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
148 /***********************/
149 /* Chainmask Selection */
150 /***********************/
152 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
153 /* Default - Number of last RSSI values that is used for
154 * chainmask selection */
155 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
156 /* Means use 3x3 chainmask instead of configured chainmask */
157 #define ATH_CHAINMASK_SEL_3X3 7
158 /* Default - Rssi threshold below which we have to switch to 3x3 */
159 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
160 /* Default - Rssi threshold above which we have to switch to
161 * user configured values */
162 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
163 /* Struct to store the chainmask select related info */
164 struct ath_chainmask_sel {
165 struct timer_list timer;
166 int cur_tx_mask; /* user configured or 3x3 */
167 int cur_rx_mask; /* user configured or 3x3 */
169 u8 switch_allowed:1, /* timer will set this */
173 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
174 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
176 /*************************/
177 /* Descriptor Management */
178 /*************************/
180 /* Number of descriptors per buffer. The only case where we see skbuff
181 chains is due to FF aggregation in the driver. */
183 /* if there's more fragment for this MSDU */
184 #define ATH_BF_MORE_MPDU 1
185 #define ATH_TXBUF_RESET(_bf) do { \
186 (_bf)->bf_status = 0; \
187 (_bf)->bf_lastbf = NULL; \
188 (_bf)->bf_lastfrm = NULL; \
189 (_bf)->bf_next = NULL; \
190 memzero(&((_bf)->bf_state), \
191 sizeof(struct ath_buf_state)); \
194 struct ath_buf_state {
195 int bfs_nframes; /* # frames in aggregate */
196 u16 bfs_al; /* length of aggregate */
197 u16 bfs_frmlen; /* length of frame */
198 int bfs_seqno; /* sequence number */
199 int bfs_tidno; /* tid of this frame */
200 int bfs_retries; /* current retries */
201 struct ath_rc_series bfs_rcs[4]; /* rate series */
202 u8 bfs_isdata:1; /* is a data frame/aggregate */
203 u8 bfs_isaggr:1; /* is an aggregate */
204 u8 bfs_isampdu:1; /* is an a-mpdu, aggregate or not */
205 u8 bfs_ht:1; /* is an HT frame */
206 u8 bfs_isretried:1; /* is retried */
207 u8 bfs_isxretried:1; /* is excessive retried */
208 u8 bfs_shpreamble:1; /* is short preamble */
209 u8 bfs_isbar:1; /* is a BAR */
210 u8 bfs_ispspoll:1; /* is a PS-Poll */
211 u8 bfs_aggrburst:1; /* is a aggr burst */
212 u8 bfs_calcairtime:1; /* requests airtime be calculated
213 when set for tx frame */
214 int bfs_rifsburst_elem; /* RIFS burst/bar */
215 int bfs_nrifsubframes; /* # of elements in burst */
216 /* key type use to encrypt this frame */
217 enum ath9k_key_type bfs_keytype;
220 #define bf_nframes bf_state.bfs_nframes
221 #define bf_al bf_state.bfs_al
222 #define bf_frmlen bf_state.bfs_frmlen
223 #define bf_retries bf_state.bfs_retries
224 #define bf_seqno bf_state.bfs_seqno
225 #define bf_tidno bf_state.bfs_tidno
226 #define bf_rcs bf_state.bfs_rcs
227 #define bf_isdata bf_state.bfs_isdata
228 #define bf_isaggr bf_state.bfs_isaggr
229 #define bf_isampdu bf_state.bfs_isampdu
230 #define bf_ht bf_state.bfs_ht
231 #define bf_isretried bf_state.bfs_isretried
232 #define bf_isxretried bf_state.bfs_isxretried
233 #define bf_shpreamble bf_state.bfs_shpreamble
234 #define bf_rifsburst_elem bf_state.bfs_rifsburst_elem
235 #define bf_nrifsubframes bf_state.bfs_nrifsubframes
236 #define bf_keytype bf_state.bfs_keytype
237 #define bf_isbar bf_state.bfs_isbar
238 #define bf_ispspoll bf_state.bfs_ispspoll
239 #define bf_aggrburst bf_state.bfs_aggrburst
240 #define bf_calcairtime bf_state.bfs_calcairtime
243 * Abstraction of a contiguous buffer to transmit/receive. There is only
244 * a single hw descriptor encapsulated here.
248 struct list_head list;
249 struct list_head *last;
250 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
252 struct ath_buf *bf_lastfrm; /* last buf of this frame */
253 struct ath_buf *bf_next; /* next subframe in the aggregate */
254 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
255 void *bf_mpdu; /* enclosing frame structure */
256 void *bf_node; /* pointer to the node */
257 struct ath_desc *bf_desc; /* virtual addr of desc */
258 dma_addr_t bf_daddr; /* physical addr of desc */
259 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
261 u16 bf_flags; /* tx descriptor flags */
262 struct ath_buf_state bf_state; /* buffer state */
263 dma_addr_t bf_dmacontext;
267 * reset the rx buffer.
268 * any new fields added to the athbuf and require
269 * reset need to be added to this macro.
270 * currently bf_status is the only one requires that
273 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
275 /* hw processing complete, desc processed by hal */
276 #define ATH_BUFSTATUS_DONE 0x00000001
277 /* hw processing complete, desc hold for hw */
278 #define ATH_BUFSTATUS_STALE 0x00000002
279 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
280 #define ATH_BUFSTATUS_FREE 0x00000004
282 /* DMA state for tx/rx descriptors */
286 struct ath_desc *dd_desc; /* descriptors */
287 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
288 u32 dd_desc_len; /* size of dd_desc */
289 struct ath_buf *dd_bufptr; /* associated buffers */
290 dma_addr_t dd_dmacontext;
293 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
295 struct ath_rx_context {
296 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
298 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
300 int ath_descdma_setup(struct ath_softc *sc,
301 struct ath_descdma *dd,
302 struct list_head *head,
306 int ath_desc_alloc(struct ath_softc *sc);
307 void ath_desc_free(struct ath_softc *sc);
308 void ath_descdma_cleanup(struct ath_softc *sc,
309 struct ath_descdma *dd,
310 struct list_head *head);
316 #define ATH_MAX_ANTENNA 3
317 #define ATH_RXBUF 512
318 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
319 #define WME_NUM_TID 16
320 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
321 #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
324 ATH_RX_NON_CONSUMED = 0,
328 /* per frame rx status block */
329 struct ath_recv_status {
330 u64 tsf; /* mac tsf */
331 int8_t rssi; /* RSSI (noise floor ajusted) */
332 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
333 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
334 int8_t abs_rssi; /* absolute RSSI */
335 u8 rateieee; /* data rate received (IEEE rate code) */
336 u8 ratecode; /* phy rate code */
337 int rateKbps; /* data rate received (Kbps) */
338 int antenna; /* rx antenna */
339 int flags; /* status of associated skb */
340 #define ATH_RX_FCS_ERROR 0x01
341 #define ATH_RX_MIC_ERROR 0x02
342 #define ATH_RX_DECRYPT_ERROR 0x04
343 #define ATH_RX_RSSI_VALID 0x08
344 /* if any of ctl,extn chainrssis are valid */
345 #define ATH_RX_CHAIN_RSSI_VALID 0x10
346 /* if extn chain rssis are valid */
347 #define ATH_RX_RSSI_EXTN_VALID 0x20
348 /* set if 40Mhz, clear if 20Mhz */
349 #define ATH_RX_40MHZ 0x40
350 /* set if short GI, clear if full GI */
351 #define ATH_RX_SHORT_GI 0x80
355 struct sk_buff *rx_wbuf;
356 unsigned long rx_time; /* system time when received */
357 struct ath_recv_status rx_status; /* cached rx status */
360 /* Per-TID aggregate receiver state for a node */
363 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
364 struct timer_list timer;
366 int baw_head; /* seq_next at head */
367 int baw_tail; /* tail of block-ack window */
368 int seq_reset; /* need to reset start sequence */
369 int addba_exchangecomplete;
370 u16 seq_next; /* next expected sequence */
371 u16 baw_size; /* block-ack window size */
374 /* Per-node receiver aggregate state */
376 struct ath_arx_tid tid[WME_NUM_TID];
379 int ath_startrecv(struct ath_softc *sc);
380 bool ath_stoprecv(struct ath_softc *sc);
381 void ath_flushrecv(struct ath_softc *sc);
382 u32 ath_calcrxfilter(struct ath_softc *sc);
383 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
384 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
385 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
386 void ath_handle_rx_intr(struct ath_softc *sc);
387 int ath_rx_init(struct ath_softc *sc, int nbufs);
388 void ath_rx_cleanup(struct ath_softc *sc);
389 int ath_rx_tasklet(struct ath_softc *sc, int flush);
390 int ath_rx_input(struct ath_softc *sc,
391 struct ath_node *node,
394 struct ath_recv_status *rx_status,
395 enum ATH_RX_TYPE *status);
396 int ath__rx_indicate(struct ath_softc *sc,
398 struct ath_recv_status *status,
400 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
401 struct ath_recv_status *status);
407 #define ATH_FRAG_PER_MSDU 1
408 #define ATH_TXBUF (512/ATH_FRAG_PER_MSDU)
409 /* max number of transmit attempts (tries) */
410 #define ATH_TXMAXTRY 13
411 /* max number of 11n transmit attempts (tries) */
412 #define ATH_11N_TXMAXTRY 10
413 /* max number of tries for management and control frames */
414 #define ATH_MGT_TXMAXTRY 4
415 #define WME_BA_BMP_SIZE 64
416 #define WME_MAX_BA WME_BA_BMP_SIZE
417 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
418 #define TID_TO_WME_AC(_tid) \
419 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
420 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
421 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
425 /* Wireless Multimedia Extension Defines */
426 #define WME_AC_BE 0 /* best effort */
427 #define WME_AC_BK 1 /* background */
428 #define WME_AC_VI 2 /* video */
429 #define WME_AC_VO 3 /* voice */
434 ATH_SM_PWRSAV_STATIC,
435 ATH_SM_PWRSAV_DYNAMIC,
439 * Data transmit queue state. One of these exists for each
440 * hardware transmit queue. Packets sent to us from above
441 * are assigned to queues based on their priority. Not all
442 * devices support a complete set of hardware transmit queues.
443 * For those devices the array sc_ac2q will map multiple
444 * priorities to fewer hardware queues (typically all to one
448 u32 axq_qnum; /* hardware q number */
449 u32 *axq_link; /* link ptr in last TX desc */
450 struct list_head axq_q; /* transmit queue */
452 unsigned long axq_lockflags; /* intr state when must cli */
453 u32 axq_depth; /* queue depth */
454 u8 axq_aggr_depth; /* aggregates queued */
455 u32 axq_totalqueued; /* total ever queued */
457 /* count to determine if descriptor should generate int on this txq. */
460 bool stopped; /* Is mac80211 queue stopped ? */
461 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
463 /* first desc of the last descriptor that contains CTS */
464 struct ath_desc *axq_lastdsWithCTS;
466 /* final desc of the gating desc that determines whether
467 lastdsWithCTS has been DMA'ed or not */
468 struct ath_desc *axq_gatingds;
470 struct list_head axq_acq;
473 /* per TID aggregate tx state for a destination */
475 struct list_head list; /* round-robin tid entry */
476 struct list_head buf_q; /* pending buffers */
478 struct ath_atx_ac *ac;
479 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
484 int baw_head; /* first un-acked tx buffer */
485 int baw_tail; /* next unused tx buffer slot */
488 int cleanup_inprogress;
489 u32 addba_exchangecomplete:1;
490 int32_t addba_exchangeinprogress;
491 int addba_exchangeattempts;
494 /* per access-category aggregate tx state for a destination */
496 int sched; /* dest-ac is scheduled */
497 int qnum; /* H/W queue number associated
499 struct list_head list; /* round-robin txq entry */
500 struct list_head tid_q; /* queue of TIDs with buffers */
503 /* per dest tx state */
505 struct ath_atx_tid tid[WME_NUM_TID];
506 struct ath_atx_ac ac[WME_NUM_AC];
509 /* per-frame tx control block */
510 struct ath_tx_control {
517 enum ath9k_pkt_type atype;
518 enum ath9k_key_type keytype;
528 struct ath_softc *dev;
529 dma_addr_t dmacontext;
532 /* per frame tx status block */
533 struct ath_xmit_status {
534 int retries; /* number of retries to successufully
535 transmit this frame */
536 int flags; /* status of transmit */
537 #define ATH_TX_ERROR 0x01
538 #define ATH_TX_XRETRY 0x02
539 #define ATH_TX_BAR 0x04
543 int rssi; /* RSSI (noise floor ajusted) */
544 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
545 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
546 int rateieee; /* data rate xmitted (IEEE rate code) */
547 int rateKbps; /* data rate xmitted (Kbps) */
548 int ratecode; /* phy rate code */
549 int flags; /* validity flags */
550 /* if any of ctl,extn chain rssis are valid */
551 #define ATH_TX_CHAIN_RSSI_VALID 0x01
552 /* if extn chain rssis are valid */
553 #define ATH_TX_RSSI_EXTN_VALID 0x02
554 u32 airtime; /* time on air per final tx rate */
557 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
558 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
559 int ath_tx_setup(struct ath_softc *sc, int haltype);
560 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
561 void ath_tx_draintxq(struct ath_softc *sc,
562 struct ath_txq *txq, bool retry_tx);
563 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
564 void ath_tx_node_cleanup(struct ath_softc *sc,
565 struct ath_node *an, bool bh_flag);
566 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
567 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
568 int ath_tx_init(struct ath_softc *sc, int nbufs);
569 int ath_tx_cleanup(struct ath_softc *sc);
570 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
571 int ath_txq_update(struct ath_softc *sc, int qnum,
572 struct ath9k_tx_queue_info *q);
573 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
574 void ath_tx_tasklet(struct ath_softc *sc);
575 u32 ath_txq_depth(struct ath_softc *sc, int qnum);
576 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
577 void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
578 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
579 struct ath_xmit_status *tx_status, struct ath_node *an);
581 /**********************/
582 /* Node / Aggregation */
583 /**********************/
585 /* indicates the node is clened up */
586 #define ATH_NODE_CLEAN 0x1
587 /* indicates the node is 80211 power save */
588 #define ATH_NODE_PWRSAVE 0x2
590 #define ADDBA_TIMEOUT 200 /* 200 milliseconds */
591 #define ADDBA_EXCHANGE_ATTEMPTS 10
592 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
593 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
594 /* number of delimiters for encryption padding */
595 #define ATH_AGGR_ENCRYPTDELIM 10
596 /* minimum h/w qdepth to be sustained to maximize aggregation */
597 #define ATH_AGGR_MIN_QDEPTH 2
598 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
599 #define IEEE80211_SEQ_SEQ_SHIFT 4
600 #define IEEE80211_SEQ_MAX 4096
601 #define IEEE80211_MIN_AMPDU_BUF 0x8
603 /* return whether a bit at index _n in bitmap _bm is set
604 * _sz is the size of the bitmap */
605 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
606 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
608 /* return block-ack bitmap index given sequence and starting sequence */
609 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
611 /* returns delimiter padding required given the packet length */
612 #define ATH_AGGR_GET_NDELIM(_len) \
613 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
614 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
616 #define BAW_WITHIN(_start, _bawsz, _seqno) \
617 ((((_seqno) - (_start)) & 4095) < (_bawsz))
619 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
620 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
621 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
622 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
624 enum ATH_AGGR_STATUS {
632 enum ATH_AGGR_CHECK {
635 AGGR_CLEANUP_PROGRESS,
636 AGGR_EXCHANGE_PROGRESS,
640 struct aggr_rifs_param {
641 int param_max_frames;
645 struct ath_rc_series *param_rcs;
648 /* Per-node aggregation state */
649 struct ath_node_aggr {
650 struct ath_atx tx; /* node transmit state */
651 struct ath_arx rx; /* node receive state */
654 /* driver-specific node state */
656 struct list_head list;
657 struct ath_softc *an_sc;
659 struct ath_chainmask_sel an_chainmask_sel;
660 struct ath_node_aggr an_aggr;
661 u8 an_smmode; /* SM Power save mode */
663 u8 an_addr[ETH_ALEN];
666 void ath_tx_resume_tid(struct ath_softc *sc,
667 struct ath_atx_tid *tid);
668 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
669 struct ath_node *an, u8 tidno);
670 void ath_tx_aggr_teardown(struct ath_softc *sc,
671 struct ath_node *an, u8 tidno);
672 void ath_rx_aggr_teardown(struct ath_softc *sc,
673 struct ath_node *an, u8 tidno);
674 int ath_rx_aggr_start(struct ath_softc *sc,
678 int ath_rx_aggr_stop(struct ath_softc *sc,
681 int ath_tx_aggr_start(struct ath_softc *sc,
685 int ath_tx_aggr_stop(struct ath_softc *sc,
688 void ath_newassoc(struct ath_softc *sc,
689 struct ath_node *node, int isnew, int isuapsd);
690 struct ath_node *ath_node_attach(struct ath_softc *sc,
691 u8 addr[ETH_ALEN], int if_id);
692 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
693 struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
694 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
695 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
697 /*******************/
698 /* Beacon Handling */
699 /*******************/
702 * Regardless of the number of beacons we stagger, (i.e. regardless of the
703 * number of BSSIDs) if a given beacon does not go out even after waiting this
704 * number of beacon intervals, the game's up.
706 #define BSTUCK_THRESH (9 * ATH_BCBUF)
707 #define ATH_BCBUF 4 /* number of beacon buffers */
708 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
709 #define ATH_DEFAULT_BMISS_LIMIT 10
710 #define ATH_BEACON_AIFS_DEFAULT 0 /* Default aifs for ap beacon q */
711 #define ATH_BEACON_CWMIN_DEFAULT 0 /* Default cwmin for ap beacon q */
712 #define ATH_BEACON_CWMAX_DEFAULT 0 /* Default cwmax for ap beacon q */
713 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
715 /* beacon configuration */
716 struct ath_beacon_config {
726 } u; /* last received beacon/probe response timestamp of this BSS. */
729 /* offsets in a beacon frame for
730 * quick acess of beacon content by low-level driver */
731 struct ath_beacon_offset {
732 u8 *bo_tim; /* start of atim/dtim */
735 void ath9k_beacon_tasklet(unsigned long data);
736 void ath_beacon_config(struct ath_softc *sc, int if_id);
737 int ath_beaconq_setup(struct ath_hal *ah);
738 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
739 void ath_bstuck_process(struct ath_softc *sc);
740 void ath_beacon_tasklet(struct ath_softc *sc, int *needmark);
741 void ath_beacon_free(struct ath_softc *sc);
742 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
743 void ath_beacon_sync(struct ath_softc *sc, int if_id);
744 void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
745 void ath_get_beaconconfig(struct ath_softc *sc,
747 struct ath_beacon_config *conf);
748 int ath_update_beacon(struct ath_softc *sc,
750 struct ath_beacon_offset *bo,
758 * Define the scheme that we select MAC address for multiple
759 * BSS on the same radio. The very first VAP will just use the MAC
760 * address from the EEPROM. For the next 3 VAPs, we set the
761 * U/L bit (bit 1) in MAC address, and use the next two bits as the
765 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
766 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
768 /* VAP configuration (from protocol layer) */
769 struct ath_vap_config {
770 u32 av_fixed_rateset;
771 u32 av_fixed_retryset;
774 /* driver-specific vap state */
776 struct ieee80211_vif *av_if_data;
777 enum ath9k_opmode av_opmode; /* VAP operational mode */
778 struct ath_buf *av_bcbuf; /* beacon buffer */
779 struct ath_beacon_offset av_boff; /* dynamic update state */
780 struct ath_tx_control av_btxctl; /* txctl information for beacon */
781 int av_bslot; /* beacon slot index */
782 struct ath_txq av_mcastq; /* multicast transmit queue */
783 struct ath_vap_config av_config;/* vap configuration parameters*/
784 struct ath_rate_node *rc_node;
787 int ath_vap_attach(struct ath_softc *sc,
789 struct ieee80211_vif *if_data,
790 enum ath9k_opmode opmode);
791 int ath_vap_detach(struct ath_softc *sc, int if_id);
792 int ath_vap_config(struct ath_softc *sc,
793 int if_id, struct ath_vap_config *if_config);
794 int ath_vap_listen(struct ath_softc *sc, int if_id);
796 /*********************/
797 /* Antenna diversity */
798 /*********************/
800 #define ATH_ANT_DIV_MAX_CFG 2
801 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
802 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
804 enum ATH_ANT_DIV_STATE{
806 ATH_ANT_DIV_SCAN, /* evaluating antenna */
810 struct ath_softc *antdiv_sc;
812 enum ATH_ANT_DIV_STATE antdiv_state;
813 u8 antdiv_num_antcfg;
816 int32_t antdivf_rssitrig;
817 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
818 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
819 u64 antdiv_laststatetsf;
820 u8 antdiv_bssid[ETH_ALEN];
823 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
824 struct ath_softc *sc, int32_t rssitrig);
825 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
828 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
829 void ath_slow_ant_div(struct ath_antdiv *antdiv,
830 struct ieee80211_hdr *wh,
831 struct ath_rx_status *rx_stats);
832 void ath_setdefantenna(void *sc, u32 antenna);
834 /********************/
835 /* Main driver core */
836 /********************/
839 * Default cache line size, in bytes.
840 * Used when PCI device not fully initialized by bootrom/BIOS
842 #define DEFAULT_CACHELINE 32
843 #define ATH_DEFAULT_NOISE_FLOOR -95
844 #define ATH_REGCLASSIDS_MAX 10
845 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
846 #define ATH_PREAMBLE_SHORT (1<<0)
847 #define ATH_PROTECT_ENABLE (1<<1)
848 #define ATH_MAX_SW_RETRIES 10
849 /* Num farmes difference in tx to flip default recv */
850 #define ATH_ANTENNA_DIFF 2
851 #define ATH_CHAN_MAX 255
852 #define IEEE80211_WEP_NKID 4 /* number of key ids */
853 #define IEEE80211_RATE_VAL 0x7f
855 * The key cache is used for h/w cipher state and also for
856 * tracking station state such as the current tx antenna.
857 * We also setup a mapping table between key cache slot indices
858 * and station state to short-circuit node lookups on rx.
859 * Different parts have different size key caches. We handle
860 * up to ATH_KEYMAX entries (could dynamically allocate state).
862 #define ATH_KEYMAX 128 /* max key cache size we handle */
864 #define RESET_RETRY_TXQ 0x00000001
865 #define ATH_IF_ID_ANY 0xff
867 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
869 #define RSSI_LPF_THRESHOLD -20
870 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
871 #define ATH_RATE_DUMMY_MARKER 0
872 #define ATH_RSSI_LPF_LEN 10
873 #define ATH_RSSI_DUMMY_MARKER 0x127
875 #define ATH_EP_MUL(x, mul) ((x) * (mul))
876 #define ATH_EP_RND(x, mul) \
877 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
878 #define ATH_RSSI_OUT(x) \
879 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
880 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
881 #define ATH_RSSI_IN(x) \
882 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
883 #define ATH_LPF_RSSI(x, y, len) \
884 ((x != ATH_RSSI_DUMMY_MARKER) ? \
885 (((x) * ((len) - 1) + (y)) / (len)) : (y))
886 #define ATH_RSSI_LPF(x, y) do { \
887 if ((y) >= RSSI_LPF_THRESHOLD) \
888 x = ATH_LPF_RSSI((x), \
889 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
906 enum ath9k_ht_macmode tx_chan_width;
913 struct ieee80211_hw *hw;
914 struct pci_dev *pdev;
916 struct tasklet_struct intr_tq;
917 struct tasklet_struct bcon_tasklet;
918 struct ath_config sc_config; /* load-time parameters */
920 struct ath_hal *sc_ah;
921 struct ath_rate_softc *sc_rc; /* tx rate control support */
923 enum ath9k_opmode sc_opmode; /* current operating mode */
924 unsigned int rx_filter;
925 u8 sc_invalid; /* being detached */
926 u8 sc_beacons; /* beacons running */
927 u8 sc_txaggr; /* enable 11n tx aggregation */
928 u8 sc_rxaggr; /* enable 11n rx aggregation */
929 u8 sc_update_chainmask; /* change chain mask */
930 u8 sc_full_reset; /* force full reset */
931 enum wireless_mode sc_curmode; /* current phy mode */
934 u8 sc_curbssid[ETH_ALEN];
935 u8 sc_myaddr[ETH_ALEN];
936 enum PROT_MODE sc_protmode;
938 u8 sc_txantenna; /* data tx antenna (fixed or auto) */
939 u8 sc_nbcnvaps; /* # of vaps sending beacons */
940 u16 sc_nvaps; /* # of active virtual ap's */
941 struct ath_vap *sc_vaps[ATH_BCBUF];
942 enum ath9k_int sc_imask;
943 u8 sc_bssidmask[ETH_ALEN];
944 u8 sc_defant; /* current default antenna */
945 u8 sc_rxotherant; /* rx's on non-default antenna */
947 int sc_slotupdate; /* slot to next advance fsm */
950 int sc_bslot[ATH_BCBUF];
951 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
952 struct list_head node_list;
953 struct ath_ht_info sc_ht_info;
954 int16_t sc_noise_floor; /* signal noise floor in dBm */
955 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
958 u8 sc_rxchaindetect_ref;
959 u8 sc_rxchaindetect_thresh5GHz;
960 u8 sc_rxchaindetect_thresh2GHz;
961 u8 sc_rxchaindetect_delta5GHz;
962 u8 sc_rxchaindetect_delta2GHz;
963 u32 sc_rtsaggrlimit; /* Chipset specific aggr limit */
965 #ifdef CONFIG_SLOW_ANT_DIV
966 struct ath_antdiv sc_antdiv;
969 OK, /* no change needed */
970 UPDATE, /* update pending */
971 COMMIT /* beacon sent, commit change */
972 } sc_updateslot; /* slot time update fsm */
975 u32 sc_keymax; /* size of key cache */
976 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
977 u8 sc_splitmic; /* split TKIP MIC keys */
981 struct list_head sc_rxbuf;
982 struct ath_descdma sc_rxdma;
983 int sc_rxbufsize; /* rx size based on mtu */
984 u32 *sc_rxlink; /* link ptr in last RX desc */
985 u32 sc_rxflush; /* rx flush in progress */
986 u64 sc_lastrx; /* tsf of last rx'd frame */
989 struct list_head sc_txbuf;
990 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
991 struct ath_descdma sc_txdma;
993 u32 sc_txintrperiod; /* tx interrupt batching */
994 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
995 u32 sc_ant_tx[8]; /* recent tx frames/antenna */
998 struct ath9k_tx_queue_info sc_beacon_qi;
999 struct ath_descdma sc_bdma;
1000 struct ath_txq *sc_cabq;
1001 struct list_head sc_bbuf;
1004 u32 ast_be_xmit; /* beacons transmitted */
1007 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
1008 const struct ath9k_rate_table *sc_currates;
1009 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
1010 u8 sc_protrix; /* protection rate index */
1012 u32 rateKbps; /* transfer rate in kbs */
1013 u8 ieeerate; /* IEEE rate */
1014 } sc_hwmap[256]; /* h/w rate ix mappings */
1017 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1018 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1019 struct ath9k_channel sc_curchan;
1022 spinlock_t sc_rxflushlock;
1023 spinlock_t sc_rxbuflock;
1024 spinlock_t sc_txbuflock;
1025 spinlock_t sc_resetlock;
1026 spinlock_t node_lock;
1029 int ath_init(u16 devid, struct ath_softc *sc);
1030 void ath_deinit(struct ath_softc *sc);
1031 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1032 int ath_suspend(struct ath_softc *sc);
1033 irqreturn_t ath_isr(int irq, void *dev);
1034 int ath_reset(struct ath_softc *sc, bool retry_tx);
1035 void ath_scan_start(struct ath_softc *sc);
1036 void ath_scan_end(struct ath_softc *sc);
1037 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
1038 void ath_setup_rate(struct ath_softc *sc,
1039 enum wireless_mode wMode,
1040 enum RATE_TYPE type,
1041 const struct ath9k_rate_table *rt);
1043 /*********************/
1044 /* Utility Functions */
1045 /*********************/
1047 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1048 int ath_keyset(struct ath_softc *sc,
1050 struct ath9k_keyval *hk,
1051 const u8 mac[ETH_ALEN]);
1052 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1053 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1054 void ath_setslottime(struct ath_softc *sc);
1055 void ath_update_txpow(struct ath_softc *sc);
1056 int ath_cabq_update(struct ath_softc *);
1057 void ath_get_currentCountry(struct ath_softc *sc,
1058 struct ath9k_country_entry *ctry);
1059 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
1060 u32 ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
1061 dma_addr_t ath_skb_map_single(struct ath_softc *sc,
1062 struct sk_buff *skb,
1065 void ath_skb_unmap_single(struct ath_softc *sc,
1066 struct sk_buff *skb,
1069 void ath_mcast_merge(struct ath_softc *sc, u32 mfilt[2]);
1070 enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);