drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  88 {
  89         int i;
  90
  91         BUG_ON(timeout < AH_TIME_QUANTUM);
  92
  93         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  94                 if ((REG_READ(ah, reg) & mask) == val)
  95                         return true;
  96
  97                 udelay(AH_TIME_QUANTUM);
  98         }
  99
 100         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 101                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 102                 timeout, reg, REG_READ(ah, reg), mask, val);
 103
 104         return false;
 105 }
 106
 107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 108 {
 109         u32 retval;
 110         int i;
 111
 112         for (i = 0, retval = 0; i < n; i++) {
 113                 retval = (retval << 1) | (val & 1);
 114                 val >>= 1;
 115         }
 116         return retval;
 117 }
 118
 119 bool ath9k_get_channel_edges(struct ath_hw *ah,
 120                              u16 flags, u16 *low,
 121                              u16 *high)
 122 {
 123         struct ath9k_hw_capabilities *pCap = &ah->caps;
 124
 125         if (flags & CHANNEL_5GHZ) {
 126                 *low = pCap->low_5ghz_chan;
 127                 *high = pCap->high_5ghz_chan;
 128                 return true;
 129         }
 130         if ((flags & CHANNEL_2GHZ)) {
 131                 *low = pCap->low_2ghz_chan;
 132                 *high = pCap->high_2ghz_chan;
 133                 return true;
 134         }
 135         return false;
 136 }
 137
 138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 139                            struct ath_rate_table *rates,
 140                            u32 frameLen, u16 rateix,
 141                            bool shortPreamble)
 142 {
 143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 144         u32 kbps;
 145
 146         kbps = rates->info[rateix].ratekbps;
 147
 148         if (kbps == 0)
 149                 return 0;
 150
 151         switch (rates->info[rateix].phy) {
 152         case WLAN_RC_PHY_CCK:
 153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 154                 if (shortPreamble && rates->info[rateix].short_preamble)
 155                         phyTime >>= 1;
 156                 numBits = frameLen << 3;
 157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 158                 break;
 159         case WLAN_RC_PHY_OFDM:
 160                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME_QUARTER
 165                                 + OFDM_PREAMBLE_TIME_QUARTER
 166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 167                 } else if (ah->curchan &&
 168                            IS_CHAN_HALF_RATE(ah->curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_HALF +
 173                                 OFDM_PREAMBLE_TIME_HALF
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 175                 } else {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 180                                 + (numSymbols * OFDM_SYMBOL_TIME);
 181                 }
 182                 break;
 183         default:
 184                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 185                         "Unknown phy %u (rate ix %u)\n",
 186                         rates->info[rateix].phy, rateix);
 187                 txTime = 0;
 188                 break;
 189         }
 190
 191         return txTime;
 192 }
 193
 194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 195                                   struct ath9k_channel *chan,
 196                                   struct chan_centers *centers)
 197 {
 198         int8_t extoff;
 199
 200         if (!IS_CHAN_HT40(chan)) {
 201                 centers->ctl_center = centers->ext_center =
 202                         centers->synth_center = chan->channel;
 203                 return;
 204         }
 205
 206         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 207             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 208                 centers->synth_center =
 209                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 210                 extoff = 1;
 211         } else {
 212                 centers->synth_center =
 213                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 214                 extoff = -1;
 215         }
 216
 217         centers->ctl_center =
 218                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 219         centers->ext_center =
 220                 centers->synth_center + (extoff *
 221                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 222                           HT40_CHANNEL_CENTER_SHIFT : 15));
 223 }
 224
 225 /******************/
 226 /* Chip Revisions */
 227 /******************/
 228
 229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 230 {
 231         u32 val;
 232
 233         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 234
 235         if (val == 0xFF) {
 236                 val = REG_READ(ah, AR_SREV);
 237                 ah->hw_version.macVersion =
 238                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 239                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 240                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 241         } else {
 242                 if (!AR_SREV_9100(ah))
 243                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 244
 245                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 246
 247                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 248                         ah->is_pciexpress = true;
 249         }
 250 }
 251
 252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 253 {
 254         u32 val;
 255         int i;
 256
 257         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 258
 259         for (i = 0; i < 8; i++)
 260                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 261         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 262         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 263
 264         return ath9k_hw_reverse_bits(val, 8);
 265 }
 266
 267 /************************************/
 268 /* HW Attach, Detach, Init Routines */
 269 /************************************/
 270
 271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 272 {
 273         if (AR_SREV_9100(ah))
 274                 return;
 275
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 285
 286         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 287 }
 288
 289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 290 {
 291         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 292         u32 regHold[2];
 293         u32 patternData[4] = { 0x55555555,
 294                                0xaaaaaaaa,
 295                                0x66666666,
 296                                0x99999999 };
 297         int i, j;
 298
 299         for (i = 0; i < 2; i++) {
 300                 u32 addr = regAddr[i];
 301                 u32 wrData, rdData;
 302
 303                 regHold[i] = REG_READ(ah, addr);
 304                 for (j = 0; j < 0x100; j++) {
 305                         wrData = (j << 16) | j;
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (rdData != wrData) {
 309                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 310                                         "address test failed "
 311                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 312                                         addr, wrData, rdData);
 313                                 return false;
 314                         }
 315                 }
 316                 for (j = 0; j < 4; j++) {
 317                         wrData = patternData[j];
 318                         REG_WRITE(ah, addr, wrData);
 319                         rdData = REG_READ(ah, addr);
 320                         if (wrData != rdData) {
 321                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 322                                         "address test failed "
 323                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 324                                         addr, wrData, rdData);
 325                                 return false;
 326                         }
 327                 }
 328                 REG_WRITE(ah, regAddr[i], regHold[i]);
 329         }
 330         udelay(100);
 331
 332         return true;
 333 }
 334
 335 static const char *ath9k_hw_devname(u16 devid)
 336 {
 337         switch (devid) {
 338         case AR5416_DEVID_PCI:
 339                 return "Atheros 5416";
 340         case AR5416_DEVID_PCIE:
 341                 return "Atheros 5418";
 342         case AR9160_DEVID_PCI:
 343                 return "Atheros 9160";
 344         case AR5416_AR9100_DEVID:
 345                 return "Atheros 9100";
 346         case AR9280_DEVID_PCI:
 347         case AR9280_DEVID_PCIE:
 348                 return "Atheros 9280";
 349         case AR9285_DEVID_PCIE:
 350                 return "Atheros 9285";
 351         }
 352
 353         return NULL;
 354 }
 355
 356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 357 {
 358         int i;
 359
 360         ah->config.dma_beacon_response_time = 2;
 361         ah->config.sw_beacon_response_time = 10;
 362         ah->config.additional_swba_backoff = 0;
 363         ah->config.ack_6mb = 0x0;
 364         ah->config.cwm_ignore_extcca = 0;
 365         ah->config.pcie_powersave_enable = 0;
 366         ah->config.pcie_clock_req = 0;
 367         ah->config.pcie_waen = 0;
 368         ah->config.analog_shiftreg = 1;
 369         ah->config.ht_enable = 1;
 370         ah->config.ofdm_trig_low = 200;
 371         ah->config.ofdm_trig_high = 500;
 372         ah->config.cck_trig_high = 200;
 373         ah->config.cck_trig_low = 100;
 374         ah->config.enable_ani = 1;
 375         ah->config.diversity_control = 0;
 376         ah->config.antenna_switch_swap = 0;
 377
 378         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 379                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 380                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 381         }
 382
 383         ah->config.intr_mitigation = true;
 384
 385         /*
 386          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 387          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 388          * This means we use it for all AR5416 devices, and the few
 389          * minor PCI AR9280 devices out there.
 390          *
 391          * Serialization is required because these devices do not handle
 392          * well the case of two concurrent reads/writes due to the latency
 393          * involved. During one read/write another read/write can be issued
 394          * on another CPU while the previous read/write may still be working
 395          * on our hardware, if we hit this case the hardware poops in a loop.
 396          * We prevent this by serializing reads and writes.
 397          *
 398          * This issue is not present on PCI-Express devices or pre-AR5416
 399          * devices (legacy, 802.11abg).
 400          */
 401         if (num_possible_cpus() > 1)
 402                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 403 }
 404
 405 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 406                                         int *status)
 407 {
 408         struct ath_hw *ah;
 409
 410         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 411         if (ah == NULL) {
 412                 DPRINTF(sc, ATH_DBG_FATAL,
 413                         "Cannot allocate memory for state block\n");
 414                 *status = -ENOMEM;
 415                 return NULL;
 416         }
 417
 418         ah->ah_sc = sc;
 419         ah->hw_version.magic = AR5416_MAGIC;
 420         ah->regulatory.country_code = CTRY_DEFAULT;
 421         ah->hw_version.devid = devid;
 422         ah->hw_version.subvendorid = 0;
 423
 424         ah->ah_flags = 0;
 425         if ((devid == AR5416_AR9100_DEVID))
 426                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 427         if (!AR_SREV_9100(ah))
 428                 ah->ah_flags = AH_USE_EEPROM;
 429
 430         ah->regulatory.power_limit = MAX_RATE_POWER;
 431         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 432         ah->atim_window = 0;
 433         ah->diversity_control = ah->config.diversity_control;
 434         ah->antenna_switch_swap =
 435                 ah->config.antenna_switch_swap;
 436         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 437         ah->beacon_interval = 100;
 438         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 439         ah->slottime = (u32) -1;
 440         ah->acktimeout = (u32) -1;
 441         ah->ctstimeout = (u32) -1;
 442         ah->globaltxtimeout = (u32) -1;
 443
 444         ah->gbeacon_rate = 0;
 445
 446         return ah;
 447 }
 448
 449 static int ath9k_hw_rfattach(struct ath_hw *ah)
 450 {
 451         bool rfStatus = false;
 452         int ecode = 0;
 453
 454         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 455         if (!rfStatus) {
 456                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 457                         "RF setup failed, status: %u\n", ecode);
 458                 return ecode;
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 465 {
 466         u32 val;
 467
 468         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 469
 470         val = ath9k_hw_get_radiorev(ah);
 471         switch (val & AR_RADIO_SREV_MAJOR) {
 472         case 0:
 473                 val = AR_RAD5133_SREV_MAJOR;
 474                 break;
 475         case AR_RAD5133_SREV_MAJOR:
 476         case AR_RAD5122_SREV_MAJOR:
 477         case AR_RAD2133_SREV_MAJOR:
 478         case AR_RAD2122_SREV_MAJOR:
 479                 break;
 480         default:
 481                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 482                         "Radio Chip Rev 0x%02X not supported\n",
 483                         val & AR_RADIO_SREV_MAJOR);
 484                 return -EOPNOTSUPP;
 485         }
 486
 487         ah->hw_version.analog5GhzRev = val;
 488
 489         return 0;
 490 }
 491
 492 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 493 {
 494         u32 sum;
 495         int i;
 496         u16 eeval;
 497
 498         sum = 0;
 499         for (i = 0; i < 3; i++) {
 500                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 501                 sum += eeval;
 502                 ah->macaddr[2 * i] = eeval >> 8;
 503                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 504         }
 505         if (sum == 0 || sum == 0xffff * 3)
 506                 return -EADDRNOTAVAIL;
 507
 508         return 0;
 509 }
 510
 511 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 512 {
 513         u32 rxgain_type;
 514
 515         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 516                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 517
 518                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 519                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 520                         ar9280Modes_backoff_13db_rxgain_9280_2,
 521                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 522                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 523                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 524                         ar9280Modes_backoff_23db_rxgain_9280_2,
 525                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 526                 else
 527                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 528                         ar9280Modes_original_rxgain_9280_2,
 529                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 530         } else {
 531                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 532                         ar9280Modes_original_rxgain_9280_2,
 533                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 534         }
 535 }
 536
 537 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 538 {
 539         u32 txgain_type;
 540
 541         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 542                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 543
 544                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 545                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 546                         ar9280Modes_high_power_tx_gain_9280_2,
 547                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 548                 else
 549                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 550                         ar9280Modes_original_tx_gain_9280_2,
 551                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 552         } else {
 553                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 554                 ar9280Modes_original_tx_gain_9280_2,
 555                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 556         }
 557 }
 558
 559 static int ath9k_hw_post_attach(struct ath_hw *ah)
 560 {
 561         int ecode;
 562
 563         if (!ath9k_hw_chip_test(ah))
 564                 return -ENODEV;
 565
 566         ecode = ath9k_hw_rf_claim(ah);
 567         if (ecode != 0)
 568                 return ecode;
 569
 570         ecode = ath9k_hw_eeprom_attach(ah);
 571         if (ecode != 0)
 572                 return ecode;
 573
 574         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 575                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 576
 577         ecode = ath9k_hw_rfattach(ah);
 578         if (ecode != 0)
 579                 return ecode;
 580
 581         if (!AR_SREV_9100(ah)) {
 582                 ath9k_hw_ani_setup(ah);
 583                 ath9k_hw_ani_attach(ah);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 590                                          int *status)
 591 {
 592         struct ath_hw *ah;
 593         int ecode;
 594         u32 i, j;
 595
 596         ah = ath9k_hw_newstate(devid, sc, status);
 597         if (ah == NULL)
 598                 return NULL;
 599
 600         ath9k_hw_set_defaults(ah);
 601
 602         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 603                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 604                 ecode = -EIO;
 605                 goto bad;
 606         }
 607
 608         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 609                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 610                 ecode = -EIO;
 611                 goto bad;
 612         }
 613
 614         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 615                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 616                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 617                         ah->config.serialize_regmode =
 618                                 SER_REG_MODE_ON;
 619                 } else {
 620                         ah->config.serialize_regmode =
 621                                 SER_REG_MODE_OFF;
 622                 }
 623         }
 624
 625         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 626                 ah->config.serialize_regmode);
 627
 628         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 629             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 630             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 631             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 632                 DPRINTF(sc, ATH_DBG_FATAL,
 633                         "Mac Chip Rev 0x%02x.%x is not supported by "
 634                         "this driver\n", ah->hw_version.macVersion,
 635                         ah->hw_version.macRev);
 636                 ecode = -EOPNOTSUPP;
 637                 goto bad;
 638         }
 639
 640         if (AR_SREV_9100(ah)) {
 641                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 642                 ah->supp_cals = IQ_MISMATCH_CAL;
 643                 ah->is_pciexpress = false;
 644         }
 645         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 646
 647         if (AR_SREV_9160_10_OR_LATER(ah)) {
 648                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 649                         ah->iq_caldata.calData = &iq_cal_single_sample;
 650                         ah->adcgain_caldata.calData =
 651                                 &adc_gain_cal_single_sample;
 652                         ah->adcdc_caldata.calData =
 653                                 &adc_dc_cal_single_sample;
 654                         ah->adcdc_calinitdata.calData =
 655                                 &adc_init_dc_cal;
 656                 } else {
 657                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 658                         ah->adcgain_caldata.calData =
 659                                 &adc_gain_cal_multi_sample;
 660                         ah->adcdc_caldata.calData =
 661                                 &adc_dc_cal_multi_sample;
 662                         ah->adcdc_calinitdata.calData =
 663                                 &adc_init_dc_cal;
 664                 }
 665                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 666         }
 667
 668         ah->ani_function = ATH9K_ANI_ALL;
 669         if (AR_SREV_9280_10_OR_LATER(ah))
 670                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 671
 672         if (AR_SREV_9285_12_OR_LATER(ah)) {
 673
 674                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 675                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 676                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 677                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 678
 679                 if (ah->config.pcie_clock_req) {
 680                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 681                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 682                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 683                 } else {
 684                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 685                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 686                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 687                                   2);
 688                 }
 689         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 690                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 691                                ARRAY_SIZE(ar9285Modes_9285), 6);
 692                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 693                                ARRAY_SIZE(ar9285Common_9285), 2);
 694
 695                 if (ah->config.pcie_clock_req) {
 696                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 697                         ar9285PciePhy_clkreq_off_L1_9285,
 698                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 699                 } else {
 700                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 701                         ar9285PciePhy_clkreq_always_on_L1_9285,
 702                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 703                 }
 704         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 705                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 706                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 707                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 708                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 709
 710                 if (ah->config.pcie_clock_req) {
 711                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 712                                ar9280PciePhy_clkreq_off_L1_9280,
 713                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 714                 } else {
 715                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 716                                ar9280PciePhy_clkreq_always_on_L1_9280,
 717                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 718                 }
 719                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 720                                ar9280Modes_fast_clock_9280_2,
 721                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 722         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 723                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 724                                ARRAY_SIZE(ar9280Modes_9280), 6);
 725                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 726                                ARRAY_SIZE(ar9280Common_9280), 2);
 727         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 728                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 729                                ARRAY_SIZE(ar5416Modes_9160), 6);
 730                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 731                                ARRAY_SIZE(ar5416Common_9160), 2);
 732                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 733                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 734                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 735                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 736                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 737                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 738                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 739                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 740                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 741                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 742                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 743                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 744                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 745                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 746                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 747                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 748                 if (AR_SREV_9160_11(ah)) {
 749                         INIT_INI_ARRAY(&ah->iniAddac,
 750                                        ar5416Addac_91601_1,
 751                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 752                 } else {
 753                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 754                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 755                 }
 756         } else if (AR_SREV_9100_OR_LATER(ah)) {
 757                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 758                                ARRAY_SIZE(ar5416Modes_9100), 6);
 759                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 760                                ARRAY_SIZE(ar5416Common_9100), 2);
 761                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 762                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 763                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 764                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 765                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 766                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 767                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 768                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 769                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 770                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 771                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 772                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 773                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 774                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 775                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 776                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 777                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 778                                ARRAY_SIZE(ar5416Addac_9100), 2);
 779         } else {
 780                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 781                                ARRAY_SIZE(ar5416Modes), 6);
 782                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 783                                ARRAY_SIZE(ar5416Common), 2);
 784                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 785                                ARRAY_SIZE(ar5416Bank0), 2);
 786                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 787                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 788                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 789                                ARRAY_SIZE(ar5416Bank1), 2);
 790                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 791                                ARRAY_SIZE(ar5416Bank2), 2);
 792                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 793                                ARRAY_SIZE(ar5416Bank3), 3);
 794                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 795                                ARRAY_SIZE(ar5416Bank6), 3);
 796                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 797                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 798                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 799                                ARRAY_SIZE(ar5416Bank7), 2);
 800                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 801                                ARRAY_SIZE(ar5416Addac), 2);
 802         }
 803
 804         if (ah->is_pciexpress)
 805                 ath9k_hw_configpcipowersave(ah, 0);
 806         else
 807                 ath9k_hw_disablepcie(ah);
 808
 809         ecode = ath9k_hw_post_attach(ah);
 810         if (ecode != 0)
 811                 goto bad;
 812
 813         if (AR_SREV_9285_12_OR_LATER(ah)) {
 814                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 815
 816                 /* txgain table */
 817                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 818                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 819                         ar9285Modes_high_power_tx_gain_9285_1_2,
 820                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 821                 } else {
 822                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 823                         ar9285Modes_original_tx_gain_9285_1_2,
 824                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 825                 }
 826
 827         }
 828
 829         /* rxgain table */
 830         if (AR_SREV_9280_20(ah))
 831                 ath9k_hw_init_rxgain_ini(ah);
 832
 833         /* txgain table */
 834         if (AR_SREV_9280_20(ah))
 835                 ath9k_hw_init_txgain_ini(ah);
 836
 837         ath9k_hw_fill_cap_info(ah);
 838
 839         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 840             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 841
 842                 /* EEPROM Fixup */
 843                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 844                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 845
 846                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 847                                 u32 val = INI_RA(&ah->iniModes, i, j);
 848
 849                                 INI_RA(&ah->iniModes, i, j) =
 850                                         ath9k_hw_ini_fixup(ah,
 851                                                            &ah->eeprom.def,
 852                                                            reg, val);
 853                         }
 854                 }
 855         }
 856
 857         ecode = ath9k_hw_init_macaddr(ah);
 858         if (ecode != 0) {
 859                 DPRINTF(sc, ATH_DBG_FATAL,
 860                         "Failed to initialize MAC address\n");
 861                 goto bad;
 862         }
 863
 864         if (AR_SREV_9285(ah))
 865                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 866         else
 867                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 868
 869         ath9k_init_nfcal_hist_buffer(ah);
 870
 871         return ah;
 872 bad:
 873         if (ah)
 874                 ath9k_hw_detach(ah);
 875         if (status)
 876                 *status = ecode;
 877
 878         return NULL;
 879 }
 880
 881 static void ath9k_hw_init_bb(struct ath_hw *ah,
 882                              struct ath9k_channel *chan)
 883 {
 884         u32 synthDelay;
 885
 886         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 887         if (IS_CHAN_B(chan))
 888                 synthDelay = (4 * synthDelay) / 22;
 889         else
 890                 synthDelay /= 10;
 891
 892         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 893
 894         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 895 }
 896
 897 static void ath9k_hw_init_qos(struct ath_hw *ah)
 898 {
 899         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 900         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 901
 902         REG_WRITE(ah, AR_QOS_NO_ACK,
 903                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 904                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 905                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 906
 907         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 908         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 909         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 910         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 911         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 912 }
 913
 914 static void ath9k_hw_init_pll(struct ath_hw *ah,
 915                               struct ath9k_channel *chan)
 916 {
 917         u32 pll;
 918
 919         if (AR_SREV_9100(ah)) {
 920                 if (chan && IS_CHAN_5GHZ(chan))
 921                         pll = 0x1450;
 922                 else
 923                         pll = 0x1458;
 924         } else {
 925                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 926                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 927
 928                         if (chan && IS_CHAN_HALF_RATE(chan))
 929                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 930                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 931                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 932
 933                         if (chan && IS_CHAN_5GHZ(chan)) {
 934                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 935
 936
 937                                 if (AR_SREV_9280_20(ah)) {
 938                                         if (((chan->channel % 20) == 0)
 939                                             || ((chan->channel % 10) == 0))
 940                                                 pll = 0x2850;
 941                                         else
 942                                                 pll = 0x142c;
 943                                 }
 944                         } else {
 945                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 946                         }
 947
 948                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 949
 950                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 951
 952                         if (chan && IS_CHAN_HALF_RATE(chan))
 953                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 954                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 955                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 956
 957                         if (chan && IS_CHAN_5GHZ(chan))
 958                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 959                         else
 960                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 961                 } else {
 962                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 963
 964                         if (chan && IS_CHAN_HALF_RATE(chan))
 965                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 966                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 967                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 968
 969                         if (chan && IS_CHAN_5GHZ(chan))
 970                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 971                         else
 972                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 973                 }
 974         }
 975         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 976
 977         udelay(RTC_PLL_SETTLE_DELAY);
 978
 979         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 980 }
 981
 982 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
 983 {
 984         int rx_chainmask, tx_chainmask;
 985
 986         rx_chainmask = ah->rxchainmask;
 987         tx_chainmask = ah->txchainmask;
 988
 989         switch (rx_chainmask) {
 990         case 0x5:
 991                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 992                             AR_PHY_SWAP_ALT_CHAIN);
 993         case 0x3:
 994                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
 995                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 996                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 997                         break;
 998                 }
 999         case 0x1:
1000         case 0x2:
1001         case 0x7:
1002                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1003                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1004                 break;
1005         default:
1006                 break;
1007         }
1008
1009         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1010         if (tx_chainmask == 0x5) {
1011                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1012                             AR_PHY_SWAP_ALT_CHAIN);
1013         }
1014         if (AR_SREV_9100(ah))
1015                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1016                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1017 }
1018
1019 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1020                                           enum nl80211_iftype opmode)
1021 {
1022         ah->mask_reg = AR_IMR_TXERR |
1023                 AR_IMR_TXURN |
1024                 AR_IMR_RXERR |
1025                 AR_IMR_RXORN |
1026                 AR_IMR_BCNMISC;
1027
1028         if (ah->config.intr_mitigation)
1029                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1030         else
1031                 ah->mask_reg |= AR_IMR_RXOK;
1032
1033         ah->mask_reg |= AR_IMR_TXOK;
1034
1035         if (opmode == NL80211_IFTYPE_AP)
1036                 ah->mask_reg |= AR_IMR_MIB;
1037
1038         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1039         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1040
1041         if (!AR_SREV_9100(ah)) {
1042                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1043                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1044                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1045         }
1046 }
1047
1048 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1049 {
1050         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1051                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1052                 ah->acktimeout = (u32) -1;
1053                 return false;
1054         } else {
1055                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1056                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1057                 ah->acktimeout = us;
1058                 return true;
1059         }
1060 }
1061
1062 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1063 {
1064         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1065                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1066                 ah->ctstimeout = (u32) -1;
1067                 return false;
1068         } else {
1069                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1070                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1071                 ah->ctstimeout = us;
1072                 return true;
1073         }
1074 }
1075
1076 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1077 {
1078         if (tu > 0xFFFF) {
1079                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1080                         "bad global tx timeout %u\n", tu);
1081                 ah->globaltxtimeout = (u32) -1;
1082                 return false;
1083         } else {
1084                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1085                 ah->globaltxtimeout = tu;
1086                 return true;
1087         }
1088 }
1089
1090 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1091 {
1092         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1093                 ah->misc_mode);
1094
1095         if (ah->misc_mode != 0)
1096                 REG_WRITE(ah, AR_PCU_MISC,
1097                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1098         if (ah->slottime != (u32) -1)
1099                 ath9k_hw_setslottime(ah, ah->slottime);
1100         if (ah->acktimeout != (u32) -1)
1101                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1102         if (ah->ctstimeout != (u32) -1)
1103                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1104         if (ah->globaltxtimeout != (u32) -1)
1105                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1106 }
1107
1108 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1109 {
1110         return vendorid == ATHEROS_VENDOR_ID ?
1111                 ath9k_hw_devname(devid) : NULL;
1112 }
1113
1114 void ath9k_hw_detach(struct ath_hw *ah)
1115 {
1116         if (!AR_SREV_9100(ah))
1117                 ath9k_hw_ani_detach(ah);
1118
1119         ath9k_hw_rfdetach(ah);
1120         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1121         kfree(ah);
1122 }
1123
1124 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1125 {
1126         struct ath_hw *ah = NULL;
1127
1128         switch (devid) {
1129         case AR5416_DEVID_PCI:
1130         case AR5416_DEVID_PCIE:
1131         case AR5416_AR9100_DEVID:
1132         case AR9160_DEVID_PCI:
1133         case AR9280_DEVID_PCI:
1134         case AR9280_DEVID_PCIE:
1135         case AR9285_DEVID_PCIE:
1136                 ah = ath9k_hw_do_attach(devid, sc, error);
1137                 break;
1138         default:
1139                 *error = -ENXIO;
1140                 break;
1141         }
1142
1143         return ah;
1144 }
1145
1146 /*******/
1147 /* INI */
1148 /*******/
1149
1150 static void ath9k_hw_override_ini(struct ath_hw *ah,
1151                                   struct ath9k_channel *chan)
1152 {
1153         /*
1154          * Set the RX_ABORT and RX_DIS and clear if off only after
1155          * RXE is set for MAC. This prevents frames with corrupted
1156          * descriptor status.
1157          */
1158         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1159
1160
1161         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1162             AR_SREV_9280_10_OR_LATER(ah))
1163                 return;
1164
1165         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1166 }
1167
1168 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1169                               struct ar5416_eeprom_def *pEepData,
1170                               u32 reg, u32 value)
1171 {
1172         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1173
1174         switch (ah->hw_version.devid) {
1175         case AR9280_DEVID_PCI:
1176                 if (reg == 0x7894) {
1177                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1178                                 "ini VAL: %x  EEPROM: %x\n", value,
1179                                 (pBase->version & 0xff));
1180
1181                         if ((pBase->version & 0xff) > 0x0a) {
1182                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1183                                         "PWDCLKIND: %d\n",
1184                                         pBase->pwdclkind);
1185                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1186                                 value |= AR_AN_TOP2_PWDCLKIND &
1187                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1188                         } else {
1189                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1190                                         "PWDCLKIND Earlier Rev\n");
1191                         }
1192
1193                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1194                                 "final ini VAL: %x\n", value);
1195                 }
1196                 break;
1197         }
1198
1199         return value;
1200 }
1201
1202 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1203                               struct ar5416_eeprom_def *pEepData,
1204                               u32 reg, u32 value)
1205 {
1206         if (ah->eep_map == EEP_MAP_4KBITS)
1207                 return value;
1208         else
1209                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1210 }
1211
1212 static void ath9k_olc_init(struct ath_hw *ah)
1213 {
1214         u32 i;
1215
1216         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1217                 ah->originalGain[i] =
1218                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1219                                         AR_PHY_TX_GAIN);
1220         ah->PDADCdelta = 0;
1221 }
1222
1223 static int ath9k_hw_process_ini(struct ath_hw *ah,
1224                                 struct ath9k_channel *chan,
1225                                 enum ath9k_ht_macmode macmode)
1226 {
1227         int i, regWrites = 0;
1228         struct ieee80211_channel *channel = chan->chan;
1229         u32 modesIndex, freqIndex;
1230         int status;
1231
1232         switch (chan->chanmode) {
1233         case CHANNEL_A:
1234         case CHANNEL_A_HT20:
1235                 modesIndex = 1;
1236                 freqIndex = 1;
1237                 break;
1238         case CHANNEL_A_HT40PLUS:
1239         case CHANNEL_A_HT40MINUS:
1240                 modesIndex = 2;
1241                 freqIndex = 1;
1242                 break;
1243         case CHANNEL_G:
1244         case CHANNEL_G_HT20:
1245         case CHANNEL_B:
1246                 modesIndex = 4;
1247                 freqIndex = 2;
1248                 break;
1249         case CHANNEL_G_HT40PLUS:
1250         case CHANNEL_G_HT40MINUS:
1251                 modesIndex = 3;
1252                 freqIndex = 2;
1253                 break;
1254
1255         default:
1256                 return -EINVAL;
1257         }
1258
1259         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1260         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1261         ah->eep_ops->set_addac(ah, chan);
1262
1263         if (AR_SREV_5416_22_OR_LATER(ah)) {
1264                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1265         } else {
1266                 struct ar5416IniArray temp;
1267                 u32 addacSize =
1268                         sizeof(u32) * ah->iniAddac.ia_rows *
1269                         ah->iniAddac.ia_columns;
1270
1271                 memcpy(ah->addac5416_21,
1272                        ah->iniAddac.ia_array, addacSize);
1273
1274                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1275
1276                 temp.ia_array = ah->addac5416_21;
1277                 temp.ia_columns = ah->iniAddac.ia_columns;
1278                 temp.ia_rows = ah->iniAddac.ia_rows;
1279                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1280         }
1281
1282         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1283
1284         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1285                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1286                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1287
1288                 REG_WRITE(ah, reg, val);
1289
1290                 if (reg >= 0x7800 && reg < 0x78a0
1291                     && ah->config.analog_shiftreg) {
1292                         udelay(100);
1293                 }
1294
1295                 DO_DELAY(regWrites);
1296         }
1297
1298         if (AR_SREV_9280(ah))
1299                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1300
1301         if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1302             AR_SREV_9285_12_OR_LATER(ah)))
1303                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1304
1305         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1306                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1307                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1308
1309                 REG_WRITE(ah, reg, val);
1310
1311                 if (reg >= 0x7800 && reg < 0x78a0
1312                     && ah->config.analog_shiftreg) {
1313                         udelay(100);
1314                 }
1315
1316                 DO_DELAY(regWrites);
1317         }
1318
1319         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1320
1321         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1322                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1323                                 regWrites);
1324         }
1325
1326         ath9k_hw_override_ini(ah, chan);
1327         ath9k_hw_set_regs(ah, chan, macmode);
1328         ath9k_hw_init_chain_masks(ah);
1329
1330         if (OLC_FOR_AR9280_20_LATER)
1331                 ath9k_olc_init(ah);
1332
1333         status = ah->eep_ops->set_txpower(ah, chan,
1334                                   ath9k_regd_get_ctl(&ah->regulatory, chan),
1335                                   channel->max_antenna_gain * 2,
1336                                   channel->max_power * 2,
1337                                   min((u32) MAX_RATE_POWER,
1338                                       (u32) ah->regulatory.power_limit));
1339         if (status != 0) {
1340                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1341                         "Error initializing transmit power\n");
1342                 return -EIO;
1343         }
1344
1345         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1346                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1347                         "ar5416SetRfRegs failed\n");
1348                 return -EIO;
1349         }
1350
1351         return 0;
1352 }
1353
1354 /****************************************/
1355 /* Reset and Channel Switching Routines */
1356 /****************************************/
1357
1358 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1359 {
1360         u32 rfMode = 0;
1361
1362         if (chan == NULL)
1363                 return;
1364
1365         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1366                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1367
1368         if (!AR_SREV_9280_10_OR_LATER(ah))
1369                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1370                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1371
1372         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1373                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1374
1375         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1376 }
1377
1378 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1379 {
1380         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1381 }
1382
1383 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1384 {
1385         u32 regval;
1386
1387         regval = REG_READ(ah, AR_AHB_MODE);
1388         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1389
1390         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1391         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1392
1393         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1394
1395         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1396         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1397
1398         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1399
1400         if (AR_SREV_9285(ah)) {
1401                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1402                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1403         } else {
1404                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1405                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1406         }
1407 }
1408
1409 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1410 {
1411         u32 val;
1412
1413         val = REG_READ(ah, AR_STA_ID1);
1414         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1415         switch (opmode) {
1416         case NL80211_IFTYPE_AP:
1417                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1418                           | AR_STA_ID1_KSRCH_MODE);
1419                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1420                 break;
1421         case NL80211_IFTYPE_ADHOC:
1422         case NL80211_IFTYPE_MESH_POINT:
1423                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1424                           | AR_STA_ID1_KSRCH_MODE);
1425                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1426                 break;
1427         case NL80211_IFTYPE_STATION:
1428         case NL80211_IFTYPE_MONITOR:
1429                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1430                 break;
1431         }
1432 }
1433
1434 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1435                                                  u32 coef_scaled,
1436                                                  u32 *coef_mantissa,
1437                                                  u32 *coef_exponent)
1438 {
1439         u32 coef_exp, coef_man;
1440
1441         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1442                 if ((coef_scaled >> coef_exp) & 0x1)
1443                         break;
1444
1445         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1446
1447         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1448
1449         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1450         *coef_exponent = coef_exp - 16;
1451 }
1452
1453 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1454                                      struct ath9k_channel *chan)
1455 {
1456         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1457         u32 clockMhzScaled = 0x64000000;
1458         struct chan_centers centers;
1459
1460         if (IS_CHAN_HALF_RATE(chan))
1461                 clockMhzScaled = clockMhzScaled >> 1;
1462         else if (IS_CHAN_QUARTER_RATE(chan))
1463                 clockMhzScaled = clockMhzScaled >> 2;
1464
1465         ath9k_hw_get_channel_centers(ah, chan, &centers);
1466         coef_scaled = clockMhzScaled / centers.synth_center;
1467
1468         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1469                                       &ds_coef_exp);
1470
1471         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1472                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1473         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1474                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1475
1476         coef_scaled = (9 * coef_scaled) / 10;
1477
1478         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1479                                       &ds_coef_exp);
1480
1481         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1482                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1483         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1484                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1485 }
1486
1487 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1488 {
1489         u32 rst_flags;
1490         u32 tmpReg;
1491
1492         if (AR_SREV_9100(ah)) {
1493                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1494                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1495                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1496                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1497                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1498         }
1499
1500         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1501                   AR_RTC_FORCE_WAKE_ON_INT);
1502
1503         if (AR_SREV_9100(ah)) {
1504                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1505                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1506         } else {
1507                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1508                 if (tmpReg &
1509                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1510                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1511                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1512                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1513                 } else {
1514                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1515                 }
1516
1517                 rst_flags = AR_RTC_RC_MAC_WARM;
1518                 if (type == ATH9K_RESET_COLD)
1519                         rst_flags |= AR_RTC_RC_MAC_COLD;
1520         }
1521
1522         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1523         udelay(50);
1524
1525         REG_WRITE(ah, AR_RTC_RC, 0);
1526         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1527                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1528                         "RTC stuck in MAC reset\n");
1529                 return false;
1530         }
1531
1532         if (!AR_SREV_9100(ah))
1533                 REG_WRITE(ah, AR_RC, 0);
1534
1535         ath9k_hw_init_pll(ah, NULL);
1536
1537         if (AR_SREV_9100(ah))
1538                 udelay(50);
1539
1540         return true;
1541 }
1542
1543 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1544 {
1545         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1546                   AR_RTC_FORCE_WAKE_ON_INT);
1547
1548         REG_WRITE(ah, AR_RTC_RESET, 0);
1549         udelay(2);
1550         REG_WRITE(ah, AR_RTC_RESET, 1);
1551
1552         if (!ath9k_hw_wait(ah,
1553                            AR_RTC_STATUS,
1554                            AR_RTC_STATUS_M,
1555                            AR_RTC_STATUS_ON,
1556                            AH_WAIT_TIMEOUT)) {
1557                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1558                 return false;
1559         }
1560
1561         ath9k_hw_read_revisions(ah);
1562
1563         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1564 }
1565
1566 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1567 {
1568         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1569                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1570
1571         switch (type) {
1572         case ATH9K_RESET_POWER_ON:
1573                 return ath9k_hw_set_reset_power_on(ah);
1574                 break;
1575         case ATH9K_RESET_WARM:
1576         case ATH9K_RESET_COLD:
1577                 return ath9k_hw_set_reset(ah, type);
1578                 break;
1579         default:
1580                 return false;
1581         }
1582 }
1583
1584 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1585                               enum ath9k_ht_macmode macmode)
1586 {
1587         u32 phymode;
1588         u32 enableDacFifo = 0;
1589
1590         if (AR_SREV_9285_10_OR_LATER(ah))
1591                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1592                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1593
1594         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1595                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1596
1597         if (IS_CHAN_HT40(chan)) {
1598                 phymode |= AR_PHY_FC_DYN2040_EN;
1599
1600                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1601                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1602                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1603
1604                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1605                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1606         }
1607         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1608
1609         ath9k_hw_set11nmac2040(ah, macmode);
1610
1611         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1612         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1613 }
1614
1615 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1616                                 struct ath9k_channel *chan)
1617 {
1618         if (OLC_FOR_AR9280_20_LATER) {
1619                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1620                         return false;
1621         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1622                 return false;
1623
1624         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1625                 return false;
1626
1627         ah->chip_fullsleep = false;
1628         ath9k_hw_init_pll(ah, chan);
1629         ath9k_hw_set_rfmode(ah, chan);
1630
1631         return true;
1632 }
1633
1634 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1635                                     struct ath9k_channel *chan,
1636                                     enum ath9k_ht_macmode macmode)
1637 {
1638         struct ieee80211_channel *channel = chan->chan;
1639         u32 synthDelay, qnum;
1640
1641         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1642                 if (ath9k_hw_numtxpending(ah, qnum)) {
1643                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1644                                 "Transmit frames pending on queue %d\n", qnum);
1645                         return false;
1646                 }
1647         }
1648
1649         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1650         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1651                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1652                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1653                         "Could not kill baseband RX\n");
1654                 return false;
1655         }
1656
1657         ath9k_hw_set_regs(ah, chan, macmode);
1658
1659         if (AR_SREV_9280_10_OR_LATER(ah)) {
1660                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1661                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1662                                 "Failed to set channel\n");
1663                         return false;
1664                 }
1665         } else {
1666                 if (!(ath9k_hw_set_channel(ah, chan))) {
1667                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1668                                 "Failed to set channel\n");
1669                         return false;
1670                 }
1671         }
1672
1673         if (ah->eep_ops->set_txpower(ah, chan,
1674                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1675                              channel->max_antenna_gain * 2,
1676                              channel->max_power * 2,
1677                              min((u32) MAX_RATE_POWER,
1678                                  (u32) ah->regulatory.power_limit)) != 0) {
1679                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1680                         "Error initializing transmit power\n");
1681                 return false;
1682         }
1683
1684         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1685         if (IS_CHAN_B(chan))
1686                 synthDelay = (4 * synthDelay) / 22;
1687         else
1688                 synthDelay /= 10;
1689
1690         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1691
1692         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1693
1694         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1695                 ath9k_hw_set_delta_slope(ah, chan);
1696
1697         if (AR_SREV_9280_10_OR_LATER(ah))
1698                 ath9k_hw_9280_spur_mitigate(ah, chan);
1699         else
1700                 ath9k_hw_spur_mitigate(ah, chan);
1701
1702         if (!chan->oneTimeCalsDone)
1703                 chan->oneTimeCalsDone = true;
1704
1705         return true;
1706 }
1707
1708 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1709 {
1710         int bb_spur = AR_NO_SPUR;
1711         int freq;
1712         int bin, cur_bin;
1713         int bb_spur_off, spur_subchannel_sd;
1714         int spur_freq_sd;
1715         int spur_delta_phase;
1716         int denominator;
1717         int upper, lower, cur_vit_mask;
1718         int tmp, newVal;
1719         int i;
1720         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1721                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1722         };
1723         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1724                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1725         };
1726         int inc[4] = { 0, 100, 0, 0 };
1727         struct chan_centers centers;
1728
1729         int8_t mask_m[123];
1730         int8_t mask_p[123];
1731         int8_t mask_amt;
1732         int tmp_mask;
1733         int cur_bb_spur;
1734         bool is2GHz = IS_CHAN_2GHZ(chan);
1735
1736         memset(&mask_m, 0, sizeof(int8_t) * 123);
1737         memset(&mask_p, 0, sizeof(int8_t) * 123);
1738
1739         ath9k_hw_get_channel_centers(ah, chan, &centers);
1740         freq = centers.synth_center;
1741
1742         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1743         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1744                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1745
1746                 if (is2GHz)
1747                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1748                 else
1749                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1750
1751                 if (AR_NO_SPUR == cur_bb_spur)
1752                         break;
1753                 cur_bb_spur = cur_bb_spur - freq;
1754
1755                 if (IS_CHAN_HT40(chan)) {
1756                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1757                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1758                                 bb_spur = cur_bb_spur;
1759                                 break;
1760                         }
1761                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1762                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1763                         bb_spur = cur_bb_spur;
1764                         break;
1765                 }
1766         }
1767
1768         if (AR_NO_SPUR == bb_spur) {
1769                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1770                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1771                 return;
1772         } else {
1773                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1774                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1775         }
1776
1777         bin = bb_spur * 320;
1778
1779         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1780
1781         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1782                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1783                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1784                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1785         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1786
1787         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1788                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1789                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1790                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1791                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1792         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1793
1794         if (IS_CHAN_HT40(chan)) {
1795                 if (bb_spur < 0) {
1796                         spur_subchannel_sd = 1;
1797                         bb_spur_off = bb_spur + 10;
1798                 } else {
1799                         spur_subchannel_sd = 0;
1800                         bb_spur_off = bb_spur - 10;
1801                 }
1802         } else {
1803                 spur_subchannel_sd = 0;
1804                 bb_spur_off = bb_spur;
1805         }
1806
1807         if (IS_CHAN_HT40(chan))
1808                 spur_delta_phase =
1809                         ((bb_spur * 262144) /
1810                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1811         else
1812                 spur_delta_phase =
1813                         ((bb_spur * 524288) /
1814                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1815
1816         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1817         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1818
1819         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1820                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1821                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1822         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1823
1824         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1825         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1826
1827         cur_bin = -6000;
1828         upper = bin + 100;
1829         lower = bin - 100;
1830
1831         for (i = 0; i < 4; i++) {
1832                 int pilot_mask = 0;
1833                 int chan_mask = 0;
1834                 int bp = 0;
1835                 for (bp = 0; bp < 30; bp++) {
1836                         if ((cur_bin > lower) && (cur_bin < upper)) {
1837                                 pilot_mask = pilot_mask | 0x1 << bp;
1838                                 chan_mask = chan_mask | 0x1 << bp;
1839                         }
1840                         cur_bin += 100;
1841                 }
1842                 cur_bin += inc[i];
1843                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1844                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1845         }
1846
1847         cur_vit_mask = 6100;
1848         upper = bin + 120;
1849         lower = bin - 120;
1850
1851         for (i = 0; i < 123; i++) {
1852                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1853
1854                         /* workaround for gcc bug #37014 */
1855                         volatile int tmp_v = abs(cur_vit_mask - bin);
1856
1857                         if (tmp_v < 75)
1858                                 mask_amt = 1;
1859                         else
1860                                 mask_amt = 0;
1861                         if (cur_vit_mask < 0)
1862                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1863                         else
1864                                 mask_p[cur_vit_mask / 100] = mask_amt;
1865                 }
1866                 cur_vit_mask -= 100;
1867         }
1868
1869         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1870                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1871                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1872                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1873                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1874                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1875                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1876                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1877         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1878         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1879
1880         tmp_mask = (mask_m[31] << 28)
1881                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1882                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1883                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1884                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1885                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1886                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1887                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1888         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1889         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1890
1891         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1892                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1893                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1894                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1895                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1896                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1897                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1898                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1899         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1900         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1901
1902         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1903                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1904                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1905                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1906                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1907                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1908                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1909                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1910         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1911         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1912
1913         tmp_mask = (mask_p[15] << 28)
1914                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1915                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1916                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1917                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1918                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1919                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1920                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1921         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1922         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1923
1924         tmp_mask = (mask_p[30] << 28)
1925                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1926                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1927                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1928                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1929                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1930                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1931                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1932         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1933         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1934
1935         tmp_mask = (mask_p[45] << 28)
1936                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1937                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1938                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1939                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1940                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1941                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1942                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1943         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1944         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1945
1946         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1947                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1948                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1949                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1950                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1951                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1952                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1953                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1954         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1955         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1956 }
1957
1958 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1959 {
1960         int bb_spur = AR_NO_SPUR;
1961         int bin, cur_bin;
1962         int spur_freq_sd;
1963         int spur_delta_phase;
1964         int denominator;
1965         int upper, lower, cur_vit_mask;
1966         int tmp, new;
1967         int i;
1968         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1969                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1970         };
1971         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1972                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1973         };
1974         int inc[4] = { 0, 100, 0, 0 };
1975
1976         int8_t mask_m[123];
1977         int8_t mask_p[123];
1978         int8_t mask_amt;
1979         int tmp_mask;
1980         int cur_bb_spur;
1981         bool is2GHz = IS_CHAN_2GHZ(chan);
1982
1983         memset(&mask_m, 0, sizeof(int8_t) * 123);
1984         memset(&mask_p, 0, sizeof(int8_t) * 123);
1985
1986         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1987                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1988                 if (AR_NO_SPUR == cur_bb_spur)
1989                         break;
1990                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1991                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1992                         bb_spur = cur_bb_spur;
1993                         break;
1994                 }
1995         }
1996
1997         if (AR_NO_SPUR == bb_spur)
1998                 return;
1999
2000         bin = bb_spur * 32;
2001
2002         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2003         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2004                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2005                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2006                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2007
2008         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2009
2010         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2011                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2012                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2013                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2014                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2015         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2016
2017         spur_delta_phase = ((bb_spur * 524288) / 100) &
2018                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2019
2020         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2021         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2022
2023         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2024                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2025                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2026         REG_WRITE(ah, AR_PHY_TIMING11, new);
2027
2028         cur_bin = -6000;
2029         upper = bin + 100;
2030         lower = bin - 100;
2031
2032         for (i = 0; i < 4; i++) {
2033                 int pilot_mask = 0;
2034                 int chan_mask = 0;
2035                 int bp = 0;
2036                 for (bp = 0; bp < 30; bp++) {
2037                         if ((cur_bin > lower) && (cur_bin < upper)) {
2038                                 pilot_mask = pilot_mask | 0x1 << bp;
2039                                 chan_mask = chan_mask | 0x1 << bp;
2040                         }
2041                         cur_bin += 100;
2042                 }
2043                 cur_bin += inc[i];
2044                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2045                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2046         }
2047
2048         cur_vit_mask = 6100;
2049         upper = bin + 120;
2050         lower = bin - 120;
2051
2052         for (i = 0; i < 123; i++) {
2053                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2054
2055                         /* workaround for gcc bug #37014 */
2056                         volatile int tmp_v = abs(cur_vit_mask - bin);
2057
2058                         if (tmp_v < 75)
2059                                 mask_amt = 1;
2060                         else
2061                                 mask_amt = 0;
2062                         if (cur_vit_mask < 0)
2063                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2064                         else
2065                                 mask_p[cur_vit_mask / 100] = mask_amt;
2066                 }
2067                 cur_vit_mask -= 100;
2068         }
2069
2070         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2071                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2072                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2073                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2074                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2075                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2076                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2077                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2078         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2079         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2080
2081         tmp_mask = (mask_m[31] << 28)
2082                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2083                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2084                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2085                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2086                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2087                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2088                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2089         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2090         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2091
2092         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2093                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2094                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2095                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2096                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2097                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2098                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2099                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2100         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2101         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2102
2103         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2104                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2105                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2106                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2107                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2108                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2109                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2110                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2111         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2112         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2113
2114         tmp_mask = (mask_p[15] << 28)
2115                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2116                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2117                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2118                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2119                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2120                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2121                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2122         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2123         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2124
2125         tmp_mask = (mask_p[30] << 28)
2126                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2127                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2128                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2129                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2130                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2131                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2132                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2133         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2134         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2135
2136         tmp_mask = (mask_p[45] << 28)
2137                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2138                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2139                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2140                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2141                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2142                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2143                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2144         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2145         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2146
2147         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2148                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2149                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2150                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2151                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2152                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2153                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2154                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2155         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2156         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2157 }
2158
2159 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2160                     bool bChannelChange)
2161 {
2162         u32 saveLedState;
2163         struct ath_softc *sc = ah->ah_sc;
2164         struct ath9k_channel *curchan = ah->curchan;
2165         u32 saveDefAntenna;
2166         u32 macStaId1;
2167         int i, rx_chainmask, r;
2168
2169         ah->extprotspacing = sc->ht_extprotspacing;
2170         ah->txchainmask = sc->tx_chainmask;
2171         ah->rxchainmask = sc->rx_chainmask;
2172
2173         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2174                 return -EIO;
2175
2176         if (curchan)
2177                 ath9k_hw_getnf(ah, curchan);
2178
2179         if (bChannelChange &&
2180             (ah->chip_fullsleep != true) &&
2181             (ah->curchan != NULL) &&
2182             (chan->channel != ah->curchan->channel) &&
2183             ((chan->channelFlags & CHANNEL_ALL) ==
2184              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2185             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2186                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2187
2188                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2189                         ath9k_hw_loadnf(ah, ah->curchan);
2190                         ath9k_hw_start_nfcal(ah);
2191                         return 0;
2192                 }
2193         }
2194
2195         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2196         if (saveDefAntenna == 0)
2197                 saveDefAntenna = 1;
2198
2199         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2200
2201         saveLedState = REG_READ(ah, AR_CFG_LED) &
2202                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2203                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2204
2205         ath9k_hw_mark_phy_inactive(ah);
2206
2207         if (!ath9k_hw_chip_reset(ah, chan)) {
2208                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2209                 return -EINVAL;
2210         }
2211
2212         if (AR_SREV_9280_10_OR_LATER(ah))
2213                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2214
2215         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2216         if (r)
2217                 return r;
2218
2219         /* Setup MFP options for CCMP */
2220         if (AR_SREV_9280_20_OR_LATER(ah)) {
2221                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2222                  * frames when constructing CCMP AAD. */
2223                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2224                               0xc7ff);
2225                 ah->sw_mgmt_crypto = false;
2226         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2227                 /* Disable hardware crypto for management frames */
2228                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2229                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2230                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2231                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2232                 ah->sw_mgmt_crypto = true;
2233         } else
2234                 ah->sw_mgmt_crypto = true;
2235
2236         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2237                 ath9k_hw_set_delta_slope(ah, chan);
2238
2239         if (AR_SREV_9280_10_OR_LATER(ah))
2240                 ath9k_hw_9280_spur_mitigate(ah, chan);
2241         else
2242                 ath9k_hw_spur_mitigate(ah, chan);
2243
2244         ah->eep_ops->set_board_values(ah, chan);
2245
2246         ath9k_hw_decrease_chain_power(ah, chan);
2247
2248         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2249         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2250                   | macStaId1
2251                   | AR_STA_ID1_RTS_USE_DEF
2252                   | (ah->config.
2253                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2254                   | ah->sta_id1_defaults);
2255         ath9k_hw_set_operating_mode(ah, ah->opmode);
2256
2257         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2258         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2259
2260         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2261
2262         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2263         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2264                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2265
2266         REG_WRITE(ah, AR_ISR, ~0);
2267
2268         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2269
2270         if (AR_SREV_9280_10_OR_LATER(ah)) {
2271                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2272                         return -EIO;
2273         } else {
2274                 if (!(ath9k_hw_set_channel(ah, chan)))
2275                         return -EIO;
2276         }
2277
2278         for (i = 0; i < AR_NUM_DCU; i++)
2279                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2280
2281         ah->intr_txqs = 0;
2282         for (i = 0; i < ah->caps.total_queues; i++)
2283                 ath9k_hw_resettxqueue(ah, i);
2284
2285         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2286         ath9k_hw_init_qos(ah);
2287
2288 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2289         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2290                 ath9k_enable_rfkill(ah);
2291 #endif
2292         ath9k_hw_init_user_settings(ah);
2293
2294         REG_WRITE(ah, AR_STA_ID1,
2295                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2296
2297         ath9k_hw_set_dma(ah);
2298
2299         REG_WRITE(ah, AR_OBS, 8);
2300
2301         if (ah->config.intr_mitigation) {
2302                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2303                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2304         }
2305
2306         ath9k_hw_init_bb(ah, chan);
2307
2308         if (!ath9k_hw_init_cal(ah, chan))
2309                 return -EIO;;
2310
2311         rx_chainmask = ah->rxchainmask;
2312         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2313                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2314                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2315         }
2316
2317         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2318
2319         if (AR_SREV_9100(ah)) {
2320                 u32 mask;
2321                 mask = REG_READ(ah, AR_CFG);
2322                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2323                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2324                                 "CFG Byte Swap Set 0x%x\n", mask);
2325                 } else {
2326                         mask =
2327                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2328                         REG_WRITE(ah, AR_CFG, mask);
2329                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2330                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2331                 }
2332         } else {
2333 #ifdef __BIG_ENDIAN
2334                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2335 #endif
2336         }
2337
2338         return 0;
2339 }
2340
2341 /************************/
2342 /* Key Cache Management */
2343 /************************/
2344
2345 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2346 {
2347         u32 keyType;
2348
2349         if (entry >= ah->caps.keycache_size) {
2350                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2351                         "keychache entry %u out of range\n", entry);
2352                 return false;
2353         }
2354
2355         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2356
2357         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2358         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2359         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2360         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2361         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2362         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2363         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2364         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2365
2366         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2367                 u16 micentry = entry + 64;
2368
2369                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2370                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2371                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2372                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2373
2374         }
2375
2376         if (ah->curchan == NULL)
2377                 return true;
2378
2379         return true;
2380 }
2381
2382 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2383 {
2384         u32 macHi, macLo;
2385
2386         if (entry >= ah->caps.keycache_size) {
2387                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2388                         "keychache entry %u out of range\n", entry);
2389                 return false;
2390         }
2391
2392         if (mac != NULL) {
2393                 macHi = (mac[5] << 8) | mac[4];
2394                 macLo = (mac[3] << 24) |
2395                         (mac[2] << 16) |
2396                         (mac[1] << 8) |
2397                         mac[0];
2398                 macLo >>= 1;
2399                 macLo |= (macHi & 1) << 31;
2400                 macHi >>= 1;
2401         } else {
2402                 macLo = macHi = 0;
2403         }
2404         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2405         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2406
2407         return true;
2408 }
2409
2410 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2411                                  const struct ath9k_keyval *k,
2412                                  const u8 *mac)
2413 {
2414         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2415         u32 key0, key1, key2, key3, key4;
2416         u32 keyType;
2417
2418         if (entry >= pCap->keycache_size) {
2419                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2420                         "keycache entry %u out of range\n", entry);
2421                 return false;
2422         }
2423
2424         switch (k->kv_type) {
2425         case ATH9K_CIPHER_AES_OCB:
2426                 keyType = AR_KEYTABLE_TYPE_AES;
2427                 break;
2428         case ATH9K_CIPHER_AES_CCM:
2429                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2430                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2431                                 "AES-CCM not supported by mac rev 0x%x\n",
2432                                 ah->hw_version.macRev);
2433                         return false;
2434                 }
2435                 keyType = AR_KEYTABLE_TYPE_CCM;
2436                 break;
2437         case ATH9K_CIPHER_TKIP:
2438                 keyType = AR_KEYTABLE_TYPE_TKIP;
2439                 if (ATH9K_IS_MIC_ENABLED(ah)
2440                     && entry + 64 >= pCap->keycache_size) {
2441                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2442                                 "entry %u inappropriate for TKIP\n", entry);
2443                         return false;
2444                 }
2445                 break;
2446         case ATH9K_CIPHER_WEP:
2447                 if (k->kv_len < LEN_WEP40) {
2448                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2449                                 "WEP key length %u too small\n", k->kv_len);
2450                         return false;
2451                 }
2452                 if (k->kv_len <= LEN_WEP40)
2453                         keyType = AR_KEYTABLE_TYPE_40;
2454                 else if (k->kv_len <= LEN_WEP104)
2455                         keyType = AR_KEYTABLE_TYPE_104;
2456                 else
2457                         keyType = AR_KEYTABLE_TYPE_128;
2458                 break;
2459         case ATH9K_CIPHER_CLR:
2460                 keyType = AR_KEYTABLE_TYPE_CLR;
2461                 break;
2462         default:
2463                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2464                         "cipher %u not supported\n", k->kv_type);
2465                 return false;
2466         }
2467
2468         key0 = get_unaligned_le32(k->kv_val + 0);
2469         key1 = get_unaligned_le16(k->kv_val + 4);
2470         key2 = get_unaligned_le32(k->kv_val + 6);
2471         key3 = get_unaligned_le16(k->kv_val + 10);
2472         key4 = get_unaligned_le32(k->kv_val + 12);
2473         if (k->kv_len <= LEN_WEP104)
2474                 key4 &= 0xff;
2475
2476         /*
2477          * Note: Key cache registers access special memory area that requires
2478          * two 32-bit writes to actually update the values in the internal
2479          * memory. Consequently, the exact order and pairs used here must be
2480          * maintained.
2481          */
2482
2483         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2484                 u16 micentry = entry + 64;
2485
2486                 /*
2487                  * Write inverted key[47:0] first to avoid Michael MIC errors
2488                  * on frames that could be sent or received at the same time.
2489                  * The correct key will be written in the end once everything
2490                  * else is ready.
2491                  */
2492                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2493                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2494
2495                 /* Write key[95:48] */
2496                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2497                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2498
2499                 /* Write key[127:96] and key type */
2500                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2501                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2502
2503                 /* Write MAC address for the entry */
2504                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2505
2506                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2507                         /*
2508                          * TKIP uses two key cache entries:
2509                          * Michael MIC TX/RX keys in the same key cache entry
2510                          * (idx = main index + 64):
2511                          * key0 [31:0] = RX key [31:0]
2512                          * key1 [15:0] = TX key [31:16]
2513                          * key1 [31:16] = reserved
2514                          * key2 [31:0] = RX key [63:32]
2515                          * key3 [15:0] = TX key [15:0]
2516                          * key3 [31:16] = reserved
2517                          * key4 [31:0] = TX key [63:32]
2518                          */
2519                         u32 mic0, mic1, mic2, mic3, mic4;
2520
2521                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2522                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2523                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2524                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2525                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2526
2527                         /* Write RX[31:0] and TX[31:16] */
2528                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2529                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2530
2531                         /* Write RX[63:32] and TX[15:0] */
2532                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2533                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2534
2535                         /* Write TX[63:32] and keyType(reserved) */
2536                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2537                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2538                                   AR_KEYTABLE_TYPE_CLR);
2539
2540                 } else {
2541                         /*
2542                          * TKIP uses four key cache entries (two for group
2543                          * keys):
2544                          * Michael MIC TX/RX keys are in different key cache
2545                          * entries (idx = main index + 64 for TX and
2546                          * main index + 32 + 96 for RX):
2547                          * key0 [31:0] = TX/RX MIC key [31:0]
2548                          * key1 [31:0] = reserved
2549                          * key2 [31:0] = TX/RX MIC key [63:32]
2550                          * key3 [31:0] = reserved
2551                          * key4 [31:0] = reserved
2552                          *
2553                          * Upper layer code will call this function separately
2554                          * for TX and RX keys when these registers offsets are
2555                          * used.
2556                          */
2557                         u32 mic0, mic2;
2558
2559                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2560                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2561
2562                         /* Write MIC key[31:0] */
2563                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2564                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2565
2566                         /* Write MIC key[63:32] */
2567                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2568                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2569
2570                         /* Write TX[63:32] and keyType(reserved) */
2571                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2572                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2573                                   AR_KEYTABLE_TYPE_CLR);
2574                 }
2575
2576                 /* MAC address registers are reserved for the MIC entry */
2577                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2578                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2579
2580                 /*
2581                  * Write the correct (un-inverted) key[47:0] last to enable
2582                  * TKIP now that all other registers are set with correct
2583                  * values.
2584                  */
2585                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2586                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2587         } else {
2588                 /* Write key[47:0] */
2589                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2590                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2591
2592                 /* Write key[95:48] */
2593                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2594                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2595
2596                 /* Write key[127:96] and key type */
2597                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2598                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2599
2600                 /* Write MAC address for the entry */
2601                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2602         }
2603
2604         return true;
2605 }
2606
2607 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2608 {
2609         if (entry < ah->caps.keycache_size) {
2610                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2611                 if (val & AR_KEYTABLE_VALID)
2612                         return true;
2613         }
2614         return false;
2615 }
2616
2617 /******************************/
2618 /* Power Management (Chipset) */
2619 /******************************/
2620
2621 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2622 {
2623         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2624         if (setChip) {
2625                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2626                             AR_RTC_FORCE_WAKE_EN);
2627                 if (!AR_SREV_9100(ah))
2628                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2629
2630                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2631                             AR_RTC_RESET_EN);
2632         }
2633 }
2634
2635 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2636 {
2637         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2638         if (setChip) {
2639                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2640
2641                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2642                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2643                                   AR_RTC_FORCE_WAKE_ON_INT);
2644                 } else {
2645                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2646                                     AR_RTC_FORCE_WAKE_EN);
2647                 }
2648         }
2649 }
2650
2651 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2652 {
2653         u32 val;
2654         int i;
2655
2656         if (setChip) {
2657                 if ((REG_READ(ah, AR_RTC_STATUS) &
2658                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2659                         if (ath9k_hw_set_reset_reg(ah,
2660                                            ATH9K_RESET_POWER_ON) != true) {
2661                                 return false;
2662                         }
2663                 }
2664                 if (AR_SREV_9100(ah))
2665                         REG_SET_BIT(ah, AR_RTC_RESET,
2666                                     AR_RTC_RESET_EN);
2667
2668                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2669                             AR_RTC_FORCE_WAKE_EN);
2670                 udelay(50);
2671
2672                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2673                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2674                         if (val == AR_RTC_STATUS_ON)
2675                                 break;
2676                         udelay(50);
2677                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2678                                     AR_RTC_FORCE_WAKE_EN);
2679                 }
2680                 if (i == 0) {
2681                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2682                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2683                         return false;
2684                 }
2685         }
2686
2687         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2688
2689         return true;
2690 }
2691
2692 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2693 {
2694         int status = true, setChip = true;
2695         static const char *modes[] = {
2696                 "AWAKE",
2697                 "FULL-SLEEP",
2698                 "NETWORK SLEEP",
2699                 "UNDEFINED"
2700         };
2701
2702         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2703                 modes[ah->power_mode], modes[mode]);
2704
2705         switch (mode) {
2706         case ATH9K_PM_AWAKE:
2707                 status = ath9k_hw_set_power_awake(ah, setChip);
2708                 break;
2709         case ATH9K_PM_FULL_SLEEP:
2710                 ath9k_set_power_sleep(ah, setChip);
2711                 ah->chip_fullsleep = true;
2712                 break;
2713         case ATH9K_PM_NETWORK_SLEEP:
2714                 ath9k_set_power_network_sleep(ah, setChip);
2715                 break;
2716         default:
2717                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2718                         "Unknown power mode %u\n", mode);
2719                 return false;
2720         }
2721         ah->power_mode = mode;
2722
2723         return status;
2724 }
2725
2726 /*
2727  * Helper for ASPM support.
2728  *
2729  * Disable PLL when in L0s as well as receiver clock when in L1.
2730  * This power saving option must be enabled through the SerDes.
2731  *
2732  * Programming the SerDes must go through the same 288 bit serial shift
2733  * register as the other analog registers.  Hence the 9 writes.
2734  */
2735 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2736 {
2737         u8 i;
2738
2739         if (ah->is_pciexpress != true)
2740                 return;
2741
2742         /* Do not touch SerDes registers */
2743         if (ah->config.pcie_powersave_enable == 2)
2744                 return;
2745
2746         /* Nothing to do on restore for 11N */
2747         if (restore)
2748                 return;
2749
2750         if (AR_SREV_9280_20_OR_LATER(ah)) {
2751                 /*
2752                  * AR9280 2.0 or later chips use SerDes values from the
2753                  * initvals.h initialized depending on chipset during
2754                  * ath9k_hw_do_attach()
2755                  */
2756                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2757                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2758                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2759                 }
2760         } else if (AR_SREV_9280(ah) &&
2761                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2762                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2763                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2764
2765                 /* RX shut off when elecidle is asserted */
2766                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2767                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2768                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2769
2770                 /* Shut off CLKREQ active in L1 */
2771                 if (ah->config.pcie_clock_req)
2772                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2773                 else
2774                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2775
2776                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2777                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2778                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2779
2780                 /* Load the new settings */
2781                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2782
2783         } else {
2784                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2785                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2786
2787                 /* RX shut off when elecidle is asserted */
2788                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2789                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2790                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2791
2792                 /*
2793                  * Ignore ah->ah_config.pcie_clock_req setting for
2794                  * pre-AR9280 11n
2795                  */
2796                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2797
2798                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2799                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2800                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2801
2802                 /* Load the new settings */
2803                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2804         }
2805
2806         udelay(1000);
2807
2808         /* set bit 19 to allow forcing of pcie core into L1 state */
2809         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2810
2811         /* Several PCIe massages to ensure proper behaviour */
2812         if (ah->config.pcie_waen) {
2813                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2814         } else {
2815                 if (AR_SREV_9285(ah))
2816                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2817                 /*
2818                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2819                  * otherwise card may disappear.
2820                  */
2821                 else if (AR_SREV_9280(ah))
2822                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2823                 else
2824                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2825         }
2826 }
2827
2828 /**********************/
2829 /* Interrupt Handling */
2830 /**********************/
2831
2832 bool ath9k_hw_intrpend(struct ath_hw *ah)
2833 {
2834         u32 host_isr;
2835
2836         if (AR_SREV_9100(ah))
2837                 return true;
2838
2839         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2840         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2841                 return true;
2842
2843         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2844         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2845             && (host_isr != AR_INTR_SPURIOUS))
2846                 return true;
2847
2848         return false;
2849 }
2850
2851 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2852 {
2853         u32 isr = 0;
2854         u32 mask2 = 0;
2855         struct ath9k_hw_capabilities *pCap = &ah->caps;
2856         u32 sync_cause = 0;
2857         bool fatal_int = false;
2858
2859         if (!AR_SREV_9100(ah)) {
2860                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2861                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2862                             == AR_RTC_STATUS_ON) {
2863                                 isr = REG_READ(ah, AR_ISR);
2864                         }
2865                 }
2866
2867                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2868                         AR_INTR_SYNC_DEFAULT;
2869
2870                 *masked = 0;
2871
2872                 if (!isr && !sync_cause)
2873                         return false;
2874         } else {
2875                 *masked = 0;
2876                 isr = REG_READ(ah, AR_ISR);
2877         }
2878
2879         if (isr) {
2880                 if (isr & AR_ISR_BCNMISC) {
2881                         u32 isr2;
2882                         isr2 = REG_READ(ah, AR_ISR_S2);
2883                         if (isr2 & AR_ISR_S2_TIM)
2884                                 mask2 |= ATH9K_INT_TIM;
2885                         if (isr2 & AR_ISR_S2_DTIM)
2886                                 mask2 |= ATH9K_INT_DTIM;
2887                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2888                                 mask2 |= ATH9K_INT_DTIMSYNC;
2889                         if (isr2 & (AR_ISR_S2_CABEND))
2890                                 mask2 |= ATH9K_INT_CABEND;
2891                         if (isr2 & AR_ISR_S2_GTT)
2892                                 mask2 |= ATH9K_INT_GTT;
2893                         if (isr2 & AR_ISR_S2_CST)
2894                                 mask2 |= ATH9K_INT_CST;
2895                         if (isr2 & AR_ISR_S2_TSFOOR)
2896                                 mask2 |= ATH9K_INT_TSFOOR;
2897                 }
2898
2899                 isr = REG_READ(ah, AR_ISR_RAC);
2900                 if (isr == 0xffffffff) {
2901                         *masked = 0;
2902                         return false;
2903                 }
2904
2905                 *masked = isr & ATH9K_INT_COMMON;
2906
2907                 if (ah->config.intr_mitigation) {
2908                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2909                                 *masked |= ATH9K_INT_RX;
2910                 }
2911
2912                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2913                         *masked |= ATH9K_INT_RX;
2914                 if (isr &
2915                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2916                      AR_ISR_TXEOL)) {
2917                         u32 s0_s, s1_s;
2918
2919                         *masked |= ATH9K_INT_TX;
2920
2921                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2922                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2923                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2924
2925                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2926                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2927                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2928                 }
2929
2930                 if (isr & AR_ISR_RXORN) {
2931                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2932                                 "receive FIFO overrun interrupt\n");
2933                 }
2934
2935                 if (!AR_SREV_9100(ah)) {
2936                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2937                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2938                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2939                                         *masked |= ATH9K_INT_TIM_TIMER;
2940                         }
2941                 }
2942
2943                 *masked |= mask2;
2944         }
2945
2946         if (AR_SREV_9100(ah))
2947                 return true;
2948
2949         if (sync_cause) {
2950                 fatal_int =
2951                         (sync_cause &
2952                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2953                         ? true : false;
2954
2955                 if (fatal_int) {
2956                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2957                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2958                                         "received PCI FATAL interrupt\n");
2959                         }
2960                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2961                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2962                                         "received PCI PERR interrupt\n");
2963                         }
2964                 }
2965                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2966                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2967                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2968                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2969                         REG_WRITE(ah, AR_RC, 0);
2970                         *masked |= ATH9K_INT_FATAL;
2971                 }
2972                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2973                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2974                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2975                 }
2976
2977                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2978                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2979         }
2980
2981         return true;
2982 }
2983
2984 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2985 {
2986         return ah->mask_reg;
2987 }
2988
2989 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2990 {
2991         u32 omask = ah->mask_reg;
2992         u32 mask, mask2;
2993         struct ath9k_hw_capabilities *pCap = &ah->caps;
2994
2995         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2996
2997         if (omask & ATH9K_INT_GLOBAL) {
2998                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2999                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3000                 (void) REG_READ(ah, AR_IER);
3001                 if (!AR_SREV_9100(ah)) {
3002                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3003                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3004
3005                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3006                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3007                 }
3008         }
3009
3010         mask = ints & ATH9K_INT_COMMON;
3011         mask2 = 0;
3012
3013         if (ints & ATH9K_INT_TX) {
3014                 if (ah->txok_interrupt_mask)
3015                         mask |= AR_IMR_TXOK;
3016                 if (ah->txdesc_interrupt_mask)
3017                         mask |= AR_IMR_TXDESC;
3018                 if (ah->txerr_interrupt_mask)
3019                         mask |= AR_IMR_TXERR;
3020                 if (ah->txeol_interrupt_mask)
3021                         mask |= AR_IMR_TXEOL;
3022         }
3023         if (ints & ATH9K_INT_RX) {
3024                 mask |= AR_IMR_RXERR;
3025                 if (ah->config.intr_mitigation)
3026                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3027                 else
3028                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3029                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3030                         mask |= AR_IMR_GENTMR;
3031         }
3032
3033         if (ints & (ATH9K_INT_BMISC)) {
3034                 mask |= AR_IMR_BCNMISC;
3035                 if (ints & ATH9K_INT_TIM)
3036                         mask2 |= AR_IMR_S2_TIM;
3037                 if (ints & ATH9K_INT_DTIM)
3038                         mask2 |= AR_IMR_S2_DTIM;
3039                 if (ints & ATH9K_INT_DTIMSYNC)
3040                         mask2 |= AR_IMR_S2_DTIMSYNC;
3041                 if (ints & ATH9K_INT_CABEND)
3042                         mask2 |= AR_IMR_S2_CABEND;
3043                 if (ints & ATH9K_INT_TSFOOR)
3044                         mask2 |= AR_IMR_S2_TSFOOR;
3045         }
3046
3047         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3048                 mask |= AR_IMR_BCNMISC;
3049                 if (ints & ATH9K_INT_GTT)
3050                         mask2 |= AR_IMR_S2_GTT;
3051                 if (ints & ATH9K_INT_CST)
3052                         mask2 |= AR_IMR_S2_CST;
3053         }
3054
3055         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3056         REG_WRITE(ah, AR_IMR, mask);
3057         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3058                                            AR_IMR_S2_DTIM |
3059                                            AR_IMR_S2_DTIMSYNC |
3060                                            AR_IMR_S2_CABEND |
3061                                            AR_IMR_S2_CABTO |
3062                                            AR_IMR_S2_TSFOOR |
3063                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3064         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3065         ah->mask_reg = ints;
3066
3067         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3068                 if (ints & ATH9K_INT_TIM_TIMER)
3069                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3070                 else
3071                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3072         }
3073
3074         if (ints & ATH9K_INT_GLOBAL) {
3075                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3076                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3077                 if (!AR_SREV_9100(ah)) {
3078                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3079                                   AR_INTR_MAC_IRQ);
3080                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3081
3082
3083                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3084                                   AR_INTR_SYNC_DEFAULT);
3085                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3086                                   AR_INTR_SYNC_DEFAULT);
3087                 }
3088                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3089                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3090         }
3091
3092         return omask;
3093 }
3094
3095 /*******************/
3096 /* Beacon Handling */
3097 /*******************/
3098
3099 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3100 {
3101         int flags = 0;
3102
3103         ah->beacon_interval = beacon_period;
3104
3105         switch (ah->opmode) {
3106         case NL80211_IFTYPE_STATION:
3107         case NL80211_IFTYPE_MONITOR:
3108                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3109                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3110                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3111                 flags |= AR_TBTT_TIMER_EN;
3112                 break;
3113         case NL80211_IFTYPE_ADHOC:
3114         case NL80211_IFTYPE_MESH_POINT:
3115                 REG_SET_BIT(ah, AR_TXCFG,
3116                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3117                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3118                           TU_TO_USEC(next_beacon +
3119                                      (ah->atim_window ? ah->
3120                                       atim_window : 1)));
3121                 flags |= AR_NDP_TIMER_EN;
3122         case NL80211_IFTYPE_AP:
3123                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3124                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3125                           TU_TO_USEC(next_beacon -
3126                                      ah->config.
3127                                      dma_beacon_response_time));
3128                 REG_WRITE(ah, AR_NEXT_SWBA,
3129                           TU_TO_USEC(next_beacon -
3130                                      ah->config.
3131                                      sw_beacon_response_time));
3132                 flags |=
3133                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3134                 break;
3135         default:
3136                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3137                         "%s: unsupported opmode: %d\n",
3138                         __func__, ah->opmode);
3139                 return;
3140                 break;
3141         }
3142
3143         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3144         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3145         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3146         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3147
3148         beacon_period &= ~ATH9K_BEACON_ENA;
3149         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3150                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3151                 ath9k_hw_reset_tsf(ah);
3152         }
3153
3154         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3155 }
3156
3157 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3158                                     const struct ath9k_beacon_state *bs)
3159 {
3160         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3161         struct ath9k_hw_capabilities *pCap = &ah->caps;
3162
3163         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3164
3165         REG_WRITE(ah, AR_BEACON_PERIOD,
3166                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3167         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3168                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3169
3170         REG_RMW_FIELD(ah, AR_RSSI_THR,
3171                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3172
3173         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3174
3175         if (bs->bs_sleepduration > beaconintval)
3176                 beaconintval = bs->bs_sleepduration;
3177
3178         dtimperiod = bs->bs_dtimperiod;
3179         if (bs->bs_sleepduration > dtimperiod)
3180                 dtimperiod = bs->bs_sleepduration;
3181
3182         if (beaconintval == dtimperiod)
3183                 nextTbtt = bs->bs_nextdtim;
3184         else
3185                 nextTbtt = bs->bs_nexttbtt;
3186
3187         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3188         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3189         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3190         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3191
3192         REG_WRITE(ah, AR_NEXT_DTIM,
3193                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3194         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3195
3196         REG_WRITE(ah, AR_SLEEP1,
3197                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3198                   | AR_SLEEP1_ASSUME_DTIM);
3199
3200         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3201                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3202         else
3203                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3204
3205         REG_WRITE(ah, AR_SLEEP2,
3206                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3207
3208         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3209         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3210
3211         REG_SET_BIT(ah, AR_TIMER_MODE,
3212                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3213                     AR_DTIM_TIMER_EN);
3214
3215         /* TSF Out of Range Threshold */
3216         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3217 }
3218
3219 /*******************/
3220 /* HW Capabilities */
3221 /*******************/
3222
3223 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3224 {
3225         struct ath9k_hw_capabilities *pCap = &ah->caps;
3226         u16 capField = 0, eeval;
3227
3228         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3229         ah->regulatory.current_rd = eeval;
3230
3231         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3232         if (AR_SREV_9285_10_OR_LATER(ah))
3233                 eeval |= AR9285_RDEXT_DEFAULT;
3234         ah->regulatory.current_rd_ext = eeval;
3235
3236         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3237
3238         if (ah->opmode != NL80211_IFTYPE_AP &&
3239             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3240                 if (ah->regulatory.current_rd == 0x64 ||
3241                     ah->regulatory.current_rd == 0x65)
3242                         ah->regulatory.current_rd += 5;
3243                 else if (ah->regulatory.current_rd == 0x41)
3244                         ah->regulatory.current_rd = 0x43;
3245                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3246                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3247         }
3248
3249         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3250         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3251
3252         if (eeval & AR5416_OPFLAGS_11A) {
3253                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3254                 if (ah->config.ht_enable) {
3255                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3256                                 set_bit(ATH9K_MODE_11NA_HT20,
3257                                         pCap->wireless_modes);
3258                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3259                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3260                                         pCap->wireless_modes);
3261                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3262                                         pCap->wireless_modes);
3263                         }
3264                 }
3265         }
3266
3267         if (eeval & AR5416_OPFLAGS_11G) {
3268                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3269                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3270                 if (ah->config.ht_enable) {
3271                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3272                                 set_bit(ATH9K_MODE_11NG_HT20,
3273                                         pCap->wireless_modes);
3274                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3275                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3276                                         pCap->wireless_modes);
3277                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3278                                         pCap->wireless_modes);
3279                         }
3280                 }
3281         }
3282
3283         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3284         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3285             !(eeval & AR5416_OPFLAGS_11A))
3286                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3287         else
3288                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3289
3290         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3291                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3292
3293         pCap->low_2ghz_chan = 2312;
3294         pCap->high_2ghz_chan = 2732;
3295
3296         pCap->low_5ghz_chan = 4920;
3297         pCap->high_5ghz_chan = 6100;
3298
3299         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3300         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3301         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3302
3303         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3304         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3305         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3306
3307         if (ah->config.ht_enable)
3308                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3309         else
3310                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3311
3312         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3313         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3314         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3315         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3316
3317         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3318                 pCap->total_queues =
3319                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3320         else
3321                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3322
3323         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3324                 pCap->keycache_size =
3325                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3326         else
3327                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3328
3329         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3330         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3331
3332         if (AR_SREV_9285_10_OR_LATER(ah))
3333                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3334         else if (AR_SREV_9280_10_OR_LATER(ah))
3335                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3336         else
3337                 pCap->num_gpio_pins = AR_NUM_GPIO;
3338
3339         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3340                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3341                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3342         } else {
3343                 pCap->rts_aggr_limit = (8 * 1024);
3344         }
3345
3346         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3347
3348 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3349         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3350         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3351                 ah->rfkill_gpio =
3352                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3353                 ah->rfkill_polarity =
3354                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3355
3356                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3357         }
3358 #endif
3359
3360         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3361             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3362             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3363             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3364             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3365                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3366         else
3367                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3368
3369         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3370                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3371         else
3372                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3373
3374         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3375                 pCap->reg_cap =
3376                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3377                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3378                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3379                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3380         } else {
3381                 pCap->reg_cap =
3382                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3383                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3384         }
3385
3386         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3387
3388         pCap->num_antcfg_5ghz =
3389                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3390         pCap->num_antcfg_2ghz =
3391                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3392
3393         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3394                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3395                 ah->btactive_gpio = 6;
3396                 ah->wlanactive_gpio = 5;
3397         }
3398 }
3399
3400 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3401                             u32 capability, u32 *result)
3402 {
3403         switch (type) {
3404         case ATH9K_CAP_CIPHER:
3405                 switch (capability) {
3406                 case ATH9K_CIPHER_AES_CCM:
3407                 case ATH9K_CIPHER_AES_OCB:
3408                 case ATH9K_CIPHER_TKIP:
3409                 case ATH9K_CIPHER_WEP:
3410                 case ATH9K_CIPHER_MIC:
3411                 case ATH9K_CIPHER_CLR:
3412                         return true;
3413                 default:
3414                         return false;
3415                 }
3416         case ATH9K_CAP_TKIP_MIC:
3417                 switch (capability) {
3418                 case 0:
3419                         return true;
3420                 case 1:
3421                         return (ah->sta_id1_defaults &
3422                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3423                         false;
3424                 }
3425         case ATH9K_CAP_TKIP_SPLIT:
3426                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3427                         false : true;
3428         case ATH9K_CAP_DIVERSITY:
3429                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3430                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3431                         true : false;
3432         case ATH9K_CAP_MCAST_KEYSRCH:
3433                 switch (capability) {
3434                 case 0:
3435                         return true;
3436                 case 1:
3437                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3438                                 return false;
3439                         } else {
3440                                 return (ah->sta_id1_defaults &
3441                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3442                                         false;
3443                         }
3444                 }
3445                 return false;
3446         case ATH9K_CAP_TXPOW:
3447                 switch (capability) {
3448                 case 0:
3449                         return 0;
3450                 case 1:
3451                         *result = ah->regulatory.power_limit;
3452                         return 0;
3453                 case 2:
3454                         *result = ah->regulatory.max_power_level;
3455                         return 0;
3456                 case 3:
3457                         *result = ah->regulatory.tp_scale;
3458                         return 0;
3459                 }
3460                 return false;
3461         case ATH9K_CAP_DS:
3462                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3463                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3464                         ? false : true;
3465         default:
3466                 return false;
3467         }
3468 }
3469
3470 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3471                             u32 capability, u32 setting, int *status)
3472 {
3473         u32 v;
3474
3475         switch (type) {
3476         case ATH9K_CAP_TKIP_MIC:
3477                 if (setting)
3478                         ah->sta_id1_defaults |=
3479                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3480                 else
3481                         ah->sta_id1_defaults &=
3482                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3483                 return true;
3484         case ATH9K_CAP_DIVERSITY:
3485                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3486                 if (setting)
3487                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3488                 else
3489                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3490                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3491                 return true;
3492         case ATH9K_CAP_MCAST_KEYSRCH:
3493                 if (setting)
3494                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3495                 else
3496                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3497                 return true;
3498         default:
3499                 return false;
3500         }
3501 }
3502
3503 /****************************/
3504 /* GPIO / RFKILL / Antennae */
3505 /****************************/
3506
3507 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3508                                          u32 gpio, u32 type)
3509 {
3510         int addr;
3511         u32 gpio_shift, tmp;
3512
3513         if (gpio > 11)
3514                 addr = AR_GPIO_OUTPUT_MUX3;
3515         else if (gpio > 5)
3516                 addr = AR_GPIO_OUTPUT_MUX2;
3517         else
3518                 addr = AR_GPIO_OUTPUT_MUX1;
3519
3520         gpio_shift = (gpio % 6) * 5;
3521
3522         if (AR_SREV_9280_20_OR_LATER(ah)
3523             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3524                 REG_RMW(ah, addr, (type << gpio_shift),
3525                         (0x1f << gpio_shift));
3526         } else {
3527                 tmp = REG_READ(ah, addr);
3528                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3529                 tmp &= ~(0x1f << gpio_shift);
3530                 tmp |= (type << gpio_shift);
3531                 REG_WRITE(ah, addr, tmp);
3532         }
3533 }
3534
3535 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3536 {
3537         u32 gpio_shift;
3538
3539         ASSERT(gpio < ah->caps.num_gpio_pins);
3540
3541         gpio_shift = gpio << 1;
3542
3543         REG_RMW(ah,
3544                 AR_GPIO_OE_OUT,
3545                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3546                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3547 }
3548
3549 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3550 {
3551 #define MS_REG_READ(x, y) \
3552         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3553
3554         if (gpio >= ah->caps.num_gpio_pins)
3555                 return 0xffffffff;
3556
3557         if (AR_SREV_9285_10_OR_LATER(ah))
3558                 return MS_REG_READ(AR9285, gpio) != 0;
3559         else if (AR_SREV_9280_10_OR_LATER(ah))
3560                 return MS_REG_READ(AR928X, gpio) != 0;
3561         else
3562                 return MS_REG_READ(AR, gpio) != 0;
3563 }
3564
3565 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3566                          u32 ah_signal_type)
3567 {
3568         u32 gpio_shift;
3569
3570         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3571
3572         gpio_shift = 2 * gpio;
3573
3574         REG_RMW(ah,
3575                 AR_GPIO_OE_OUT,
3576                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3577                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3578 }
3579
3580 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3581 {
3582         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3583                 AR_GPIO_BIT(gpio));
3584 }
3585
3586 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3587 void ath9k_enable_rfkill(struct ath_hw *ah)
3588 {
3589         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3590                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3591
3592         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3593                     AR_GPIO_INPUT_MUX2_RFSILENT);
3594
3595         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3596         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3597 }
3598 #endif
3599
3600 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3601 {
3602         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3603 }
3604
3605 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3606 {
3607         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3608 }
3609
3610 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3611                                enum ath9k_ant_setting settings,
3612                                struct ath9k_channel *chan,
3613                                u8 *tx_chainmask,
3614                                u8 *rx_chainmask,
3615                                u8 *antenna_cfgd)
3616 {
3617         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3618
3619         if (AR_SREV_9280(ah)) {
3620                 if (!tx_chainmask_cfg) {
3621
3622                         tx_chainmask_cfg = *tx_chainmask;
3623                         rx_chainmask_cfg = *rx_chainmask;
3624                 }
3625
3626                 switch (settings) {
3627                 case ATH9K_ANT_FIXED_A:
3628                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3629                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3630                         *antenna_cfgd = true;
3631                         break;
3632                 case ATH9K_ANT_FIXED_B:
3633                         if (ah->caps.tx_chainmask >
3634                             ATH9K_ANTENNA1_CHAINMASK) {
3635                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3636                         }
3637                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3638                         *antenna_cfgd = true;
3639                         break;
3640                 case ATH9K_ANT_VARIABLE:
3641                         *tx_chainmask = tx_chainmask_cfg;
3642                         *rx_chainmask = rx_chainmask_cfg;
3643                         *antenna_cfgd = true;
3644                         break;
3645                 default:
3646                         break;
3647                 }
3648         } else {
3649                 ah->diversity_control = settings;
3650         }
3651
3652         return true;
3653 }
3654
3655 /*********************/
3656 /* General Operation */
3657 /*********************/
3658
3659 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3660 {
3661         u32 bits = REG_READ(ah, AR_RX_FILTER);
3662         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3663
3664         if (phybits & AR_PHY_ERR_RADAR)
3665                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3666         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3667                 bits |= ATH9K_RX_FILTER_PHYERR;
3668
3669         return bits;
3670 }
3671
3672 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3673 {
3674         u32 phybits;
3675
3676         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3677         phybits = 0;
3678         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3679                 phybits |= AR_PHY_ERR_RADAR;
3680         if (bits & ATH9K_RX_FILTER_PHYERR)
3681                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3682         REG_WRITE(ah, AR_PHY_ERR, phybits);
3683
3684         if (phybits)
3685                 REG_WRITE(ah, AR_RXCFG,
3686                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3687         else
3688                 REG_WRITE(ah, AR_RXCFG,
3689                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3690 }
3691
3692 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3693 {
3694         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3695 }
3696
3697 bool ath9k_hw_disable(struct ath_hw *ah)
3698 {
3699         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3700                 return false;
3701
3702         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3703 }
3704
3705 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3706 {
3707         struct ath9k_channel *chan = ah->curchan;
3708         struct ieee80211_channel *channel = chan->chan;
3709
3710         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3711
3712         if (ah->eep_ops->set_txpower(ah, chan,
3713                              ath9k_regd_get_ctl(&ah->regulatory, chan),
3714                              channel->max_antenna_gain * 2,
3715                              channel->max_power * 2,
3716                              min((u32) MAX_RATE_POWER,
3717                                  (u32) ah->regulatory.power_limit)) != 0)
3718                 return false;
3719
3720         return true;
3721 }
3722
3723 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3724 {
3725         memcpy(ah->macaddr, mac, ETH_ALEN);
3726 }
3727
3728 void ath9k_hw_setopmode(struct ath_hw *ah)
3729 {
3730         ath9k_hw_set_operating_mode(ah, ah->opmode);
3731 }
3732
3733 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3734 {
3735         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3736         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3737 }
3738
3739 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3740 {
3741         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3742         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3743 }
3744
3745 void ath9k_hw_write_associd(struct ath_softc *sc)
3746 {
3747         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3748         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3749                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3750 }
3751
3752 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3753 {
3754         u64 tsf;
3755
3756         tsf = REG_READ(ah, AR_TSF_U32);
3757         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3758
3759         return tsf;
3760 }
3761
3762 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3763 {
3764         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3765         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3766 }
3767
3768 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3769 {
3770         int count;
3771
3772         count = 0;
3773         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3774                 count++;
3775                 if (count > 10) {
3776                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3777                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3778                         break;
3779                 }
3780                 udelay(10);
3781         }
3782         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3783 }
3784
3785 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3786 {
3787         if (setting)
3788                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3789         else
3790                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3791
3792         return true;
3793 }
3794
3795 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3796 {
3797         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3798                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3799                 ah->slottime = (u32) -1;
3800                 return false;
3801         } else {
3802                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3803                 ah->slottime = us;
3804                 return true;
3805         }
3806 }
3807
3808 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3809 {
3810         u32 macmode;
3811
3812         if (mode == ATH9K_HT_MACMODE_2040 &&
3813             !ah->config.cwm_ignore_extcca)
3814                 macmode = AR_2040_JOINED_RX_CLEAR;
3815         else
3816                 macmode = 0;
3817
3818         REG_WRITE(ah, AR_2040_MODE, macmode);
3819 }
3820
3821 /***************************/
3822 /*  Bluetooth Coexistence  */
3823 /***************************/
3824
3825 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3826 {
3827         /* connect bt_active to baseband */
3828         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3829                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3830                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3831
3832         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3833                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3834
3835         /* Set input mux for bt_active to gpio pin */
3836         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3837                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3838                         ah->btactive_gpio);
3839
3840         /* Configure the desired gpio port for input */
3841         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3842
3843         /* Configure the desired GPIO port for TX_FRAME output */
3844         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3845                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3846 }