drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  27
  28 extern struct hal_percal_data iq_cal_multi_sample;
  29 extern struct hal_percal_data iq_cal_single_sample;
  30 extern struct hal_percal_data adc_gain_cal_multi_sample;
  31 extern struct hal_percal_data adc_gain_cal_single_sample;
  32 extern struct hal_percal_data adc_dc_cal_multi_sample;
  33 extern struct hal_percal_data adc_dc_cal_single_sample;
  34 extern struct hal_percal_data adc_init_dc_cal;
  35
  36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  38                               enum ath9k_ht_macmode macmode);
  39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  40                               struct ar5416_eeprom *pEepData,
  41                               u32 reg, u32 value);
  42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  44
  45 /********************/
  46 /* Helper Functions */
  47 /********************/
  48
  49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  50 {
  51         if (ah->ah_curchan != NULL)
  52                 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
  53         else
  54                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
  55 }
  56
  57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  58 {
  59         struct ath9k_channel *chan = ah->ah_curchan;
  60
  61         if (chan && IS_CHAN_HT40(chan))
  62                 return ath9k_hw_mac_usec(ah, clks) / 2;
  63         else
  64                 return ath9k_hw_mac_usec(ah, clks);
  65 }
  66
  67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  68 {
  69         if (ah->ah_curchan != NULL)
  70                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
  71                         ah->ah_curchan)];
  72         else
  73                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
  74 }
  75
  76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  77 {
  78         struct ath9k_channel *chan = ah->ah_curchan;
  79
  80         if (chan && IS_CHAN_HT40(chan))
  81                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  82         else
  83                 return ath9k_hw_mac_clks(ah, usecs);
  84 }
  85
  86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
  87                                const struct ath9k_channel *chan)
  88 {
  89         if (IS_CHAN_B(chan))
  90                 return ATH9K_MODE_11B;
  91         if (IS_CHAN_G(chan))
  92                 return ATH9K_MODE_11G;
  93
  94         return ATH9K_MODE_11A;
  95 }
  96
  97 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  98 {
  99         int i;
 100
 101         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 102                 if ((REG_READ(ah, reg) & mask) == val)
 103                         return true;
 104
 105                 udelay(AH_TIME_QUANTUM);
 106         }
 107         DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 108                 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 109                 __func__, reg, REG_READ(ah, reg), mask, val);
 110
 111         return false;
 112 }
 113
 114 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 115 {
 116         u32 retval;
 117         int i;
 118
 119         for (i = 0, retval = 0; i < n; i++) {
 120                 retval = (retval << 1) | (val & 1);
 121                 val >>= 1;
 122         }
 123         return retval;
 124 }
 125
 126 bool ath9k_get_channel_edges(struct ath_hal *ah,
 127                              u16 flags, u16 *low,
 128                              u16 *high)
 129 {
 130         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 131
 132         if (flags & CHANNEL_5GHZ) {
 133                 *low = pCap->low_5ghz_chan;
 134                 *high = pCap->high_5ghz_chan;
 135                 return true;
 136         }
 137         if ((flags & CHANNEL_2GHZ)) {
 138                 *low = pCap->low_2ghz_chan;
 139                 *high = pCap->high_2ghz_chan;
 140                 return true;
 141         }
 142         return false;
 143 }
 144
 145 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 146                            struct ath_rate_table *rates,
 147                            u32 frameLen, u16 rateix,
 148                            bool shortPreamble)
 149 {
 150         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 151         u32 kbps;
 152
 153         kbps = rates->info[rateix].ratekbps;
 154
 155         if (kbps == 0)
 156                 return 0;
 157
 158         switch (rates->info[rateix].phy) {
 159         case WLAN_RC_PHY_CCK:
 160                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 161                 if (shortPreamble && rates->info[rateix].short_preamble)
 162                         phyTime >>= 1;
 163                 numBits = frameLen << 3;
 164                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 165                 break;
 166         case WLAN_RC_PHY_OFDM:
 167                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 168                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 169                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 170                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 171                         txTime = OFDM_SIFS_TIME_QUARTER
 172                                 + OFDM_PREAMBLE_TIME_QUARTER
 173                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 174                 } else if (ah->ah_curchan &&
 175                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME_HALF +
 180                                 OFDM_PREAMBLE_TIME_HALF
 181                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 182                 } else {
 183                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 184                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 185                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 186                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 187                                 + (numSymbols * OFDM_SYMBOL_TIME);
 188                 }
 189                 break;
 190         default:
 191                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
 192                         "%s: unknown phy %u (rate ix %u)\n", __func__,
 193                         rates->info[rateix].phy, rateix);
 194                 txTime = 0;
 195                 break;
 196         }
 197
 198         return txTime;
 199 }
 200
 201 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 202 {
 203         if (flags & CHANNEL_2GHZ) {
 204                 if (freq == 2484)
 205                         return 14;
 206                 if (freq < 2484)
 207                         return (freq - 2407) / 5;
 208                 else
 209                         return 15 + ((freq - 2512) / 20);
 210         } else if (flags & CHANNEL_5GHZ) {
 211                 if (ath9k_regd_is_public_safety_sku(ah) &&
 212                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 213                         return ((freq * 10) +
 214                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
 215                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
 216                         return (freq - 4000) / 5;
 217                 } else {
 218                         return (freq - 5000) / 5;
 219                 }
 220         } else {
 221                 if (freq == 2484)
 222                         return 14;
 223                 if (freq < 2484)
 224                         return (freq - 2407) / 5;
 225                 if (freq < 5000) {
 226                         if (ath9k_regd_is_public_safety_sku(ah)
 227                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 228                                 return ((freq * 10) +
 229                                         (((freq % 5) ==
 230                                           2) ? 5 : 0) - 49400) / 5;
 231                         } else if (freq > 4900) {
 232                                 return (freq - 4000) / 5;
 233                         } else {
 234                                 return 15 + ((freq - 2512) / 20);
 235                         }
 236                 }
 237                 return (freq - 5000) / 5;
 238         }
 239 }
 240
 241 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 242                                   struct ath9k_channel *chan,
 243                                   struct chan_centers *centers)
 244 {
 245         int8_t extoff;
 246         struct ath_hal_5416 *ahp = AH5416(ah);
 247
 248         if (!IS_CHAN_HT40(chan)) {
 249                 centers->ctl_center = centers->ext_center =
 250                         centers->synth_center = chan->channel;
 251                 return;
 252         }
 253
 254         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 255             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 256                 centers->synth_center =
 257                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 258                 extoff = 1;
 259         } else {
 260                 centers->synth_center =
 261                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 262                 extoff = -1;
 263         }
 264
 265         centers->ctl_center =
 266                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 267         centers->ext_center =
 268                 centers->synth_center + (extoff *
 269                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 270                           HT40_CHANNEL_CENTER_SHIFT : 15));
 271
 272 }
 273
 274 /******************/
 275 /* Chip Revisions */
 276 /******************/
 277
 278 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 279 {
 280         u32 val;
 281
 282         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 283
 284         if (val == 0xFF) {
 285                 val = REG_READ(ah, AR_SREV);
 286                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 287                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 288                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 289         } else {
 290                 if (!AR_SREV_9100(ah))
 291                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 292
 293                 ah->ah_macRev = val & AR_SREV_REVISION;
 294
 295                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 296                         ah->ah_isPciExpress = true;
 297         }
 298 }
 299
 300 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 301 {
 302         u32 val;
 303         int i;
 304
 305         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 306
 307         for (i = 0; i < 8; i++)
 308                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 309         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 310         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 311
 312         return ath9k_hw_reverse_bits(val, 8);
 313 }
 314
 315 /************************************/
 316 /* HW Attach, Detach, Init Routines */
 317 /************************************/
 318
 319 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 320 {
 321         if (!AR_SREV_9100(ah))
 322                 return;
 323
 324         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 325         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 326         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 327         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 328         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 329         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 330         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 331         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 332         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 333
 334         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 335 }
 336
 337 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 338 {
 339         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 340         u32 regHold[2];
 341         u32 patternData[4] = { 0x55555555,
 342                                0xaaaaaaaa,
 343                                0x66666666,
 344                                0x99999999 };
 345         int i, j;
 346
 347         for (i = 0; i < 2; i++) {
 348                 u32 addr = regAddr[i];
 349                 u32 wrData, rdData;
 350
 351                 regHold[i] = REG_READ(ah, addr);
 352                 for (j = 0; j < 0x100; j++) {
 353                         wrData = (j << 16) | j;
 354                         REG_WRITE(ah, addr, wrData);
 355                         rdData = REG_READ(ah, addr);
 356                         if (rdData != wrData) {
 357                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 358                                         "%s: address test failed "
 359                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 360                                         __func__, addr, wrData, rdData);
 361                                 return false;
 362                         }
 363                 }
 364                 for (j = 0; j < 4; j++) {
 365                         wrData = patternData[j];
 366                         REG_WRITE(ah, addr, wrData);
 367                         rdData = REG_READ(ah, addr);
 368                         if (wrData != rdData) {
 369                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 370                                         "%s: address test failed "
 371                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 372                                         __func__, addr, wrData, rdData);
 373                                 return false;
 374                         }
 375                 }
 376                 REG_WRITE(ah, regAddr[i], regHold[i]);
 377         }
 378         udelay(100);
 379         return true;
 380 }
 381
 382 static const char *ath9k_hw_devname(u16 devid)
 383 {
 384         switch (devid) {
 385         case AR5416_DEVID_PCI:
 386                 return "Atheros 5416";
 387         case AR5416_DEVID_PCIE:
 388                 return "Atheros 5418";
 389         case AR9160_DEVID_PCI:
 390                 return "Atheros 9160";
 391         case AR9280_DEVID_PCI:
 392         case AR9280_DEVID_PCIE:
 393                 return "Atheros 9280";
 394         }
 395
 396         return NULL;
 397 }
 398
 399 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 400 {
 401         int i;
 402
 403         ah->ah_config.dma_beacon_response_time = 2;
 404         ah->ah_config.sw_beacon_response_time = 10;
 405         ah->ah_config.additional_swba_backoff = 0;
 406         ah->ah_config.ack_6mb = 0x0;
 407         ah->ah_config.cwm_ignore_extcca = 0;
 408         ah->ah_config.pcie_powersave_enable = 0;
 409         ah->ah_config.pcie_l1skp_enable = 0;
 410         ah->ah_config.pcie_clock_req = 0;
 411         ah->ah_config.pcie_power_reset = 0x100;
 412         ah->ah_config.pcie_restore = 0;
 413         ah->ah_config.pcie_waen = 0;
 414         ah->ah_config.analog_shiftreg = 1;
 415         ah->ah_config.ht_enable = 1;
 416         ah->ah_config.ofdm_trig_low = 200;
 417         ah->ah_config.ofdm_trig_high = 500;
 418         ah->ah_config.cck_trig_high = 200;
 419         ah->ah_config.cck_trig_low = 100;
 420         ah->ah_config.enable_ani = 1;
 421         ah->ah_config.noise_immunity_level = 4;
 422         ah->ah_config.ofdm_weaksignal_det = 1;
 423         ah->ah_config.cck_weaksignal_thr = 0;
 424         ah->ah_config.spur_immunity_level = 2;
 425         ah->ah_config.firstep_level = 0;
 426         ah->ah_config.rssi_thr_high = 40;
 427         ah->ah_config.rssi_thr_low = 7;
 428         ah->ah_config.diversity_control = 0;
 429         ah->ah_config.antenna_switch_swap = 0;
 430
 431         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 432                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 433                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 434         }
 435
 436         ah->ah_config.intr_mitigation = 1;
 437 }
 438
 439 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 440                                               struct ath_softc *sc,
 441                                               void __iomem *mem,
 442                                               int *status)
 443 {
 444         static const u8 defbssidmask[ETH_ALEN] =
 445                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 446         struct ath_hal_5416 *ahp;
 447         struct ath_hal *ah;
 448
 449         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 450         if (ahp == NULL) {
 451                 DPRINTF(sc, ATH_DBG_FATAL,
 452                         "%s: cannot allocate memory for state block\n",
 453                         __func__);
 454                 *status = -ENOMEM;
 455                 return NULL;
 456         }
 457
 458         ah = &ahp->ah;
 459         ah->ah_sc = sc;
 460         ah->ah_sh = mem;
 461         ah->ah_magic = AR5416_MAGIC;
 462         ah->ah_countryCode = CTRY_DEFAULT;
 463         ah->ah_devid = devid;
 464         ah->ah_subvendorid = 0;
 465
 466         ah->ah_flags = 0;
 467         if ((devid == AR5416_AR9100_DEVID))
 468                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 469         if (!AR_SREV_9100(ah))
 470                 ah->ah_flags = AH_USE_EEPROM;
 471
 472         ah->ah_powerLimit = MAX_RATE_POWER;
 473         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 474         ahp->ah_atimWindow = 0;
 475         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 476         ahp->ah_antennaSwitchSwap =
 477                 ah->ah_config.antenna_switch_swap;
 478         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 479         ahp->ah_beaconInterval = 100;
 480         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 481         ahp->ah_slottime = (u32) -1;
 482         ahp->ah_acktimeout = (u32) -1;
 483         ahp->ah_ctstimeout = (u32) -1;
 484         ahp->ah_globaltxtimeout = (u32) -1;
 485         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 486
 487         ahp->ah_gBeaconRate = 0;
 488
 489         return ahp;
 490 }
 491
 492 static int ath9k_hw_rfattach(struct ath_hal *ah)
 493 {
 494         bool rfStatus = false;
 495         int ecode = 0;
 496
 497         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 498         if (!rfStatus) {
 499                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 500                         "%s: RF setup failed, status %u\n", __func__,
 501                         ecode);
 502                 return ecode;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 509 {
 510         u32 val;
 511
 512         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 513
 514         val = ath9k_hw_get_radiorev(ah);
 515         switch (val & AR_RADIO_SREV_MAJOR) {
 516         case 0:
 517                 val = AR_RAD5133_SREV_MAJOR;
 518                 break;
 519         case AR_RAD5133_SREV_MAJOR:
 520         case AR_RAD5122_SREV_MAJOR:
 521         case AR_RAD2133_SREV_MAJOR:
 522         case AR_RAD2122_SREV_MAJOR:
 523                 break;
 524         default:
 525                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 526                         "%s: 5G Radio Chip Rev 0x%02X is not "
 527                         "supported by this driver\n",
 528                         __func__, ah->ah_analog5GhzRev);
 529                 return -EOPNOTSUPP;
 530         }
 531
 532         ah->ah_analog5GhzRev = val;
 533
 534         return 0;
 535 }
 536
 537 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 538 {
 539         u32 sum;
 540         int i;
 541         u16 eeval;
 542         struct ath_hal_5416 *ahp = AH5416(ah);
 543
 544         sum = 0;
 545         for (i = 0; i < 3; i++) {
 546                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 547                 sum += eeval;
 548                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 549                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 550         }
 551         if (sum == 0 || sum == 0xffff * 3) {
 552                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 553                         "%s: mac address read failed: %pM\n", __func__,
 554                         ahp->ah_macaddr);
 555                 return -EADDRNOTAVAIL;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 562 {
 563         u32 rxgain_type;
 564         struct ath_hal_5416 *ahp = AH5416(ah);
 565
 566         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 567                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 568
 569                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 570                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 571                         ar9280Modes_backoff_13db_rxgain_9280_2,
 572                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 573                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 574                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 575                         ar9280Modes_backoff_23db_rxgain_9280_2,
 576                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 577                 else
 578                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 579                         ar9280Modes_original_rxgain_9280_2,
 580                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 581         } else
 582                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 583                         ar9280Modes_original_rxgain_9280_2,
 584                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 585 }
 586
 587 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 588 {
 589         u32 txgain_type;
 590         struct ath_hal_5416 *ahp = AH5416(ah);
 591
 592         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 593                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 594
 595                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 596                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 597                         ar9280Modes_high_power_tx_gain_9280_2,
 598                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 599                 else
 600                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 601                         ar9280Modes_original_tx_gain_9280_2,
 602                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 603         } else
 604                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 605                 ar9280Modes_original_tx_gain_9280_2,
 606                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 607 }
 608
 609 static int ath9k_hw_post_attach(struct ath_hal *ah)
 610 {
 611         int ecode;
 612
 613         if (!ath9k_hw_chip_test(ah)) {
 614                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 615                         "%s: hardware self-test failed\n", __func__);
 616                 return -ENODEV;
 617         }
 618
 619         ecode = ath9k_hw_rf_claim(ah);
 620         if (ecode != 0)
 621                 return ecode;
 622
 623         ecode = ath9k_hw_eeprom_attach(ah);
 624         if (ecode != 0)
 625                 return ecode;
 626         ecode = ath9k_hw_rfattach(ah);
 627         if (ecode != 0)
 628                 return ecode;
 629
 630         if (!AR_SREV_9100(ah)) {
 631                 ath9k_hw_ani_setup(ah);
 632                 ath9k_hw_ani_attach(ah);
 633         }
 634
 635         return 0;
 636 }
 637
 638 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 639                                           void __iomem *mem, int *status)
 640 {
 641         struct ath_hal_5416 *ahp;
 642         struct ath_hal *ah;
 643         int ecode;
 644 #ifndef CONFIG_SLOW_ANT_DIV
 645         u32 i;
 646         u32 j;
 647 #endif
 648
 649         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 650         if (ahp == NULL)
 651                 return NULL;
 652
 653         ah = &ahp->ah;
 654
 655         ath9k_hw_set_defaults(ah);
 656
 657         if (ah->ah_config.intr_mitigation != 0)
 658                 ahp->ah_intrMitigation = true;
 659
 660         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 661                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
 662                          __func__);
 663                 ecode = -EIO;
 664                 goto bad;
 665         }
 666
 667         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 668                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
 669                          __func__);
 670                 ecode = -EIO;
 671                 goto bad;
 672         }
 673
 674         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 675                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 676                         ah->ah_config.serialize_regmode =
 677                                 SER_REG_MODE_ON;
 678                 } else {
 679                         ah->ah_config.serialize_regmode =
 680                                 SER_REG_MODE_OFF;
 681                 }
 682         }
 683
 684         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 685                 "%s: serialize_regmode is %d\n",
 686                 __func__, ah->ah_config.serialize_regmode);
 687
 688         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 689             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 690             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 691             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
 692                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 693                         "%s: Mac Chip Rev 0x%02x.%x is not supported by "
 694                         "this driver\n", __func__,
 695                         ah->ah_macVersion, ah->ah_macRev);
 696                 ecode = -EOPNOTSUPP;
 697                 goto bad;
 698         }
 699
 700         if (AR_SREV_9100(ah)) {
 701                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 702                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 703                 ah->ah_isPciExpress = false;
 704         }
 705         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 706
 707         if (AR_SREV_9160_10_OR_LATER(ah)) {
 708                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 709                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 710                         ahp->ah_adcGainCalData.calData =
 711                                 &adc_gain_cal_single_sample;
 712                         ahp->ah_adcDcCalData.calData =
 713                                 &adc_dc_cal_single_sample;
 714                         ahp->ah_adcDcCalInitData.calData =
 715                                 &adc_init_dc_cal;
 716                 } else {
 717                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 718                         ahp->ah_adcGainCalData.calData =
 719                                 &adc_gain_cal_multi_sample;
 720                         ahp->ah_adcDcCalData.calData =
 721                                 &adc_dc_cal_multi_sample;
 722                         ahp->ah_adcDcCalInitData.calData =
 723                                 &adc_init_dc_cal;
 724                 }
 725                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 726         }
 727
 728         if (AR_SREV_9160(ah)) {
 729                 ah->ah_config.enable_ani = 1;
 730                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 731                                         ATH9K_ANI_FIRSTEP_LEVEL);
 732         } else {
 733                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 734                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 735                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 736                 }
 737         }
 738
 739         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 740                 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
 741                 ah->ah_macVersion, ah->ah_macRev);
 742
 743         if (AR_SREV_9280_20_OR_LATER(ah)) {
 744                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 745                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 746                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 747                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 748
 749                 if (ah->ah_config.pcie_clock_req) {
 750                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 751                                ar9280PciePhy_clkreq_off_L1_9280,
 752                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 753                 } else {
 754                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 755                                ar9280PciePhy_clkreq_always_on_L1_9280,
 756                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 757                 }
 758                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 759                                ar9280Modes_fast_clock_9280_2,
 760                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 761         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 762                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 763                                ARRAY_SIZE(ar9280Modes_9280), 6);
 764                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 765                                ARRAY_SIZE(ar9280Common_9280), 2);
 766         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 767                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 768                                ARRAY_SIZE(ar5416Modes_9160), 6);
 769                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 770                                ARRAY_SIZE(ar5416Common_9160), 2);
 771                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 772                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 773                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 774                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 775                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 776                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 777                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 778                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 779                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 780                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 781                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 782                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 783                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 784                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 785                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 786                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 787                 if (AR_SREV_9160_11(ah)) {
 788                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 789                                        ar5416Addac_91601_1,
 790                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 791                 } else {
 792                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 793                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 794                 }
 795         } else if (AR_SREV_9100_OR_LATER(ah)) {
 796                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 797                                ARRAY_SIZE(ar5416Modes_9100), 6);
 798                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 799                                ARRAY_SIZE(ar5416Common_9100), 2);
 800                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 801                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 802                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 803                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 804                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 805                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 806                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 807                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 808                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 809                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 810                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 811                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 812                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 813                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 814                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 815                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 816                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 817                                ARRAY_SIZE(ar5416Addac_9100), 2);
 818         } else {
 819                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 820                                ARRAY_SIZE(ar5416Modes), 6);
 821                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 822                                ARRAY_SIZE(ar5416Common), 2);
 823                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 824                                ARRAY_SIZE(ar5416Bank0), 2);
 825                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 826                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 827                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 828                                ARRAY_SIZE(ar5416Bank1), 2);
 829                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 830                                ARRAY_SIZE(ar5416Bank2), 2);
 831                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 832                                ARRAY_SIZE(ar5416Bank3), 3);
 833                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 834                                ARRAY_SIZE(ar5416Bank6), 3);
 835                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 836                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 837                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 838                                ARRAY_SIZE(ar5416Bank7), 2);
 839                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 840                                ARRAY_SIZE(ar5416Addac), 2);
 841         }
 842
 843         if (ah->ah_isPciExpress)
 844                 ath9k_hw_configpcipowersave(ah, 0);
 845         else
 846                 ath9k_hw_disablepcie(ah);
 847
 848         ecode = ath9k_hw_post_attach(ah);
 849         if (ecode != 0)
 850                 goto bad;
 851
 852         /* rxgain table */
 853         if (AR_SREV_9280_20_OR_LATER(ah))
 854                 ath9k_hw_init_rxgain_ini(ah);
 855
 856         /* txgain table */
 857         if (AR_SREV_9280_20_OR_LATER(ah))
 858                 ath9k_hw_init_txgain_ini(ah);
 859
 860 #ifndef CONFIG_SLOW_ANT_DIV
 861         if (ah->ah_devid == AR9280_DEVID_PCI) {
 862                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 863                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 864
 865                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 866                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 867
 868                                 INI_RA(&ahp->ah_iniModes, i, j) =
 869                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
 870                                                            reg, val);
 871                         }
 872                 }
 873         }
 874 #endif
 875         if (!ath9k_hw_fill_cap_info(ah)) {
 876                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 877                         "%s:failed ath9k_hw_fill_cap_info\n", __func__);
 878                 ecode = -EINVAL;
 879                 goto bad;
 880         }
 881
 882         ecode = ath9k_hw_init_macaddr(ah);
 883         if (ecode != 0) {
 884                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 885                         "%s: failed initializing mac address\n",
 886                         __func__);
 887                 goto bad;
 888         }
 889
 890         if (AR_SREV_9285(ah))
 891                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 892         else
 893                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 894
 895         ath9k_init_nfcal_hist_buffer(ah);
 896
 897         return ah;
 898 bad:
 899         if (ahp)
 900                 ath9k_hw_detach((struct ath_hal *) ahp);
 901         if (status)
 902                 *status = ecode;
 903
 904         return NULL;
 905 }
 906
 907 static void ath9k_hw_init_bb(struct ath_hal *ah,
 908                              struct ath9k_channel *chan)
 909 {
 910         u32 synthDelay;
 911
 912         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 913         if (IS_CHAN_B(chan))
 914                 synthDelay = (4 * synthDelay) / 22;
 915         else
 916                 synthDelay /= 10;
 917
 918         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 919
 920         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 921 }
 922
 923 static void ath9k_hw_init_qos(struct ath_hal *ah)
 924 {
 925         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 926         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 927
 928         REG_WRITE(ah, AR_QOS_NO_ACK,
 929                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 930                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 931                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 932
 933         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 934         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 935         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 936         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 937         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 938 }
 939
 940 static void ath9k_hw_init_pll(struct ath_hal *ah,
 941                               struct ath9k_channel *chan)
 942 {
 943         u32 pll;
 944
 945         if (AR_SREV_9100(ah)) {
 946                 if (chan && IS_CHAN_5GHZ(chan))
 947                         pll = 0x1450;
 948                 else
 949                         pll = 0x1458;
 950         } else {
 951                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 952                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 953
 954                         if (chan && IS_CHAN_HALF_RATE(chan))
 955                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 956                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 957                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 958
 959                         if (chan && IS_CHAN_5GHZ(chan)) {
 960                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 961
 962
 963                                 if (AR_SREV_9280_20(ah)) {
 964                                         if (((chan->channel % 20) == 0)
 965                                             || ((chan->channel % 10) == 0))
 966                                                 pll = 0x2850;
 967                                         else
 968                                                 pll = 0x142c;
 969                                 }
 970                         } else {
 971                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 972                         }
 973
 974                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 975
 976                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 977
 978                         if (chan && IS_CHAN_HALF_RATE(chan))
 979                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 980                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 981                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 982
 983                         if (chan && IS_CHAN_5GHZ(chan))
 984                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 985                         else
 986                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 987                 } else {
 988                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 989
 990                         if (chan && IS_CHAN_HALF_RATE(chan))
 991                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 992                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 993                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 994
 995                         if (chan && IS_CHAN_5GHZ(chan))
 996                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 997                         else
 998                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 999                 }
1000         }
1001         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1002
1003         udelay(RTC_PLL_SETTLE_DELAY);
1004
1005         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1006 }
1007
1008 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1009 {
1010         struct ath_hal_5416 *ahp = AH5416(ah);
1011         int rx_chainmask, tx_chainmask;
1012
1013         rx_chainmask = ahp->ah_rxchainmask;
1014         tx_chainmask = ahp->ah_txchainmask;
1015
1016         switch (rx_chainmask) {
1017         case 0x5:
1018                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1019                             AR_PHY_SWAP_ALT_CHAIN);
1020         case 0x3:
1021                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1022                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1023                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1024                         break;
1025                 }
1026         case 0x1:
1027         case 0x2:
1028                 if (!AR_SREV_9280(ah))
1029                         break;
1030         case 0x7:
1031                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1032                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1033                 break;
1034         default:
1035                 break;
1036         }
1037
1038         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1039         if (tx_chainmask == 0x5) {
1040                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1041                             AR_PHY_SWAP_ALT_CHAIN);
1042         }
1043         if (AR_SREV_9100(ah))
1044                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1045                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1046 }
1047
1048 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
1049 {
1050         struct ath_hal_5416 *ahp = AH5416(ah);
1051
1052         ahp->ah_maskReg = AR_IMR_TXERR |
1053                 AR_IMR_TXURN |
1054                 AR_IMR_RXERR |
1055                 AR_IMR_RXORN |
1056                 AR_IMR_BCNMISC;
1057
1058         if (ahp->ah_intrMitigation)
1059                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1060         else
1061                 ahp->ah_maskReg |= AR_IMR_RXOK;
1062
1063         ahp->ah_maskReg |= AR_IMR_TXOK;
1064
1065         if (opmode == ATH9K_M_HOSTAP)
1066                 ahp->ah_maskReg |= AR_IMR_MIB;
1067
1068         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1069         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1070
1071         if (!AR_SREV_9100(ah)) {
1072                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1073                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1074                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1075         }
1076 }
1077
1078 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1079 {
1080         struct ath_hal_5416 *ahp = AH5416(ah);
1081
1082         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1083                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
1084                          __func__, us);
1085                 ahp->ah_acktimeout = (u32) -1;
1086                 return false;
1087         } else {
1088                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1089                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1090                 ahp->ah_acktimeout = us;
1091                 return true;
1092         }
1093 }
1094
1095 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1096 {
1097         struct ath_hal_5416 *ahp = AH5416(ah);
1098
1099         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1100                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
1101                          __func__, us);
1102                 ahp->ah_ctstimeout = (u32) -1;
1103                 return false;
1104         } else {
1105                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1106                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1107                 ahp->ah_ctstimeout = us;
1108                 return true;
1109         }
1110 }
1111
1112 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1113 {
1114         struct ath_hal_5416 *ahp = AH5416(ah);
1115
1116         if (tu > 0xFFFF) {
1117                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1118                         "%s: bad global tx timeout %u\n", __func__, tu);
1119                 ahp->ah_globaltxtimeout = (u32) -1;
1120                 return false;
1121         } else {
1122                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1123                 ahp->ah_globaltxtimeout = tu;
1124                 return true;
1125         }
1126 }
1127
1128 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1129 {
1130         struct ath_hal_5416 *ahp = AH5416(ah);
1131
1132         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
1133                  __func__, ahp->ah_miscMode);
1134
1135         if (ahp->ah_miscMode != 0)
1136                 REG_WRITE(ah, AR_PCU_MISC,
1137                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1138         if (ahp->ah_slottime != (u32) -1)
1139                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1140         if (ahp->ah_acktimeout != (u32) -1)
1141                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1142         if (ahp->ah_ctstimeout != (u32) -1)
1143                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1144         if (ahp->ah_globaltxtimeout != (u32) -1)
1145                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1146 }
1147
1148 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1149 {
1150         return vendorid == ATHEROS_VENDOR_ID ?
1151                 ath9k_hw_devname(devid) : NULL;
1152 }
1153
1154 void ath9k_hw_detach(struct ath_hal *ah)
1155 {
1156         if (!AR_SREV_9100(ah))
1157                 ath9k_hw_ani_detach(ah);
1158
1159         ath9k_hw_rfdetach(ah);
1160         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1161         kfree(ah);
1162 }
1163
1164 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1165                                 void __iomem *mem, int *error)
1166 {
1167         struct ath_hal *ah = NULL;
1168
1169         switch (devid) {
1170         case AR5416_DEVID_PCI:
1171         case AR5416_DEVID_PCIE:
1172         case AR9160_DEVID_PCI:
1173         case AR9280_DEVID_PCI:
1174         case AR9280_DEVID_PCIE:
1175                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1176                 break;
1177         default:
1178                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1179                          "devid=0x%x not supported.\n", devid);
1180                 ah = NULL;
1181                 *error = -ENXIO;
1182                 break;
1183         }
1184
1185         return ah;
1186 }
1187
1188 /*******/
1189 /* INI */
1190 /*******/
1191
1192 static void ath9k_hw_override_ini(struct ath_hal *ah,
1193                                   struct ath9k_channel *chan)
1194 {
1195         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1196             AR_SREV_9280_10_OR_LATER(ah))
1197                 return;
1198
1199         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1200 }
1201
1202 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1203                               struct ar5416_eeprom *pEepData,
1204                               u32 reg, u32 value)
1205 {
1206         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1207
1208         switch (ah->ah_devid) {
1209         case AR9280_DEVID_PCI:
1210                 if (reg == 0x7894) {
1211                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1212                                 "ini VAL: %x  EEPROM: %x\n", value,
1213                                 (pBase->version & 0xff));
1214
1215                         if ((pBase->version & 0xff) > 0x0a) {
1216                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1217                                         "PWDCLKIND: %d\n",
1218                                         pBase->pwdclkind);
1219                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1220                                 value |= AR_AN_TOP2_PWDCLKIND &
1221                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1222                         } else {
1223                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1224                                         "PWDCLKIND Earlier Rev\n");
1225                         }
1226
1227                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1228                                 "final ini VAL: %x\n", value);
1229                 }
1230                 break;
1231         }
1232
1233         return value;
1234 }
1235
1236 static int ath9k_hw_process_ini(struct ath_hal *ah,
1237                                 struct ath9k_channel *chan,
1238                                 enum ath9k_ht_macmode macmode)
1239 {
1240         int i, regWrites = 0;
1241         struct ath_hal_5416 *ahp = AH5416(ah);
1242         u32 modesIndex, freqIndex;
1243         int status;
1244
1245         switch (chan->chanmode) {
1246         case CHANNEL_A:
1247         case CHANNEL_A_HT20:
1248                 modesIndex = 1;
1249                 freqIndex = 1;
1250                 break;
1251         case CHANNEL_A_HT40PLUS:
1252         case CHANNEL_A_HT40MINUS:
1253                 modesIndex = 2;
1254                 freqIndex = 1;
1255                 break;
1256         case CHANNEL_G:
1257         case CHANNEL_G_HT20:
1258         case CHANNEL_B:
1259                 modesIndex = 4;
1260                 freqIndex = 2;
1261                 break;
1262         case CHANNEL_G_HT40PLUS:
1263         case CHANNEL_G_HT40MINUS:
1264                 modesIndex = 3;
1265                 freqIndex = 2;
1266                 break;
1267
1268         default:
1269                 return -EINVAL;
1270         }
1271
1272         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1273
1274         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1275
1276         ath9k_hw_set_addac(ah, chan);
1277
1278         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1279                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1280         } else {
1281                 struct ar5416IniArray temp;
1282                 u32 addacSize =
1283                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1284                         ahp->ah_iniAddac.ia_columns;
1285
1286                 memcpy(ahp->ah_addac5416_21,
1287                        ahp->ah_iniAddac.ia_array, addacSize);
1288
1289                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1290
1291                 temp.ia_array = ahp->ah_addac5416_21;
1292                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1293                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1294                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1295         }
1296
1297         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1298
1299         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1300                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1301                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1302
1303 #ifdef CONFIG_SLOW_ANT_DIV
1304                 if (ah->ah_devid == AR9280_DEVID_PCI)
1305                         val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
1306 #endif
1307
1308                 REG_WRITE(ah, reg, val);
1309
1310                 if (reg >= 0x7800 && reg < 0x78a0
1311                     && ah->ah_config.analog_shiftreg) {
1312                         udelay(100);
1313                 }
1314
1315                 DO_DELAY(regWrites);
1316         }
1317
1318         if (AR_SREV_9280_20_OR_LATER(ah))
1319                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1320
1321         if (AR_SREV_9280_20_OR_LATER(ah))
1322                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1323
1324         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1325                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1326                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1327
1328                 REG_WRITE(ah, reg, val);
1329
1330                 if (reg >= 0x7800 && reg < 0x78a0
1331                     && ah->ah_config.analog_shiftreg) {
1332                         udelay(100);
1333                 }
1334
1335                 DO_DELAY(regWrites);
1336         }
1337
1338         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1339
1340         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1341                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1342                                 regWrites);
1343         }
1344
1345         ath9k_hw_override_ini(ah, chan);
1346         ath9k_hw_set_regs(ah, chan, macmode);
1347         ath9k_hw_init_chain_masks(ah);
1348
1349         status = ath9k_hw_set_txpower(ah, chan,
1350                                       ath9k_regd_get_ctl(ah, chan),
1351                                       ath9k_regd_get_antenna_allowed(ah,
1352                                                                      chan),
1353                                       chan->maxRegTxPower * 2,
1354                                       min((u32) MAX_RATE_POWER,
1355                                           (u32) ah->ah_powerLimit));
1356         if (status != 0) {
1357                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1358                         "%s: error init'ing transmit power\n", __func__);
1359                 return -EIO;
1360         }
1361
1362         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1363                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1364                         "%s: ar5416SetRfRegs failed\n", __func__);
1365                 return -EIO;
1366         }
1367
1368         return 0;
1369 }
1370
1371 /****************************************/
1372 /* Reset and Channel Switching Routines */
1373 /****************************************/
1374
1375 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1376 {
1377         u32 rfMode = 0;
1378
1379         if (chan == NULL)
1380                 return;
1381
1382         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1383                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1384
1385         if (!AR_SREV_9280_10_OR_LATER(ah))
1386                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1387                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1388
1389         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1390                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1391
1392         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1393 }
1394
1395 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1396 {
1397         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1398 }
1399
1400 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1401 {
1402         u32 regval;
1403
1404         regval = REG_READ(ah, AR_AHB_MODE);
1405         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1406
1407         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1408         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1409
1410         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1411
1412         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1413         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1414
1415         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1416
1417         if (AR_SREV_9285(ah)) {
1418                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1419                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1420         } else {
1421                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1422                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1423         }
1424 }
1425
1426 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1427 {
1428         u32 val;
1429
1430         val = REG_READ(ah, AR_STA_ID1);
1431         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1432         switch (opmode) {
1433         case ATH9K_M_HOSTAP:
1434                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1435                           | AR_STA_ID1_KSRCH_MODE);
1436                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1437                 break;
1438         case ATH9K_M_IBSS:
1439                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1440                           | AR_STA_ID1_KSRCH_MODE);
1441                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1442                 break;
1443         case ATH9K_M_STA:
1444         case ATH9K_M_MONITOR:
1445                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1446                 break;
1447         }
1448 }
1449
1450 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1451                                                  u32 coef_scaled,
1452                                                  u32 *coef_mantissa,
1453                                                  u32 *coef_exponent)
1454 {
1455         u32 coef_exp, coef_man;
1456
1457         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1458                 if ((coef_scaled >> coef_exp) & 0x1)
1459                         break;
1460
1461         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1462
1463         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1464
1465         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1466         *coef_exponent = coef_exp - 16;
1467 }
1468
1469 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1470                                      struct ath9k_channel *chan)
1471 {
1472         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1473         u32 clockMhzScaled = 0x64000000;
1474         struct chan_centers centers;
1475
1476         if (IS_CHAN_HALF_RATE(chan))
1477                 clockMhzScaled = clockMhzScaled >> 1;
1478         else if (IS_CHAN_QUARTER_RATE(chan))
1479                 clockMhzScaled = clockMhzScaled >> 2;
1480
1481         ath9k_hw_get_channel_centers(ah, chan, &centers);
1482         coef_scaled = clockMhzScaled / centers.synth_center;
1483
1484         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1485                                       &ds_coef_exp);
1486
1487         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1488                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1489         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1490                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1491
1492         coef_scaled = (9 * coef_scaled) / 10;
1493
1494         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1495                                       &ds_coef_exp);
1496
1497         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1498                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1499         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1500                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1501 }
1502
1503 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1504 {
1505         u32 rst_flags;
1506         u32 tmpReg;
1507
1508         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1509                   AR_RTC_FORCE_WAKE_ON_INT);
1510
1511         if (AR_SREV_9100(ah)) {
1512                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1513                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1514         } else {
1515                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1516                 if (tmpReg &
1517                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1518                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1519                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1520                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1521                 } else {
1522                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1523                 }
1524
1525                 rst_flags = AR_RTC_RC_MAC_WARM;
1526                 if (type == ATH9K_RESET_COLD)
1527                         rst_flags |= AR_RTC_RC_MAC_COLD;
1528         }
1529
1530         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1531         udelay(50);
1532
1533         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1534         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1535                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1536                         "%s: RTC stuck in MAC reset\n",
1537                         __func__);
1538                 return false;
1539         }
1540
1541         if (!AR_SREV_9100(ah))
1542                 REG_WRITE(ah, AR_RC, 0);
1543
1544         ath9k_hw_init_pll(ah, NULL);
1545
1546         if (AR_SREV_9100(ah))
1547                 udelay(50);
1548
1549         return true;
1550 }
1551
1552 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1553 {
1554         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1555                   AR_RTC_FORCE_WAKE_ON_INT);
1556
1557         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1558         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1559
1560         if (!ath9k_hw_wait(ah,
1561                            AR_RTC_STATUS,
1562                            AR_RTC_STATUS_M,
1563                            AR_RTC_STATUS_ON)) {
1564                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1565                          __func__);
1566                 return false;
1567         }
1568
1569         ath9k_hw_read_revisions(ah);
1570
1571         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1572 }
1573
1574 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1575 {
1576         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1577                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1578
1579         switch (type) {
1580         case ATH9K_RESET_POWER_ON:
1581                 return ath9k_hw_set_reset_power_on(ah);
1582                 break;
1583         case ATH9K_RESET_WARM:
1584         case ATH9K_RESET_COLD:
1585                 return ath9k_hw_set_reset(ah, type);
1586                 break;
1587         default:
1588                 return false;
1589         }
1590 }
1591
1592 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1593                               enum ath9k_ht_macmode macmode)
1594 {
1595         u32 phymode;
1596         struct ath_hal_5416 *ahp = AH5416(ah);
1597
1598         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1599                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1600
1601         if (IS_CHAN_HT40(chan)) {
1602                 phymode |= AR_PHY_FC_DYN2040_EN;
1603
1604                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1605                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1606                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1607
1608                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1609                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1610         }
1611         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1612
1613         ath9k_hw_set11nmac2040(ah, macmode);
1614
1615         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1616         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1617 }
1618
1619 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1620                                 struct ath9k_channel *chan)
1621 {
1622         struct ath_hal_5416 *ahp = AH5416(ah);
1623
1624         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1625                 return false;
1626
1627         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1628                 return false;
1629
1630         ahp->ah_chipFullSleep = false;
1631
1632         ath9k_hw_init_pll(ah, chan);
1633
1634         ath9k_hw_set_rfmode(ah, chan);
1635
1636         return true;
1637 }
1638
1639 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1640                                                  struct ath9k_channel *chan)
1641 {
1642         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1643                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1644                         "%s: invalid channel %u/0x%x; not marked as "
1645                         "2GHz or 5GHz\n", __func__, chan->channel,
1646                         chan->channelFlags);
1647                 return NULL;
1648         }
1649
1650         if (!IS_CHAN_OFDM(chan) &&
1651             !IS_CHAN_B(chan) &&
1652             !IS_CHAN_HT20(chan) &&
1653             !IS_CHAN_HT40(chan)) {
1654                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1655                         "%s: invalid channel %u/0x%x; not marked as "
1656                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1657                         __func__, chan->channel, chan->channelFlags);
1658                 return NULL;
1659         }
1660
1661         return ath9k_regd_check_channel(ah, chan);
1662 }
1663
1664 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1665                                     struct ath9k_channel *chan,
1666                                     enum ath9k_ht_macmode macmode)
1667 {
1668         u32 synthDelay, qnum;
1669
1670         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1671                 if (ath9k_hw_numtxpending(ah, qnum)) {
1672                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1673                                 "%s: Transmit frames pending on queue %d\n",
1674                                 __func__, qnum);
1675                         return false;
1676                 }
1677         }
1678
1679         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1680         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1681                            AR_PHY_RFBUS_GRANT_EN)) {
1682                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1683                         "%s: Could not kill baseband RX\n", __func__);
1684                 return false;
1685         }
1686
1687         ath9k_hw_set_regs(ah, chan, macmode);
1688
1689         if (AR_SREV_9280_10_OR_LATER(ah)) {
1690                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1691                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692                                 "%s: failed to set channel\n", __func__);
1693                         return false;
1694                 }
1695         } else {
1696                 if (!(ath9k_hw_set_channel(ah, chan))) {
1697                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1698                                 "%s: failed to set channel\n", __func__);
1699                         return false;
1700                 }
1701         }
1702
1703         if (ath9k_hw_set_txpower(ah, chan,
1704                                  ath9k_regd_get_ctl(ah, chan),
1705                                  ath9k_regd_get_antenna_allowed(ah, chan),
1706                                  chan->maxRegTxPower * 2,
1707                                  min((u32) MAX_RATE_POWER,
1708                                      (u32) ah->ah_powerLimit)) != 0) {
1709                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1710                         "%s: error init'ing transmit power\n", __func__);
1711                 return false;
1712         }
1713
1714         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1715         if (IS_CHAN_B(chan))
1716                 synthDelay = (4 * synthDelay) / 22;
1717         else
1718                 synthDelay /= 10;
1719
1720         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1721
1722         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1723
1724         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1725                 ath9k_hw_set_delta_slope(ah, chan);
1726
1727         if (AR_SREV_9280_10_OR_LATER(ah))
1728                 ath9k_hw_9280_spur_mitigate(ah, chan);
1729         else
1730                 ath9k_hw_spur_mitigate(ah, chan);
1731
1732         if (!chan->oneTimeCalsDone)
1733                 chan->oneTimeCalsDone = true;
1734
1735         return true;
1736 }
1737
1738 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1739 {
1740         int bb_spur = AR_NO_SPUR;
1741         int freq;
1742         int bin, cur_bin;
1743         int bb_spur_off, spur_subchannel_sd;
1744         int spur_freq_sd;
1745         int spur_delta_phase;
1746         int denominator;
1747         int upper, lower, cur_vit_mask;
1748         int tmp, newVal;
1749         int i;
1750         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1751                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1752         };
1753         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1754                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1755         };
1756         int inc[4] = { 0, 100, 0, 0 };
1757         struct chan_centers centers;
1758
1759         int8_t mask_m[123];
1760         int8_t mask_p[123];
1761         int8_t mask_amt;
1762         int tmp_mask;
1763         int cur_bb_spur;
1764         bool is2GHz = IS_CHAN_2GHZ(chan);
1765
1766         memset(&mask_m, 0, sizeof(int8_t) * 123);
1767         memset(&mask_p, 0, sizeof(int8_t) * 123);
1768
1769         ath9k_hw_get_channel_centers(ah, chan, &centers);
1770         freq = centers.synth_center;
1771
1772         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1773         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1774                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1775
1776                 if (is2GHz)
1777                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1778                 else
1779                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1780
1781                 if (AR_NO_SPUR == cur_bb_spur)
1782                         break;
1783                 cur_bb_spur = cur_bb_spur - freq;
1784
1785                 if (IS_CHAN_HT40(chan)) {
1786                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1787                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1788                                 bb_spur = cur_bb_spur;
1789                                 break;
1790                         }
1791                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1792                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1793                         bb_spur = cur_bb_spur;
1794                         break;
1795                 }
1796         }
1797
1798         if (AR_NO_SPUR == bb_spur) {
1799                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1800                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1801                 return;
1802         } else {
1803                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1804                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1805         }
1806
1807         bin = bb_spur * 320;
1808
1809         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1810
1811         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1812                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1813                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1814                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1815         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1816
1817         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1818                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1819                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1820                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1821                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1822         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1823
1824         if (IS_CHAN_HT40(chan)) {
1825                 if (bb_spur < 0) {
1826                         spur_subchannel_sd = 1;
1827                         bb_spur_off = bb_spur + 10;
1828                 } else {
1829                         spur_subchannel_sd = 0;
1830                         bb_spur_off = bb_spur - 10;
1831                 }
1832         } else {
1833                 spur_subchannel_sd = 0;
1834                 bb_spur_off = bb_spur;
1835         }
1836
1837         if (IS_CHAN_HT40(chan))
1838                 spur_delta_phase =
1839                         ((bb_spur * 262144) /
1840                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1841         else
1842                 spur_delta_phase =
1843                         ((bb_spur * 524288) /
1844                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1845
1846         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1847         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1848
1849         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1850                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1851                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1852         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1853
1854         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1855         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1856
1857         cur_bin = -6000;
1858         upper = bin + 100;
1859         lower = bin - 100;
1860
1861         for (i = 0; i < 4; i++) {
1862                 int pilot_mask = 0;
1863                 int chan_mask = 0;
1864                 int bp = 0;
1865                 for (bp = 0; bp < 30; bp++) {
1866                         if ((cur_bin > lower) && (cur_bin < upper)) {
1867                                 pilot_mask = pilot_mask | 0x1 << bp;
1868                                 chan_mask = chan_mask | 0x1 << bp;
1869                         }
1870                         cur_bin += 100;
1871                 }
1872                 cur_bin += inc[i];
1873                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1874                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1875         }
1876
1877         cur_vit_mask = 6100;
1878         upper = bin + 120;
1879         lower = bin - 120;
1880
1881         for (i = 0; i < 123; i++) {
1882                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1883
1884                         /* workaround for gcc bug #37014 */
1885                         volatile int tmp = abs(cur_vit_mask - bin);
1886
1887                         if (tmp < 75)
1888                                 mask_amt = 1;
1889                         else
1890                                 mask_amt = 0;
1891                         if (cur_vit_mask < 0)
1892                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1893                         else
1894                                 mask_p[cur_vit_mask / 100] = mask_amt;
1895                 }
1896                 cur_vit_mask -= 100;
1897         }
1898
1899         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1900                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1901                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1902                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1903                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1904                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1905                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1906                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1907         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1908         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1909
1910         tmp_mask = (mask_m[31] << 28)
1911                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1912                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1913                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1914                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1915                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1916                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1917                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1918         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1919         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1920
1921         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1922                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1923                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1924                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1925                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1926                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1927                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1928                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1929         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1930         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1931
1932         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1933                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1934                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1935                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1936                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1937                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1938                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1939                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1940         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1941         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1942
1943         tmp_mask = (mask_p[15] << 28)
1944                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1945                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1946                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1947                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1948                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1949                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1950                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1951         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1952         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1953
1954         tmp_mask = (mask_p[30] << 28)
1955                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1956                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1957                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1958                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1959                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1960                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1961                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1962         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1963         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1964
1965         tmp_mask = (mask_p[45] << 28)
1966                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1967                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1968                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1969                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1970                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1971                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1972                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1973         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1974         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1975
1976         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1977                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1978                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1979                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1980                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1981                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1982                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1983                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1984         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1985         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1986 }
1987
1988 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1989 {
1990         int bb_spur = AR_NO_SPUR;
1991         int bin, cur_bin;
1992         int spur_freq_sd;
1993         int spur_delta_phase;
1994         int denominator;
1995         int upper, lower, cur_vit_mask;
1996         int tmp, new;
1997         int i;
1998         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1999                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2000         };
2001         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2002                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2003         };
2004         int inc[4] = { 0, 100, 0, 0 };
2005
2006         int8_t mask_m[123];
2007         int8_t mask_p[123];
2008         int8_t mask_amt;
2009         int tmp_mask;
2010         int cur_bb_spur;
2011         bool is2GHz = IS_CHAN_2GHZ(chan);
2012
2013         memset(&mask_m, 0, sizeof(int8_t) * 123);
2014         memset(&mask_p, 0, sizeof(int8_t) * 123);
2015
2016         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2017                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2018                 if (AR_NO_SPUR == cur_bb_spur)
2019                         break;
2020                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2021                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2022                         bb_spur = cur_bb_spur;
2023                         break;
2024                 }
2025         }
2026
2027         if (AR_NO_SPUR == bb_spur)
2028                 return;
2029
2030         bin = bb_spur * 32;
2031
2032         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2033         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2034                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2035                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2036                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2037
2038         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2039
2040         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2041                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2042                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2043                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2044                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2045         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2046
2047         spur_delta_phase = ((bb_spur * 524288) / 100) &
2048                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2049
2050         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2051         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2052
2053         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2054                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2055                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2056         REG_WRITE(ah, AR_PHY_TIMING11, new);
2057
2058         cur_bin = -6000;
2059         upper = bin + 100;
2060         lower = bin - 100;
2061
2062         for (i = 0; i < 4; i++) {
2063                 int pilot_mask = 0;
2064                 int chan_mask = 0;
2065                 int bp = 0;
2066                 for (bp = 0; bp < 30; bp++) {
2067                         if ((cur_bin > lower) && (cur_bin < upper)) {
2068                                 pilot_mask = pilot_mask | 0x1 << bp;
2069                                 chan_mask = chan_mask | 0x1 << bp;
2070                         }
2071                         cur_bin += 100;
2072                 }
2073                 cur_bin += inc[i];
2074                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2075                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2076         }
2077
2078         cur_vit_mask = 6100;
2079         upper = bin + 120;
2080         lower = bin - 120;
2081
2082         for (i = 0; i < 123; i++) {
2083                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2084
2085                         /* workaround for gcc bug #37014 */
2086                         volatile int tmp = abs(cur_vit_mask - bin);
2087
2088                         if (tmp < 75)
2089                                 mask_amt = 1;
2090                         else
2091                                 mask_amt = 0;
2092                         if (cur_vit_mask < 0)
2093                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2094                         else
2095                                 mask_p[cur_vit_mask / 100] = mask_amt;
2096                 }
2097                 cur_vit_mask -= 100;
2098         }
2099
2100         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2101                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2102                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2103                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2104                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2105                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2106                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2107                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2108         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2109         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2110
2111         tmp_mask = (mask_m[31] << 28)
2112                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2113                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2114                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2115                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2116                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2117                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2118                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2119         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2120         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2121
2122         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2123                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2124                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2125                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2126                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2127                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2128                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2129                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2130         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2131         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2132
2133         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2134                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2135                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2136                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2137                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2138                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2139                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2140                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2141         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2142         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2143
2144         tmp_mask = (mask_p[15] << 28)
2145                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2146                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2147                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2148                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2149                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2150                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2151                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2152         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2153         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2154
2155         tmp_mask = (mask_p[30] << 28)
2156                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2157                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2158                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2159                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2160                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2161                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2162                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2163         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2164         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2165
2166         tmp_mask = (mask_p[45] << 28)
2167                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2168                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2169                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2170                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2171                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2172                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2173                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2174         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2175         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2176
2177         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2178                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2179                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2180                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2181                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2182                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2183                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2184                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2185         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2186         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2187 }
2188
2189 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2190                     enum ath9k_ht_macmode macmode,
2191                     u8 txchainmask, u8 rxchainmask,
2192                     enum ath9k_ht_extprotspacing extprotspacing,
2193                     bool bChannelChange, int *status)
2194 {
2195         u32 saveLedState;
2196         struct ath_hal_5416 *ahp = AH5416(ah);
2197         struct ath9k_channel *curchan = ah->ah_curchan;
2198         u32 saveDefAntenna;
2199         u32 macStaId1;
2200         int ecode;
2201         int i, rx_chainmask;
2202
2203         ahp->ah_extprotspacing = extprotspacing;
2204         ahp->ah_txchainmask = txchainmask;
2205         ahp->ah_rxchainmask = rxchainmask;
2206
2207         if (AR_SREV_9280(ah)) {
2208                 ahp->ah_txchainmask &= 0x3;
2209                 ahp->ah_rxchainmask &= 0x3;
2210         }
2211
2212         if (ath9k_hw_check_chan(ah, chan) == NULL) {
2213                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2214                         "%s: invalid channel %u/0x%x; no mapping\n",
2215                         __func__, chan->channel, chan->channelFlags);
2216                 ecode = -EINVAL;
2217                 goto bad;
2218         }
2219
2220         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2221                 ecode = -EIO;
2222                 goto bad;
2223         }
2224
2225         if (curchan)
2226                 ath9k_hw_getnf(ah, curchan);
2227
2228         if (bChannelChange &&
2229             (ahp->ah_chipFullSleep != true) &&
2230             (ah->ah_curchan != NULL) &&
2231             (chan->channel != ah->ah_curchan->channel) &&
2232             ((chan->channelFlags & CHANNEL_ALL) ==
2233              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2234             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2235                                    !IS_CHAN_A_5MHZ_SPACED(ah->
2236                                                           ah_curchan)))) {
2237
2238                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2239                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2240                         ath9k_hw_start_nfcal(ah);
2241                         return true;
2242                 }
2243         }
2244
2245         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2246         if (saveDefAntenna == 0)
2247                 saveDefAntenna = 1;
2248
2249         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2250
2251         saveLedState = REG_READ(ah, AR_CFG_LED) &
2252                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2253                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2254
2255         ath9k_hw_mark_phy_inactive(ah);
2256
2257         if (!ath9k_hw_chip_reset(ah, chan)) {
2258                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
2259                          __func__);
2260                 ecode = -EINVAL;
2261                 goto bad;
2262         }
2263
2264         if (AR_SREV_9280(ah)) {
2265                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2266                             AR_GPIO_JTAG_DISABLE);
2267
2268                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2269                         if (IS_CHAN_5GHZ(chan))
2270                                 ath9k_hw_set_gpio(ah, 9, 0);
2271                         else
2272                                 ath9k_hw_set_gpio(ah, 9, 1);
2273                 }
2274                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2275         }
2276
2277         ecode = ath9k_hw_process_ini(ah, chan, macmode);
2278         if (ecode != 0) {
2279                 ecode = -EINVAL;
2280                 goto bad;
2281         }
2282
2283         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2284                 ath9k_hw_set_delta_slope(ah, chan);
2285
2286         if (AR_SREV_9280_10_OR_LATER(ah))
2287                 ath9k_hw_9280_spur_mitigate(ah, chan);
2288         else
2289                 ath9k_hw_spur_mitigate(ah, chan);
2290
2291         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2292                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2293                         "%s: error setting board options\n", __func__);
2294                 ecode = -EIO;
2295                 goto bad;
2296         }
2297
2298         ath9k_hw_decrease_chain_power(ah, chan);
2299
2300         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2301         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2302                   | macStaId1
2303                   | AR_STA_ID1_RTS_USE_DEF
2304                   | (ah->ah_config.
2305                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2306                   | ahp->ah_staId1Defaults);
2307         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2308
2309         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2310         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2311
2312         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2313
2314         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2315         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2316                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2317
2318         REG_WRITE(ah, AR_ISR, ~0);
2319
2320         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2321
2322         if (AR_SREV_9280_10_OR_LATER(ah)) {
2323                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2324                         ecode = -EIO;
2325                         goto bad;
2326                 }
2327         } else {
2328                 if (!(ath9k_hw_set_channel(ah, chan))) {
2329                         ecode = -EIO;
2330                         goto bad;
2331                 }
2332         }
2333
2334         for (i = 0; i < AR_NUM_DCU; i++)
2335                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2336
2337         ahp->ah_intrTxqs = 0;
2338         for (i = 0; i < ah->ah_caps.total_queues; i++)
2339                 ath9k_hw_resettxqueue(ah, i);
2340
2341         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2342         ath9k_hw_init_qos(ah);
2343
2344 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2345         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2346                 ath9k_enable_rfkill(ah);
2347 #endif
2348         ath9k_hw_init_user_settings(ah);
2349
2350         REG_WRITE(ah, AR_STA_ID1,
2351                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2352
2353         ath9k_hw_set_dma(ah);
2354
2355         REG_WRITE(ah, AR_OBS, 8);
2356
2357         if (ahp->ah_intrMitigation) {
2358
2359                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2360                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2361         }
2362
2363         ath9k_hw_init_bb(ah, chan);
2364
2365         if (!ath9k_hw_init_cal(ah, chan)){
2366                 ecode = -EIO;;
2367                 goto bad;
2368         }
2369
2370         rx_chainmask = ahp->ah_rxchainmask;
2371         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2372                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2373                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2374         }
2375
2376         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2377
2378         if (AR_SREV_9100(ah)) {
2379                 u32 mask;
2380                 mask = REG_READ(ah, AR_CFG);
2381                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2382                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2383                                 "%s CFG Byte Swap Set 0x%x\n", __func__,
2384                                 mask);
2385                 } else {
2386                         mask =
2387                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2388                         REG_WRITE(ah, AR_CFG, mask);
2389                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2390                                 "%s Setting CFG 0x%x\n", __func__,
2391                                 REG_READ(ah, AR_CFG));
2392                 }
2393         } else {
2394 #ifdef __BIG_ENDIAN
2395                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2396 #endif
2397         }
2398
2399         return true;
2400 bad:
2401         if (status)
2402                 *status = ecode;
2403         return false;
2404 }
2405
2406 /************************/
2407 /* Key Cache Management */
2408 /************************/
2409
2410 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2411 {
2412         u32 keyType;
2413
2414         if (entry >= ah->ah_caps.keycache_size) {
2415                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2416                         "%s: entry %u out of range\n", __func__, entry);
2417                 return false;
2418         }
2419
2420         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2421
2422         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2423         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2424         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2425         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2426         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2427         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2428         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2429         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2430
2431         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2432                 u16 micentry = entry + 64;
2433
2434                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2435                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2436                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2437                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2438
2439         }
2440
2441         if (ah->ah_curchan == NULL)
2442                 return true;
2443
2444         return true;
2445 }
2446
2447 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2448 {
2449         u32 macHi, macLo;
2450
2451         if (entry >= ah->ah_caps.keycache_size) {
2452                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2453                         "%s: entry %u out of range\n", __func__, entry);
2454                 return false;
2455         }
2456
2457         if (mac != NULL) {
2458                 macHi = (mac[5] << 8) | mac[4];
2459                 macLo = (mac[3] << 24) |
2460                         (mac[2] << 16) |
2461                         (mac[1] << 8) |
2462                         mac[0];
2463                 macLo >>= 1;
2464                 macLo |= (macHi & 1) << 31;
2465                 macHi >>= 1;
2466         } else {
2467                 macLo = macHi = 0;
2468         }
2469         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2470         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2471
2472         return true;
2473 }
2474
2475 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2476                                  const struct ath9k_keyval *k,
2477                                  const u8 *mac, int xorKey)
2478 {
2479         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2480         u32 key0, key1, key2, key3, key4;
2481         u32 keyType;
2482         u32 xorMask = xorKey ?
2483                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2484                  | ATH9K_KEY_XOR) : 0;
2485         struct ath_hal_5416 *ahp = AH5416(ah);
2486
2487         if (entry >= pCap->keycache_size) {
2488                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2489                         "%s: entry %u out of range\n", __func__, entry);
2490                 return false;
2491         }
2492
2493         switch (k->kv_type) {
2494         case ATH9K_CIPHER_AES_OCB:
2495                 keyType = AR_KEYTABLE_TYPE_AES;
2496                 break;
2497         case ATH9K_CIPHER_AES_CCM:
2498                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2499                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2500                                 "%s: AES-CCM not supported by "
2501                                 "mac rev 0x%x\n", __func__,
2502                                 ah->ah_macRev);
2503                         return false;
2504                 }
2505                 keyType = AR_KEYTABLE_TYPE_CCM;
2506                 break;
2507         case ATH9K_CIPHER_TKIP:
2508                 keyType = AR_KEYTABLE_TYPE_TKIP;
2509                 if (ATH9K_IS_MIC_ENABLED(ah)
2510                     && entry + 64 >= pCap->keycache_size) {
2511                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2512                                 "%s: entry %u inappropriate for TKIP\n",
2513                                 __func__, entry);
2514                         return false;
2515                 }
2516                 break;
2517         case ATH9K_CIPHER_WEP:
2518                 if (k->kv_len < LEN_WEP40) {
2519                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2520                                 "%s: WEP key length %u too small\n",
2521                                 __func__, k->kv_len);
2522                         return false;
2523                 }
2524                 if (k->kv_len <= LEN_WEP40)
2525                         keyType = AR_KEYTABLE_TYPE_40;
2526                 else if (k->kv_len <= LEN_WEP104)
2527                         keyType = AR_KEYTABLE_TYPE_104;
2528                 else
2529                         keyType = AR_KEYTABLE_TYPE_128;
2530                 break;
2531         case ATH9K_CIPHER_CLR:
2532                 keyType = AR_KEYTABLE_TYPE_CLR;
2533                 break;
2534         default:
2535                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2536                         "%s: cipher %u not supported\n", __func__,
2537                         k->kv_type);
2538                 return false;
2539         }
2540
2541         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2542         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2543         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2544         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2545         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2546         if (k->kv_len <= LEN_WEP104)
2547                 key4 &= 0xff;
2548
2549         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2550                 u16 micentry = entry + 64;
2551
2552                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2553                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2554                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2555                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2556                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2557                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2558                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2559
2560                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2561                         u32 mic0, mic1, mic2, mic3, mic4;
2562
2563                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2564                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2565                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2566                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2567                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2568                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2569                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2570                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2571                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2572                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2573                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2574                                   AR_KEYTABLE_TYPE_CLR);
2575
2576                 } else {
2577                         u32 mic0, mic2;
2578
2579                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2580                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2581                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2582                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2583                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2584                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2585                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2586                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2587                                   AR_KEYTABLE_TYPE_CLR);
2588                 }
2589                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2590                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2591                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2592                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2593         } else {
2594                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2595                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2596                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2597                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2598                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2599                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2600
2601                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2602         }
2603
2604         if (ah->ah_curchan == NULL)
2605                 return true;
2606
2607         return true;
2608 }
2609
2610 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2611 {
2612         if (entry < ah->ah_caps.keycache_size) {
2613                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2614                 if (val & AR_KEYTABLE_VALID)
2615                         return true;
2616         }
2617         return false;
2618 }
2619
2620 /******************************/
2621 /* Power Management (Chipset) */
2622 /******************************/
2623
2624 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2625 {
2626         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2627         if (setChip) {
2628                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2629                             AR_RTC_FORCE_WAKE_EN);
2630                 if (!AR_SREV_9100(ah))
2631                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2632
2633                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2634                             AR_RTC_RESET_EN);
2635         }
2636 }
2637
2638 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2639 {
2640         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2641         if (setChip) {
2642                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2643
2644                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2645                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2646                                   AR_RTC_FORCE_WAKE_ON_INT);
2647                 } else {
2648                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2649                                     AR_RTC_FORCE_WAKE_EN);
2650                 }
2651         }
2652 }
2653
2654 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2655                                      int setChip)
2656 {
2657         u32 val;
2658         int i;
2659
2660         if (setChip) {
2661                 if ((REG_READ(ah, AR_RTC_STATUS) &
2662                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2663                         if (ath9k_hw_set_reset_reg(ah,
2664                                            ATH9K_RESET_POWER_ON) != true) {
2665                                 return false;
2666                         }
2667                 }
2668                 if (AR_SREV_9100(ah))
2669                         REG_SET_BIT(ah, AR_RTC_RESET,
2670                                     AR_RTC_RESET_EN);
2671
2672                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2673                             AR_RTC_FORCE_WAKE_EN);
2674                 udelay(50);
2675
2676                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2677                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2678                         if (val == AR_RTC_STATUS_ON)
2679                                 break;
2680                         udelay(50);
2681                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2682                                     AR_RTC_FORCE_WAKE_EN);
2683                 }
2684                 if (i == 0) {
2685                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2686                                 "%s: Failed to wakeup in %uus\n",
2687                                 __func__, POWER_UP_TIME / 20);
2688                         return false;
2689                 }
2690         }
2691
2692         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2693
2694         return true;
2695 }
2696
2697 bool ath9k_hw_setpower(struct ath_hal *ah,
2698                        enum ath9k_power_mode mode)
2699 {
2700         struct ath_hal_5416 *ahp = AH5416(ah);
2701         static const char *modes[] = {
2702                 "AWAKE",
2703                 "FULL-SLEEP",
2704                 "NETWORK SLEEP",
2705                 "UNDEFINED"
2706         };
2707         int status = true, setChip = true;
2708
2709         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
2710                 modes[ahp->ah_powerMode], modes[mode],
2711                 setChip ? "set chip " : "");
2712
2713         switch (mode) {
2714         case ATH9K_PM_AWAKE:
2715                 status = ath9k_hw_set_power_awake(ah, setChip);
2716                 break;
2717         case ATH9K_PM_FULL_SLEEP:
2718                 ath9k_set_power_sleep(ah, setChip);
2719                 ahp->ah_chipFullSleep = true;
2720                 break;
2721         case ATH9K_PM_NETWORK_SLEEP:
2722                 ath9k_set_power_network_sleep(ah, setChip);
2723                 break;
2724         default:
2725                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2726                         "%s: unknown power mode %u\n", __func__, mode);
2727                 return false;
2728         }
2729         ahp->ah_powerMode = mode;
2730
2731         return status;
2732 }
2733
2734 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2735 {
2736         struct ath_hal_5416 *ahp = AH5416(ah);
2737         u8 i;
2738
2739         if (ah->ah_isPciExpress != true)
2740                 return;
2741
2742         if (ah->ah_config.pcie_powersave_enable == 2)
2743                 return;
2744
2745         if (restore)
2746                 return;
2747
2748         if (AR_SREV_9280_20_OR_LATER(ah)) {
2749                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2750                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2751                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2752                 }
2753                 udelay(1000);
2754         } else if (AR_SREV_9280(ah) &&
2755                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2756                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2757                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2758
2759                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2760                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2761                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2762
2763                 if (ah->ah_config.pcie_clock_req)
2764                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2765                 else
2766                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2767
2768                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2769                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2770                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2771
2772                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2773
2774                 udelay(1000);
2775         } else {
2776                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2777                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2778                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2779                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2780                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2781                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2782                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2783                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2784                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2785                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2786         }
2787
2788         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2789
2790         if (ah->ah_config.pcie_waen) {
2791                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2792         } else {
2793                 if (AR_SREV_9280(ah))
2794                         REG_WRITE(ah, AR_WA, 0x0040073f);
2795                 else
2796                         REG_WRITE(ah, AR_WA, 0x0000073f);
2797         }
2798 }
2799
2800 /**********************/
2801 /* Interrupt Handling */
2802 /**********************/
2803
2804 bool ath9k_hw_intrpend(struct ath_hal *ah)
2805 {
2806         u32 host_isr;
2807
2808         if (AR_SREV_9100(ah))
2809                 return true;
2810
2811         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2812         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2813                 return true;
2814
2815         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2816         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2817             && (host_isr != AR_INTR_SPURIOUS))
2818                 return true;
2819
2820         return false;
2821 }
2822
2823 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2824 {
2825         u32 isr = 0;
2826         u32 mask2 = 0;
2827         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2828         u32 sync_cause = 0;
2829         bool fatal_int = false;
2830         struct ath_hal_5416 *ahp = AH5416(ah);
2831
2832         if (!AR_SREV_9100(ah)) {
2833                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2834                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2835                             == AR_RTC_STATUS_ON) {
2836                                 isr = REG_READ(ah, AR_ISR);
2837                         }
2838                 }
2839
2840                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2841                         AR_INTR_SYNC_DEFAULT;
2842
2843                 *masked = 0;
2844
2845                 if (!isr && !sync_cause)
2846                         return false;
2847         } else {
2848                 *masked = 0;
2849                 isr = REG_READ(ah, AR_ISR);
2850         }
2851
2852         if (isr) {
2853                 if (isr & AR_ISR_BCNMISC) {
2854                         u32 isr2;
2855                         isr2 = REG_READ(ah, AR_ISR_S2);
2856                         if (isr2 & AR_ISR_S2_TIM)
2857                                 mask2 |= ATH9K_INT_TIM;
2858                         if (isr2 & AR_ISR_S2_DTIM)
2859                                 mask2 |= ATH9K_INT_DTIM;
2860                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2861                                 mask2 |= ATH9K_INT_DTIMSYNC;
2862                         if (isr2 & (AR_ISR_S2_CABEND))
2863                                 mask2 |= ATH9K_INT_CABEND;
2864                         if (isr2 & AR_ISR_S2_GTT)
2865                                 mask2 |= ATH9K_INT_GTT;
2866                         if (isr2 & AR_ISR_S2_CST)
2867                                 mask2 |= ATH9K_INT_CST;
2868                 }
2869
2870                 isr = REG_READ(ah, AR_ISR_RAC);
2871                 if (isr == 0xffffffff) {
2872                         *masked = 0;
2873                         return false;
2874                 }
2875
2876                 *masked = isr & ATH9K_INT_COMMON;
2877
2878                 if (ahp->ah_intrMitigation) {
2879                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2880                                 *masked |= ATH9K_INT_RX;
2881                 }
2882
2883                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2884                         *masked |= ATH9K_INT_RX;
2885                 if (isr &
2886                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2887                      AR_ISR_TXEOL)) {
2888                         u32 s0_s, s1_s;
2889
2890                         *masked |= ATH9K_INT_TX;
2891
2892                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2893                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2894                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2895
2896                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2897                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2898                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2899                 }
2900
2901                 if (isr & AR_ISR_RXORN) {
2902                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2903                                 "%s: receive FIFO overrun interrupt\n",
2904                                 __func__);
2905                 }
2906
2907                 if (!AR_SREV_9100(ah)) {
2908                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2909                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2910                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2911                                         *masked |= ATH9K_INT_TIM_TIMER;
2912                         }
2913                 }
2914
2915                 *masked |= mask2;
2916         }
2917
2918         if (AR_SREV_9100(ah))
2919                 return true;
2920
2921         if (sync_cause) {
2922                 fatal_int =
2923                         (sync_cause &
2924                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2925                         ? true : false;
2926
2927                 if (fatal_int) {
2928                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2929                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2930                                         "%s: received PCI FATAL interrupt\n",
2931                                         __func__);
2932                         }
2933                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2934                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2935                                         "%s: received PCI PERR interrupt\n",
2936                                         __func__);
2937                         }
2938                 }
2939                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2940                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2941                                 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
2942                                 __func__);
2943                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2944                         REG_WRITE(ah, AR_RC, 0);
2945                         *masked |= ATH9K_INT_FATAL;
2946                 }
2947                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2948                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2949                                 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
2950                                 __func__);
2951                 }
2952
2953                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2954                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2955         }
2956
2957         return true;
2958 }
2959
2960 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2961 {
2962         return AH5416(ah)->ah_maskReg;
2963 }
2964
2965 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2966 {
2967         struct ath_hal_5416 *ahp = AH5416(ah);
2968         u32 omask = ahp->ah_maskReg;
2969         u32 mask, mask2;
2970         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2971
2972         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
2973                  omask, ints);
2974
2975         if (omask & ATH9K_INT_GLOBAL) {
2976                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
2977                          __func__);
2978                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2979                 (void) REG_READ(ah, AR_IER);
2980                 if (!AR_SREV_9100(ah)) {
2981                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2982                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2983
2984                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2985                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2986                 }
2987         }
2988
2989         mask = ints & ATH9K_INT_COMMON;
2990         mask2 = 0;
2991
2992         if (ints & ATH9K_INT_TX) {
2993                 if (ahp->ah_txOkInterruptMask)
2994                         mask |= AR_IMR_TXOK;
2995                 if (ahp->ah_txDescInterruptMask)
2996                         mask |= AR_IMR_TXDESC;
2997                 if (ahp->ah_txErrInterruptMask)
2998                         mask |= AR_IMR_TXERR;
2999                 if (ahp->ah_txEolInterruptMask)
3000                         mask |= AR_IMR_TXEOL;
3001         }
3002         if (ints & ATH9K_INT_RX) {
3003                 mask |= AR_IMR_RXERR;
3004                 if (ahp->ah_intrMitigation)
3005                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3006                 else
3007                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3008                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3009                         mask |= AR_IMR_GENTMR;
3010         }
3011
3012         if (ints & (ATH9K_INT_BMISC)) {
3013                 mask |= AR_IMR_BCNMISC;
3014                 if (ints & ATH9K_INT_TIM)
3015                         mask2 |= AR_IMR_S2_TIM;
3016                 if (ints & ATH9K_INT_DTIM)
3017                         mask2 |= AR_IMR_S2_DTIM;
3018                 if (ints & ATH9K_INT_DTIMSYNC)
3019                         mask2 |= AR_IMR_S2_DTIMSYNC;
3020                 if (ints & ATH9K_INT_CABEND)
3021                         mask2 |= (AR_IMR_S2_CABEND);
3022         }
3023
3024         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3025                 mask |= AR_IMR_BCNMISC;
3026                 if (ints & ATH9K_INT_GTT)
3027                         mask2 |= AR_IMR_S2_GTT;
3028                 if (ints & ATH9K_INT_CST)
3029                         mask2 |= AR_IMR_S2_CST;
3030         }
3031
3032         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
3033                  mask);
3034         REG_WRITE(ah, AR_IMR, mask);
3035         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3036                                            AR_IMR_S2_DTIM |
3037                                            AR_IMR_S2_DTIMSYNC |
3038                                            AR_IMR_S2_CABEND |
3039                                            AR_IMR_S2_CABTO |
3040                                            AR_IMR_S2_TSFOOR |
3041                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3042         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3043         ahp->ah_maskReg = ints;
3044
3045         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3046                 if (ints & ATH9K_INT_TIM_TIMER)
3047                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3048                 else
3049                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3050         }
3051
3052         if (ints & ATH9K_INT_GLOBAL) {
3053                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
3054                          __func__);
3055                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3056                 if (!AR_SREV_9100(ah)) {
3057                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3058                                   AR_INTR_MAC_IRQ);
3059                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3060
3061
3062                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3063                                   AR_INTR_SYNC_DEFAULT);
3064                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3065                                   AR_INTR_SYNC_DEFAULT);
3066                 }
3067                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3068                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3069         }
3070
3071         return omask;
3072 }
3073
3074 /*******************/
3075 /* Beacon Handling */
3076 /*******************/
3077
3078 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3079 {
3080         struct ath_hal_5416 *ahp = AH5416(ah);
3081         int flags = 0;
3082
3083         ahp->ah_beaconInterval = beacon_period;
3084
3085         switch (ah->ah_opmode) {
3086         case ATH9K_M_STA:
3087         case ATH9K_M_MONITOR:
3088                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3089                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3090                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3091                 flags |= AR_TBTT_TIMER_EN;
3092                 break;
3093         case ATH9K_M_IBSS:
3094                 REG_SET_BIT(ah, AR_TXCFG,
3095                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3096                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3097                           TU_TO_USEC(next_beacon +
3098                                      (ahp->ah_atimWindow ? ahp->
3099                                       ah_atimWindow : 1)));
3100                 flags |= AR_NDP_TIMER_EN;
3101         case ATH9K_M_HOSTAP:
3102                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3103                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3104                           TU_TO_USEC(next_beacon -
3105                                      ah->ah_config.
3106                                      dma_beacon_response_time));
3107                 REG_WRITE(ah, AR_NEXT_SWBA,
3108                           TU_TO_USEC(next_beacon -
3109                                      ah->ah_config.
3110                                      sw_beacon_response_time));
3111                 flags |=
3112                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3113                 break;
3114         }
3115
3116         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3117         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3118         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3119         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3120
3121         beacon_period &= ~ATH9K_BEACON_ENA;
3122         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3123                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3124                 ath9k_hw_reset_tsf(ah);
3125         }
3126
3127         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3128 }
3129
3130 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3131                                     const struct ath9k_beacon_state *bs)
3132 {
3133         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3134         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3135
3136         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3137
3138         REG_WRITE(ah, AR_BEACON_PERIOD,
3139                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3140         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3141                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3142
3143         REG_RMW_FIELD(ah, AR_RSSI_THR,
3144                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3145
3146         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3147
3148         if (bs->bs_sleepduration > beaconintval)
3149                 beaconintval = bs->bs_sleepduration;
3150
3151         dtimperiod = bs->bs_dtimperiod;
3152         if (bs->bs_sleepduration > dtimperiod)
3153                 dtimperiod = bs->bs_sleepduration;
3154
3155         if (beaconintval == dtimperiod)
3156                 nextTbtt = bs->bs_nextdtim;
3157         else
3158                 nextTbtt = bs->bs_nexttbtt;
3159
3160         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
3161                  bs->bs_nextdtim);
3162         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
3163                  nextTbtt);
3164         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
3165                  beaconintval);
3166         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
3167                  dtimperiod);
3168
3169         REG_WRITE(ah, AR_NEXT_DTIM,
3170                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3171         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3172
3173         REG_WRITE(ah, AR_SLEEP1,
3174                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3175                   | AR_SLEEP1_ASSUME_DTIM);
3176
3177         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3178                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3179         else
3180                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3181
3182         REG_WRITE(ah, AR_SLEEP2,
3183                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3184
3185         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3186         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3187
3188         REG_SET_BIT(ah, AR_TIMER_MODE,
3189                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3190                     AR_DTIM_TIMER_EN);
3191
3192 }
3193
3194 /*******************/
3195 /* HW Capabilities */
3196 /*******************/
3197
3198 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3199 {
3200         struct ath_hal_5416 *ahp = AH5416(ah);
3201         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3202         u16 capField = 0, eeval;
3203
3204         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3205
3206         ah->ah_currentRD = eeval;
3207
3208         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3209         ah->ah_currentRDExt = eeval;
3210
3211         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3212
3213         if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3214             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3215                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3216                         ah->ah_currentRD += 5;
3217                 else if (ah->ah_currentRD == 0x41)
3218                         ah->ah_currentRD = 0x43;
3219                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3220                         "%s: regdomain mapped to 0x%x\n", __func__,
3221                         ah->ah_currentRD);
3222         }
3223
3224         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3225         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3226
3227         if (eeval & AR5416_OPFLAGS_11A) {
3228                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3229                 if (ah->ah_config.ht_enable) {
3230                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3231                                 set_bit(ATH9K_MODE_11NA_HT20,
3232                                         pCap->wireless_modes);
3233                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3234                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3235                                         pCap->wireless_modes);
3236                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3237                                         pCap->wireless_modes);
3238                         }
3239                 }
3240         }
3241
3242         if (eeval & AR5416_OPFLAGS_11G) {
3243                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3244                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3245                 if (ah->ah_config.ht_enable) {
3246                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3247                                 set_bit(ATH9K_MODE_11NG_HT20,
3248                                         pCap->wireless_modes);
3249                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3250                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3251                                         pCap->wireless_modes);
3252                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3253                                         pCap->wireless_modes);
3254                         }
3255                 }
3256         }
3257
3258         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3259         if ((ah->ah_isPciExpress)
3260             || (eeval & AR5416_OPFLAGS_11A)) {
3261                 pCap->rx_chainmask =
3262                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3263         } else {
3264                 pCap->rx_chainmask =
3265                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3266         }
3267
3268         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3269                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3270
3271         pCap->low_2ghz_chan = 2312;
3272         pCap->high_2ghz_chan = 2732;
3273
3274         pCap->low_5ghz_chan = 4920;
3275         pCap->high_5ghz_chan = 6100;
3276
3277         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3278         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3279         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3280
3281         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3282         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3283         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3284
3285         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3286
3287         if (ah->ah_config.ht_enable)
3288                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3289         else
3290                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3291
3292         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3293         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3294         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3295         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3296
3297         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3298                 pCap->total_queues =
3299                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3300         else
3301                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3302
3303         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3304                 pCap->keycache_size =
3305                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3306         else
3307                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3308
3309         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3310         pCap->num_mr_retries = 4;
3311         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3312
3313         if (AR_SREV_9280_10_OR_LATER(ah))
3314                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3315         else
3316                 pCap->num_gpio_pins = AR_NUM_GPIO;
3317
3318         if (AR_SREV_9280_10_OR_LATER(ah)) {
3319                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3320                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3321         } else {
3322                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3323                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3324         }
3325
3326         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3327                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3328                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3329         } else {
3330                 pCap->rts_aggr_limit = (8 * 1024);
3331         }
3332
3333         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3334
3335 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3336         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3337         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3338                 ah->ah_rfkill_gpio =
3339                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3340                 ah->ah_rfkill_polarity =
3341                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3342
3343                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3344         }
3345 #endif
3346
3347         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3348             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3349             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3350             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3351             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3352                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3353         else
3354                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3355
3356         if (AR_SREV_9280(ah))
3357                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3358         else
3359                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3360
3361         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3362                 pCap->reg_cap =
3363                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3364                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3365                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3366                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3367         } else {
3368                 pCap->reg_cap =
3369                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3370                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3371         }
3372
3373         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3374
3375         pCap->num_antcfg_5ghz =
3376                 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3377         pCap->num_antcfg_2ghz =
3378                 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
3379
3380         return true;
3381 }
3382
3383 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3384                             u32 capability, u32 *result)
3385 {
3386         struct ath_hal_5416 *ahp = AH5416(ah);
3387         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3388
3389         switch (type) {
3390         case ATH9K_CAP_CIPHER:
3391                 switch (capability) {
3392                 case ATH9K_CIPHER_AES_CCM:
3393                 case ATH9K_CIPHER_AES_OCB:
3394                 case ATH9K_CIPHER_TKIP:
3395                 case ATH9K_CIPHER_WEP:
3396                 case ATH9K_CIPHER_MIC:
3397                 case ATH9K_CIPHER_CLR:
3398                         return true;
3399                 default:
3400                         return false;
3401                 }
3402         case ATH9K_CAP_TKIP_MIC:
3403                 switch (capability) {
3404                 case 0:
3405                         return true;
3406                 case 1:
3407                         return (ahp->ah_staId1Defaults &
3408                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3409                         false;
3410                 }
3411         case ATH9K_CAP_TKIP_SPLIT:
3412                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3413                         false : true;
3414         case ATH9K_CAP_WME_TKIPMIC:
3415                 return 0;
3416         case ATH9K_CAP_PHYCOUNTERS:
3417                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3418         case ATH9K_CAP_DIVERSITY:
3419                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3420                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3421                         true : false;
3422         case ATH9K_CAP_PHYDIAG:
3423                 return true;
3424         case ATH9K_CAP_MCAST_KEYSRCH:
3425                 switch (capability) {
3426                 case 0:
3427                         return true;
3428                 case 1:
3429                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3430                                 return false;
3431                         } else {
3432                                 return (ahp->ah_staId1Defaults &
3433                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3434                                         false;
3435                         }
3436                 }
3437                 return false;
3438         case ATH9K_CAP_TSF_ADJUST:
3439                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3440                         true : false;
3441         case ATH9K_CAP_RFSILENT:
3442                 if (capability == 3)
3443                         return false;
3444         case ATH9K_CAP_ANT_CFG_2GHZ:
3445                 *result = pCap->num_antcfg_2ghz;
3446                 return true;
3447         case ATH9K_CAP_ANT_CFG_5GHZ:
3448                 *result = pCap->num_antcfg_5ghz;
3449                 return true;
3450         case ATH9K_CAP_TXPOW:
3451                 switch (capability) {
3452                 case 0:
3453                         return 0;
3454                 case 1:
3455                         *result = ah->ah_powerLimit;
3456                         return 0;
3457                 case 2:
3458                         *result = ah->ah_maxPowerLevel;
3459                         return 0;
3460                 case 3:
3461                         *result = ah->ah_tpScale;
3462                         return 0;
3463                 }
3464                 return false;
3465         default:
3466                 return false;
3467         }
3468 }
3469
3470 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3471                             u32 capability, u32 setting, int *status)
3472 {
3473         struct ath_hal_5416 *ahp = AH5416(ah);
3474         u32 v;
3475
3476         switch (type) {
3477         case ATH9K_CAP_TKIP_MIC:
3478                 if (setting)
3479                         ahp->ah_staId1Defaults |=
3480                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3481                 else
3482                         ahp->ah_staId1Defaults &=
3483                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3484                 return true;
3485         case ATH9K_CAP_DIVERSITY:
3486                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3487                 if (setting)
3488                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3489                 else
3490                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3491                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3492                 return true;
3493         case ATH9K_CAP_MCAST_KEYSRCH:
3494                 if (setting)
3495                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3496                 else
3497                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3498                 return true;
3499         case ATH9K_CAP_TSF_ADJUST:
3500                 if (setting)
3501                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3502                 else
3503                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3504                 return true;
3505         default:
3506                 return false;
3507         }
3508 }
3509
3510 /****************************/
3511 /* GPIO / RFKILL / Antennae */
3512 /****************************/
3513
3514 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3515                                          u32 gpio, u32 type)
3516 {
3517         int addr;
3518         u32 gpio_shift, tmp;
3519
3520         if (gpio > 11)
3521                 addr = AR_GPIO_OUTPUT_MUX3;
3522         else if (gpio > 5)
3523                 addr = AR_GPIO_OUTPUT_MUX2;
3524         else
3525                 addr = AR_GPIO_OUTPUT_MUX1;
3526
3527         gpio_shift = (gpio % 6) * 5;
3528
3529         if (AR_SREV_9280_20_OR_LATER(ah)
3530             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3531                 REG_RMW(ah, addr, (type << gpio_shift),
3532                         (0x1f << gpio_shift));
3533         } else {
3534                 tmp = REG_READ(ah, addr);
3535                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3536                 tmp &= ~(0x1f << gpio_shift);
3537                 tmp |= (type << gpio_shift);
3538                 REG_WRITE(ah, addr, tmp);
3539         }
3540 }
3541
3542 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3543 {
3544         u32 gpio_shift;
3545
3546         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3547
3548         gpio_shift = gpio << 1;
3549
3550         REG_RMW(ah,
3551                 AR_GPIO_OE_OUT,
3552                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3553                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3554 }
3555
3556 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3557 {
3558         if (gpio >= ah->ah_caps.num_gpio_pins)
3559                 return 0xffffffff;
3560
3561         if (AR_SREV_9280_10_OR_LATER(ah)) {
3562                 return (MS
3563                         (REG_READ(ah, AR_GPIO_IN_OUT),
3564                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3565         } else {
3566                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3567                         AR_GPIO_BIT(gpio)) != 0;
3568         }
3569 }
3570
3571 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3572                          u32 ah_signal_type)
3573 {
3574         u32 gpio_shift;
3575
3576         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3577
3578         gpio_shift = 2 * gpio;
3579
3580         REG_RMW(ah,
3581                 AR_GPIO_OE_OUT,
3582                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3583                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3584 }
3585
3586 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3587 {
3588         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3589                 AR_GPIO_BIT(gpio));
3590 }
3591
3592 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3593 void ath9k_enable_rfkill(struct ath_hal *ah)
3594 {
3595         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3596                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3597
3598         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3599                     AR_GPIO_INPUT_MUX2_RFSILENT);
3600
3601         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3602         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3603 }
3604 #endif
3605
3606 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3607 {
3608         struct ath9k_channel *chan = ah->ah_curchan;
3609         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3610         u16 ant_config;
3611         u32 halNumAntConfig;
3612
3613         halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3614                 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3615
3616         if (cfg < halNumAntConfig) {
3617                 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3618                                                      cfg, &ant_config)) {
3619                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3620                         return 0;
3621                 }
3622         }
3623
3624         return -EINVAL;
3625 }
3626
3627 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3628 {
3629         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3630 }
3631
3632 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3633 {
3634         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3635 }
3636
3637 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3638                                enum ath9k_ant_setting settings,
3639                                struct ath9k_channel *chan,
3640                                u8 *tx_chainmask,
3641                                u8 *rx_chainmask,
3642                                u8 *antenna_cfgd)
3643 {
3644         struct ath_hal_5416 *ahp = AH5416(ah);
3645         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3646
3647         if (AR_SREV_9280(ah)) {
3648                 if (!tx_chainmask_cfg) {
3649
3650                         tx_chainmask_cfg = *tx_chainmask;
3651                         rx_chainmask_cfg = *rx_chainmask;
3652                 }
3653
3654                 switch (settings) {
3655                 case ATH9K_ANT_FIXED_A:
3656                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3657                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3658                         *antenna_cfgd = true;
3659                         break;
3660                 case ATH9K_ANT_FIXED_B:
3661                         if (ah->ah_caps.tx_chainmask >
3662                             ATH9K_ANTENNA1_CHAINMASK) {
3663                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3664                         }
3665                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3666                         *antenna_cfgd = true;
3667                         break;
3668                 case ATH9K_ANT_VARIABLE:
3669                         *tx_chainmask = tx_chainmask_cfg;
3670                         *rx_chainmask = rx_chainmask_cfg;
3671                         *antenna_cfgd = true;
3672                         break;
3673                 default:
3674                         break;
3675                 }
3676         } else {
3677                 ahp->ah_diversityControl = settings;
3678         }
3679
3680         return true;
3681 }
3682
3683 /*********************/
3684 /* General Operation */
3685 /*********************/
3686
3687 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3688 {
3689         u32 bits = REG_READ(ah, AR_RX_FILTER);
3690         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3691
3692         if (phybits & AR_PHY_ERR_RADAR)
3693                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3694         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3695                 bits |= ATH9K_RX_FILTER_PHYERR;
3696
3697         return bits;
3698 }
3699
3700 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3701 {
3702         u32 phybits;
3703
3704         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3705         phybits = 0;
3706         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3707                 phybits |= AR_PHY_ERR_RADAR;
3708         if (bits & ATH9K_RX_FILTER_PHYERR)
3709                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3710         REG_WRITE(ah, AR_PHY_ERR, phybits);
3711
3712         if (phybits)
3713                 REG_WRITE(ah, AR_RXCFG,
3714                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3715         else
3716                 REG_WRITE(ah, AR_RXCFG,
3717                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3718 }
3719
3720 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3721 {
3722         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3723 }
3724
3725 bool ath9k_hw_disable(struct ath_hal *ah)
3726 {
3727         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3728                 return false;
3729
3730         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3731 }
3732
3733 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3734 {
3735         struct ath9k_channel *chan = ah->ah_curchan;
3736
3737         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3738
3739         if (ath9k_hw_set_txpower(ah, chan,
3740                                  ath9k_regd_get_ctl(ah, chan),
3741                                  ath9k_regd_get_antenna_allowed(ah, chan),
3742                                  chan->maxRegTxPower * 2,
3743                                  min((u32) MAX_RATE_POWER,
3744                                      (u32) ah->ah_powerLimit)) != 0)
3745                 return false;
3746
3747         return true;
3748 }
3749
3750 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3751 {
3752         struct ath_hal_5416 *ahp = AH5416(ah);
3753
3754         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3755 }
3756
3757 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3758 {
3759         struct ath_hal_5416 *ahp = AH5416(ah);
3760
3761         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3762
3763         return true;
3764 }
3765
3766 void ath9k_hw_setopmode(struct ath_hal *ah)
3767 {
3768         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3769 }
3770
3771 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3772 {
3773         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3774         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3775 }
3776
3777 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3778 {
3779         struct ath_hal_5416 *ahp = AH5416(ah);
3780
3781         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3782 }
3783
3784 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3785 {
3786         struct ath_hal_5416 *ahp = AH5416(ah);
3787
3788         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3789
3790         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3791         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3792
3793         return true;
3794 }
3795
3796 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3797 {
3798         struct ath_hal_5416 *ahp = AH5416(ah);
3799
3800         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3801         ahp->ah_assocId = assocId;
3802
3803         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3804         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3805                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3806 }
3807
3808 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3809 {
3810         u64 tsf;
3811
3812         tsf = REG_READ(ah, AR_TSF_U32);
3813         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3814
3815         return tsf;
3816 }
3817
3818 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3819 {
3820         int count;
3821
3822         count = 0;
3823         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3824                 count++;
3825                 if (count > 10) {
3826                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3827                                 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
3828                                 __func__);
3829                         break;
3830                 }
3831                 udelay(10);
3832         }
3833         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3834 }
3835
3836 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3837 {
3838         struct ath_hal_5416 *ahp = AH5416(ah);
3839
3840         if (setting)
3841                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3842         else
3843                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3844
3845         return true;
3846 }
3847
3848 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3849 {
3850         struct ath_hal_5416 *ahp = AH5416(ah);
3851
3852         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3853                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
3854                          __func__, us);
3855                 ahp->ah_slottime = (u32) -1;
3856                 return false;
3857         } else {
3858                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3859                 ahp->ah_slottime = us;
3860                 return true;
3861         }
3862 }
3863
3864 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3865 {
3866         u32 macmode;
3867
3868         if (mode == ATH9K_HT_MACMODE_2040 &&
3869             !ah->ah_config.cwm_ignore_extcca)
3870                 macmode = AR_2040_JOINED_RX_CLEAR;
3871         else
3872                 macmode = 0;
3873
3874         REG_WRITE(ah, AR_2040_MODE, macmode);
3875 }