2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info = "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
120 sc->hw_rate_table[ATH9K_MODE_11G];
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
134 sc->hw_rate_table[ATH9K_MODE_11A];
142 static void ath_update_txpow(struct ath_softc *sc)
144 struct ath_hw *ah = sc->sc_ah;
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
155 static u8 parse_mpdudensity(u8 mpdudensity)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
208 if (rate_table == NULL)
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
217 maxrates = rate_table->rate_cnt;
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
242 struct ath_hw *ah = sc->sc_ah;
243 bool fastcc = true, stopped;
244 struct ieee80211_channel *channel = hw->conf.channel;
247 if (sc->sc_flags & SC_OP_INVALID)
253 * This is only performed if the channel settings have
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
261 ath9k_hw_set_interrupts(ah, 0);
262 ath_drain_all_txq(sc, false);
263 stopped = ath_stoprecv(sc);
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc->sc_ah->curchan->channel,
275 channel->center_freq, sc->tx_chan_width);
277 spin_lock_bh(&sc->sc_resetlock);
279 r = ath9k_hw_reset(ah, hchan, fastcc);
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
288 spin_unlock_bh(&sc->sc_resetlock);
290 sc->sc_flags &= ~SC_OP_FULL_RESET;
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
300 ath9k_hw_set_interrupts(ah, sc->imask);
301 ath9k_ps_restore(sc);
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
312 static void ath_ani_calibrate(unsigned long data)
314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
320 u32 cal_interval, short_cal_interval;
322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
329 if (sc->sc_flags & SC_OP_SCANNING)
332 /* Long calibration runs independently of short calibration. */
333 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
335 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
336 sc->ani.longcal_timer = timestamp;
339 /* Short calibration applies only while caldone is false */
340 if (!sc->ani.caldone) {
341 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
344 sc->ani.shortcal_timer = timestamp;
345 sc->ani.resetcal_timer = timestamp;
348 if ((timestamp - sc->ani.resetcal_timer) >=
349 ATH_RESTART_CALINTERVAL) {
350 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 sc->ani.resetcal_timer = timestamp;
356 /* Verify whether we must check ANI */
357 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
359 sc->ani.checkani_timer = timestamp;
362 /* Skip all processing if there's nothing to do. */
363 if (longcal || shortcal || aniflag) {
364 /* Call ANI routine if necessary */
366 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
372 if (ath9k_hw_calibrate(ah, ah->curchan,
373 sc->rx_chainmask, longcal,
376 sc->ani.noise_floor =
377 ath9k_hw_getchan_noise(ah,
380 DPRINTF(sc, ATH_DBG_ANI,
381 "calibrate chan %u/%x nf: %d\n",
382 ah->curchan->channel,
383 ah->curchan->channelFlags,
384 sc->ani.noise_floor);
386 DPRINTF(sc, ATH_DBG_ANY,
387 "calibrate chan %u/%x failed\n",
388 ah->curchan->channel,
389 ah->curchan->channelFlags);
391 sc->ani.caldone = iscaldone;
397 * Set timer interval based on previous results.
398 * The interval must be the shortest necessary to satisfy ANI,
399 * short calibration and long calibration.
401 cal_interval = ATH_LONG_CALINTERVAL;
402 if (sc->sc_ah->config.enable_ani)
403 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
404 if (!sc->ani.caldone)
405 cal_interval = min(cal_interval, (u32)short_cal_interval);
407 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
416 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
428 sc->tx_chainmask, sc->rx_chainmask);
431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
435 an = (struct ath_node *)sta->drv_priv;
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
453 static void ath9k_tasklet(unsigned long data)
455 struct ath_softc *sc = (struct ath_softc *)data;
456 u32 status = sc->intrstatus;
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
466 spin_lock_bh(&sc->rx.rxflushlock);
467 ath_rx_tasklet(sc, 0);
468 spin_unlock_bh(&sc->rx.rxflushlock);
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
475 /* re-enable hardware interrupt */
476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
479 irqreturn_t ath_isr(int irq, void *dev)
481 struct ath_softc *sc = dev;
482 struct ath_hw *ah = sc->sc_ah;
483 enum ath9k_int status;
487 if (sc->sc_flags & SC_OP_INVALID) {
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
507 status &= sc->imask; /* discard unasked-for bits */
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
516 sc->intrstatus = status;
519 if (status & ATH9K_INT_FATAL) {
520 /* need a chip reset */
522 } else if (status & ATH9K_INT_RXORN) {
523 /* need a chip reset */
526 if (status & ATH9K_INT_SWBA) {
527 /* schedule a tasklet for beacon handling */
528 tasklet_schedule(&sc->bcon_tasklet);
530 if (status & ATH9K_INT_RXEOL) {
532 * NB: the hardware should re-read the link when
533 * RXE bit is written, but it doesn't work
534 * at least on older hardware revs.
539 if (status & ATH9K_INT_TXURN)
540 /* bump tx trigger level */
541 ath9k_hw_updatetxtriglevel(ah, true);
542 /* XXX: optimize this */
543 if (status & ATH9K_INT_RX)
545 if (status & ATH9K_INT_TX)
547 if (status & ATH9K_INT_BMISS)
549 /* carrier sense timeout */
550 if (status & ATH9K_INT_CST)
552 if (status & ATH9K_INT_MIB) {
554 * Disable interrupts until we service the MIB
555 * interrupt; otherwise it will continue to
558 ath9k_hw_set_interrupts(ah, 0);
560 * Let the hal handle the event. We assume
561 * it will clear whatever condition caused
564 ath9k_hw_procmibevent(ah, &sc->nodestats);
565 ath9k_hw_set_interrupts(ah, sc->imask);
567 if (status & ATH9K_INT_TIM_TIMER) {
568 if (!(ah->caps.hw_caps &
569 ATH9K_HW_CAP_AUTOSLEEP)) {
570 /* Clear RxAbort bit so that we can
572 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
573 ath9k_hw_setrxabort(ah, 0);
575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
578 if (status & ATH9K_INT_TSFOOR) {
579 /* FIXME: Handle this interrupt for power save */
583 ath9k_ps_restore(sc);
586 ath_debug_stat_interrupt(sc, status);
589 /* turn off every interrupt except SWBA */
590 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
591 tasklet_schedule(&sc->intr_tq);
597 static u32 ath_get_extchanmode(struct ath_softc *sc,
598 struct ieee80211_channel *chan,
599 enum nl80211_channel_type channel_type)
603 switch (chan->band) {
604 case IEEE80211_BAND_2GHZ:
605 switch(channel_type) {
606 case NL80211_CHAN_NO_HT:
607 case NL80211_CHAN_HT20:
608 chanmode = CHANNEL_G_HT20;
610 case NL80211_CHAN_HT40PLUS:
611 chanmode = CHANNEL_G_HT40PLUS;
613 case NL80211_CHAN_HT40MINUS:
614 chanmode = CHANNEL_G_HT40MINUS;
618 case IEEE80211_BAND_5GHZ:
619 switch(channel_type) {
620 case NL80211_CHAN_NO_HT:
621 case NL80211_CHAN_HT20:
622 chanmode = CHANNEL_A_HT20;
624 case NL80211_CHAN_HT40PLUS:
625 chanmode = CHANNEL_A_HT40PLUS;
627 case NL80211_CHAN_HT40MINUS:
628 chanmode = CHANNEL_A_HT40MINUS;
639 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
640 struct ath9k_keyval *hk, const u8 *addr,
646 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
647 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
651 * Group key installation - only two key cache entries are used
652 * regardless of splitmic capability since group key is only
653 * used either for TX or RX.
656 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
657 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
660 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
662 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
665 /* TX and RX keys share the same key cache entry. */
666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
668 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
671 /* Separate key cache entries for TX and RX */
673 /* TX key goes at first index, RX key at +32. */
674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
675 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
676 /* TX MIC entry failed. No need to proceed further */
677 DPRINTF(sc, ATH_DBG_FATAL,
678 "Setting TX MIC Key Failed\n");
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 /* XXX delete tx key on failure? */
684 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
691 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
692 if (test_bit(i, sc->keymap) ||
693 test_bit(i + 64, sc->keymap))
694 continue; /* At least one part of TKIP key allocated */
696 (test_bit(i + 32, sc->keymap) ||
697 test_bit(i + 64 + 32, sc->keymap)))
698 continue; /* At least one part of TKIP key allocated */
700 /* Found a free slot for a TKIP key */
706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
710 /* First, try to find slots that would not be available for TKIP. */
712 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
713 if (!test_bit(i, sc->keymap) &&
714 (test_bit(i + 32, sc->keymap) ||
715 test_bit(i + 64, sc->keymap) ||
716 test_bit(i + 64 + 32, sc->keymap)))
718 if (!test_bit(i + 32, sc->keymap) &&
719 (test_bit(i, sc->keymap) ||
720 test_bit(i + 64, sc->keymap) ||
721 test_bit(i + 64 + 32, sc->keymap)))
723 if (!test_bit(i + 64, sc->keymap) &&
724 (test_bit(i , sc->keymap) ||
725 test_bit(i + 32, sc->keymap) ||
726 test_bit(i + 64 + 32, sc->keymap)))
728 if (!test_bit(i + 64 + 32, sc->keymap) &&
729 (test_bit(i, sc->keymap) ||
730 test_bit(i + 32, sc->keymap) ||
731 test_bit(i + 64, sc->keymap)))
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 test_bit(i + 64, sc->keymap))
739 if (test_bit(i, sc->keymap) &&
740 !test_bit(i + 64, sc->keymap))
745 /* No partially used TKIP slots, pick any available slot */
746 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
747 /* Do not allow slots that could be needed for TKIP group keys
748 * to be used. This limitation could be removed if we know that
749 * TKIP will not be used. */
750 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
755 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
759 if (!test_bit(i, sc->keymap))
760 return i; /* Found a free slot for a key */
763 /* No free slot found */
767 static int ath_key_config(struct ath_softc *sc,
768 struct ieee80211_vif *vif,
769 struct ieee80211_sta *sta,
770 struct ieee80211_key_conf *key)
772 struct ath9k_keyval hk;
773 const u8 *mac = NULL;
777 memset(&hk, 0, sizeof(hk));
781 hk.kv_type = ATH9K_CIPHER_WEP;
784 hk.kv_type = ATH9K_CIPHER_TKIP;
787 hk.kv_type = ATH9K_CIPHER_AES_CCM;
793 hk.kv_len = key->keylen;
794 memcpy(hk.kv_val, key->key, key->keylen);
796 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
797 /* For now, use the default keys for broadcast keys. This may
798 * need to change with virtual interfaces. */
800 } else if (key->keyidx) {
805 if (vif->type != NL80211_IFTYPE_AP) {
806 /* Only keyidx 0 should be used with unicast key, but
807 * allow this for client mode for now. */
816 if (key->alg == ALG_TKIP)
817 idx = ath_reserve_key_cache_slot_tkip(sc);
819 idx = ath_reserve_key_cache_slot(sc);
821 return -ENOSPC; /* no free key cache entries */
824 if (key->alg == ALG_TKIP)
825 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
826 vif->type == NL80211_IFTYPE_AP);
828 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
833 set_bit(idx, sc->keymap);
834 if (key->alg == ALG_TKIP) {
835 set_bit(idx + 64, sc->keymap);
837 set_bit(idx + 32, sc->keymap);
838 set_bit(idx + 64 + 32, sc->keymap);
845 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
847 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
848 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 clear_bit(key->hw_key_idx, sc->keymap);
852 if (key->alg != ALG_TKIP)
855 clear_bit(key->hw_key_idx + 64, sc->keymap);
857 clear_bit(key->hw_key_idx + 32, sc->keymap);
858 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
862 static void setup_ht_cap(struct ath_softc *sc,
863 struct ieee80211_sta_ht_cap *ht_info)
865 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
866 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
868 ht_info->ht_supported = true;
869 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
870 IEEE80211_HT_CAP_SM_PS |
871 IEEE80211_HT_CAP_SGI_40 |
872 IEEE80211_HT_CAP_DSSSCCK40;
874 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
875 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
877 /* set up supported mcs set */
878 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
880 switch(sc->rx_chainmask) {
882 ht_info->mcs.rx_mask[0] = 0xff;
888 ht_info->mcs.rx_mask[0] = 0xff;
889 ht_info->mcs.rx_mask[1] = 0xff;
893 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
896 static void ath9k_bss_assoc_info(struct ath_softc *sc,
897 struct ieee80211_vif *vif,
898 struct ieee80211_bss_conf *bss_conf)
900 struct ath_vif *avp = (void *)vif->drv_priv;
902 if (bss_conf->assoc) {
903 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
904 bss_conf->aid, sc->curbssid);
906 /* New association, store aid */
907 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
908 sc->curaid = bss_conf->aid;
909 ath9k_hw_write_associd(sc);
912 /* Configure the beacon */
913 ath_beacon_config(sc, vif);
915 /* Reset rssi stats */
916 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
917 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
918 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
922 mod_timer(&sc->ani.timer,
923 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
930 /********************************/
932 /********************************/
934 static void ath_led_blink_work(struct work_struct *work)
936 struct ath_softc *sc = container_of(work, struct ath_softc,
937 ath_led_blink_work.work);
939 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
943 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
944 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
947 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
949 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
950 (sc->sc_flags & SC_OP_LED_ON) ?
951 msecs_to_jiffies(sc->led_off_duration) :
952 msecs_to_jiffies(sc->led_on_duration));
954 sc->led_on_duration = sc->led_on_cnt ?
955 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
956 ATH_LED_ON_DURATION_IDLE;
957 sc->led_off_duration = sc->led_off_cnt ?
958 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
959 ATH_LED_OFF_DURATION_IDLE;
960 sc->led_on_cnt = sc->led_off_cnt = 0;
961 if (sc->sc_flags & SC_OP_LED_ON)
962 sc->sc_flags &= ~SC_OP_LED_ON;
964 sc->sc_flags |= SC_OP_LED_ON;
967 static void ath_led_brightness(struct led_classdev *led_cdev,
968 enum led_brightness brightness)
970 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
971 struct ath_softc *sc = led->sc;
973 switch (brightness) {
975 if (led->led_type == ATH_LED_ASSOC ||
976 led->led_type == ATH_LED_RADIO) {
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
978 (led->led_type == ATH_LED_RADIO));
979 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
980 if (led->led_type == ATH_LED_RADIO)
981 sc->sc_flags &= ~SC_OP_LED_ON;
987 if (led->led_type == ATH_LED_ASSOC) {
988 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
989 queue_delayed_work(sc->hw->workqueue,
990 &sc->ath_led_blink_work, 0);
991 } else if (led->led_type == ATH_LED_RADIO) {
992 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
993 sc->sc_flags |= SC_OP_LED_ON;
1003 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1009 led->led_cdev.name = led->name;
1010 led->led_cdev.default_trigger = trigger;
1011 led->led_cdev.brightness_set = ath_led_brightness;
1013 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1015 DPRINTF(sc, ATH_DBG_FATAL,
1016 "Failed to register led:%s", led->name);
1018 led->registered = 1;
1022 static void ath_unregister_led(struct ath_led *led)
1024 if (led->registered) {
1025 led_classdev_unregister(&led->led_cdev);
1026 led->registered = 0;
1030 static void ath_deinit_leds(struct ath_softc *sc)
1032 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1033 ath_unregister_led(&sc->assoc_led);
1034 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1035 ath_unregister_led(&sc->tx_led);
1036 ath_unregister_led(&sc->rx_led);
1037 ath_unregister_led(&sc->radio_led);
1038 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1041 static void ath_init_leds(struct ath_softc *sc)
1046 /* Configure gpio 1 for output */
1047 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1048 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1049 /* LED off, active low */
1050 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1052 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1054 trigger = ieee80211_get_radio_led_name(sc->hw);
1055 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1056 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1057 ret = ath_register_led(sc, &sc->radio_led, trigger);
1058 sc->radio_led.led_type = ATH_LED_RADIO;
1062 trigger = ieee80211_get_assoc_led_name(sc->hw);
1063 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1064 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1065 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1066 sc->assoc_led.led_type = ATH_LED_ASSOC;
1070 trigger = ieee80211_get_tx_led_name(sc->hw);
1071 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1072 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1073 ret = ath_register_led(sc, &sc->tx_led, trigger);
1074 sc->tx_led.led_type = ATH_LED_TX;
1078 trigger = ieee80211_get_rx_led_name(sc->hw);
1079 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1080 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1081 ret = ath_register_led(sc, &sc->rx_led, trigger);
1082 sc->rx_led.led_type = ATH_LED_RX;
1089 ath_deinit_leds(sc);
1092 void ath_radio_enable(struct ath_softc *sc)
1094 struct ath_hw *ah = sc->sc_ah;
1095 struct ieee80211_channel *channel = sc->hw->conf.channel;
1098 ath9k_ps_wakeup(sc);
1099 spin_lock_bh(&sc->sc_resetlock);
1101 r = ath9k_hw_reset(ah, ah->curchan, false);
1104 DPRINTF(sc, ATH_DBG_FATAL,
1105 "Unable to reset channel %u (%uMhz) ",
1106 "reset status %u\n",
1107 channel->center_freq, r);
1109 spin_unlock_bh(&sc->sc_resetlock);
1111 ath_update_txpow(sc);
1112 if (ath_startrecv(sc) != 0) {
1113 DPRINTF(sc, ATH_DBG_FATAL,
1114 "Unable to restart recv logic\n");
1118 if (sc->sc_flags & SC_OP_BEACONS)
1119 ath_beacon_config(sc, NULL); /* restart beacons */
1121 /* Re-Enable interrupts */
1122 ath9k_hw_set_interrupts(ah, sc->imask);
1125 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1126 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129 ieee80211_wake_queues(sc->hw);
1130 ath9k_ps_restore(sc);
1133 void ath_radio_disable(struct ath_softc *sc)
1135 struct ath_hw *ah = sc->sc_ah;
1136 struct ieee80211_channel *channel = sc->hw->conf.channel;
1139 ath9k_ps_wakeup(sc);
1140 ieee80211_stop_queues(sc->hw);
1143 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1144 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146 /* Disable interrupts */
1147 ath9k_hw_set_interrupts(ah, 0);
1149 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1150 ath_stoprecv(sc); /* turn off frame recv */
1151 ath_flushrecv(sc); /* flush recv queue */
1153 spin_lock_bh(&sc->sc_resetlock);
1154 r = ath9k_hw_reset(ah, ah->curchan, false);
1156 DPRINTF(sc, ATH_DBG_FATAL,
1157 "Unable to reset channel %u (%uMhz) "
1158 "reset status %u\n",
1159 channel->center_freq, r);
1161 spin_unlock_bh(&sc->sc_resetlock);
1163 ath9k_hw_phy_disable(ah);
1164 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1165 ath9k_ps_restore(sc);
1168 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1170 /*******************/
1172 /*******************/
1174 static bool ath_is_rfkill_set(struct ath_softc *sc)
1176 struct ath_hw *ah = sc->sc_ah;
1178 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1179 ah->rfkill_polarity;
1182 /* h/w rfkill poll function */
1183 static void ath_rfkill_poll(struct work_struct *work)
1185 struct ath_softc *sc = container_of(work, struct ath_softc,
1186 rf_kill.rfkill_poll.work);
1189 if (sc->sc_flags & SC_OP_INVALID)
1192 radio_on = !ath_is_rfkill_set(sc);
1195 * enable/disable radio only when there is a
1196 * state change in RF switch
1198 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1199 enum rfkill_state state;
1201 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1202 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1203 : RFKILL_STATE_HARD_BLOCKED;
1204 } else if (radio_on) {
1205 ath_radio_enable(sc);
1206 state = RFKILL_STATE_UNBLOCKED;
1208 ath_radio_disable(sc);
1209 state = RFKILL_STATE_HARD_BLOCKED;
1212 if (state == RFKILL_STATE_HARD_BLOCKED)
1213 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1215 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1217 rfkill_force_state(sc->rf_kill.rfkill, state);
1220 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1221 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1224 /* s/w rfkill handler */
1225 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1227 struct ath_softc *sc = data;
1230 case RFKILL_STATE_SOFT_BLOCKED:
1231 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1232 SC_OP_RFKILL_SW_BLOCKED)))
1233 ath_radio_disable(sc);
1234 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1236 case RFKILL_STATE_UNBLOCKED:
1237 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1238 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1239 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1240 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1241 "radio as it is disabled by h/w\n");
1244 ath_radio_enable(sc);
1252 /* Init s/w rfkill */
1253 static int ath_init_sw_rfkill(struct ath_softc *sc)
1255 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1257 if (!sc->rf_kill.rfkill) {
1258 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1262 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1263 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1264 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1265 sc->rf_kill.rfkill->data = sc;
1266 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1267 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1272 /* Deinitialize rfkill */
1273 static void ath_deinit_rfkill(struct ath_softc *sc)
1275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1276 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1278 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1279 rfkill_unregister(sc->rf_kill.rfkill);
1280 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1281 sc->rf_kill.rfkill = NULL;
1285 static int ath_start_rfkill_poll(struct ath_softc *sc)
1287 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1288 queue_delayed_work(sc->hw->workqueue,
1289 &sc->rf_kill.rfkill_poll, 0);
1291 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1292 if (rfkill_register(sc->rf_kill.rfkill)) {
1293 DPRINTF(sc, ATH_DBG_FATAL,
1294 "Unable to register rfkill\n");
1295 rfkill_free(sc->rf_kill.rfkill);
1297 /* Deinitialize the device */
1301 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1307 #endif /* CONFIG_RFKILL */
1309 void ath_cleanup(struct ath_softc *sc)
1312 free_irq(sc->irq, sc);
1313 ath_bus_cleanup(sc);
1314 kfree(sc->sec_wiphy);
1315 ieee80211_free_hw(sc->hw);
1318 void ath_detach(struct ath_softc *sc)
1320 struct ieee80211_hw *hw = sc->hw;
1323 ath9k_ps_wakeup(sc);
1325 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1327 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1328 ath_deinit_rfkill(sc);
1330 ath_deinit_leds(sc);
1331 cancel_work_sync(&sc->chan_work);
1332 cancel_delayed_work_sync(&sc->wiphy_work);
1334 for (i = 0; i < sc->num_sec_wiphy; i++) {
1335 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1338 sc->sec_wiphy[i] = NULL;
1339 ieee80211_unregister_hw(aphy->hw);
1340 ieee80211_free_hw(aphy->hw);
1342 ieee80211_unregister_hw(hw);
1346 tasklet_kill(&sc->intr_tq);
1347 tasklet_kill(&sc->bcon_tasklet);
1349 if (!(sc->sc_flags & SC_OP_INVALID))
1350 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1352 /* cleanup tx queues */
1353 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1354 if (ATH_TXQ_SETUP(sc, i))
1355 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1357 ath9k_hw_detach(sc->sc_ah);
1358 ath9k_exit_debug(sc);
1359 ath9k_ps_restore(sc);
1362 static int ath_init(u16 devid, struct ath_softc *sc)
1364 struct ath_hw *ah = NULL;
1369 /* XXX: hardware will not be ready until ath_open() being called */
1370 sc->sc_flags |= SC_OP_INVALID;
1372 if (ath9k_init_debug(sc) < 0)
1373 printk(KERN_ERR "Unable to create debugfs files\n");
1375 spin_lock_init(&sc->wiphy_lock);
1376 spin_lock_init(&sc->sc_resetlock);
1377 spin_lock_init(&sc->sc_serial_rw);
1378 mutex_init(&sc->mutex);
1379 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1380 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1384 * Cache line size is used to size and align various
1385 * structures used to communicate with the hardware.
1387 ath_read_cachesize(sc, &csz);
1388 /* XXX assert csz is non-zero */
1389 sc->cachelsz = csz << 2; /* convert to bytes */
1391 ah = ath9k_hw_attach(devid, sc, &status);
1393 DPRINTF(sc, ATH_DBG_FATAL,
1394 "Unable to attach hardware; HAL status %d\n", status);
1400 /* Get the hardware key cache size. */
1401 sc->keymax = ah->caps.keycache_size;
1402 if (sc->keymax > ATH_KEYMAX) {
1403 DPRINTF(sc, ATH_DBG_ANY,
1404 "Warning, using only %u entries in %u key cache\n",
1405 ATH_KEYMAX, sc->keymax);
1406 sc->keymax = ATH_KEYMAX;
1410 * Reset the key cache since some parts do not
1411 * reset the contents on initial power up.
1413 for (i = 0; i < sc->keymax; i++)
1414 ath9k_hw_keyreset(ah, (u16) i);
1416 if (ath9k_regd_init(sc->sc_ah))
1419 /* default to MONITOR mode */
1420 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1422 /* Setup rate tables */
1424 ath_rate_attach(sc);
1425 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1426 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1429 * Allocate hardware transmit queues: one queue for
1430 * beacon frames and one data queue for each QoS
1431 * priority. Note that the hal handles reseting
1432 * these queues at the needed time.
1434 sc->beacon.beaconq = ath_beaconq_setup(ah);
1435 if (sc->beacon.beaconq == -1) {
1436 DPRINTF(sc, ATH_DBG_FATAL,
1437 "Unable to setup a beacon xmit queue\n");
1441 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1442 if (sc->beacon.cabq == NULL) {
1443 DPRINTF(sc, ATH_DBG_FATAL,
1444 "Unable to setup CAB xmit queue\n");
1449 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1450 ath_cabq_update(sc);
1452 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1453 sc->tx.hwq_map[i] = -1;
1455 /* Setup data queues */
1456 /* NB: ensure BK queue is the lowest priority h/w queue */
1457 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1458 DPRINTF(sc, ATH_DBG_FATAL,
1459 "Unable to setup xmit queue for BK traffic\n");
1464 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1465 DPRINTF(sc, ATH_DBG_FATAL,
1466 "Unable to setup xmit queue for BE traffic\n");
1470 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1471 DPRINTF(sc, ATH_DBG_FATAL,
1472 "Unable to setup xmit queue for VI traffic\n");
1476 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1477 DPRINTF(sc, ATH_DBG_FATAL,
1478 "Unable to setup xmit queue for VO traffic\n");
1483 /* Initializes the noise floor to a reasonable default value.
1484 * Later on this will be updated during ANI processing. */
1486 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1487 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1489 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1490 ATH9K_CIPHER_TKIP, NULL)) {
1492 * Whether we should enable h/w TKIP MIC.
1493 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1494 * report WMM capable, so it's always safe to turn on
1495 * TKIP MIC in this case.
1497 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1502 * Check whether the separate key cache entries
1503 * are required to handle both tx+rx MIC keys.
1504 * With split mic keys the number of stations is limited
1505 * to 27 otherwise 59.
1507 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1508 ATH9K_CIPHER_TKIP, NULL)
1509 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1510 ATH9K_CIPHER_MIC, NULL)
1511 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1515 /* turn on mcast key search if possible */
1516 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1517 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1520 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1522 /* 11n Capabilities */
1523 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1524 sc->sc_flags |= SC_OP_TXAGGR;
1525 sc->sc_flags |= SC_OP_RXAGGR;
1528 sc->tx_chainmask = ah->caps.tx_chainmask;
1529 sc->rx_chainmask = ah->caps.rx_chainmask;
1531 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1532 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1534 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1535 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1537 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1539 /* initialize beacon slots */
1540 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1541 sc->beacon.bslot[i] = NULL;
1542 sc->beacon.bslot_aphy[i] = NULL;
1545 /* save MISC configurations */
1546 sc->config.swBeaconProcess = 1;
1548 /* setup channels and rates */
1550 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1551 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1552 sc->rates[IEEE80211_BAND_2GHZ];
1553 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1554 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1555 ARRAY_SIZE(ath9k_2ghz_chantable);
1557 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1558 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1559 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1560 sc->rates[IEEE80211_BAND_5GHZ];
1561 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1562 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1563 ARRAY_SIZE(ath9k_5ghz_chantable);
1566 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1567 ath9k_hw_btcoex_enable(sc->sc_ah);
1571 /* cleanup tx queues */
1572 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1573 if (ATH_TXQ_SETUP(sc, i))
1574 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1577 ath9k_hw_detach(ah);
1578 ath9k_exit_debug(sc);
1583 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1585 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1586 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1587 IEEE80211_HW_SIGNAL_DBM |
1588 IEEE80211_HW_AMPDU_AGGREGATION |
1589 IEEE80211_HW_SUPPORTS_PS |
1590 IEEE80211_HW_PS_NULLFUNC_STACK |
1591 IEEE80211_HW_SPECTRUM_MGMT;
1593 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1594 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1596 hw->wiphy->interface_modes =
1597 BIT(NL80211_IFTYPE_AP) |
1598 BIT(NL80211_IFTYPE_STATION) |
1599 BIT(NL80211_IFTYPE_ADHOC) |
1600 BIT(NL80211_IFTYPE_MESH_POINT);
1602 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1603 hw->wiphy->strict_regulatory = true;
1607 hw->channel_change_time = 5000;
1608 hw->max_listen_interval = 10;
1609 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1610 hw->sta_data_size = sizeof(struct ath_node);
1611 hw->vif_data_size = sizeof(struct ath_vif);
1613 hw->rate_control_algorithm = "ath9k_rate_control";
1615 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1616 &sc->sbands[IEEE80211_BAND_2GHZ];
1617 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1618 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1619 &sc->sbands[IEEE80211_BAND_5GHZ];
1622 int ath_attach(u16 devid, struct ath_softc *sc)
1624 struct ieee80211_hw *hw = sc->hw;
1625 const struct ieee80211_regdomain *regd;
1628 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1630 error = ath_init(devid, sc);
1634 /* get mac address from hardware and set in mac80211 */
1636 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1638 ath_set_hw_capab(sc, hw);
1640 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1641 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1642 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1643 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1646 /* initialize tx/rx engine */
1647 error = ath_tx_init(sc, ATH_TXBUF);
1651 error = ath_rx_init(sc, ATH_RXBUF);
1655 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1656 /* Initialze h/w Rfkill */
1657 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1658 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1660 /* Initialize s/w rfkill */
1661 error = ath_init_sw_rfkill(sc);
1666 if (ath9k_is_world_regd(sc->sc_ah)) {
1667 /* Anything applied here (prior to wiphy registration) gets
1668 * saved on the wiphy orig_* parameters */
1669 regd = ath9k_world_regdomain(sc->sc_ah);
1670 hw->wiphy->custom_regulatory = true;
1671 hw->wiphy->strict_regulatory = false;
1673 /* This gets applied in the case of the absense of CRDA,
1674 * it's our own custom world regulatory domain, similar to
1675 * cfg80211's but we enable passive scanning */
1676 regd = ath9k_default_world_regdomain();
1678 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1679 ath9k_reg_apply_radar_flags(hw->wiphy);
1680 ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1682 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1683 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1684 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1686 error = ieee80211_register_hw(hw);
1688 if (!ath9k_is_world_regd(sc->sc_ah)) {
1689 error = regulatory_hint(hw->wiphy,
1690 sc->sc_ah->regulatory.alpha2);
1695 /* Initialize LED control */
1702 /* cleanup tx queues */
1703 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1704 if (ATH_TXQ_SETUP(sc, i))
1705 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1707 ath9k_hw_detach(sc->sc_ah);
1708 ath9k_exit_debug(sc);
1713 int ath_reset(struct ath_softc *sc, bool retry_tx)
1715 struct ath_hw *ah = sc->sc_ah;
1716 struct ieee80211_hw *hw = sc->hw;
1719 ath9k_hw_set_interrupts(ah, 0);
1720 ath_drain_all_txq(sc, retry_tx);
1724 spin_lock_bh(&sc->sc_resetlock);
1725 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1727 DPRINTF(sc, ATH_DBG_FATAL,
1728 "Unable to reset hardware; reset status %u\n", r);
1729 spin_unlock_bh(&sc->sc_resetlock);
1731 if (ath_startrecv(sc) != 0)
1732 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1735 * We may be doing a reset in response to a request
1736 * that changes the channel so update any state that
1737 * might change as a result.
1739 ath_cache_conf_rate(sc, &hw->conf);
1741 ath_update_txpow(sc);
1743 if (sc->sc_flags & SC_OP_BEACONS)
1744 ath_beacon_config(sc, NULL); /* restart beacons */
1746 ath9k_hw_set_interrupts(ah, sc->imask);
1750 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1751 if (ATH_TXQ_SETUP(sc, i)) {
1752 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1753 ath_txq_schedule(sc, &sc->tx.txq[i]);
1754 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1763 * This function will allocate both the DMA descriptor structure, and the
1764 * buffers it contains. These are used to contain the descriptors used
1767 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1768 struct list_head *head, const char *name,
1769 int nbuf, int ndesc)
1771 #define DS2PHYS(_dd, _ds) \
1772 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1773 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1774 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1776 struct ath_desc *ds;
1778 int i, bsize, error;
1780 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1783 INIT_LIST_HEAD(head);
1784 /* ath_desc must be a multiple of DWORDs */
1785 if ((sizeof(struct ath_desc) % 4) != 0) {
1786 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1787 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1792 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1795 * Need additional DMA memory because we can't use
1796 * descriptors that cross the 4K page boundary. Assume
1797 * one skipped descriptor per 4K page.
1799 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1801 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1804 while (ndesc_skipped) {
1805 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1806 dd->dd_desc_len += dma_len;
1808 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1812 /* allocate descriptors */
1813 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1814 &dd->dd_desc_paddr, GFP_KERNEL);
1815 if (dd->dd_desc == NULL) {
1820 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1821 name, ds, (u32) dd->dd_desc_len,
1822 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1824 /* allocate buffers */
1825 bsize = sizeof(struct ath_buf) * nbuf;
1826 bf = kzalloc(bsize, GFP_KERNEL);
1833 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1835 bf->bf_daddr = DS2PHYS(dd, ds);
1837 if (!(sc->sc_ah->caps.hw_caps &
1838 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1840 * Skip descriptor addresses which can cause 4KB
1841 * boundary crossing (addr + length) with a 32 dword
1844 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1845 ASSERT((caddr_t) bf->bf_desc <
1846 ((caddr_t) dd->dd_desc +
1851 bf->bf_daddr = DS2PHYS(dd, ds);
1854 list_add_tail(&bf->list, head);
1858 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1861 memset(dd, 0, sizeof(*dd));
1863 #undef ATH_DESC_4KB_BOUND_CHECK
1864 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1868 void ath_descdma_cleanup(struct ath_softc *sc,
1869 struct ath_descdma *dd,
1870 struct list_head *head)
1872 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1875 INIT_LIST_HEAD(head);
1876 kfree(dd->dd_bufptr);
1877 memset(dd, 0, sizeof(*dd));
1880 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1886 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1889 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1892 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1895 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1898 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1905 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1910 case ATH9K_WME_AC_VO:
1913 case ATH9K_WME_AC_VI:
1916 case ATH9K_WME_AC_BE:
1919 case ATH9K_WME_AC_BK:
1930 /* XXX: Remove me once we don't depend on ath9k_channel for all
1931 * this redundant data */
1932 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1933 struct ath9k_channel *ichan)
1935 struct ieee80211_channel *chan = hw->conf.channel;
1936 struct ieee80211_conf *conf = &hw->conf;
1938 ichan->channel = chan->center_freq;
1941 if (chan->band == IEEE80211_BAND_2GHZ) {
1942 ichan->chanmode = CHANNEL_G;
1943 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1945 ichan->chanmode = CHANNEL_A;
1946 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1949 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1951 if (conf_is_ht(conf)) {
1952 if (conf_is_ht40(conf))
1953 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1955 ichan->chanmode = ath_get_extchanmode(sc, chan,
1956 conf->channel_type);
1960 /**********************/
1961 /* mac80211 callbacks */
1962 /**********************/
1964 static int ath9k_start(struct ieee80211_hw *hw)
1966 struct ath_wiphy *aphy = hw->priv;
1967 struct ath_softc *sc = aphy->sc;
1968 struct ieee80211_channel *curchan = hw->conf.channel;
1969 struct ath9k_channel *init_channel;
1972 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1973 "initial channel: %d MHz\n", curchan->center_freq);
1975 mutex_lock(&sc->mutex);
1977 if (ath9k_wiphy_started(sc)) {
1978 if (sc->chan_idx == curchan->hw_value) {
1980 * Already on the operational channel, the new wiphy
1981 * can be marked active.
1983 aphy->state = ATH_WIPHY_ACTIVE;
1984 ieee80211_wake_queues(hw);
1987 * Another wiphy is on another channel, start the new
1988 * wiphy in paused state.
1990 aphy->state = ATH_WIPHY_PAUSED;
1991 ieee80211_stop_queues(hw);
1993 mutex_unlock(&sc->mutex);
1996 aphy->state = ATH_WIPHY_ACTIVE;
1998 /* setup initial channel */
2000 pos = curchan->hw_value;
2003 init_channel = &sc->sc_ah->channels[pos];
2004 ath9k_update_ichannel(sc, hw, init_channel);
2006 /* Reset SERDES registers */
2007 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2010 * The basic interface to setting the hardware in a good
2011 * state is ``reset''. On return the hardware is known to
2012 * be powered up and with interrupts disabled. This must
2013 * be followed by initialization of the appropriate bits
2014 * and then setup of the interrupt mask.
2016 spin_lock_bh(&sc->sc_resetlock);
2017 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2019 DPRINTF(sc, ATH_DBG_FATAL,
2020 "Unable to reset hardware; reset status %u "
2021 "(freq %u MHz)\n", r,
2022 curchan->center_freq);
2023 spin_unlock_bh(&sc->sc_resetlock);
2026 spin_unlock_bh(&sc->sc_resetlock);
2029 * This is needed only to setup initial state
2030 * but it's best done after a reset.
2032 ath_update_txpow(sc);
2035 * Setup the hardware after reset:
2036 * The receive engine is set going.
2037 * Frame transmit is handled entirely
2038 * in the frame output path; there's nothing to do
2039 * here except setup the interrupt mask.
2041 if (ath_startrecv(sc) != 0) {
2042 DPRINTF(sc, ATH_DBG_FATAL,
2043 "Unable to start recv logic\n");
2048 /* Setup our intr mask. */
2049 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2050 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2051 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2053 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2054 sc->imask |= ATH9K_INT_GTT;
2056 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2057 sc->imask |= ATH9K_INT_CST;
2059 ath_cache_conf_rate(sc, &hw->conf);
2061 sc->sc_flags &= ~SC_OP_INVALID;
2063 /* Disable BMISS interrupt when we're not associated */
2064 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2065 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2067 ieee80211_wake_queues(hw);
2069 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2070 r = ath_start_rfkill_poll(sc);
2074 mutex_unlock(&sc->mutex);
2079 static int ath9k_tx(struct ieee80211_hw *hw,
2080 struct sk_buff *skb)
2082 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2083 struct ath_wiphy *aphy = hw->priv;
2084 struct ath_softc *sc = aphy->sc;
2085 struct ath_tx_control txctl;
2086 int hdrlen, padsize;
2088 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2089 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2090 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2094 memset(&txctl, 0, sizeof(struct ath_tx_control));
2097 * As a temporary workaround, assign seq# here; this will likely need
2098 * to be cleaned up to work better with Beacon transmission and virtual
2101 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2102 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2103 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2104 sc->tx.seq_no += 0x10;
2105 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2106 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2109 /* Add the padding after the header if this is not already done */
2110 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2112 padsize = hdrlen % 4;
2113 if (skb_headroom(skb) < padsize)
2115 skb_push(skb, padsize);
2116 memmove(skb->data, skb->data + padsize, hdrlen);
2119 /* Check if a tx queue is available */
2121 txctl.txq = ath_test_get_txq(sc, skb);
2125 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2127 if (ath_tx_start(hw, skb, &txctl) != 0) {
2128 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2134 dev_kfree_skb_any(skb);
2138 static void ath9k_stop(struct ieee80211_hw *hw)
2140 struct ath_wiphy *aphy = hw->priv;
2141 struct ath_softc *sc = aphy->sc;
2143 aphy->state = ATH_WIPHY_INACTIVE;
2145 if (sc->sc_flags & SC_OP_INVALID) {
2146 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2150 mutex_lock(&sc->mutex);
2152 ieee80211_stop_queues(hw);
2154 if (ath9k_wiphy_started(sc)) {
2155 mutex_unlock(&sc->mutex);
2156 return; /* another wiphy still in use */
2159 /* make sure h/w will not generate any interrupt
2160 * before setting the invalid flag. */
2161 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2163 if (!(sc->sc_flags & SC_OP_INVALID)) {
2164 ath_drain_all_txq(sc, false);
2166 ath9k_hw_phy_disable(sc->sc_ah);
2168 sc->rx.rxlink = NULL;
2170 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2171 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2172 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2174 /* disable HAL and put h/w to sleep */
2175 ath9k_hw_disable(sc->sc_ah);
2176 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2178 sc->sc_flags |= SC_OP_INVALID;
2180 mutex_unlock(&sc->mutex);
2182 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2185 static int ath9k_add_interface(struct ieee80211_hw *hw,
2186 struct ieee80211_if_init_conf *conf)
2188 struct ath_wiphy *aphy = hw->priv;
2189 struct ath_softc *sc = aphy->sc;
2190 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2191 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2194 mutex_lock(&sc->mutex);
2196 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2202 switch (conf->type) {
2203 case NL80211_IFTYPE_STATION:
2204 ic_opmode = NL80211_IFTYPE_STATION;
2206 case NL80211_IFTYPE_ADHOC:
2207 case NL80211_IFTYPE_AP:
2208 case NL80211_IFTYPE_MESH_POINT:
2209 if (sc->nbcnvifs >= ATH_BCBUF) {
2213 ic_opmode = conf->type;
2216 DPRINTF(sc, ATH_DBG_FATAL,
2217 "Interface type %d not yet supported\n", conf->type);
2222 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2224 /* Set the VIF opmode */
2225 avp->av_opmode = ic_opmode;
2230 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2231 ath9k_set_bssid_mask(hw);
2234 goto out; /* skip global settings for secondary vif */
2236 if (ic_opmode == NL80211_IFTYPE_AP) {
2237 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2238 sc->sc_flags |= SC_OP_TSF_RESET;
2241 /* Set the device opmode */
2242 sc->sc_ah->opmode = ic_opmode;
2245 * Enable MIB interrupts when there are hardware phy counters.
2246 * Note we only do this (at the moment) for station mode.
2248 if ((conf->type == NL80211_IFTYPE_STATION) ||
2249 (conf->type == NL80211_IFTYPE_ADHOC) ||
2250 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2251 if (ath9k_hw_phycounters(sc->sc_ah))
2252 sc->imask |= ATH9K_INT_MIB;
2253 sc->imask |= ATH9K_INT_TSFOOR;
2257 * Some hardware processes the TIM IE and fires an
2258 * interrupt when the TIM bit is set. For hardware
2259 * that does, if not overridden by configuration,
2260 * enable the TIM interrupt when operating as station.
2262 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2263 (conf->type == NL80211_IFTYPE_STATION) &&
2264 !sc->config.swBeaconProcess)
2265 sc->imask |= ATH9K_INT_TIM;
2267 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2269 if (conf->type == NL80211_IFTYPE_AP) {
2270 /* TODO: is this a suitable place to start ANI for AP mode? */
2272 mod_timer(&sc->ani.timer,
2273 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2277 mutex_unlock(&sc->mutex);
2281 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2282 struct ieee80211_if_init_conf *conf)
2284 struct ath_wiphy *aphy = hw->priv;
2285 struct ath_softc *sc = aphy->sc;
2286 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2289 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2291 mutex_lock(&sc->mutex);
2294 del_timer_sync(&sc->ani.timer);
2296 /* Reclaim beacon resources */
2297 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2298 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2299 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2300 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2301 ath_beacon_return(sc, avp);
2304 sc->sc_flags &= ~SC_OP_BEACONS;
2306 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2307 if (sc->beacon.bslot[i] == conf->vif) {
2308 printk(KERN_DEBUG "%s: vif had allocated beacon "
2309 "slot\n", __func__);
2310 sc->beacon.bslot[i] = NULL;
2311 sc->beacon.bslot_aphy[i] = NULL;
2317 mutex_unlock(&sc->mutex);
2320 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2322 struct ath_wiphy *aphy = hw->priv;
2323 struct ath_softc *sc = aphy->sc;
2324 struct ieee80211_conf *conf = &hw->conf;
2325 struct ath_hw *ah = sc->sc_ah;
2327 mutex_lock(&sc->mutex);
2329 if (changed & IEEE80211_CONF_CHANGE_PS) {
2330 if (conf->flags & IEEE80211_CONF_PS) {
2331 if (!(ah->caps.hw_caps &
2332 ATH9K_HW_CAP_AUTOSLEEP)) {
2333 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2334 sc->imask |= ATH9K_INT_TIM_TIMER;
2335 ath9k_hw_set_interrupts(sc->sc_ah,
2338 ath9k_hw_setrxabort(sc->sc_ah, 1);
2340 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2342 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2343 if (!(ah->caps.hw_caps &
2344 ATH9K_HW_CAP_AUTOSLEEP)) {
2345 ath9k_hw_setrxabort(sc->sc_ah, 0);
2346 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2347 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2348 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2349 ath9k_hw_set_interrupts(sc->sc_ah,
2356 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2357 struct ieee80211_channel *curchan = hw->conf.channel;
2358 int pos = curchan->hw_value;
2360 aphy->chan_idx = pos;
2361 aphy->chan_is_ht = conf_is_ht(conf);
2363 if (aphy->state == ATH_WIPHY_SCAN ||
2364 aphy->state == ATH_WIPHY_ACTIVE)
2365 ath9k_wiphy_pause_all_forced(sc, aphy);
2368 * Do not change operational channel based on a paused
2371 goto skip_chan_change;
2374 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2375 curchan->center_freq);
2377 /* XXX: remove me eventualy */
2378 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2380 ath_update_chainmask(sc, conf_is_ht(conf));
2382 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2383 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2384 mutex_unlock(&sc->mutex);
2390 if (changed & IEEE80211_CONF_CHANGE_POWER)
2391 sc->config.txpowlimit = 2 * conf->power_level;
2394 * The HW TSF has to be reset when the beacon interval changes.
2395 * We set the flag here, and ath_beacon_config_ap() would take this
2396 * into account when it gets called through the subsequent
2397 * config_interface() call - with IFCC_BEACON in the changed field.
2400 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2401 sc->sc_flags |= SC_OP_TSF_RESET;
2403 mutex_unlock(&sc->mutex);
2408 static int ath9k_config_interface(struct ieee80211_hw *hw,
2409 struct ieee80211_vif *vif,
2410 struct ieee80211_if_conf *conf)
2412 struct ath_wiphy *aphy = hw->priv;
2413 struct ath_softc *sc = aphy->sc;
2414 struct ath_hw *ah = sc->sc_ah;
2415 struct ath_vif *avp = (void *)vif->drv_priv;
2419 mutex_lock(&sc->mutex);
2421 /* TODO: Need to decide which hw opmode to use for multi-interface
2423 if (vif->type == NL80211_IFTYPE_AP &&
2424 ah->opmode != NL80211_IFTYPE_AP) {
2425 ah->opmode = NL80211_IFTYPE_STATION;
2426 ath9k_hw_setopmode(ah);
2427 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2429 ath9k_hw_write_associd(sc);
2430 /* Request full reset to get hw opmode changed properly */
2431 sc->sc_flags |= SC_OP_FULL_RESET;
2434 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2435 !is_zero_ether_addr(conf->bssid)) {
2436 switch (vif->type) {
2437 case NL80211_IFTYPE_STATION:
2438 case NL80211_IFTYPE_ADHOC:
2439 case NL80211_IFTYPE_MESH_POINT:
2441 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2442 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2444 ath9k_hw_write_associd(sc);
2446 /* Set aggregation protection mode parameters */
2447 sc->config.ath_aggr_prot = 0;
2449 DPRINTF(sc, ATH_DBG_CONFIG,
2450 "RX filter 0x%x bssid %pM aid 0x%x\n",
2451 rfilt, sc->curbssid, sc->curaid);
2453 /* need to reconfigure the beacon */
2454 sc->sc_flags &= ~SC_OP_BEACONS ;
2462 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2463 (vif->type == NL80211_IFTYPE_AP) ||
2464 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2465 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2466 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2467 conf->enable_beacon)) {
2469 * Allocate and setup the beacon frame.
2471 * Stop any previous beacon DMA. This may be
2472 * necessary, for example, when an ibss merge
2473 * causes reconfiguration; we may be called
2474 * with beacon transmission active.
2476 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2478 error = ath_beacon_alloc(aphy, vif);
2480 mutex_unlock(&sc->mutex);
2484 ath_beacon_config(sc, vif);
2488 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2489 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2490 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2491 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2492 ath9k_hw_keysetmac(sc->sc_ah,
2497 /* Only legacy IBSS for now */
2498 if (vif->type == NL80211_IFTYPE_ADHOC)
2499 ath_update_chainmask(sc, 0);
2501 mutex_unlock(&sc->mutex);
2506 #define SUPPORTED_FILTERS \
2507 (FIF_PROMISC_IN_BSS | \
2511 FIF_BCN_PRBRESP_PROMISC | \
2514 /* FIXME: sc->sc_full_reset ? */
2515 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2516 unsigned int changed_flags,
2517 unsigned int *total_flags,
2519 struct dev_mc_list *mclist)
2521 struct ath_wiphy *aphy = hw->priv;
2522 struct ath_softc *sc = aphy->sc;
2525 changed_flags &= SUPPORTED_FILTERS;
2526 *total_flags &= SUPPORTED_FILTERS;
2528 sc->rx.rxfilter = *total_flags;
2529 rfilt = ath_calcrxfilter(sc);
2530 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2532 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2535 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2536 struct ieee80211_vif *vif,
2537 enum sta_notify_cmd cmd,
2538 struct ieee80211_sta *sta)
2540 struct ath_wiphy *aphy = hw->priv;
2541 struct ath_softc *sc = aphy->sc;
2544 case STA_NOTIFY_ADD:
2545 ath_node_attach(sc, sta);
2547 case STA_NOTIFY_REMOVE:
2548 ath_node_detach(sc, sta);
2555 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2556 const struct ieee80211_tx_queue_params *params)
2558 struct ath_wiphy *aphy = hw->priv;
2559 struct ath_softc *sc = aphy->sc;
2560 struct ath9k_tx_queue_info qi;
2563 if (queue >= WME_NUM_AC)
2566 mutex_lock(&sc->mutex);
2568 qi.tqi_aifs = params->aifs;
2569 qi.tqi_cwmin = params->cw_min;
2570 qi.tqi_cwmax = params->cw_max;
2571 qi.tqi_burstTime = params->txop;
2572 qnum = ath_get_hal_qnum(queue, sc);
2574 DPRINTF(sc, ATH_DBG_CONFIG,
2575 "Configure tx [queue/halq] [%d/%d], "
2576 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2577 queue, qnum, params->aifs, params->cw_min,
2578 params->cw_max, params->txop);
2580 ret = ath_txq_update(sc, qnum, &qi);
2582 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2584 mutex_unlock(&sc->mutex);
2589 static int ath9k_set_key(struct ieee80211_hw *hw,
2590 enum set_key_cmd cmd,
2591 struct ieee80211_vif *vif,
2592 struct ieee80211_sta *sta,
2593 struct ieee80211_key_conf *key)
2595 struct ath_wiphy *aphy = hw->priv;
2596 struct ath_softc *sc = aphy->sc;
2599 if (modparam_nohwcrypt)
2602 mutex_lock(&sc->mutex);
2603 ath9k_ps_wakeup(sc);
2604 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2608 ret = ath_key_config(sc, vif, sta, key);
2610 key->hw_key_idx = ret;
2611 /* push IV and Michael MIC generation to stack */
2612 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2613 if (key->alg == ALG_TKIP)
2614 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2615 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2616 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2621 ath_key_delete(sc, key);
2627 ath9k_ps_restore(sc);
2628 mutex_unlock(&sc->mutex);
2633 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2634 struct ieee80211_vif *vif,
2635 struct ieee80211_bss_conf *bss_conf,
2638 struct ath_wiphy *aphy = hw->priv;
2639 struct ath_softc *sc = aphy->sc;
2641 mutex_lock(&sc->mutex);
2643 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2644 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2645 bss_conf->use_short_preamble);
2646 if (bss_conf->use_short_preamble)
2647 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2649 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2652 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2653 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2654 bss_conf->use_cts_prot);
2655 if (bss_conf->use_cts_prot &&
2656 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2657 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2659 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2662 if (changed & BSS_CHANGED_ASSOC) {
2663 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2665 ath9k_bss_assoc_info(sc, vif, bss_conf);
2668 mutex_unlock(&sc->mutex);
2671 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2674 struct ath_wiphy *aphy = hw->priv;
2675 struct ath_softc *sc = aphy->sc;
2677 mutex_lock(&sc->mutex);
2678 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2679 mutex_unlock(&sc->mutex);
2684 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2686 struct ath_wiphy *aphy = hw->priv;
2687 struct ath_softc *sc = aphy->sc;
2689 mutex_lock(&sc->mutex);
2690 ath9k_hw_settsf64(sc->sc_ah, tsf);
2691 mutex_unlock(&sc->mutex);
2694 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2696 struct ath_wiphy *aphy = hw->priv;
2697 struct ath_softc *sc = aphy->sc;
2699 mutex_lock(&sc->mutex);
2700 ath9k_hw_reset_tsf(sc->sc_ah);
2701 mutex_unlock(&sc->mutex);
2704 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2705 enum ieee80211_ampdu_mlme_action action,
2706 struct ieee80211_sta *sta,
2709 struct ath_wiphy *aphy = hw->priv;
2710 struct ath_softc *sc = aphy->sc;
2714 case IEEE80211_AMPDU_RX_START:
2715 if (!(sc->sc_flags & SC_OP_RXAGGR))
2718 case IEEE80211_AMPDU_RX_STOP:
2720 case IEEE80211_AMPDU_TX_START:
2721 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2723 DPRINTF(sc, ATH_DBG_FATAL,
2724 "Unable to start TX aggregation\n");
2726 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2728 case IEEE80211_AMPDU_TX_STOP:
2729 ret = ath_tx_aggr_stop(sc, sta, tid);
2731 DPRINTF(sc, ATH_DBG_FATAL,
2732 "Unable to stop TX aggregation\n");
2734 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2736 case IEEE80211_AMPDU_TX_OPERATIONAL:
2737 ath_tx_aggr_resume(sc, sta, tid);
2740 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2746 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2748 struct ath_wiphy *aphy = hw->priv;
2749 struct ath_softc *sc = aphy->sc;
2751 if (ath9k_wiphy_scanning(sc)) {
2752 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2755 * Do not allow the concurrent scanning state for now. This
2756 * could be improved with scanning control moved into ath9k.
2761 aphy->state = ATH_WIPHY_SCAN;
2762 ath9k_wiphy_pause_all_forced(sc, aphy);
2764 mutex_lock(&sc->mutex);
2765 sc->sc_flags |= SC_OP_SCANNING;
2766 mutex_unlock(&sc->mutex);
2769 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2771 struct ath_wiphy *aphy = hw->priv;
2772 struct ath_softc *sc = aphy->sc;
2774 mutex_lock(&sc->mutex);
2775 aphy->state = ATH_WIPHY_ACTIVE;
2776 sc->sc_flags &= ~SC_OP_SCANNING;
2777 mutex_unlock(&sc->mutex);
2780 struct ieee80211_ops ath9k_ops = {
2782 .start = ath9k_start,
2784 .add_interface = ath9k_add_interface,
2785 .remove_interface = ath9k_remove_interface,
2786 .config = ath9k_config,
2787 .config_interface = ath9k_config_interface,
2788 .configure_filter = ath9k_configure_filter,
2789 .sta_notify = ath9k_sta_notify,
2790 .conf_tx = ath9k_conf_tx,
2791 .bss_info_changed = ath9k_bss_info_changed,
2792 .set_key = ath9k_set_key,
2793 .get_tsf = ath9k_get_tsf,
2794 .set_tsf = ath9k_set_tsf,
2795 .reset_tsf = ath9k_reset_tsf,
2796 .ampdu_action = ath9k_ampdu_action,
2797 .sw_scan_start = ath9k_sw_scan_start,
2798 .sw_scan_complete = ath9k_sw_scan_complete,
2804 } ath_mac_bb_names[] = {
2805 { AR_SREV_VERSION_5416_PCI, "5416" },
2806 { AR_SREV_VERSION_5416_PCIE, "5418" },
2807 { AR_SREV_VERSION_9100, "9100" },
2808 { AR_SREV_VERSION_9160, "9160" },
2809 { AR_SREV_VERSION_9280, "9280" },
2810 { AR_SREV_VERSION_9285, "9285" }
2816 } ath_rf_names[] = {
2818 { AR_RAD5133_SREV_MAJOR, "5133" },
2819 { AR_RAD5122_SREV_MAJOR, "5122" },
2820 { AR_RAD2133_SREV_MAJOR, "2133" },
2821 { AR_RAD2122_SREV_MAJOR, "2122" }
2825 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2828 ath_mac_bb_name(u32 mac_bb_version)
2832 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2833 if (ath_mac_bb_names[i].version == mac_bb_version) {
2834 return ath_mac_bb_names[i].name;
2842 * Return the RF name. "????" is returned if the RF is unknown.
2845 ath_rf_name(u16 rf_version)
2849 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2850 if (ath_rf_names[i].version == rf_version) {
2851 return ath_rf_names[i].name;
2858 static int __init ath9k_init(void)
2862 /* Register rate control algorithm */
2863 error = ath_rate_control_register();
2866 "ath9k: Unable to register rate control "
2872 error = ath9k_debug_create_root();
2875 "ath9k: Unable to create debugfs root: %d\n",
2877 goto err_rate_unregister;
2880 error = ath_pci_init();
2883 "ath9k: No PCI devices found, driver not installed.\n");
2885 goto err_remove_root;
2888 error = ath_ahb_init();
2900 ath9k_debug_remove_root();
2901 err_rate_unregister:
2902 ath_rate_control_unregister();
2906 module_init(ath9k_init);
2908 static void __exit ath9k_exit(void)
2912 ath9k_debug_remove_root();
2913 ath_rate_control_unregister();
2914 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2916 module_exit(ath9k_exit);