4 #include <linux/kernel.h>
5 #include <linux/spinlock.h>
6 #include <linux/interrupt.h>
7 #include <linux/hw_random.h>
8 #include <linux/ssb/ssb.h>
9 #include <net/mac80211.h>
17 #ifdef CONFIG_B43_DEBUG
23 #define B43_RX_MAX_SSI 60
26 #define B43_MMIO_DMA0_REASON 0x20
27 #define B43_MMIO_DMA0_IRQ_MASK 0x24
28 #define B43_MMIO_DMA1_REASON 0x28
29 #define B43_MMIO_DMA1_IRQ_MASK 0x2C
30 #define B43_MMIO_DMA2_REASON 0x30
31 #define B43_MMIO_DMA2_IRQ_MASK 0x34
32 #define B43_MMIO_DMA3_REASON 0x38
33 #define B43_MMIO_DMA3_IRQ_MASK 0x3C
34 #define B43_MMIO_DMA4_REASON 0x40
35 #define B43_MMIO_DMA4_IRQ_MASK 0x44
36 #define B43_MMIO_DMA5_REASON 0x48
37 #define B43_MMIO_DMA5_IRQ_MASK 0x4C
38 #define B43_MMIO_MACCTL 0x120 /* MAC control */
39 #define B43_MMIO_MACCMD 0x124 /* MAC command */
40 #define B43_MMIO_GEN_IRQ_REASON 0x128
41 #define B43_MMIO_GEN_IRQ_MASK 0x12C
42 #define B43_MMIO_RAM_CONTROL 0x130
43 #define B43_MMIO_RAM_DATA 0x134
44 #define B43_MMIO_PS_STATUS 0x140
45 #define B43_MMIO_RADIO_HWENABLED_HI 0x158
46 #define B43_MMIO_SHM_CONTROL 0x160
47 #define B43_MMIO_SHM_DATA 0x164
48 #define B43_MMIO_SHM_DATA_UNALIGNED 0x166
49 #define B43_MMIO_XMITSTAT_0 0x170
50 #define B43_MMIO_XMITSTAT_1 0x174
51 #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
52 #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
53 #define B43_MMIO_TSF_CFP_REP 0x188
54 #define B43_MMIO_TSF_CFP_START 0x18C
55 #define B43_MMIO_TSF_CFP_MAXDUR 0x190
58 #define B43_MMIO_DMA32_BASE0 0x200
59 #define B43_MMIO_DMA32_BASE1 0x220
60 #define B43_MMIO_DMA32_BASE2 0x240
61 #define B43_MMIO_DMA32_BASE3 0x260
62 #define B43_MMIO_DMA32_BASE4 0x280
63 #define B43_MMIO_DMA32_BASE5 0x2A0
65 #define B43_MMIO_DMA64_BASE0 0x200
66 #define B43_MMIO_DMA64_BASE1 0x240
67 #define B43_MMIO_DMA64_BASE2 0x280
68 #define B43_MMIO_DMA64_BASE3 0x2C0
69 #define B43_MMIO_DMA64_BASE4 0x300
70 #define B43_MMIO_DMA64_BASE5 0x340
72 #define B43_MMIO_PHY_VER 0x3E0
73 #define B43_MMIO_PHY_RADIO 0x3E2
74 #define B43_MMIO_PHY0 0x3E6
75 #define B43_MMIO_ANTENNA 0x3E8
76 #define B43_MMIO_CHANNEL 0x3F0
77 #define B43_MMIO_CHANNEL_EXT 0x3F4
78 #define B43_MMIO_RADIO_CONTROL 0x3F6
79 #define B43_MMIO_RADIO_DATA_HIGH 0x3F8
80 #define B43_MMIO_RADIO_DATA_LOW 0x3FA
81 #define B43_MMIO_PHY_CONTROL 0x3FC
82 #define B43_MMIO_PHY_DATA 0x3FE
83 #define B43_MMIO_MACFILTER_CONTROL 0x420
84 #define B43_MMIO_MACFILTER_DATA 0x422
85 #define B43_MMIO_RCMTA_COUNT 0x43C
86 #define B43_MMIO_RADIO_HWENABLED_LO 0x49A
87 #define B43_MMIO_GPIO_CONTROL 0x49C
88 #define B43_MMIO_GPIO_MASK 0x49E
89 #define B43_MMIO_TSF_CFP_START_LOW 0x604
90 #define B43_MMIO_TSF_CFP_START_HIGH 0x606
91 #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
92 #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
93 #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
94 #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
95 #define B43_MMIO_RNG 0x65A
96 #define B43_MMIO_POWERUP_DELAY 0x6A8
98 /* SPROM boardflags_lo values */
99 #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
100 #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
101 #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
102 #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
103 #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
104 #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
105 #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
106 #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
107 #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
108 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
109 #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
110 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
111 #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
112 #define B43_BFL_HGPA 0x2000 /* had high gain PA */
113 #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
114 #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
116 /* GPIO register offset, in both ChipCommon and PCI core. */
117 #define B43_GPIO_CONTROL 0x6c
121 B43_SHM_UCODE, /* Microcode memory */
122 B43_SHM_SHARED, /* Shared memory */
123 B43_SHM_SCRATCH, /* Scratch memory */
124 B43_SHM_HW, /* Internal hardware register */
125 B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
127 /* SHM Routing modifiers */
128 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
129 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
130 #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
133 /* Misc SHM_SHARED offsets */
134 #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
135 #define B43_SHM_SH_PCTLWDPOS 0x0008
136 #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
137 #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
138 #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
139 #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
140 #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
141 #define B43_SHM_SH_HOSTFHI 0x0060 /* Hostflags for ucode options (high) */
142 #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
143 #define B43_SHM_SH_RADAR 0x0066 /* Radar register */
144 #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
145 #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
146 #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
147 #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
148 #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
149 /* SHM_SHARED TX FIFO variables */
150 #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
151 #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
152 #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
153 #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
154 /* SHM_SHARED background noise */
155 #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
156 #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
157 #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
158 /* SHM_SHARED crypto engine */
159 #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
160 #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
161 #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
162 #define B43_SHM_SH_TKIPTSCTTAK 0x0318
163 #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
164 #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
165 /* SHM_SHARED WME variables */
166 #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
167 #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
168 #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
169 /* SHM_SHARED powersave mode related */
170 #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
171 #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
172 #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
173 /* SHM_SHARED beacon variables */
174 #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
175 #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
176 #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
177 #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
178 #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
179 #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
180 #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
181 /* SHM_SHARED ACK/CTS control */
182 #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
183 /* SHM_SHARED probe response variables */
184 #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
185 #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
186 #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
187 #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
188 #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
189 /* SHM_SHARED rate tables */
190 #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
191 #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
192 #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
193 #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
194 /* SHM_SHARED microcode soft registers */
195 #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
196 #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
197 #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
198 #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
199 #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
200 #define B43_SHM_SH_UCODESTAT_INVALID 0
201 #define B43_SHM_SH_UCODESTAT_INIT 1
202 #define B43_SHM_SH_UCODESTAT_ACTIVE 2
203 #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
204 #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
205 #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
206 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
207 #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
209 /* SHM_SCRATCH offsets */
210 #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
211 #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
212 #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
213 #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
214 #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
215 #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
216 #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
217 #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
218 #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
219 #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
221 /* Hardware Radio Enable masks */
222 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
223 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
225 /* HostFlags. See b43_hf_read/write() */
226 #define B43_HF_ANTDIVHELP 0x00000001 /* ucode antenna div helper */
227 #define B43_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
228 #define B43_HF_RXPULLW 0x00000004 /* RX pullup workaround */
229 #define B43_HF_CCKBOOST 0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
230 #define B43_HF_BTCOEX 0x00000010 /* Bluetooth coexistance */
231 #define B43_HF_GDCW 0x00000020 /* G-PHY DV canceller filter bw workaround */
232 #define B43_HF_OFDMPABOOST 0x00000040 /* Enable PA gain boost for OFDM */
233 #define B43_HF_ACPR 0x00000080 /* Disable for Japan, channel 14 */
234 #define B43_HF_EDCF 0x00000100 /* on if WME and MAC suspended */
235 #define B43_HF_TSSIRPSMW 0x00000200 /* TSSI reset PSM ucode workaround */
236 #define B43_HF_DSCRQ 0x00000400 /* Disable slow clock request in ucode */
237 #define B43_HF_ACIW 0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
238 #define B43_HF_2060W 0x00001000 /* 2060 radio workaround */
239 #define B43_HF_RADARW 0x00002000 /* Radar workaround */
240 #define B43_HF_USEDEFKEYS 0x00004000 /* Enable use of default keys */
241 #define B43_HF_BT4PRIOCOEX 0x00010000 /* Bluetooth 2-priority coexistance */
242 #define B43_HF_FWKUP 0x00020000 /* Fast wake-up ucode */
243 #define B43_HF_VCORECALC 0x00040000 /* Force VCO recalculation when powering up synthpu */
244 #define B43_HF_PCISCW 0x00080000 /* PCI slow clock workaround */
245 #define B43_HF_4318TSSI 0x00200000 /* 4318 TSSI */
246 #define B43_HF_FBCMCFIFO 0x00400000 /* Flush bcast/mcast FIFO immediately */
247 #define B43_HF_HWPCTL 0x00800000 /* Enable hardwarre power control */
248 #define B43_HF_BTCOEXALT 0x01000000 /* Bluetooth coexistance in alternate pins */
249 #define B43_HF_TXBTCHECK 0x02000000 /* Bluetooth check during transmission */
250 #define B43_HF_SKCFPUP 0x04000000 /* Skip CFP update */
252 /* MacFilter offsets. */
253 #define B43_MACFILTER_SELF 0x0000
254 #define B43_MACFILTER_BSSID 0x0003
257 #define B43_PCTL_IN 0xB0
258 #define B43_PCTL_OUT 0xB4
259 #define B43_PCTL_OUTENABLE 0xB8
260 #define B43_PCTL_XTAL_POWERUP 0x40
261 #define B43_PCTL_PLL_POWERDOWN 0x80
263 /* PowerControl Clock Modes */
264 #define B43_PCTL_CLK_FAST 0x00
265 #define B43_PCTL_CLK_SLOW 0x01
266 #define B43_PCTL_CLK_DYNAMIC 0x02
268 #define B43_PCTL_FORCE_SLOW 0x0800
269 #define B43_PCTL_FORCE_PLL 0x1000
270 #define B43_PCTL_DYN_XTAL 0x2000
273 #define B43_PHYTYPE_A 0x00
274 #define B43_PHYTYPE_B 0x01
275 #define B43_PHYTYPE_G 0x02
276 #define B43_PHYTYPE_N 0x04
277 #define B43_PHYTYPE_LP 0x05
280 #define B43_PHY_ILT_A_CTRL 0x0072
281 #define B43_PHY_ILT_A_DATA1 0x0073
282 #define B43_PHY_ILT_A_DATA2 0x0074
283 #define B43_PHY_G_LO_CONTROL 0x0810
284 #define B43_PHY_ILT_G_CTRL 0x0472
285 #define B43_PHY_ILT_G_DATA1 0x0473
286 #define B43_PHY_ILT_G_DATA2 0x0474
287 #define B43_PHY_A_PCTL 0x007B
288 #define B43_PHY_G_PCTL 0x0029
289 #define B43_PHY_A_CRS 0x0029
290 #define B43_PHY_RADIO_BITFIELD 0x0401
291 #define B43_PHY_G_CRS 0x0429
292 #define B43_PHY_NRSSILT_CTRL 0x0803
293 #define B43_PHY_NRSSILT_DATA 0x0804
296 #define B43_RADIOCTL_ID 0x01
298 /* MAC Control bitfield */
299 #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
300 #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
301 #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
302 #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
303 #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
304 #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
305 #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
306 #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
307 #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
308 #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
309 #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
310 #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
311 #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
312 #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
313 #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
314 #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
315 #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
316 #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
317 #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
318 #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
319 #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
320 #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
321 #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
322 #define B43_MACCTL_GMODE 0x80000000 /* G Mode */
324 /* MAC Command bitfield */
325 #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
326 #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
327 #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
328 #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
329 #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
331 /* 802.11 core specific TM State Low flags */
332 #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
333 #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select */
334 #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
335 #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
336 #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
338 /* 802.11 core specific TM State High flags */
339 #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
340 #define B43_TMSHIGH_APHY 0x00020000 /* A-PHY available (rev >= 5) */
341 #define B43_TMSHIGH_GPHY 0x00010000 /* G-PHY available (rev >= 5) */
343 /* Generic-Interrupt reasons. */
344 #define B43_IRQ_MAC_SUSPENDED 0x00000001
345 #define B43_IRQ_BEACON 0x00000002
346 #define B43_IRQ_TBTT_INDI 0x00000004
347 #define B43_IRQ_BEACON_TX_OK 0x00000008
348 #define B43_IRQ_BEACON_CANCEL 0x00000010
349 #define B43_IRQ_ATIM_END 0x00000020
350 #define B43_IRQ_PMQ 0x00000040
351 #define B43_IRQ_PIO_WORKAROUND 0x00000100
352 #define B43_IRQ_MAC_TXERR 0x00000200
353 #define B43_IRQ_PHY_TXERR 0x00000800
354 #define B43_IRQ_PMEVENT 0x00001000
355 #define B43_IRQ_TIMER0 0x00002000
356 #define B43_IRQ_TIMER1 0x00004000
357 #define B43_IRQ_DMA 0x00008000
358 #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
359 #define B43_IRQ_CCA_MEASURE_OK 0x00020000
360 #define B43_IRQ_NOISESAMPLE_OK 0x00040000
361 #define B43_IRQ_UCODE_DEBUG 0x08000000
362 #define B43_IRQ_RFKILL 0x10000000
363 #define B43_IRQ_TX_OK 0x20000000
364 #define B43_IRQ_PHY_G_CHANGED 0x40000000
365 #define B43_IRQ_TIMEOUT 0x80000000
367 #define B43_IRQ_ALL 0xFFFFFFFF
368 #define B43_IRQ_MASKTEMPLATE (B43_IRQ_MAC_SUSPENDED | \
370 B43_IRQ_TBTT_INDI | \
373 B43_IRQ_MAC_TXERR | \
374 B43_IRQ_PHY_TXERR | \
376 B43_IRQ_TXFIFO_FLUSH_OK | \
377 B43_IRQ_NOISESAMPLE_OK | \
378 B43_IRQ_UCODE_DEBUG | \
382 /* Device specific rate values.
383 * The actual values defined here are (rate_in_mbps * 2).
384 * Some code depends on this. Don't change it. */
385 #define B43_CCK_RATE_1MB 0x02
386 #define B43_CCK_RATE_2MB 0x04
387 #define B43_CCK_RATE_5MB 0x0B
388 #define B43_CCK_RATE_11MB 0x16
389 #define B43_OFDM_RATE_6MB 0x0C
390 #define B43_OFDM_RATE_9MB 0x12
391 #define B43_OFDM_RATE_12MB 0x18
392 #define B43_OFDM_RATE_18MB 0x24
393 #define B43_OFDM_RATE_24MB 0x30
394 #define B43_OFDM_RATE_36MB 0x48
395 #define B43_OFDM_RATE_48MB 0x60
396 #define B43_OFDM_RATE_54MB 0x6C
397 /* Convert a b43 rate value to a rate in 100kbps */
398 #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
400 #define B43_DEFAULT_SHORT_RETRY_LIMIT 7
401 #define B43_DEFAULT_LONG_RETRY_LIMIT 4
403 #define B43_PHY_TX_BADNESS_LIMIT 1000
405 /* Max size of a security key */
406 #define B43_SEC_KEYSIZE 16
407 /* Security algorithms. */
409 B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
414 B43_SEC_ALGO_AES_LEGACY,
420 /* The firmware file header */
421 #define B43_FW_TYPE_UCODE 'u'
422 #define B43_FW_TYPE_PCM 'p'
423 #define B43_FW_TYPE_IV 'i'
424 struct b43_fw_header {
427 /* File format version */
430 /* Size of the data. For ucode and PCM this is in bytes.
431 * For IV this is number-of-ivs. */
433 } __attribute__((__packed__));
435 /* Initial Value file format */
436 #define B43_IV_OFFSET_MASK 0x7FFF
437 #define B43_IV_32BIT 0x8000
443 } data __attribute__((__packed__));
444 } __attribute__((__packed__));
447 #define B43_PHYMODE(phytype) (1 << (phytype))
448 #define B43_PHYMODE_A B43_PHYMODE(B43_PHYTYPE_A)
449 #define B43_PHYMODE_B B43_PHYMODE(B43_PHYTYPE_B)
450 #define B43_PHYMODE_G B43_PHYMODE(B43_PHYTYPE_G)
453 /* Possible PHYMODEs on this PHY */
454 u8 possible_phymodes;
455 /* GMODE bit enabled? */
457 /* Possible ieee80211 subsystem hwmodes for this PHY.
458 * Which mode is selected, depends on thr GMODE enabled bit */
459 #define B43_MAX_PHYHWMODES 2
460 struct ieee80211_hw_mode hwmodes[B43_MAX_PHYHWMODES];
466 /* PHY revision number. */
469 /* Radio versioning */
470 u16 radio_manuf; /* Radio manufacturer */
471 u16 radio_ver; /* Radio version */
472 u8 radio_rev; /* Radio revision */
474 bool locked; /* Only used in b43_phy_{un}lock() */
475 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
477 /* ACI (adjacent channel interference) flags. */
479 bool aci_wlan_automatic;
482 /* Radio switched on/off */
485 /* Values saved when turning the radio off.
486 * They are needed when turning it on again. */
495 /* TSSI to dBm table in use */
497 /* Target idle TSSI */
499 /* Current idle TSSI */
502 /* LocalOscillator control values. */
503 struct b43_txpower_lo_control *lo_control;
504 /* Values from b43_calc_loopback_gain() */
505 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
506 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
507 s16 lna_lod_gain; /* LNA lod */
508 s16 lna_gain; /* LNA */
509 s16 pga_gain; /* PGA */
511 /* PHY lock for core.rev < 3
512 * This lock is only used by b43_phy_{un}lock()
516 /* Desired TX power level (in dBm).
517 * This is set by the user and adjusted in b43_phy_xmitpower(). */
519 /* A-PHY TX Power control value. */
522 /* Current TX power level attenuation control values */
523 struct b43_bbatt bbatt;
524 struct b43_rfatt rfatt;
525 u8 tx_control; /* B43_TXCTL_XXX */
526 #ifdef CONFIG_B43_DEBUG
527 bool manual_txpower_control; /* Manual TX-power control enabled? */
529 /* Hardware Power Control enabled? */
530 bool hardware_power_control;
532 /* Current Interference Mitigation mode */
534 /* Stack of saved values from the Interference Mitigation code.
535 * Each value in the stack is layed out as follows:
537 * bit 12-15: register ID
539 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
541 #define B43_INTERFSTACK_SIZE 26
542 u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
544 /* Saved values from the NRSSI Slope calculation */
547 /* In memory nrssi lookup table. */
550 /* current channel */
555 u16 initval; //FIXME rename?
557 /* PHY TX errors counter. */
560 /* The device does address auto increment for the OFDM tables.
561 * We cache the previously used address here and omit the address
562 * write on the next table access, if possible. */
563 u16 ofdmtab_addr; /* The address currently set in hardware. */
564 enum { /* The last data flow direction. */
565 B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
566 B43_OFDMTAB_DIRECTION_READ,
567 B43_OFDMTAB_DIRECTION_WRITE,
568 } ofdmtab_addr_direction;
571 /* Data structures for DMA transmission, per 80211 core. */
573 struct b43_dmaring *tx_ring0;
574 struct b43_dmaring *tx_ring1;
575 struct b43_dmaring *tx_ring2;
576 struct b43_dmaring *tx_ring3;
577 struct b43_dmaring *tx_ring4;
578 struct b43_dmaring *tx_ring5;
580 struct b43_dmaring *rx_ring0;
581 struct b43_dmaring *rx_ring3; /* only available on core.rev < 5 */
584 /* Context information for a noise calculation (Link Quality). */
585 struct b43_noise_calculation {
587 bool calculation_running;
594 /* Store the last TX/RX times here for updating the leds. */
595 unsigned long last_tx;
596 unsigned long last_rx;
600 /* If keyconf is NULL, this key is disabled.
601 * keyconf is a cookie. Don't derefenrence it outside of the set_key
602 * path, because b43 doesn't own it. */
603 struct ieee80211_key_conf *keyconf;
609 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
611 /* Pointer to the active wireless device on this chip */
612 struct b43_wldev *current_dev;
613 /* Pointer to the ieee80211 hardware data structure */
614 struct ieee80211_hw *hw;
618 spinlock_t leds_lock;
620 /* We can only have one operating interface (802.11 core)
621 * at a time. General information about this interface follows.
624 /* Opaque ID of the operating interface from the ieee80211
625 * subsystem. Do not modify.
628 /* The MAC address of the operating interface. */
629 u8 mac_addr[ETH_ALEN];
632 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
634 /* Is the card operating in AP, STA or IBSS mode? */
637 unsigned int filter_flags;
638 /* Stats about the wireless interface */
639 struct ieee80211_low_level_stats ieee_stats;
643 char rng_name[30 + 1];
645 /* The RF-kill button */
646 struct b43_rfkill rfkill;
648 /* List of all wireless devices on this chip */
649 struct list_head devlist;
652 bool radiotap_enabled;
655 /* Pointers to the firmware data and meta information about it. */
656 struct b43_firmware {
658 const struct firmware *ucode;
660 const struct firmware *pcm;
661 /* Initial MMIO values for the firmware */
662 const struct firmware *initvals;
663 /* Initial MMIO values for the firmware, band-specific */
664 const struct firmware *initvals_band;
665 /* Firmware revision */
667 /* Firmware patchlevel */
671 /* Device (802.11 core) initialization status. */
673 B43_STAT_UNINIT = 0, /* Uninitialized. */
674 B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
675 B43_STAT_STARTED = 2, /* Up and running. */
677 #define b43_status(wldev) atomic_read(&(wldev)->__init_status)
678 #define b43_set_status(wldev, stat) do { \
679 atomic_set(&(wldev)->__init_status, (stat)); \
683 /* XXX--- HOW LOCKING WORKS IN B43 ---XXX
685 * You should always acquire both, wl->mutex and wl->irq_lock unless:
686 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
687 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
688 * and packet TX path (and _ONLY_ there.)
691 /* Data structure for one wireless device (802.11 core) */
693 struct ssb_device *dev;
696 /* The device initialization status.
697 * Use b43_status() to query. */
698 atomic_t __init_status;
699 /* Saved init status for handling suspend. */
700 int suspend_init_status;
702 bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
703 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
704 bool short_preamble; /* TRUE, if short preamble is enabled. */
705 bool short_slot; /* TRUE, if short slot timing is enabled. */
706 bool radio_hw_enable; /* saved state of radio hardware enabled state */
708 /* PHY/Radio device. */
714 /* Various statistics about the physical device. */
715 struct b43_stats stats;
717 /* The device LEDs. */
718 struct b43_led led_tx;
719 struct b43_led led_rx;
720 struct b43_led led_assoc;
721 struct b43_led led_radio;
723 /* Reason code of the last interrupt. */
726 /* saved irq enable/disable state bitfield. */
728 /* Link Quality calculation context. */
729 struct b43_noise_calculation noisecalc;
730 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
733 /* Interrupt Service Routine tasklet (bottom-half) */
734 struct tasklet_struct isr_tasklet;
737 struct delayed_work periodic_work;
738 unsigned int periodic_state;
740 struct work_struct restart_work;
742 /* encryption/decryption */
743 u16 ktp; /* Key table pointer */
745 struct b43_key key[58];
747 /* Cached beacon template while uploading the template. */
748 struct sk_buff *cached_beacon;
751 struct b43_firmware fw;
753 /* Devicelist in struct b43_wl (all 802.11 cores) */
754 struct list_head list;
756 /* Debugging stuff follows. */
757 #ifdef CONFIG_B43_DEBUG
758 struct b43_dfsentry *dfsentry;
762 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
767 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
769 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
770 return ssb_get_drvdata(ssb_dev);
773 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
774 static inline int b43_is_mode(struct b43_wl *wl, int type)
776 return (wl->operating && wl->if_type == type);
779 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
781 return ssb_read16(dev->dev, offset);
784 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
786 ssb_write16(dev->dev, offset, value);
789 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
791 return ssb_read32(dev->dev, offset);
794 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
796 ssb_write32(dev->dev, offset, value);
799 /* Message printing */
800 void b43info(struct b43_wl *wl, const char *fmt, ...)
801 __attribute__ ((format(printf, 2, 3)));
802 void b43err(struct b43_wl *wl, const char *fmt, ...)
803 __attribute__ ((format(printf, 2, 3)));
804 void b43warn(struct b43_wl *wl, const char *fmt, ...)
805 __attribute__ ((format(printf, 2, 3)));
807 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
808 __attribute__ ((format(printf, 2, 3)));
810 # define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
813 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
814 * This _also_ evaluates the arg with debugging disabled. */
816 # define B43_WARN_ON(x) WARN_ON(x)
818 static inline bool __b43_warn_on_dummy(bool x) { return x; }
819 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
822 /** Limit a value between two limits */
826 #define limit_value(value, min, max) \
828 typeof(value) __value = (value); \
829 typeof(value) __min = (min); \
830 typeof(value) __max = (max); \
831 if (__value < __min) \
833 else if (__value > __max) \
838 /* Convert an integer to a Q5.2 value */
839 #define INT_TO_Q52(i) ((i) << 2)
840 /* Convert a Q5.2 value to an integer (precision loss!) */
841 #define Q52_TO_INT(q52) ((q52) >> 2)
842 /* Macros for printing a value in Q5.2 format */
843 #define Q52_FMT "%u.%u"
844 #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)