drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/slab.h>
  42 #include <asm/div64.h>
  43
  44
  45 /* Required number of TX DMA slots per TX frame.
  46  * This currently is 2, because we put the header and the ieee80211 frame
  47  * into separate slots. */
  48 #define TX_SLOTS_PER_FRAME      2
  49
  50 static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr,
  51                            enum b43_addrtype addrtype)
  52 {
  53         u32 uninitialized_var(addr);
  54
  55         switch (addrtype) {
  56         case B43_DMA_ADDR_LOW:
  57                 addr = lower_32_bits(dmaaddr);
  58                 if (dma->translation_in_low) {
  59                         addr &= ~SSB_DMA_TRANSLATION_MASK;
  60                         addr |= dma->translation;
  61                 }
  62                 break;
  63         case B43_DMA_ADDR_HIGH:
  64                 addr = upper_32_bits(dmaaddr);
  65                 if (!dma->translation_in_low) {
  66                         addr &= ~SSB_DMA_TRANSLATION_MASK;
  67                         addr |= dma->translation;
  68                 }
  69                 break;
  70         case B43_DMA_ADDR_EXT:
  71                 if (dma->translation_in_low)
  72                         addr = lower_32_bits(dmaaddr);
  73                 else
  74                         addr = upper_32_bits(dmaaddr);
  75                 addr &= SSB_DMA_TRANSLATION_MASK;
  76                 addr >>= SSB_DMA_TRANSLATION_SHIFT;
  77                 break;
  78         }
  79
  80         return addr;
  81 }
  82
  83 /* 32bit DMA ops. */
  84 static
  85 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  86                                           int slot,
  87                                           struct b43_dmadesc_meta **meta)
  88 {
  89         struct b43_dmadesc32 *desc;
  90
  91         *meta = &(ring->meta[slot]);
  92         desc = ring->descbase;
  93         desc = &(desc[slot]);
  94
  95         return (struct b43_dmadesc_generic *)desc;
  96 }
  97
  98 static void op32_fill_descriptor(struct b43_dmaring *ring,
  99                                  struct b43_dmadesc_generic *desc,
 100                                  dma_addr_t dmaaddr, u16 bufsize,
 101                                  int start, int end, int irq)
 102 {
 103         struct b43_dmadesc32 *descbase = ring->descbase;
 104         int slot;
 105         u32 ctl;
 106         u32 addr;
 107         u32 addrext;
 108
 109         slot = (int)(&(desc->dma32) - descbase);
 110         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 111
 112         addr = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
 113         addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
 114
 115         ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
 116         if (slot == ring->nr_slots - 1)
 117                 ctl |= B43_DMA32_DCTL_DTABLEEND;
 118         if (start)
 119                 ctl |= B43_DMA32_DCTL_FRAMESTART;
 120         if (end)
 121                 ctl |= B43_DMA32_DCTL_FRAMEEND;
 122         if (irq)
 123                 ctl |= B43_DMA32_DCTL_IRQ;
 124         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
 125             & B43_DMA32_DCTL_ADDREXT_MASK;
 126
 127         desc->dma32.control = cpu_to_le32(ctl);
 128         desc->dma32.address = cpu_to_le32(addr);
 129 }
 130
 131 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
 132 {
 133         b43_dma_write(ring, B43_DMA32_TXINDEX,
 134                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 135 }
 136
 137 static void op32_tx_suspend(struct b43_dmaring *ring)
 138 {
 139         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 140                       | B43_DMA32_TXSUSPEND);
 141 }
 142
 143 static void op32_tx_resume(struct b43_dmaring *ring)
 144 {
 145         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 146                       & ~B43_DMA32_TXSUSPEND);
 147 }
 148
 149 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 150 {
 151         u32 val;
 152
 153         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 154         val &= B43_DMA32_RXDPTR;
 155
 156         return (val / sizeof(struct b43_dmadesc32));
 157 }
 158
 159 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 160 {
 161         b43_dma_write(ring, B43_DMA32_RXINDEX,
 162                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 163 }
 164
 165 static const struct b43_dma_ops dma32_ops = {
 166         .idx2desc = op32_idx2desc,
 167         .fill_descriptor = op32_fill_descriptor,
 168         .poke_tx = op32_poke_tx,
 169         .tx_suspend = op32_tx_suspend,
 170         .tx_resume = op32_tx_resume,
 171         .get_current_rxslot = op32_get_current_rxslot,
 172         .set_current_rxslot = op32_set_current_rxslot,
 173 };
 174
 175 /* 64bit DMA ops. */
 176 static
 177 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 178                                           int slot,
 179                                           struct b43_dmadesc_meta **meta)
 180 {
 181         struct b43_dmadesc64 *desc;
 182
 183         *meta = &(ring->meta[slot]);
 184         desc = ring->descbase;
 185         desc = &(desc[slot]);
 186
 187         return (struct b43_dmadesc_generic *)desc;
 188 }
 189
 190 static void op64_fill_descriptor(struct b43_dmaring *ring,
 191                                  struct b43_dmadesc_generic *desc,
 192                                  dma_addr_t dmaaddr, u16 bufsize,
 193                                  int start, int end, int irq)
 194 {
 195         struct b43_dmadesc64 *descbase = ring->descbase;
 196         int slot;
 197         u32 ctl0 = 0, ctl1 = 0;
 198         u32 addrlo, addrhi;
 199         u32 addrext;
 200
 201         slot = (int)(&(desc->dma64) - descbase);
 202         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 203
 204         addrlo = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
 205         addrhi = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_HIGH);
 206         addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
 207
 208         if (slot == ring->nr_slots - 1)
 209                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 210         if (start)
 211                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 212         if (end)
 213                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 214         if (irq)
 215                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 216         ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
 217         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 218             & B43_DMA64_DCTL1_ADDREXT_MASK;
 219
 220         desc->dma64.control0 = cpu_to_le32(ctl0);
 221         desc->dma64.control1 = cpu_to_le32(ctl1);
 222         desc->dma64.address_low = cpu_to_le32(addrlo);
 223         desc->dma64.address_high = cpu_to_le32(addrhi);
 224 }
 225
 226 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 227 {
 228         b43_dma_write(ring, B43_DMA64_TXINDEX,
 229                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 230 }
 231
 232 static void op64_tx_suspend(struct b43_dmaring *ring)
 233 {
 234         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 235                       | B43_DMA64_TXSUSPEND);
 236 }
 237
 238 static void op64_tx_resume(struct b43_dmaring *ring)
 239 {
 240         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 241                       & ~B43_DMA64_TXSUSPEND);
 242 }
 243
 244 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 245 {
 246         u32 val;
 247
 248         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 249         val &= B43_DMA64_RXSTATDPTR;
 250
 251         return (val / sizeof(struct b43_dmadesc64));
 252 }
 253
 254 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 255 {
 256         b43_dma_write(ring, B43_DMA64_RXINDEX,
 257                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 258 }
 259
 260 static const struct b43_dma_ops dma64_ops = {
 261         .idx2desc = op64_idx2desc,
 262         .fill_descriptor = op64_fill_descriptor,
 263         .poke_tx = op64_poke_tx,
 264         .tx_suspend = op64_tx_suspend,
 265         .tx_resume = op64_tx_resume,
 266         .get_current_rxslot = op64_get_current_rxslot,
 267         .set_current_rxslot = op64_set_current_rxslot,
 268 };
 269
 270 static inline int free_slots(struct b43_dmaring *ring)
 271 {
 272         return (ring->nr_slots - ring->used_slots);
 273 }
 274
 275 static inline int next_slot(struct b43_dmaring *ring, int slot)
 276 {
 277         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 278         if (slot == ring->nr_slots - 1)
 279                 return 0;
 280         return slot + 1;
 281 }
 282
 283 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 284 {
 285         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 286         if (slot == 0)
 287                 return ring->nr_slots - 1;
 288         return slot - 1;
 289 }
 290
 291 #ifdef CONFIG_B43_DEBUG
 292 static void update_max_used_slots(struct b43_dmaring *ring,
 293                                   int current_used_slots)
 294 {
 295         if (current_used_slots <= ring->max_used_slots)
 296                 return;
 297         ring->max_used_slots = current_used_slots;
 298         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 299                 b43dbg(ring->dev->wl,
 300                        "max_used_slots increased to %d on %s ring %d\n",
 301                        ring->max_used_slots,
 302                        ring->tx ? "TX" : "RX", ring->index);
 303         }
 304 }
 305 #else
 306 static inline
 307     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 308 {
 309 }
 310 #endif /* DEBUG */
 311
 312 /* Request a slot for usage. */
 313 static inline int request_slot(struct b43_dmaring *ring)
 314 {
 315         int slot;
 316
 317         B43_WARN_ON(!ring->tx);
 318         B43_WARN_ON(ring->stopped);
 319         B43_WARN_ON(free_slots(ring) == 0);
 320
 321         slot = next_slot(ring, ring->current_slot);
 322         ring->current_slot = slot;
 323         ring->used_slots++;
 324
 325         update_max_used_slots(ring, ring->used_slots);
 326
 327         return slot;
 328 }
 329
 330 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
 331 {
 332         static const u16 map64[] = {
 333                 B43_MMIO_DMA64_BASE0,
 334                 B43_MMIO_DMA64_BASE1,
 335                 B43_MMIO_DMA64_BASE2,
 336                 B43_MMIO_DMA64_BASE3,
 337                 B43_MMIO_DMA64_BASE4,
 338                 B43_MMIO_DMA64_BASE5,
 339         };
 340         static const u16 map32[] = {
 341                 B43_MMIO_DMA32_BASE0,
 342                 B43_MMIO_DMA32_BASE1,
 343                 B43_MMIO_DMA32_BASE2,
 344                 B43_MMIO_DMA32_BASE3,
 345                 B43_MMIO_DMA32_BASE4,
 346                 B43_MMIO_DMA32_BASE5,
 347         };
 348
 349         if (type == B43_DMA_64BIT) {
 350                 B43_WARN_ON(!(controller_idx >= 0 &&
 351                               controller_idx < ARRAY_SIZE(map64)));
 352                 return map64[controller_idx];
 353         }
 354         B43_WARN_ON(!(controller_idx >= 0 &&
 355                       controller_idx < ARRAY_SIZE(map32)));
 356         return map32[controller_idx];
 357 }
 358
 359 static inline
 360     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 361                               unsigned char *buf, size_t len, int tx)
 362 {
 363         dma_addr_t dmaaddr;
 364
 365         if (tx) {
 366                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
 367                                          buf, len, DMA_TO_DEVICE);
 368         } else {
 369                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
 370                                          buf, len, DMA_FROM_DEVICE);
 371         }
 372
 373         return dmaaddr;
 374 }
 375
 376 static inline
 377     void unmap_descbuffer(struct b43_dmaring *ring,
 378                           dma_addr_t addr, size_t len, int tx)
 379 {
 380         if (tx) {
 381                 dma_unmap_single(ring->dev->dev->dma_dev,
 382                                  addr, len, DMA_TO_DEVICE);
 383         } else {
 384                 dma_unmap_single(ring->dev->dev->dma_dev,
 385                                  addr, len, DMA_FROM_DEVICE);
 386         }
 387 }
 388
 389 static inline
 390     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 391                                  dma_addr_t addr, size_t len)
 392 {
 393         B43_WARN_ON(ring->tx);
 394         dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
 395                                     addr, len, DMA_FROM_DEVICE);
 396 }
 397
 398 static inline
 399     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 400                                     dma_addr_t addr, size_t len)
 401 {
 402         B43_WARN_ON(ring->tx);
 403         dma_sync_single_for_device(ring->dev->dev->dma_dev,
 404                                    addr, len, DMA_FROM_DEVICE);
 405 }
 406
 407 static inline
 408     void free_descriptor_buffer(struct b43_dmaring *ring,
 409                                 struct b43_dmadesc_meta *meta)
 410 {
 411         if (meta->skb) {
 412                 dev_kfree_skb_any(meta->skb);
 413                 meta->skb = NULL;
 414         }
 415 }
 416
 417 static int alloc_ringmemory(struct b43_dmaring *ring)
 418 {
 419         gfp_t flags = GFP_KERNEL;
 420
 421         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 422          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 423          * has shown that 4K is sufficient for the latter as long as the buffer
 424          * does not cross an 8K boundary.
 425          *
 426          */
 427         ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
 428                                             B43_DMA_RINGMEMSIZE,
 429                                             &(ring->dmabase), flags);
 430         if (!ring->descbase) {
 431                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 432                 return -ENOMEM;
 433         }
 434         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 435
 436         return 0;
 437 }
 438
 439 static void free_ringmemory(struct b43_dmaring *ring)
 440 {
 441         dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
 442                           ring->descbase, ring->dmabase);
 443 }
 444
 445 /* Reset the RX DMA channel */
 446 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
 447                                       enum b43_dmatype type)
 448 {
 449         int i;
 450         u32 value;
 451         u16 offset;
 452
 453         might_sleep();
 454
 455         offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 456         b43_write32(dev, mmio_base + offset, 0);
 457         for (i = 0; i < 10; i++) {
 458                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
 459                                                    B43_DMA32_RXSTATUS;
 460                 value = b43_read32(dev, mmio_base + offset);
 461                 if (type == B43_DMA_64BIT) {
 462                         value &= B43_DMA64_RXSTAT;
 463                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 464                                 i = -1;
 465                                 break;
 466                         }
 467                 } else {
 468                         value &= B43_DMA32_RXSTATE;
 469                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 470                                 i = -1;
 471                                 break;
 472                         }
 473                 }
 474                 msleep(1);
 475         }
 476         if (i != -1) {
 477                 b43err(dev->wl, "DMA RX reset timed out\n");
 478                 return -ENODEV;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /* Reset the TX DMA channel */
 485 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
 486                                       enum b43_dmatype type)
 487 {
 488         int i;
 489         u32 value;
 490         u16 offset;
 491
 492         might_sleep();
 493
 494         for (i = 0; i < 10; i++) {
 495                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 496                                                    B43_DMA32_TXSTATUS;
 497                 value = b43_read32(dev, mmio_base + offset);
 498                 if (type == B43_DMA_64BIT) {
 499                         value &= B43_DMA64_TXSTAT;
 500                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 501                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 502                             value == B43_DMA64_TXSTAT_STOPPED)
 503                                 break;
 504                 } else {
 505                         value &= B43_DMA32_TXSTATE;
 506                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 507                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 508                             value == B43_DMA32_TXSTAT_STOPPED)
 509                                 break;
 510                 }
 511                 msleep(1);
 512         }
 513         offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 514         b43_write32(dev, mmio_base + offset, 0);
 515         for (i = 0; i < 10; i++) {
 516                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 517                                                    B43_DMA32_TXSTATUS;
 518                 value = b43_read32(dev, mmio_base + offset);
 519                 if (type == B43_DMA_64BIT) {
 520                         value &= B43_DMA64_TXSTAT;
 521                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 522                                 i = -1;
 523                                 break;
 524                         }
 525                 } else {
 526                         value &= B43_DMA32_TXSTATE;
 527                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 528                                 i = -1;
 529                                 break;
 530                         }
 531                 }
 532                 msleep(1);
 533         }
 534         if (i != -1) {
 535                 b43err(dev->wl, "DMA TX reset timed out\n");
 536                 return -ENODEV;
 537         }
 538         /* ensure the reset is completed. */
 539         msleep(1);
 540
 541         return 0;
 542 }
 543
 544 /* Check if a DMA mapping address is invalid. */
 545 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
 546                                   dma_addr_t addr,
 547                                   size_t buffersize, bool dma_to_device)
 548 {
 549         if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
 550                 return 1;
 551
 552         switch (ring->type) {
 553         case B43_DMA_30BIT:
 554                 if ((u64)addr + buffersize > (1ULL << 30))
 555                         goto address_error;
 556                 break;
 557         case B43_DMA_32BIT:
 558                 if ((u64)addr + buffersize > (1ULL << 32))
 559                         goto address_error;
 560                 break;
 561         case B43_DMA_64BIT:
 562                 /* Currently we can't have addresses beyond
 563                  * 64bit in the kernel. */
 564                 break;
 565         }
 566
 567         /* The address is OK. */
 568         return 0;
 569
 570 address_error:
 571         /* We can't support this address. Unmap it again. */
 572         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
 573
 574         return 1;
 575 }
 576
 577 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
 578 {
 579         unsigned char *f = skb->data + ring->frameoffset;
 580
 581         return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
 582 }
 583
 584 static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
 585 {
 586         struct b43_rxhdr_fw4 *rxhdr;
 587         unsigned char *frame;
 588
 589         /* This poisons the RX buffer to detect DMA failures. */
 590
 591         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 592         rxhdr->frame_len = 0;
 593
 594         B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
 595         frame = skb->data + ring->frameoffset;
 596         memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
 597 }
 598
 599 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 600                                struct b43_dmadesc_generic *desc,
 601                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 602 {
 603         dma_addr_t dmaaddr;
 604         struct sk_buff *skb;
 605
 606         B43_WARN_ON(ring->tx);
 607
 608         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 609         if (unlikely(!skb))
 610                 return -ENOMEM;
 611         b43_poison_rx_buffer(ring, skb);
 612         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 613         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 614                 /* ugh. try to realloc in zone_dma */
 615                 gfp_flags |= GFP_DMA;
 616
 617                 dev_kfree_skb_any(skb);
 618
 619                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 620                 if (unlikely(!skb))
 621                         return -ENOMEM;
 622                 b43_poison_rx_buffer(ring, skb);
 623                 dmaaddr = map_descbuffer(ring, skb->data,
 624                                          ring->rx_buffersize, 0);
 625                 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 626                         b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
 627                         dev_kfree_skb_any(skb);
 628                         return -EIO;
 629                 }
 630         }
 631
 632         meta->skb = skb;
 633         meta->dmaaddr = dmaaddr;
 634         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 635                                    ring->rx_buffersize, 0, 0, 0);
 636
 637         return 0;
 638 }
 639
 640 /* Allocate the initial descbuffers.
 641  * This is used for an RX ring only.
 642  */
 643 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 644 {
 645         int i, err = -ENOMEM;
 646         struct b43_dmadesc_generic *desc;
 647         struct b43_dmadesc_meta *meta;
 648
 649         for (i = 0; i < ring->nr_slots; i++) {
 650                 desc = ring->ops->idx2desc(ring, i, &meta);
 651
 652                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 653                 if (err) {
 654                         b43err(ring->dev->wl,
 655                                "Failed to allocate initial descbuffers\n");
 656                         goto err_unwind;
 657                 }
 658         }
 659         mb();
 660         ring->used_slots = ring->nr_slots;
 661         err = 0;
 662       out:
 663         return err;
 664
 665       err_unwind:
 666         for (i--; i >= 0; i--) {
 667                 desc = ring->ops->idx2desc(ring, i, &meta);
 668
 669                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 670                 dev_kfree_skb(meta->skb);
 671         }
 672         goto out;
 673 }
 674
 675 /* Do initial setup of the DMA controller.
 676  * Reset the controller, write the ring busaddress
 677  * and switch the "enable" bit on.
 678  */
 679 static int dmacontroller_setup(struct b43_dmaring *ring)
 680 {
 681         int err = 0;
 682         u32 value;
 683         u32 addrext;
 684         bool parity = ring->dev->dma.parity;
 685         u32 addrlo;
 686         u32 addrhi;
 687
 688         if (ring->tx) {
 689                 if (ring->type == B43_DMA_64BIT) {
 690                         u64 ringbase = (u64) (ring->dmabase);
 691                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 692                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 693                         addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
 694
 695                         value = B43_DMA64_TXENABLE;
 696                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 697                             & B43_DMA64_TXADDREXT_MASK;
 698                         if (!parity)
 699                                 value |= B43_DMA64_TXPARITYDISABLE;
 700                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 701                         b43_dma_write(ring, B43_DMA64_TXRINGLO, addrlo);
 702                         b43_dma_write(ring, B43_DMA64_TXRINGHI, addrhi);
 703                 } else {
 704                         u32 ringbase = (u32) (ring->dmabase);
 705                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 706                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 707
 708                         value = B43_DMA32_TXENABLE;
 709                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 710                             & B43_DMA32_TXADDREXT_MASK;
 711                         if (!parity)
 712                                 value |= B43_DMA32_TXPARITYDISABLE;
 713                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 714                         b43_dma_write(ring, B43_DMA32_TXRING, addrlo);
 715                 }
 716         } else {
 717                 err = alloc_initial_descbuffers(ring);
 718                 if (err)
 719                         goto out;
 720                 if (ring->type == B43_DMA_64BIT) {
 721                         u64 ringbase = (u64) (ring->dmabase);
 722                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 723                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 724                         addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
 725
 726                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 727                         value |= B43_DMA64_RXENABLE;
 728                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 729                             & B43_DMA64_RXADDREXT_MASK;
 730                         if (!parity)
 731                                 value |= B43_DMA64_RXPARITYDISABLE;
 732                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 733                         b43_dma_write(ring, B43_DMA64_RXRINGLO, addrlo);
 734                         b43_dma_write(ring, B43_DMA64_RXRINGHI, addrhi);
 735                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 736                                       sizeof(struct b43_dmadesc64));
 737                 } else {
 738                         u32 ringbase = (u32) (ring->dmabase);
 739                         addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
 740                         addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
 741
 742                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 743                         value |= B43_DMA32_RXENABLE;
 744                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 745                             & B43_DMA32_RXADDREXT_MASK;
 746                         if (!parity)
 747                                 value |= B43_DMA32_RXPARITYDISABLE;
 748                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 749                         b43_dma_write(ring, B43_DMA32_RXRING, addrlo);
 750                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 751                                       sizeof(struct b43_dmadesc32));
 752                 }
 753         }
 754
 755 out:
 756         return err;
 757 }
 758
 759 /* Shutdown the DMA controller. */
 760 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 761 {
 762         if (ring->tx) {
 763                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 764                                            ring->type);
 765                 if (ring->type == B43_DMA_64BIT) {
 766                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 767                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 768                 } else
 769                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 770         } else {
 771                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 772                                            ring->type);
 773                 if (ring->type == B43_DMA_64BIT) {
 774                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 775                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 776                 } else
 777                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 778         }
 779 }
 780
 781 static void free_all_descbuffers(struct b43_dmaring *ring)
 782 {
 783         struct b43_dmadesc_meta *meta;
 784         int i;
 785
 786         if (!ring->used_slots)
 787                 return;
 788         for (i = 0; i < ring->nr_slots; i++) {
 789                 /* get meta - ignore returned value */
 790                 ring->ops->idx2desc(ring, i, &meta);
 791
 792                 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
 793                         B43_WARN_ON(!ring->tx);
 794                         continue;
 795                 }
 796                 if (ring->tx) {
 797                         unmap_descbuffer(ring, meta->dmaaddr,
 798                                          meta->skb->len, 1);
 799                 } else {
 800                         unmap_descbuffer(ring, meta->dmaaddr,
 801                                          ring->rx_buffersize, 0);
 802                 }
 803                 free_descriptor_buffer(ring, meta);
 804         }
 805 }
 806
 807 static u64 supported_dma_mask(struct b43_wldev *dev)
 808 {
 809         u32 tmp;
 810         u16 mmio_base;
 811
 812         tmp = b43_read32(dev, SSB_TMSHIGH);
 813         if (tmp & SSB_TMSHIGH_DMA64)
 814                 return DMA_BIT_MASK(64);
 815         mmio_base = b43_dmacontroller_base(0, 0);
 816         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 817         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 818         if (tmp & B43_DMA32_TXADDREXT_MASK)
 819                 return DMA_BIT_MASK(32);
 820
 821         return DMA_BIT_MASK(30);
 822 }
 823
 824 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
 825 {
 826         if (dmamask == DMA_BIT_MASK(30))
 827                 return B43_DMA_30BIT;
 828         if (dmamask == DMA_BIT_MASK(32))
 829                 return B43_DMA_32BIT;
 830         if (dmamask == DMA_BIT_MASK(64))
 831                 return B43_DMA_64BIT;
 832         B43_WARN_ON(1);
 833         return B43_DMA_30BIT;
 834 }
 835
 836 /* Main initialization function. */
 837 static
 838 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 839                                       int controller_index,
 840                                       int for_tx,
 841                                       enum b43_dmatype type)
 842 {
 843         struct b43_dmaring *ring;
 844         int i, err;
 845         dma_addr_t dma_test;
 846
 847         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 848         if (!ring)
 849                 goto out;
 850
 851         ring->nr_slots = B43_RXRING_SLOTS;
 852         if (for_tx)
 853                 ring->nr_slots = B43_TXRING_SLOTS;
 854
 855         ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
 856                              GFP_KERNEL);
 857         if (!ring->meta)
 858                 goto err_kfree_ring;
 859         for (i = 0; i < ring->nr_slots; i++)
 860                 ring->meta->skb = B43_DMA_PTR_POISON;
 861
 862         ring->type = type;
 863         ring->dev = dev;
 864         ring->mmio_base = b43_dmacontroller_base(type, controller_index);
 865         ring->index = controller_index;
 866         if (type == B43_DMA_64BIT)
 867                 ring->ops = &dma64_ops;
 868         else
 869                 ring->ops = &dma32_ops;
 870         if (for_tx) {
 871                 ring->tx = 1;
 872                 ring->current_slot = -1;
 873         } else {
 874                 if (ring->index == 0) {
 875                         switch (dev->fw.hdr_format) {
 876                         case B43_FW_HDR_598:
 877                                 ring->rx_buffersize = B43_DMA0_RX_FW598_BUFSIZE;
 878                                 ring->frameoffset = B43_DMA0_RX_FW598_FO;
 879                                 break;
 880                         case B43_FW_HDR_410:
 881                         case B43_FW_HDR_351:
 882                                 ring->rx_buffersize = B43_DMA0_RX_FW351_BUFSIZE;
 883                                 ring->frameoffset = B43_DMA0_RX_FW351_FO;
 884                                 break;
 885                         }
 886                 } else
 887                         B43_WARN_ON(1);
 888         }
 889 #ifdef CONFIG_B43_DEBUG
 890         ring->last_injected_overflow = jiffies;
 891 #endif
 892
 893         if (for_tx) {
 894                 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
 895                 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
 896
 897                 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 898                                             b43_txhdr_size(dev),
 899                                             GFP_KERNEL);
 900                 if (!ring->txhdr_cache)
 901                         goto err_kfree_meta;
 902
 903                 /* test for ability to dma to txhdr_cache */
 904                 dma_test = dma_map_single(dev->dev->dma_dev,
 905                                           ring->txhdr_cache,
 906                                           b43_txhdr_size(dev),
 907                                           DMA_TO_DEVICE);
 908
 909                 if (b43_dma_mapping_error(ring, dma_test,
 910                                           b43_txhdr_size(dev), 1)) {
 911                         /* ugh realloc */
 912                         kfree(ring->txhdr_cache);
 913                         ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 914                                                     b43_txhdr_size(dev),
 915                                                     GFP_KERNEL | GFP_DMA);
 916                         if (!ring->txhdr_cache)
 917                                 goto err_kfree_meta;
 918
 919                         dma_test = dma_map_single(dev->dev->dma_dev,
 920                                                   ring->txhdr_cache,
 921                                                   b43_txhdr_size(dev),
 922                                                   DMA_TO_DEVICE);
 923
 924                         if (b43_dma_mapping_error(ring, dma_test,
 925                                                   b43_txhdr_size(dev), 1)) {
 926
 927                                 b43err(dev->wl,
 928                                        "TXHDR DMA allocation failed\n");
 929                                 goto err_kfree_txhdr_cache;
 930                         }
 931                 }
 932
 933                 dma_unmap_single(dev->dev->dma_dev,
 934                                  dma_test, b43_txhdr_size(dev),
 935                                  DMA_TO_DEVICE);
 936         }
 937
 938         err = alloc_ringmemory(ring);
 939         if (err)
 940                 goto err_kfree_txhdr_cache;
 941         err = dmacontroller_setup(ring);
 942         if (err)
 943                 goto err_free_ringmemory;
 944
 945       out:
 946         return ring;
 947
 948       err_free_ringmemory:
 949         free_ringmemory(ring);
 950       err_kfree_txhdr_cache:
 951         kfree(ring->txhdr_cache);
 952       err_kfree_meta:
 953         kfree(ring->meta);
 954       err_kfree_ring:
 955         kfree(ring);
 956         ring = NULL;
 957         goto out;
 958 }
 959
 960 #define divide(a, b)    ({      \
 961         typeof(a) __a = a;      \
 962         do_div(__a, b);         \
 963         __a;                    \
 964   })
 965
 966 #define modulo(a, b)    ({      \
 967         typeof(a) __a = a;      \
 968         do_div(__a, b);         \
 969   })
 970
 971 /* Main cleanup function. */
 972 static void b43_destroy_dmaring(struct b43_dmaring *ring,
 973                                 const char *ringname)
 974 {
 975         if (!ring)
 976                 return;
 977
 978 #ifdef CONFIG_B43_DEBUG
 979         {
 980                 /* Print some statistics. */
 981                 u64 failed_packets = ring->nr_failed_tx_packets;
 982                 u64 succeed_packets = ring->nr_succeed_tx_packets;
 983                 u64 nr_packets = failed_packets + succeed_packets;
 984                 u64 permille_failed = 0, average_tries = 0;
 985
 986                 if (nr_packets)
 987                         permille_failed = divide(failed_packets * 1000, nr_packets);
 988                 if (nr_packets)
 989                         average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
 990
 991                 b43dbg(ring->dev->wl, "DMA-%u %s: "
 992                        "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
 993                        "Average tries %llu.%02llu\n",
 994                        (unsigned int)(ring->type), ringname,
 995                        ring->max_used_slots,
 996                        ring->nr_slots,
 997                        (unsigned long long)failed_packets,
 998                        (unsigned long long)nr_packets,
 999                        (unsigned long long)divide(permille_failed, 10),
1000                        (unsigned long long)modulo(permille_failed, 10),
1001                        (unsigned long long)divide(average_tries, 100),
1002                        (unsigned long long)modulo(average_tries, 100));
1003         }
1004 #endif /* DEBUG */
1005
1006         /* Device IRQs are disabled prior entering this function,
1007          * so no need to take care of concurrency with rx handler stuff.
1008          */
1009         dmacontroller_cleanup(ring);
1010         free_all_descbuffers(ring);
1011         free_ringmemory(ring);
1012
1013         kfree(ring->txhdr_cache);
1014         kfree(ring->meta);
1015         kfree(ring);
1016 }
1017
1018 #define destroy_ring(dma, ring) do {                            \
1019         b43_destroy_dmaring((dma)->ring, __stringify(ring));    \
1020         (dma)->ring = NULL;                                     \
1021     } while (0)
1022
1023 void b43_dma_free(struct b43_wldev *dev)
1024 {
1025         struct b43_dma *dma;
1026
1027         if (b43_using_pio_transfers(dev))
1028                 return;
1029         dma = &dev->dma;
1030
1031         destroy_ring(dma, rx_ring);
1032         destroy_ring(dma, tx_ring_AC_BK);
1033         destroy_ring(dma, tx_ring_AC_BE);
1034         destroy_ring(dma, tx_ring_AC_VI);
1035         destroy_ring(dma, tx_ring_AC_VO);
1036         destroy_ring(dma, tx_ring_mcast);
1037 }
1038
1039 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1040 {
1041         u64 orig_mask = mask;
1042         bool fallback = 0;
1043         int err;
1044
1045         /* Try to set the DMA mask. If it fails, try falling back to a
1046          * lower mask, as we can always also support a lower one. */
1047         while (1) {
1048                 err = dma_set_mask(dev->dev->dma_dev, mask);
1049                 if (!err) {
1050                         err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1051                         if (!err)
1052                                 break;
1053                 }
1054                 if (mask == DMA_BIT_MASK(64)) {
1055                         mask = DMA_BIT_MASK(32);
1056                         fallback = 1;
1057                         continue;
1058                 }
1059                 if (mask == DMA_BIT_MASK(32)) {
1060                         mask = DMA_BIT_MASK(30);
1061                         fallback = 1;
1062                         continue;
1063                 }
1064                 b43err(dev->wl, "The machine/kernel does not support "
1065                        "the required %u-bit DMA mask\n",
1066                        (unsigned int)dma_mask_to_engine_type(orig_mask));
1067                 return -EOPNOTSUPP;
1068         }
1069         if (fallback) {
1070                 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1071                         (unsigned int)dma_mask_to_engine_type(orig_mask),
1072                         (unsigned int)dma_mask_to_engine_type(mask));
1073         }
1074
1075         return 0;
1076 }
1077
1078 /* Some hardware with 64-bit DMA seems to be bugged and looks for translation
1079  * bit in low address word instead of high one.
1080  */
1081 static bool b43_dma_translation_in_low_word(struct b43_wldev *dev,
1082                                             enum b43_dmatype type)
1083 {
1084         if (type != B43_DMA_64BIT)
1085                 return 1;
1086
1087 #ifdef CONFIG_B43_SSB
1088         if (dev->dev->bus_type == B43_BUS_SSB &&
1089             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
1090             !(dev->dev->sdev->bus->host_pci->is_pcie &&
1091               ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64))
1092                         return 1;
1093 #endif
1094         return 0;
1095 }
1096
1097 int b43_dma_init(struct b43_wldev *dev)
1098 {
1099         struct b43_dma *dma = &dev->dma;
1100         int err;
1101         u64 dmamask;
1102         enum b43_dmatype type;
1103
1104         dmamask = supported_dma_mask(dev);
1105         type = dma_mask_to_engine_type(dmamask);
1106         err = b43_dma_set_mask(dev, dmamask);
1107         if (err)
1108                 return err;
1109
1110         switch (dev->dev->bus_type) {
1111 #ifdef CONFIG_B43_BCMA
1112         case B43_BUS_BCMA:
1113                 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1114                 break;
1115 #endif
1116 #ifdef CONFIG_B43_SSB
1117         case B43_BUS_SSB:
1118                 dma->translation = ssb_dma_translation(dev->dev->sdev);
1119                 break;
1120 #endif
1121         }
1122         dma->translation_in_low = b43_dma_translation_in_low_word(dev, type);
1123
1124         dma->parity = true;
1125 #ifdef CONFIG_B43_BCMA
1126         /* TODO: find out which SSB devices need disabling parity */
1127         if (dev->dev->bus_type == B43_BUS_BCMA)
1128                 dma->parity = false;
1129 #endif
1130
1131         err = -ENOMEM;
1132         /* setup TX DMA channels. */
1133         dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1134         if (!dma->tx_ring_AC_BK)
1135                 goto out;
1136
1137         dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1138         if (!dma->tx_ring_AC_BE)
1139                 goto err_destroy_bk;
1140
1141         dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1142         if (!dma->tx_ring_AC_VI)
1143                 goto err_destroy_be;
1144
1145         dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1146         if (!dma->tx_ring_AC_VO)
1147                 goto err_destroy_vi;
1148
1149         dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1150         if (!dma->tx_ring_mcast)
1151                 goto err_destroy_vo;
1152
1153         /* setup RX DMA channel. */
1154         dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1155         if (!dma->rx_ring)
1156                 goto err_destroy_mcast;
1157
1158         /* No support for the TX status DMA ring. */
1159         B43_WARN_ON(dev->dev->core_rev < 5);
1160
1161         b43dbg(dev->wl, "%u-bit DMA initialized\n",
1162                (unsigned int)type);
1163         err = 0;
1164 out:
1165         return err;
1166
1167 err_destroy_mcast:
1168         destroy_ring(dma, tx_ring_mcast);
1169 err_destroy_vo:
1170         destroy_ring(dma, tx_ring_AC_VO);
1171 err_destroy_vi:
1172         destroy_ring(dma, tx_ring_AC_VI);
1173 err_destroy_be:
1174         destroy_ring(dma, tx_ring_AC_BE);
1175 err_destroy_bk:
1176         destroy_ring(dma, tx_ring_AC_BK);
1177         return err;
1178 }
1179
1180 /* Generate a cookie for the TX header. */
1181 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1182 {
1183         u16 cookie;
1184
1185         /* Use the upper 4 bits of the cookie as
1186          * DMA controller ID and store the slot number
1187          * in the lower 12 bits.
1188          * Note that the cookie must never be 0, as this
1189          * is a special value used in RX path.
1190          * It can also not be 0xFFFF because that is special
1191          * for multicast frames.
1192          */
1193         cookie = (((u16)ring->index + 1) << 12);
1194         B43_WARN_ON(slot & ~0x0FFF);
1195         cookie |= (u16)slot;
1196
1197         return cookie;
1198 }
1199
1200 /* Inspect a cookie and find out to which controller/slot it belongs. */
1201 static
1202 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1203 {
1204         struct b43_dma *dma = &dev->dma;
1205         struct b43_dmaring *ring = NULL;
1206
1207         switch (cookie & 0xF000) {
1208         case 0x1000:
1209                 ring = dma->tx_ring_AC_BK;
1210                 break;
1211         case 0x2000:
1212                 ring = dma->tx_ring_AC_BE;
1213                 break;
1214         case 0x3000:
1215                 ring = dma->tx_ring_AC_VI;
1216                 break;
1217         case 0x4000:
1218                 ring = dma->tx_ring_AC_VO;
1219                 break;
1220         case 0x5000:
1221                 ring = dma->tx_ring_mcast;
1222                 break;
1223         }
1224         *slot = (cookie & 0x0FFF);
1225         if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1226                 b43dbg(dev->wl, "TX-status contains "
1227                        "invalid cookie: 0x%04X\n", cookie);
1228                 return NULL;
1229         }
1230
1231         return ring;
1232 }
1233
1234 static int dma_tx_fragment(struct b43_dmaring *ring,
1235                            struct sk_buff *skb)
1236 {
1237         const struct b43_dma_ops *ops = ring->ops;
1238         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1239         struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1240         u8 *header;
1241         int slot, old_top_slot, old_used_slots;
1242         int err;
1243         struct b43_dmadesc_generic *desc;
1244         struct b43_dmadesc_meta *meta;
1245         struct b43_dmadesc_meta *meta_hdr;
1246         u16 cookie;
1247         size_t hdrsize = b43_txhdr_size(ring->dev);
1248
1249         /* Important note: If the number of used DMA slots per TX frame
1250          * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1251          * the file has to be updated, too!
1252          */
1253
1254         old_top_slot = ring->current_slot;
1255         old_used_slots = ring->used_slots;
1256
1257         /* Get a slot for the header. */
1258         slot = request_slot(ring);
1259         desc = ops->idx2desc(ring, slot, &meta_hdr);
1260         memset(meta_hdr, 0, sizeof(*meta_hdr));
1261
1262         header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1263         cookie = generate_cookie(ring, slot);
1264         err = b43_generate_txhdr(ring->dev, header,
1265                                  skb, info, cookie);
1266         if (unlikely(err)) {
1267                 ring->current_slot = old_top_slot;
1268                 ring->used_slots = old_used_slots;
1269                 return err;
1270         }
1271
1272         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1273                                            hdrsize, 1);
1274         if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1275                 ring->current_slot = old_top_slot;
1276                 ring->used_slots = old_used_slots;
1277                 return -EIO;
1278         }
1279         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1280                              hdrsize, 1, 0, 0);
1281
1282         /* Get a slot for the payload. */
1283         slot = request_slot(ring);
1284         desc = ops->idx2desc(ring, slot, &meta);
1285         memset(meta, 0, sizeof(*meta));
1286
1287         meta->skb = skb;
1288         meta->is_last_fragment = 1;
1289         priv_info->bouncebuffer = NULL;
1290
1291         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1292         /* create a bounce buffer in zone_dma on mapping failure. */
1293         if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1294                 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1295                                                   GFP_ATOMIC | GFP_DMA);
1296                 if (!priv_info->bouncebuffer) {
1297                         ring->current_slot = old_top_slot;
1298                         ring->used_slots = old_used_slots;
1299                         err = -ENOMEM;
1300                         goto out_unmap_hdr;
1301                 }
1302
1303                 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1304                 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1305                         kfree(priv_info->bouncebuffer);
1306                         priv_info->bouncebuffer = NULL;
1307                         ring->current_slot = old_top_slot;
1308                         ring->used_slots = old_used_slots;
1309                         err = -EIO;
1310                         goto out_unmap_hdr;
1311                 }
1312         }
1313
1314         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1315
1316         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1317                 /* Tell the firmware about the cookie of the last
1318                  * mcast frame, so it can clear the more-data bit in it. */
1319                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1320                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1321         }
1322         /* Now transfer the whole frame. */
1323         wmb();
1324         ops->poke_tx(ring, next_slot(ring, slot));
1325         return 0;
1326
1327 out_unmap_hdr:
1328         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1329                          hdrsize, 1);
1330         return err;
1331 }
1332
1333 static inline int should_inject_overflow(struct b43_dmaring *ring)
1334 {
1335 #ifdef CONFIG_B43_DEBUG
1336         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1337                 /* Check if we should inject another ringbuffer overflow
1338                  * to test handling of this situation in the stack. */
1339                 unsigned long next_overflow;
1340
1341                 next_overflow = ring->last_injected_overflow + HZ;
1342                 if (time_after(jiffies, next_overflow)) {
1343                         ring->last_injected_overflow = jiffies;
1344                         b43dbg(ring->dev->wl,
1345                                "Injecting TX ring overflow on "
1346                                "DMA controller %d\n", ring->index);
1347                         return 1;
1348                 }
1349         }
1350 #endif /* CONFIG_B43_DEBUG */
1351         return 0;
1352 }
1353
1354 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1355 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1356                                                    u8 queue_prio)
1357 {
1358         struct b43_dmaring *ring;
1359
1360         if (dev->qos_enabled) {
1361                 /* 0 = highest priority */
1362                 switch (queue_prio) {
1363                 default:
1364                         B43_WARN_ON(1);
1365                         /* fallthrough */
1366                 case 0:
1367                         ring = dev->dma.tx_ring_AC_VO;
1368                         break;
1369                 case 1:
1370                         ring = dev->dma.tx_ring_AC_VI;
1371                         break;
1372                 case 2:
1373                         ring = dev->dma.tx_ring_AC_BE;
1374                         break;
1375                 case 3:
1376                         ring = dev->dma.tx_ring_AC_BK;
1377                         break;
1378                 }
1379         } else
1380                 ring = dev->dma.tx_ring_AC_BE;
1381
1382         return ring;
1383 }
1384
1385 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1386 {
1387         struct b43_dmaring *ring;
1388         struct ieee80211_hdr *hdr;
1389         int err = 0;
1390         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1391
1392         hdr = (struct ieee80211_hdr *)skb->data;
1393         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1394                 /* The multicast ring will be sent after the DTIM */
1395                 ring = dev->dma.tx_ring_mcast;
1396                 /* Set the more-data bit. Ucode will clear it on
1397                  * the last frame for us. */
1398                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1399         } else {
1400                 /* Decide by priority where to put this frame. */
1401                 ring = select_ring_by_priority(
1402                         dev, skb_get_queue_mapping(skb));
1403         }
1404
1405         B43_WARN_ON(!ring->tx);
1406
1407         if (unlikely(ring->stopped)) {
1408                 /* We get here only because of a bug in mac80211.
1409                  * Because of a race, one packet may be queued after
1410                  * the queue is stopped, thus we got called when we shouldn't.
1411                  * For now, just refuse the transmit. */
1412                 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1413                         b43err(dev->wl, "Packet after queue stopped\n");
1414                 err = -ENOSPC;
1415                 goto out;
1416         }
1417
1418         if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1419                 /* If we get here, we have a real error with the queue
1420                  * full, but queues not stopped. */
1421                 b43err(dev->wl, "DMA queue overflow\n");
1422                 err = -ENOSPC;
1423                 goto out;
1424         }
1425
1426         /* Assign the queue number to the ring (if not already done before)
1427          * so TX status handling can use it. The queue to ring mapping is
1428          * static, so we don't need to store it per frame. */
1429         ring->queue_prio = skb_get_queue_mapping(skb);
1430
1431         err = dma_tx_fragment(ring, skb);
1432         if (unlikely(err == -ENOKEY)) {
1433                 /* Drop this packet, as we don't have the encryption key
1434                  * anymore and must not transmit it unencrypted. */
1435                 dev_kfree_skb_any(skb);
1436                 err = 0;
1437                 goto out;
1438         }
1439         if (unlikely(err)) {
1440                 b43err(dev->wl, "DMA tx mapping failure\n");
1441                 goto out;
1442         }
1443         if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1444             should_inject_overflow(ring)) {
1445                 /* This TX ring is full. */
1446                 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1447                 ring->stopped = 1;
1448                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1449                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1450                 }
1451         }
1452 out:
1453
1454         return err;
1455 }
1456
1457 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1458                              const struct b43_txstatus *status)
1459 {
1460         const struct b43_dma_ops *ops;
1461         struct b43_dmaring *ring;
1462         struct b43_dmadesc_meta *meta;
1463         int slot, firstused;
1464         bool frame_succeed;
1465
1466         ring = parse_cookie(dev, status->cookie, &slot);
1467         if (unlikely(!ring))
1468                 return;
1469         B43_WARN_ON(!ring->tx);
1470
1471         /* Sanity check: TX packets are processed in-order on one ring.
1472          * Check if the slot deduced from the cookie really is the first
1473          * used slot. */
1474         firstused = ring->current_slot - ring->used_slots + 1;
1475         if (firstused < 0)
1476                 firstused = ring->nr_slots + firstused;
1477         if (unlikely(slot != firstused)) {
1478                 /* This possibly is a firmware bug and will result in
1479                  * malfunction, memory leaks and/or stall of DMA functionality. */
1480                 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1481                        "Expected %d, but got %d\n",
1482                        ring->index, firstused, slot);
1483                 return;
1484         }
1485
1486         ops = ring->ops;
1487         while (1) {
1488                 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1489                 /* get meta - ignore returned value */
1490                 ops->idx2desc(ring, slot, &meta);
1491
1492                 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1493                         b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1494                                "on ring %d\n",
1495                                slot, firstused, ring->index);
1496                         break;
1497                 }
1498                 if (meta->skb) {
1499                         struct b43_private_tx_info *priv_info =
1500                                 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1501
1502                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1503                         kfree(priv_info->bouncebuffer);
1504                         priv_info->bouncebuffer = NULL;
1505                 } else {
1506                         unmap_descbuffer(ring, meta->dmaaddr,
1507                                          b43_txhdr_size(dev), 1);
1508                 }
1509
1510                 if (meta->is_last_fragment) {
1511                         struct ieee80211_tx_info *info;
1512
1513                         if (unlikely(!meta->skb)) {
1514                                 /* This is a scatter-gather fragment of a frame, so
1515                                  * the skb pointer must not be NULL. */
1516                                 b43dbg(dev->wl, "TX status unexpected NULL skb "
1517                                        "at slot %d (first=%d) on ring %d\n",
1518                                        slot, firstused, ring->index);
1519                                 break;
1520                         }
1521
1522                         info = IEEE80211_SKB_CB(meta->skb);
1523
1524                         /*
1525                          * Call back to inform the ieee80211 subsystem about
1526                          * the status of the transmission.
1527                          */
1528                         frame_succeed = b43_fill_txstatus_report(dev, info, status);
1529 #ifdef CONFIG_B43_DEBUG
1530                         if (frame_succeed)
1531                                 ring->nr_succeed_tx_packets++;
1532                         else
1533                                 ring->nr_failed_tx_packets++;
1534                         ring->nr_total_packet_tries += status->frame_count;
1535 #endif /* DEBUG */
1536                         ieee80211_tx_status(dev->wl->hw, meta->skb);
1537
1538                         /* skb will be freed by ieee80211_tx_status().
1539                          * Poison our pointer. */
1540                         meta->skb = B43_DMA_PTR_POISON;
1541                 } else {
1542                         /* No need to call free_descriptor_buffer here, as
1543                          * this is only the txhdr, which is not allocated.
1544                          */
1545                         if (unlikely(meta->skb)) {
1546                                 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1547                                        "at slot %d (first=%d) on ring %d\n",
1548                                        slot, firstused, ring->index);
1549                                 break;
1550                         }
1551                 }
1552
1553                 /* Everything unmapped and free'd. So it's not used anymore. */
1554                 ring->used_slots--;
1555
1556                 if (meta->is_last_fragment) {
1557                         /* This is the last scatter-gather
1558                          * fragment of the frame. We are done. */
1559                         break;
1560                 }
1561                 slot = next_slot(ring, slot);
1562         }
1563         if (ring->stopped) {
1564                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1565                 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1566                 ring->stopped = 0;
1567                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1568                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1569                 }
1570         }
1571 }
1572
1573 static void dma_rx(struct b43_dmaring *ring, int *slot)
1574 {
1575         const struct b43_dma_ops *ops = ring->ops;
1576         struct b43_dmadesc_generic *desc;
1577         struct b43_dmadesc_meta *meta;
1578         struct b43_rxhdr_fw4 *rxhdr;
1579         struct sk_buff *skb;
1580         u16 len;
1581         int err;
1582         dma_addr_t dmaaddr;
1583
1584         desc = ops->idx2desc(ring, *slot, &meta);
1585
1586         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1587         skb = meta->skb;
1588
1589         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1590         len = le16_to_cpu(rxhdr->frame_len);
1591         if (len == 0) {
1592                 int i = 0;
1593
1594                 do {
1595                         udelay(2);
1596                         barrier();
1597                         len = le16_to_cpu(rxhdr->frame_len);
1598                 } while (len == 0 && i++ < 5);
1599                 if (unlikely(len == 0)) {
1600                         dmaaddr = meta->dmaaddr;
1601                         goto drop_recycle_buffer;
1602                 }
1603         }
1604         if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1605                 /* Something went wrong with the DMA.
1606                  * The device did not touch the buffer and did not overwrite the poison. */
1607                 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1608                 dmaaddr = meta->dmaaddr;
1609                 goto drop_recycle_buffer;
1610         }
1611         if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1612                 /* The data did not fit into one descriptor buffer
1613                  * and is split over multiple buffers.
1614                  * This should never happen, as we try to allocate buffers
1615                  * big enough. So simply ignore this packet.
1616                  */
1617                 int cnt = 0;
1618                 s32 tmp = len;
1619
1620                 while (1) {
1621                         desc = ops->idx2desc(ring, *slot, &meta);
1622                         /* recycle the descriptor buffer. */
1623                         b43_poison_rx_buffer(ring, meta->skb);
1624                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1625                                                    ring->rx_buffersize);
1626                         *slot = next_slot(ring, *slot);
1627                         cnt++;
1628                         tmp -= ring->rx_buffersize;
1629                         if (tmp <= 0)
1630                                 break;
1631                 }
1632                 b43err(ring->dev->wl, "DMA RX buffer too small "
1633                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1634                        len, ring->rx_buffersize, cnt);
1635                 goto drop;
1636         }
1637
1638         dmaaddr = meta->dmaaddr;
1639         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1640         if (unlikely(err)) {
1641                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1642                 goto drop_recycle_buffer;
1643         }
1644
1645         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1646         skb_put(skb, len + ring->frameoffset);
1647         skb_pull(skb, ring->frameoffset);
1648
1649         b43_rx(ring->dev, skb, rxhdr);
1650 drop:
1651         return;
1652
1653 drop_recycle_buffer:
1654         /* Poison and recycle the RX buffer. */
1655         b43_poison_rx_buffer(ring, skb);
1656         sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1657 }
1658
1659 void b43_dma_rx(struct b43_dmaring *ring)
1660 {
1661         const struct b43_dma_ops *ops = ring->ops;
1662         int slot, current_slot;
1663         int used_slots = 0;
1664
1665         B43_WARN_ON(ring->tx);
1666         current_slot = ops->get_current_rxslot(ring);
1667         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1668
1669         slot = ring->current_slot;
1670         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1671                 dma_rx(ring, &slot);
1672                 update_max_used_slots(ring, ++used_slots);
1673         }
1674         wmb();
1675         ops->set_current_rxslot(ring, slot);
1676         ring->current_slot = slot;
1677 }
1678
1679 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1680 {
1681         B43_WARN_ON(!ring->tx);
1682         ring->ops->tx_suspend(ring);
1683 }
1684
1685 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1686 {
1687         B43_WARN_ON(!ring->tx);
1688         ring->ops->tx_resume(ring);
1689 }
1690
1691 void b43_dma_tx_suspend(struct b43_wldev *dev)
1692 {
1693         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1694         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1695         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1696         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1697         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1698         b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1699 }
1700
1701 void b43_dma_tx_resume(struct b43_wldev *dev)
1702 {
1703         b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1704         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1705         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1706         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1707         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1708         b43_power_saving_ctl_bits(dev, 0);
1709 }
1710
1711 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1712                            u16 mmio_base, bool enable)
1713 {
1714         u32 ctl;
1715
1716         if (type == B43_DMA_64BIT) {
1717                 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1718                 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1719                 if (enable)
1720                         ctl |= B43_DMA64_RXDIRECTFIFO;
1721                 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1722         } else {
1723                 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1724                 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1725                 if (enable)
1726                         ctl |= B43_DMA32_RXDIRECTFIFO;
1727                 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1728         }
1729 }
1730
1731 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1732  * This is called from PIO code, so DMA structures are not available. */
1733 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1734                             unsigned int engine_index, bool enable)
1735 {
1736         enum b43_dmatype type;
1737         u16 mmio_base;
1738
1739         type = dma_mask_to_engine_type(supported_dma_mask(dev));
1740
1741         mmio_base = b43_dmacontroller_base(type, engine_index);
1742         direct_fifo_rx(dev, type, mmio_base, enable);
1743 }