drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/slab.h>
  42 #include <asm/div64.h>
  43
  44
  45 /* Required number of TX DMA slots per TX frame.
  46  * This currently is 2, because we put the header and the ieee80211 frame
  47  * into separate slots. */
  48 #define TX_SLOTS_PER_FRAME      2
  49
  50
  51 /* 32bit DMA ops. */
  52 static
  53 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  54                                           int slot,
  55                                           struct b43_dmadesc_meta **meta)
  56 {
  57         struct b43_dmadesc32 *desc;
  58
  59         *meta = &(ring->meta[slot]);
  60         desc = ring->descbase;
  61         desc = &(desc[slot]);
  62
  63         return (struct b43_dmadesc_generic *)desc;
  64 }
  65
  66 static void op32_fill_descriptor(struct b43_dmaring *ring,
  67                                  struct b43_dmadesc_generic *desc,
  68                                  dma_addr_t dmaaddr, u16 bufsize,
  69                                  int start, int end, int irq)
  70 {
  71         struct b43_dmadesc32 *descbase = ring->descbase;
  72         int slot;
  73         u32 ctl;
  74         u32 addr;
  75         u32 addrext;
  76
  77         slot = (int)(&(desc->dma32) - descbase);
  78         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
  79
  80         addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
  81         addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
  82             >> SSB_DMA_TRANSLATION_SHIFT;
  83         addr |= ssb_dma_translation(ring->dev->dev);
  84         ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
  85         if (slot == ring->nr_slots - 1)
  86                 ctl |= B43_DMA32_DCTL_DTABLEEND;
  87         if (start)
  88                 ctl |= B43_DMA32_DCTL_FRAMESTART;
  89         if (end)
  90                 ctl |= B43_DMA32_DCTL_FRAMEEND;
  91         if (irq)
  92                 ctl |= B43_DMA32_DCTL_IRQ;
  93         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
  94             & B43_DMA32_DCTL_ADDREXT_MASK;
  95
  96         desc->dma32.control = cpu_to_le32(ctl);
  97         desc->dma32.address = cpu_to_le32(addr);
  98 }
  99
 100 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
 101 {
 102         b43_dma_write(ring, B43_DMA32_TXINDEX,
 103                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 104 }
 105
 106 static void op32_tx_suspend(struct b43_dmaring *ring)
 107 {
 108         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 109                       | B43_DMA32_TXSUSPEND);
 110 }
 111
 112 static void op32_tx_resume(struct b43_dmaring *ring)
 113 {
 114         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 115                       & ~B43_DMA32_TXSUSPEND);
 116 }
 117
 118 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 119 {
 120         u32 val;
 121
 122         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 123         val &= B43_DMA32_RXDPTR;
 124
 125         return (val / sizeof(struct b43_dmadesc32));
 126 }
 127
 128 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 129 {
 130         b43_dma_write(ring, B43_DMA32_RXINDEX,
 131                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 132 }
 133
 134 static const struct b43_dma_ops dma32_ops = {
 135         .idx2desc = op32_idx2desc,
 136         .fill_descriptor = op32_fill_descriptor,
 137         .poke_tx = op32_poke_tx,
 138         .tx_suspend = op32_tx_suspend,
 139         .tx_resume = op32_tx_resume,
 140         .get_current_rxslot = op32_get_current_rxslot,
 141         .set_current_rxslot = op32_set_current_rxslot,
 142 };
 143
 144 /* 64bit DMA ops. */
 145 static
 146 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 147                                           int slot,
 148                                           struct b43_dmadesc_meta **meta)
 149 {
 150         struct b43_dmadesc64 *desc;
 151
 152         *meta = &(ring->meta[slot]);
 153         desc = ring->descbase;
 154         desc = &(desc[slot]);
 155
 156         return (struct b43_dmadesc_generic *)desc;
 157 }
 158
 159 static void op64_fill_descriptor(struct b43_dmaring *ring,
 160                                  struct b43_dmadesc_generic *desc,
 161                                  dma_addr_t dmaaddr, u16 bufsize,
 162                                  int start, int end, int irq)
 163 {
 164         struct b43_dmadesc64 *descbase = ring->descbase;
 165         int slot;
 166         u32 ctl0 = 0, ctl1 = 0;
 167         u32 addrlo, addrhi;
 168         u32 addrext;
 169
 170         slot = (int)(&(desc->dma64) - descbase);
 171         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 172
 173         addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
 174         addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
 175         addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
 176             >> SSB_DMA_TRANSLATION_SHIFT;
 177         addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
 178         if (slot == ring->nr_slots - 1)
 179                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 180         if (start)
 181                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 182         if (end)
 183                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 184         if (irq)
 185                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 186         ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
 187         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 188             & B43_DMA64_DCTL1_ADDREXT_MASK;
 189
 190         desc->dma64.control0 = cpu_to_le32(ctl0);
 191         desc->dma64.control1 = cpu_to_le32(ctl1);
 192         desc->dma64.address_low = cpu_to_le32(addrlo);
 193         desc->dma64.address_high = cpu_to_le32(addrhi);
 194 }
 195
 196 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 197 {
 198         b43_dma_write(ring, B43_DMA64_TXINDEX,
 199                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 200 }
 201
 202 static void op64_tx_suspend(struct b43_dmaring *ring)
 203 {
 204         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 205                       | B43_DMA64_TXSUSPEND);
 206 }
 207
 208 static void op64_tx_resume(struct b43_dmaring *ring)
 209 {
 210         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 211                       & ~B43_DMA64_TXSUSPEND);
 212 }
 213
 214 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 215 {
 216         u32 val;
 217
 218         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 219         val &= B43_DMA64_RXSTATDPTR;
 220
 221         return (val / sizeof(struct b43_dmadesc64));
 222 }
 223
 224 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 225 {
 226         b43_dma_write(ring, B43_DMA64_RXINDEX,
 227                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 228 }
 229
 230 static const struct b43_dma_ops dma64_ops = {
 231         .idx2desc = op64_idx2desc,
 232         .fill_descriptor = op64_fill_descriptor,
 233         .poke_tx = op64_poke_tx,
 234         .tx_suspend = op64_tx_suspend,
 235         .tx_resume = op64_tx_resume,
 236         .get_current_rxslot = op64_get_current_rxslot,
 237         .set_current_rxslot = op64_set_current_rxslot,
 238 };
 239
 240 static inline int free_slots(struct b43_dmaring *ring)
 241 {
 242         return (ring->nr_slots - ring->used_slots);
 243 }
 244
 245 static inline int next_slot(struct b43_dmaring *ring, int slot)
 246 {
 247         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 248         if (slot == ring->nr_slots - 1)
 249                 return 0;
 250         return slot + 1;
 251 }
 252
 253 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 254 {
 255         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 256         if (slot == 0)
 257                 return ring->nr_slots - 1;
 258         return slot - 1;
 259 }
 260
 261 #ifdef CONFIG_B43_DEBUG
 262 static void update_max_used_slots(struct b43_dmaring *ring,
 263                                   int current_used_slots)
 264 {
 265         if (current_used_slots <= ring->max_used_slots)
 266                 return;
 267         ring->max_used_slots = current_used_slots;
 268         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 269                 b43dbg(ring->dev->wl,
 270                        "max_used_slots increased to %d on %s ring %d\n",
 271                        ring->max_used_slots,
 272                        ring->tx ? "TX" : "RX", ring->index);
 273         }
 274 }
 275 #else
 276 static inline
 277     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 278 {
 279 }
 280 #endif /* DEBUG */
 281
 282 /* Request a slot for usage. */
 283 static inline int request_slot(struct b43_dmaring *ring)
 284 {
 285         int slot;
 286
 287         B43_WARN_ON(!ring->tx);
 288         B43_WARN_ON(ring->stopped);
 289         B43_WARN_ON(free_slots(ring) == 0);
 290
 291         slot = next_slot(ring, ring->current_slot);
 292         ring->current_slot = slot;
 293         ring->used_slots++;
 294
 295         update_max_used_slots(ring, ring->used_slots);
 296
 297         return slot;
 298 }
 299
 300 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
 301 {
 302         static const u16 map64[] = {
 303                 B43_MMIO_DMA64_BASE0,
 304                 B43_MMIO_DMA64_BASE1,
 305                 B43_MMIO_DMA64_BASE2,
 306                 B43_MMIO_DMA64_BASE3,
 307                 B43_MMIO_DMA64_BASE4,
 308                 B43_MMIO_DMA64_BASE5,
 309         };
 310         static const u16 map32[] = {
 311                 B43_MMIO_DMA32_BASE0,
 312                 B43_MMIO_DMA32_BASE1,
 313                 B43_MMIO_DMA32_BASE2,
 314                 B43_MMIO_DMA32_BASE3,
 315                 B43_MMIO_DMA32_BASE4,
 316                 B43_MMIO_DMA32_BASE5,
 317         };
 318
 319         if (type == B43_DMA_64BIT) {
 320                 B43_WARN_ON(!(controller_idx >= 0 &&
 321                               controller_idx < ARRAY_SIZE(map64)));
 322                 return map64[controller_idx];
 323         }
 324         B43_WARN_ON(!(controller_idx >= 0 &&
 325                       controller_idx < ARRAY_SIZE(map32)));
 326         return map32[controller_idx];
 327 }
 328
 329 static inline
 330     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 331                               unsigned char *buf, size_t len, int tx)
 332 {
 333         dma_addr_t dmaaddr;
 334
 335         if (tx) {
 336                 dmaaddr = ssb_dma_map_single(ring->dev->dev,
 337                                              buf, len, DMA_TO_DEVICE);
 338         } else {
 339                 dmaaddr = ssb_dma_map_single(ring->dev->dev,
 340                                              buf, len, DMA_FROM_DEVICE);
 341         }
 342
 343         return dmaaddr;
 344 }
 345
 346 static inline
 347     void unmap_descbuffer(struct b43_dmaring *ring,
 348                           dma_addr_t addr, size_t len, int tx)
 349 {
 350         if (tx) {
 351                 ssb_dma_unmap_single(ring->dev->dev,
 352                                      addr, len, DMA_TO_DEVICE);
 353         } else {
 354                 ssb_dma_unmap_single(ring->dev->dev,
 355                                      addr, len, DMA_FROM_DEVICE);
 356         }
 357 }
 358
 359 static inline
 360     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 361                                  dma_addr_t addr, size_t len)
 362 {
 363         B43_WARN_ON(ring->tx);
 364         ssb_dma_sync_single_for_cpu(ring->dev->dev,
 365                                     addr, len, DMA_FROM_DEVICE);
 366 }
 367
 368 static inline
 369     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 370                                     dma_addr_t addr, size_t len)
 371 {
 372         B43_WARN_ON(ring->tx);
 373         ssb_dma_sync_single_for_device(ring->dev->dev,
 374                                        addr, len, DMA_FROM_DEVICE);
 375 }
 376
 377 static inline
 378     void free_descriptor_buffer(struct b43_dmaring *ring,
 379                                 struct b43_dmadesc_meta *meta)
 380 {
 381         if (meta->skb) {
 382                 dev_kfree_skb_any(meta->skb);
 383                 meta->skb = NULL;
 384         }
 385 }
 386
 387 static int alloc_ringmemory(struct b43_dmaring *ring)
 388 {
 389         gfp_t flags = GFP_KERNEL;
 390
 391         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 392          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 393          * has shown that 4K is sufficient for the latter as long as the buffer
 394          * does not cross an 8K boundary.
 395          *
 396          * For unknown reasons - possibly a hardware error - the BCM4311 rev
 397          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
 398          * which accounts for the GFP_DMA flag below.
 399          *
 400          * The flags here must match the flags in free_ringmemory below!
 401          */
 402         if (ring->type == B43_DMA_64BIT)
 403                 flags |= GFP_DMA;
 404         ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
 405                                                   B43_DMA_RINGMEMSIZE,
 406                                                   &(ring->dmabase), flags);
 407         if (!ring->descbase) {
 408                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 409                 return -ENOMEM;
 410         }
 411         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 412
 413         return 0;
 414 }
 415
 416 static void free_ringmemory(struct b43_dmaring *ring)
 417 {
 418         gfp_t flags = GFP_KERNEL;
 419
 420         if (ring->type == B43_DMA_64BIT)
 421                 flags |= GFP_DMA;
 422
 423         ssb_dma_free_consistent(ring->dev->dev, B43_DMA_RINGMEMSIZE,
 424                                 ring->descbase, ring->dmabase, flags);
 425 }
 426
 427 /* Reset the RX DMA channel */
 428 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
 429                                       enum b43_dmatype type)
 430 {
 431         int i;
 432         u32 value;
 433         u16 offset;
 434
 435         might_sleep();
 436
 437         offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 438         b43_write32(dev, mmio_base + offset, 0);
 439         for (i = 0; i < 10; i++) {
 440                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
 441                                                    B43_DMA32_RXSTATUS;
 442                 value = b43_read32(dev, mmio_base + offset);
 443                 if (type == B43_DMA_64BIT) {
 444                         value &= B43_DMA64_RXSTAT;
 445                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 446                                 i = -1;
 447                                 break;
 448                         }
 449                 } else {
 450                         value &= B43_DMA32_RXSTATE;
 451                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 452                                 i = -1;
 453                                 break;
 454                         }
 455                 }
 456                 msleep(1);
 457         }
 458         if (i != -1) {
 459                 b43err(dev->wl, "DMA RX reset timed out\n");
 460                 return -ENODEV;
 461         }
 462
 463         return 0;
 464 }
 465
 466 /* Reset the TX DMA channel */
 467 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
 468                                       enum b43_dmatype type)
 469 {
 470         int i;
 471         u32 value;
 472         u16 offset;
 473
 474         might_sleep();
 475
 476         for (i = 0; i < 10; i++) {
 477                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 478                                                    B43_DMA32_TXSTATUS;
 479                 value = b43_read32(dev, mmio_base + offset);
 480                 if (type == B43_DMA_64BIT) {
 481                         value &= B43_DMA64_TXSTAT;
 482                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 483                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 484                             value == B43_DMA64_TXSTAT_STOPPED)
 485                                 break;
 486                 } else {
 487                         value &= B43_DMA32_TXSTATE;
 488                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 489                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 490                             value == B43_DMA32_TXSTAT_STOPPED)
 491                                 break;
 492                 }
 493                 msleep(1);
 494         }
 495         offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 496         b43_write32(dev, mmio_base + offset, 0);
 497         for (i = 0; i < 10; i++) {
 498                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 499                                                    B43_DMA32_TXSTATUS;
 500                 value = b43_read32(dev, mmio_base + offset);
 501                 if (type == B43_DMA_64BIT) {
 502                         value &= B43_DMA64_TXSTAT;
 503                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 504                                 i = -1;
 505                                 break;
 506                         }
 507                 } else {
 508                         value &= B43_DMA32_TXSTATE;
 509                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 510                                 i = -1;
 511                                 break;
 512                         }
 513                 }
 514                 msleep(1);
 515         }
 516         if (i != -1) {
 517                 b43err(dev->wl, "DMA TX reset timed out\n");
 518                 return -ENODEV;
 519         }
 520         /* ensure the reset is completed. */
 521         msleep(1);
 522
 523         return 0;
 524 }
 525
 526 /* Check if a DMA mapping address is invalid. */
 527 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
 528                                   dma_addr_t addr,
 529                                   size_t buffersize, bool dma_to_device)
 530 {
 531         if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
 532                 return 1;
 533
 534         switch (ring->type) {
 535         case B43_DMA_30BIT:
 536                 if ((u64)addr + buffersize > (1ULL << 30))
 537                         goto address_error;
 538                 break;
 539         case B43_DMA_32BIT:
 540                 if ((u64)addr + buffersize > (1ULL << 32))
 541                         goto address_error;
 542                 break;
 543         case B43_DMA_64BIT:
 544                 /* Currently we can't have addresses beyond
 545                  * 64bit in the kernel. */
 546                 break;
 547         }
 548
 549         /* The address is OK. */
 550         return 0;
 551
 552 address_error:
 553         /* We can't support this address. Unmap it again. */
 554         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
 555
 556         return 1;
 557 }
 558
 559 static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
 560 {
 561         unsigned char *f = skb->data + ring->frameoffset;
 562
 563         return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
 564 }
 565
 566 static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
 567 {
 568         struct b43_rxhdr_fw4 *rxhdr;
 569         unsigned char *frame;
 570
 571         /* This poisons the RX buffer to detect DMA failures. */
 572
 573         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 574         rxhdr->frame_len = 0;
 575
 576         B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
 577         frame = skb->data + ring->frameoffset;
 578         memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
 579 }
 580
 581 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 582                                struct b43_dmadesc_generic *desc,
 583                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 584 {
 585         dma_addr_t dmaaddr;
 586         struct sk_buff *skb;
 587
 588         B43_WARN_ON(ring->tx);
 589
 590         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 591         if (unlikely(!skb))
 592                 return -ENOMEM;
 593         b43_poison_rx_buffer(ring, skb);
 594         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 595         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 596                 /* ugh. try to realloc in zone_dma */
 597                 gfp_flags |= GFP_DMA;
 598
 599                 dev_kfree_skb_any(skb);
 600
 601                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 602                 if (unlikely(!skb))
 603                         return -ENOMEM;
 604                 b43_poison_rx_buffer(ring, skb);
 605                 dmaaddr = map_descbuffer(ring, skb->data,
 606                                          ring->rx_buffersize, 0);
 607                 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 608                         b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
 609                         dev_kfree_skb_any(skb);
 610                         return -EIO;
 611                 }
 612         }
 613
 614         meta->skb = skb;
 615         meta->dmaaddr = dmaaddr;
 616         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 617                                    ring->rx_buffersize, 0, 0, 0);
 618
 619         return 0;
 620 }
 621
 622 /* Allocate the initial descbuffers.
 623  * This is used for an RX ring only.
 624  */
 625 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 626 {
 627         int i, err = -ENOMEM;
 628         struct b43_dmadesc_generic *desc;
 629         struct b43_dmadesc_meta *meta;
 630
 631         for (i = 0; i < ring->nr_slots; i++) {
 632                 desc = ring->ops->idx2desc(ring, i, &meta);
 633
 634                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 635                 if (err) {
 636                         b43err(ring->dev->wl,
 637                                "Failed to allocate initial descbuffers\n");
 638                         goto err_unwind;
 639                 }
 640         }
 641         mb();
 642         ring->used_slots = ring->nr_slots;
 643         err = 0;
 644       out:
 645         return err;
 646
 647       err_unwind:
 648         for (i--; i >= 0; i--) {
 649                 desc = ring->ops->idx2desc(ring, i, &meta);
 650
 651                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 652                 dev_kfree_skb(meta->skb);
 653         }
 654         goto out;
 655 }
 656
 657 /* Do initial setup of the DMA controller.
 658  * Reset the controller, write the ring busaddress
 659  * and switch the "enable" bit on.
 660  */
 661 static int dmacontroller_setup(struct b43_dmaring *ring)
 662 {
 663         int err = 0;
 664         u32 value;
 665         u32 addrext;
 666         u32 trans = ssb_dma_translation(ring->dev->dev);
 667
 668         if (ring->tx) {
 669                 if (ring->type == B43_DMA_64BIT) {
 670                         u64 ringbase = (u64) (ring->dmabase);
 671
 672                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 673                             >> SSB_DMA_TRANSLATION_SHIFT;
 674                         value = B43_DMA64_TXENABLE;
 675                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 676                             & B43_DMA64_TXADDREXT_MASK;
 677                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 678                         b43_dma_write(ring, B43_DMA64_TXRINGLO,
 679                                       (ringbase & 0xFFFFFFFF));
 680                         b43_dma_write(ring, B43_DMA64_TXRINGHI,
 681                                       ((ringbase >> 32) &
 682                                        ~SSB_DMA_TRANSLATION_MASK)
 683                                       | (trans << 1));
 684                 } else {
 685                         u32 ringbase = (u32) (ring->dmabase);
 686
 687                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 688                             >> SSB_DMA_TRANSLATION_SHIFT;
 689                         value = B43_DMA32_TXENABLE;
 690                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 691                             & B43_DMA32_TXADDREXT_MASK;
 692                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 693                         b43_dma_write(ring, B43_DMA32_TXRING,
 694                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 695                                       | trans);
 696                 }
 697         } else {
 698                 err = alloc_initial_descbuffers(ring);
 699                 if (err)
 700                         goto out;
 701                 if (ring->type == B43_DMA_64BIT) {
 702                         u64 ringbase = (u64) (ring->dmabase);
 703
 704                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 705                             >> SSB_DMA_TRANSLATION_SHIFT;
 706                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 707                         value |= B43_DMA64_RXENABLE;
 708                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 709                             & B43_DMA64_RXADDREXT_MASK;
 710                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 711                         b43_dma_write(ring, B43_DMA64_RXRINGLO,
 712                                       (ringbase & 0xFFFFFFFF));
 713                         b43_dma_write(ring, B43_DMA64_RXRINGHI,
 714                                       ((ringbase >> 32) &
 715                                        ~SSB_DMA_TRANSLATION_MASK)
 716                                       | (trans << 1));
 717                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 718                                       sizeof(struct b43_dmadesc64));
 719                 } else {
 720                         u32 ringbase = (u32) (ring->dmabase);
 721
 722                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 723                             >> SSB_DMA_TRANSLATION_SHIFT;
 724                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 725                         value |= B43_DMA32_RXENABLE;
 726                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 727                             & B43_DMA32_RXADDREXT_MASK;
 728                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 729                         b43_dma_write(ring, B43_DMA32_RXRING,
 730                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 731                                       | trans);
 732                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 733                                       sizeof(struct b43_dmadesc32));
 734                 }
 735         }
 736
 737 out:
 738         return err;
 739 }
 740
 741 /* Shutdown the DMA controller. */
 742 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 743 {
 744         if (ring->tx) {
 745                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 746                                            ring->type);
 747                 if (ring->type == B43_DMA_64BIT) {
 748                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 749                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 750                 } else
 751                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 752         } else {
 753                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 754                                            ring->type);
 755                 if (ring->type == B43_DMA_64BIT) {
 756                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 757                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 758                 } else
 759                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 760         }
 761 }
 762
 763 static void free_all_descbuffers(struct b43_dmaring *ring)
 764 {
 765         struct b43_dmadesc_generic *desc;
 766         struct b43_dmadesc_meta *meta;
 767         int i;
 768
 769         if (!ring->used_slots)
 770                 return;
 771         for (i = 0; i < ring->nr_slots; i++) {
 772                 desc = ring->ops->idx2desc(ring, i, &meta);
 773
 774                 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
 775                         B43_WARN_ON(!ring->tx);
 776                         continue;
 777                 }
 778                 if (ring->tx) {
 779                         unmap_descbuffer(ring, meta->dmaaddr,
 780                                          meta->skb->len, 1);
 781                 } else {
 782                         unmap_descbuffer(ring, meta->dmaaddr,
 783                                          ring->rx_buffersize, 0);
 784                 }
 785                 free_descriptor_buffer(ring, meta);
 786         }
 787 }
 788
 789 static u64 supported_dma_mask(struct b43_wldev *dev)
 790 {
 791         u32 tmp;
 792         u16 mmio_base;
 793
 794         tmp = b43_read32(dev, SSB_TMSHIGH);
 795         if (tmp & SSB_TMSHIGH_DMA64)
 796                 return DMA_BIT_MASK(64);
 797         mmio_base = b43_dmacontroller_base(0, 0);
 798         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 799         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 800         if (tmp & B43_DMA32_TXADDREXT_MASK)
 801                 return DMA_BIT_MASK(32);
 802
 803         return DMA_BIT_MASK(30);
 804 }
 805
 806 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
 807 {
 808         if (dmamask == DMA_BIT_MASK(30))
 809                 return B43_DMA_30BIT;
 810         if (dmamask == DMA_BIT_MASK(32))
 811                 return B43_DMA_32BIT;
 812         if (dmamask == DMA_BIT_MASK(64))
 813                 return B43_DMA_64BIT;
 814         B43_WARN_ON(1);
 815         return B43_DMA_30BIT;
 816 }
 817
 818 /* Main initialization function. */
 819 static
 820 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 821                                       int controller_index,
 822                                       int for_tx,
 823                                       enum b43_dmatype type)
 824 {
 825         struct b43_dmaring *ring;
 826         int i, err;
 827         dma_addr_t dma_test;
 828
 829         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 830         if (!ring)
 831                 goto out;
 832
 833         ring->nr_slots = B43_RXRING_SLOTS;
 834         if (for_tx)
 835                 ring->nr_slots = B43_TXRING_SLOTS;
 836
 837         ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
 838                              GFP_KERNEL);
 839         if (!ring->meta)
 840                 goto err_kfree_ring;
 841         for (i = 0; i < ring->nr_slots; i++)
 842                 ring->meta->skb = B43_DMA_PTR_POISON;
 843
 844         ring->type = type;
 845         ring->dev = dev;
 846         ring->mmio_base = b43_dmacontroller_base(type, controller_index);
 847         ring->index = controller_index;
 848         if (type == B43_DMA_64BIT)
 849                 ring->ops = &dma64_ops;
 850         else
 851                 ring->ops = &dma32_ops;
 852         if (for_tx) {
 853                 ring->tx = 1;
 854                 ring->current_slot = -1;
 855         } else {
 856                 if (ring->index == 0) {
 857                         ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
 858                         ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
 859                 } else
 860                         B43_WARN_ON(1);
 861         }
 862 #ifdef CONFIG_B43_DEBUG
 863         ring->last_injected_overflow = jiffies;
 864 #endif
 865
 866         if (for_tx) {
 867                 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
 868                 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
 869
 870                 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 871                                             b43_txhdr_size(dev),
 872                                             GFP_KERNEL);
 873                 if (!ring->txhdr_cache)
 874                         goto err_kfree_meta;
 875
 876                 /* test for ability to dma to txhdr_cache */
 877                 dma_test = ssb_dma_map_single(dev->dev,
 878                                               ring->txhdr_cache,
 879                                               b43_txhdr_size(dev),
 880                                               DMA_TO_DEVICE);
 881
 882                 if (b43_dma_mapping_error(ring, dma_test,
 883                                           b43_txhdr_size(dev), 1)) {
 884                         /* ugh realloc */
 885                         kfree(ring->txhdr_cache);
 886                         ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
 887                                                     b43_txhdr_size(dev),
 888                                                     GFP_KERNEL | GFP_DMA);
 889                         if (!ring->txhdr_cache)
 890                                 goto err_kfree_meta;
 891
 892                         dma_test = ssb_dma_map_single(dev->dev,
 893                                                       ring->txhdr_cache,
 894                                                       b43_txhdr_size(dev),
 895                                                       DMA_TO_DEVICE);
 896
 897                         if (b43_dma_mapping_error(ring, dma_test,
 898                                                   b43_txhdr_size(dev), 1)) {
 899
 900                                 b43err(dev->wl,
 901                                        "TXHDR DMA allocation failed\n");
 902                                 goto err_kfree_txhdr_cache;
 903                         }
 904                 }
 905
 906                 ssb_dma_unmap_single(dev->dev,
 907                                      dma_test, b43_txhdr_size(dev),
 908                                      DMA_TO_DEVICE);
 909         }
 910
 911         err = alloc_ringmemory(ring);
 912         if (err)
 913                 goto err_kfree_txhdr_cache;
 914         err = dmacontroller_setup(ring);
 915         if (err)
 916                 goto err_free_ringmemory;
 917
 918       out:
 919         return ring;
 920
 921       err_free_ringmemory:
 922         free_ringmemory(ring);
 923       err_kfree_txhdr_cache:
 924         kfree(ring->txhdr_cache);
 925       err_kfree_meta:
 926         kfree(ring->meta);
 927       err_kfree_ring:
 928         kfree(ring);
 929         ring = NULL;
 930         goto out;
 931 }
 932
 933 #define divide(a, b)    ({      \
 934         typeof(a) __a = a;      \
 935         do_div(__a, b);         \
 936         __a;                    \
 937   })
 938
 939 #define modulo(a, b)    ({      \
 940         typeof(a) __a = a;      \
 941         do_div(__a, b);         \
 942   })
 943
 944 /* Main cleanup function. */
 945 static void b43_destroy_dmaring(struct b43_dmaring *ring,
 946                                 const char *ringname)
 947 {
 948         if (!ring)
 949                 return;
 950
 951 #ifdef CONFIG_B43_DEBUG
 952         {
 953                 /* Print some statistics. */
 954                 u64 failed_packets = ring->nr_failed_tx_packets;
 955                 u64 succeed_packets = ring->nr_succeed_tx_packets;
 956                 u64 nr_packets = failed_packets + succeed_packets;
 957                 u64 permille_failed = 0, average_tries = 0;
 958
 959                 if (nr_packets)
 960                         permille_failed = divide(failed_packets * 1000, nr_packets);
 961                 if (nr_packets)
 962                         average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
 963
 964                 b43dbg(ring->dev->wl, "DMA-%u %s: "
 965                        "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
 966                        "Average tries %llu.%02llu\n",
 967                        (unsigned int)(ring->type), ringname,
 968                        ring->max_used_slots,
 969                        ring->nr_slots,
 970                        (unsigned long long)failed_packets,
 971                        (unsigned long long)nr_packets,
 972                        (unsigned long long)divide(permille_failed, 10),
 973                        (unsigned long long)modulo(permille_failed, 10),
 974                        (unsigned long long)divide(average_tries, 100),
 975                        (unsigned long long)modulo(average_tries, 100));
 976         }
 977 #endif /* DEBUG */
 978
 979         /* Device IRQs are disabled prior entering this function,
 980          * so no need to take care of concurrency with rx handler stuff.
 981          */
 982         dmacontroller_cleanup(ring);
 983         free_all_descbuffers(ring);
 984         free_ringmemory(ring);
 985
 986         kfree(ring->txhdr_cache);
 987         kfree(ring->meta);
 988         kfree(ring);
 989 }
 990
 991 #define destroy_ring(dma, ring) do {                            \
 992         b43_destroy_dmaring((dma)->ring, __stringify(ring));    \
 993         (dma)->ring = NULL;                                     \
 994     } while (0)
 995
 996 void b43_dma_free(struct b43_wldev *dev)
 997 {
 998         struct b43_dma *dma;
 999
1000         if (b43_using_pio_transfers(dev))
1001                 return;
1002         dma = &dev->dma;
1003
1004         destroy_ring(dma, rx_ring);
1005         destroy_ring(dma, tx_ring_AC_BK);
1006         destroy_ring(dma, tx_ring_AC_BE);
1007         destroy_ring(dma, tx_ring_AC_VI);
1008         destroy_ring(dma, tx_ring_AC_VO);
1009         destroy_ring(dma, tx_ring_mcast);
1010 }
1011
1012 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1013 {
1014         u64 orig_mask = mask;
1015         bool fallback = 0;
1016         int err;
1017
1018         /* Try to set the DMA mask. If it fails, try falling back to a
1019          * lower mask, as we can always also support a lower one. */
1020         while (1) {
1021                 err = ssb_dma_set_mask(dev->dev, mask);
1022                 if (!err)
1023                         break;
1024                 if (mask == DMA_BIT_MASK(64)) {
1025                         mask = DMA_BIT_MASK(32);
1026                         fallback = 1;
1027                         continue;
1028                 }
1029                 if (mask == DMA_BIT_MASK(32)) {
1030                         mask = DMA_BIT_MASK(30);
1031                         fallback = 1;
1032                         continue;
1033                 }
1034                 b43err(dev->wl, "The machine/kernel does not support "
1035                        "the required %u-bit DMA mask\n",
1036                        (unsigned int)dma_mask_to_engine_type(orig_mask));
1037                 return -EOPNOTSUPP;
1038         }
1039         if (fallback) {
1040                 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1041                         (unsigned int)dma_mask_to_engine_type(orig_mask),
1042                         (unsigned int)dma_mask_to_engine_type(mask));
1043         }
1044
1045         return 0;
1046 }
1047
1048 int b43_dma_init(struct b43_wldev *dev)
1049 {
1050         struct b43_dma *dma = &dev->dma;
1051         int err;
1052         u64 dmamask;
1053         enum b43_dmatype type;
1054
1055         dmamask = supported_dma_mask(dev);
1056         type = dma_mask_to_engine_type(dmamask);
1057         err = b43_dma_set_mask(dev, dmamask);
1058         if (err)
1059                 return err;
1060
1061         err = -ENOMEM;
1062         /* setup TX DMA channels. */
1063         dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1064         if (!dma->tx_ring_AC_BK)
1065                 goto out;
1066
1067         dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1068         if (!dma->tx_ring_AC_BE)
1069                 goto err_destroy_bk;
1070
1071         dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1072         if (!dma->tx_ring_AC_VI)
1073                 goto err_destroy_be;
1074
1075         dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1076         if (!dma->tx_ring_AC_VO)
1077                 goto err_destroy_vi;
1078
1079         dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1080         if (!dma->tx_ring_mcast)
1081                 goto err_destroy_vo;
1082
1083         /* setup RX DMA channel. */
1084         dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1085         if (!dma->rx_ring)
1086                 goto err_destroy_mcast;
1087
1088         /* No support for the TX status DMA ring. */
1089         B43_WARN_ON(dev->dev->id.revision < 5);
1090
1091         b43dbg(dev->wl, "%u-bit DMA initialized\n",
1092                (unsigned int)type);
1093         err = 0;
1094 out:
1095         return err;
1096
1097 err_destroy_mcast:
1098         destroy_ring(dma, tx_ring_mcast);
1099 err_destroy_vo:
1100         destroy_ring(dma, tx_ring_AC_VO);
1101 err_destroy_vi:
1102         destroy_ring(dma, tx_ring_AC_VI);
1103 err_destroy_be:
1104         destroy_ring(dma, tx_ring_AC_BE);
1105 err_destroy_bk:
1106         destroy_ring(dma, tx_ring_AC_BK);
1107         return err;
1108 }
1109
1110 /* Generate a cookie for the TX header. */
1111 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1112 {
1113         u16 cookie;
1114
1115         /* Use the upper 4 bits of the cookie as
1116          * DMA controller ID and store the slot number
1117          * in the lower 12 bits.
1118          * Note that the cookie must never be 0, as this
1119          * is a special value used in RX path.
1120          * It can also not be 0xFFFF because that is special
1121          * for multicast frames.
1122          */
1123         cookie = (((u16)ring->index + 1) << 12);
1124         B43_WARN_ON(slot & ~0x0FFF);
1125         cookie |= (u16)slot;
1126
1127         return cookie;
1128 }
1129
1130 /* Inspect a cookie and find out to which controller/slot it belongs. */
1131 static
1132 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1133 {
1134         struct b43_dma *dma = &dev->dma;
1135         struct b43_dmaring *ring = NULL;
1136
1137         switch (cookie & 0xF000) {
1138         case 0x1000:
1139                 ring = dma->tx_ring_AC_BK;
1140                 break;
1141         case 0x2000:
1142                 ring = dma->tx_ring_AC_BE;
1143                 break;
1144         case 0x3000:
1145                 ring = dma->tx_ring_AC_VI;
1146                 break;
1147         case 0x4000:
1148                 ring = dma->tx_ring_AC_VO;
1149                 break;
1150         case 0x5000:
1151                 ring = dma->tx_ring_mcast;
1152                 break;
1153         }
1154         *slot = (cookie & 0x0FFF);
1155         if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1156                 b43dbg(dev->wl, "TX-status contains "
1157                        "invalid cookie: 0x%04X\n", cookie);
1158                 return NULL;
1159         }
1160
1161         return ring;
1162 }
1163
1164 static int dma_tx_fragment(struct b43_dmaring *ring,
1165                            struct sk_buff *skb)
1166 {
1167         const struct b43_dma_ops *ops = ring->ops;
1168         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1169         struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1170         u8 *header;
1171         int slot, old_top_slot, old_used_slots;
1172         int err;
1173         struct b43_dmadesc_generic *desc;
1174         struct b43_dmadesc_meta *meta;
1175         struct b43_dmadesc_meta *meta_hdr;
1176         u16 cookie;
1177         size_t hdrsize = b43_txhdr_size(ring->dev);
1178
1179         /* Important note: If the number of used DMA slots per TX frame
1180          * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1181          * the file has to be updated, too!
1182          */
1183
1184         old_top_slot = ring->current_slot;
1185         old_used_slots = ring->used_slots;
1186
1187         /* Get a slot for the header. */
1188         slot = request_slot(ring);
1189         desc = ops->idx2desc(ring, slot, &meta_hdr);
1190         memset(meta_hdr, 0, sizeof(*meta_hdr));
1191
1192         header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1193         cookie = generate_cookie(ring, slot);
1194         err = b43_generate_txhdr(ring->dev, header,
1195                                  skb, info, cookie);
1196         if (unlikely(err)) {
1197                 ring->current_slot = old_top_slot;
1198                 ring->used_slots = old_used_slots;
1199                 return err;
1200         }
1201
1202         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1203                                            hdrsize, 1);
1204         if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1205                 ring->current_slot = old_top_slot;
1206                 ring->used_slots = old_used_slots;
1207                 return -EIO;
1208         }
1209         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1210                              hdrsize, 1, 0, 0);
1211
1212         /* Get a slot for the payload. */
1213         slot = request_slot(ring);
1214         desc = ops->idx2desc(ring, slot, &meta);
1215         memset(meta, 0, sizeof(*meta));
1216
1217         meta->skb = skb;
1218         meta->is_last_fragment = 1;
1219         priv_info->bouncebuffer = NULL;
1220
1221         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1222         /* create a bounce buffer in zone_dma on mapping failure. */
1223         if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1224                 priv_info->bouncebuffer = kmalloc(skb->len, GFP_ATOMIC | GFP_DMA);
1225                 if (!priv_info->bouncebuffer) {
1226                         ring->current_slot = old_top_slot;
1227                         ring->used_slots = old_used_slots;
1228                         err = -ENOMEM;
1229                         goto out_unmap_hdr;
1230                 }
1231                 memcpy(priv_info->bouncebuffer, skb->data, skb->len);
1232
1233                 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1234                 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1235                         kfree(priv_info->bouncebuffer);
1236                         priv_info->bouncebuffer = NULL;
1237                         ring->current_slot = old_top_slot;
1238                         ring->used_slots = old_used_slots;
1239                         err = -EIO;
1240                         goto out_unmap_hdr;
1241                 }
1242         }
1243
1244         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1245
1246         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1247                 /* Tell the firmware about the cookie of the last
1248                  * mcast frame, so it can clear the more-data bit in it. */
1249                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1250                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1251         }
1252         /* Now transfer the whole frame. */
1253         wmb();
1254         ops->poke_tx(ring, next_slot(ring, slot));
1255         return 0;
1256
1257 out_unmap_hdr:
1258         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1259                          hdrsize, 1);
1260         return err;
1261 }
1262
1263 static inline int should_inject_overflow(struct b43_dmaring *ring)
1264 {
1265 #ifdef CONFIG_B43_DEBUG
1266         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1267                 /* Check if we should inject another ringbuffer overflow
1268                  * to test handling of this situation in the stack. */
1269                 unsigned long next_overflow;
1270
1271                 next_overflow = ring->last_injected_overflow + HZ;
1272                 if (time_after(jiffies, next_overflow)) {
1273                         ring->last_injected_overflow = jiffies;
1274                         b43dbg(ring->dev->wl,
1275                                "Injecting TX ring overflow on "
1276                                "DMA controller %d\n", ring->index);
1277                         return 1;
1278                 }
1279         }
1280 #endif /* CONFIG_B43_DEBUG */
1281         return 0;
1282 }
1283
1284 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1285 static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1286                                                    u8 queue_prio)
1287 {
1288         struct b43_dmaring *ring;
1289
1290         if (dev->qos_enabled) {
1291                 /* 0 = highest priority */
1292                 switch (queue_prio) {
1293                 default:
1294                         B43_WARN_ON(1);
1295                         /* fallthrough */
1296                 case 0:
1297                         ring = dev->dma.tx_ring_AC_VO;
1298                         break;
1299                 case 1:
1300                         ring = dev->dma.tx_ring_AC_VI;
1301                         break;
1302                 case 2:
1303                         ring = dev->dma.tx_ring_AC_BE;
1304                         break;
1305                 case 3:
1306                         ring = dev->dma.tx_ring_AC_BK;
1307                         break;
1308                 }
1309         } else
1310                 ring = dev->dma.tx_ring_AC_BE;
1311
1312         return ring;
1313 }
1314
1315 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1316 {
1317         struct b43_dmaring *ring;
1318         struct ieee80211_hdr *hdr;
1319         int err = 0;
1320         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1321
1322         hdr = (struct ieee80211_hdr *)skb->data;
1323         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1324                 /* The multicast ring will be sent after the DTIM */
1325                 ring = dev->dma.tx_ring_mcast;
1326                 /* Set the more-data bit. Ucode will clear it on
1327                  * the last frame for us. */
1328                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1329         } else {
1330                 /* Decide by priority where to put this frame. */
1331                 ring = select_ring_by_priority(
1332                         dev, skb_get_queue_mapping(skb));
1333         }
1334
1335         B43_WARN_ON(!ring->tx);
1336
1337         if (unlikely(ring->stopped)) {
1338                 /* We get here only because of a bug in mac80211.
1339                  * Because of a race, one packet may be queued after
1340                  * the queue is stopped, thus we got called when we shouldn't.
1341                  * For now, just refuse the transmit. */
1342                 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1343                         b43err(dev->wl, "Packet after queue stopped\n");
1344                 err = -ENOSPC;
1345                 goto out;
1346         }
1347
1348         if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1349                 /* If we get here, we have a real error with the queue
1350                  * full, but queues not stopped. */
1351                 b43err(dev->wl, "DMA queue overflow\n");
1352                 err = -ENOSPC;
1353                 goto out;
1354         }
1355
1356         /* Assign the queue number to the ring (if not already done before)
1357          * so TX status handling can use it. The queue to ring mapping is
1358          * static, so we don't need to store it per frame. */
1359         ring->queue_prio = skb_get_queue_mapping(skb);
1360
1361         err = dma_tx_fragment(ring, skb);
1362         if (unlikely(err == -ENOKEY)) {
1363                 /* Drop this packet, as we don't have the encryption key
1364                  * anymore and must not transmit it unencrypted. */
1365                 dev_kfree_skb_any(skb);
1366                 err = 0;
1367                 goto out;
1368         }
1369         if (unlikely(err)) {
1370                 b43err(dev->wl, "DMA tx mapping failure\n");
1371                 goto out;
1372         }
1373         if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1374             should_inject_overflow(ring)) {
1375                 /* This TX ring is full. */
1376                 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1377                 ring->stopped = 1;
1378                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1379                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1380                 }
1381         }
1382 out:
1383
1384         return err;
1385 }
1386
1387 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1388                              const struct b43_txstatus *status)
1389 {
1390         const struct b43_dma_ops *ops;
1391         struct b43_dmaring *ring;
1392         struct b43_dmadesc_generic *desc;
1393         struct b43_dmadesc_meta *meta;
1394         int slot, firstused;
1395         bool frame_succeed;
1396
1397         ring = parse_cookie(dev, status->cookie, &slot);
1398         if (unlikely(!ring))
1399                 return;
1400         B43_WARN_ON(!ring->tx);
1401
1402         /* Sanity check: TX packets are processed in-order on one ring.
1403          * Check if the slot deduced from the cookie really is the first
1404          * used slot. */
1405         firstused = ring->current_slot - ring->used_slots + 1;
1406         if (firstused < 0)
1407                 firstused = ring->nr_slots + firstused;
1408         if (unlikely(slot != firstused)) {
1409                 /* This possibly is a firmware bug and will result in
1410                  * malfunction, memory leaks and/or stall of DMA functionality. */
1411                 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1412                        "Expected %d, but got %d\n",
1413                        ring->index, firstused, slot);
1414                 return;
1415         }
1416
1417         ops = ring->ops;
1418         while (1) {
1419                 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1420                 desc = ops->idx2desc(ring, slot, &meta);
1421
1422                 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1423                         b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1424                                "on ring %d\n",
1425                                slot, firstused, ring->index);
1426                         break;
1427                 }
1428                 if (meta->skb) {
1429                         struct b43_private_tx_info *priv_info =
1430                                 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1431
1432                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1433                         kfree(priv_info->bouncebuffer);
1434                         priv_info->bouncebuffer = NULL;
1435                 } else {
1436                         unmap_descbuffer(ring, meta->dmaaddr,
1437                                          b43_txhdr_size(dev), 1);
1438                 }
1439
1440                 if (meta->is_last_fragment) {
1441                         struct ieee80211_tx_info *info;
1442
1443                         if (unlikely(!meta->skb)) {
1444                                 /* This is a scatter-gather fragment of a frame, so
1445                                  * the skb pointer must not be NULL. */
1446                                 b43dbg(dev->wl, "TX status unexpected NULL skb "
1447                                        "at slot %d (first=%d) on ring %d\n",
1448                                        slot, firstused, ring->index);
1449                                 break;
1450                         }
1451
1452                         info = IEEE80211_SKB_CB(meta->skb);
1453
1454                         /*
1455                          * Call back to inform the ieee80211 subsystem about
1456                          * the status of the transmission.
1457                          */
1458                         frame_succeed = b43_fill_txstatus_report(dev, info, status);
1459 #ifdef CONFIG_B43_DEBUG
1460                         if (frame_succeed)
1461                                 ring->nr_succeed_tx_packets++;
1462                         else
1463                                 ring->nr_failed_tx_packets++;
1464                         ring->nr_total_packet_tries += status->frame_count;
1465 #endif /* DEBUG */
1466                         ieee80211_tx_status(dev->wl->hw, meta->skb);
1467
1468                         /* skb will be freed by ieee80211_tx_status().
1469                          * Poison our pointer. */
1470                         meta->skb = B43_DMA_PTR_POISON;
1471                 } else {
1472                         /* No need to call free_descriptor_buffer here, as
1473                          * this is only the txhdr, which is not allocated.
1474                          */
1475                         if (unlikely(meta->skb)) {
1476                                 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1477                                        "at slot %d (first=%d) on ring %d\n",
1478                                        slot, firstused, ring->index);
1479                                 break;
1480                         }
1481                 }
1482
1483                 /* Everything unmapped and free'd. So it's not used anymore. */
1484                 ring->used_slots--;
1485
1486                 if (meta->is_last_fragment) {
1487                         /* This is the last scatter-gather
1488                          * fragment of the frame. We are done. */
1489                         break;
1490                 }
1491                 slot = next_slot(ring, slot);
1492         }
1493         if (ring->stopped) {
1494                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1495                 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1496                 ring->stopped = 0;
1497                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1498                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1499                 }
1500         }
1501 }
1502
1503 static void dma_rx(struct b43_dmaring *ring, int *slot)
1504 {
1505         const struct b43_dma_ops *ops = ring->ops;
1506         struct b43_dmadesc_generic *desc;
1507         struct b43_dmadesc_meta *meta;
1508         struct b43_rxhdr_fw4 *rxhdr;
1509         struct sk_buff *skb;
1510         u16 len;
1511         int err;
1512         dma_addr_t dmaaddr;
1513
1514         desc = ops->idx2desc(ring, *slot, &meta);
1515
1516         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1517         skb = meta->skb;
1518
1519         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1520         len = le16_to_cpu(rxhdr->frame_len);
1521         if (len == 0) {
1522                 int i = 0;
1523
1524                 do {
1525                         udelay(2);
1526                         barrier();
1527                         len = le16_to_cpu(rxhdr->frame_len);
1528                 } while (len == 0 && i++ < 5);
1529                 if (unlikely(len == 0)) {
1530                         dmaaddr = meta->dmaaddr;
1531                         goto drop_recycle_buffer;
1532                 }
1533         }
1534         if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1535                 /* Something went wrong with the DMA.
1536                  * The device did not touch the buffer and did not overwrite the poison. */
1537                 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1538                 dmaaddr = meta->dmaaddr;
1539                 goto drop_recycle_buffer;
1540         }
1541         if (unlikely(len > ring->rx_buffersize)) {
1542                 /* The data did not fit into one descriptor buffer
1543                  * and is split over multiple buffers.
1544                  * This should never happen, as we try to allocate buffers
1545                  * big enough. So simply ignore this packet.
1546                  */
1547                 int cnt = 0;
1548                 s32 tmp = len;
1549
1550                 while (1) {
1551                         desc = ops->idx2desc(ring, *slot, &meta);
1552                         /* recycle the descriptor buffer. */
1553                         b43_poison_rx_buffer(ring, meta->skb);
1554                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1555                                                    ring->rx_buffersize);
1556                         *slot = next_slot(ring, *slot);
1557                         cnt++;
1558                         tmp -= ring->rx_buffersize;
1559                         if (tmp <= 0)
1560                                 break;
1561                 }
1562                 b43err(ring->dev->wl, "DMA RX buffer too small "
1563                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1564                        len, ring->rx_buffersize, cnt);
1565                 goto drop;
1566         }
1567
1568         dmaaddr = meta->dmaaddr;
1569         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1570         if (unlikely(err)) {
1571                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1572                 goto drop_recycle_buffer;
1573         }
1574
1575         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1576         skb_put(skb, len + ring->frameoffset);
1577         skb_pull(skb, ring->frameoffset);
1578
1579         b43_rx(ring->dev, skb, rxhdr);
1580 drop:
1581         return;
1582
1583 drop_recycle_buffer:
1584         /* Poison and recycle the RX buffer. */
1585         b43_poison_rx_buffer(ring, skb);
1586         sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1587 }
1588
1589 void b43_dma_rx(struct b43_dmaring *ring)
1590 {
1591         const struct b43_dma_ops *ops = ring->ops;
1592         int slot, current_slot;
1593         int used_slots = 0;
1594
1595         B43_WARN_ON(ring->tx);
1596         current_slot = ops->get_current_rxslot(ring);
1597         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1598
1599         slot = ring->current_slot;
1600         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1601                 dma_rx(ring, &slot);
1602                 update_max_used_slots(ring, ++used_slots);
1603         }
1604         ops->set_current_rxslot(ring, slot);
1605         ring->current_slot = slot;
1606 }
1607
1608 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1609 {
1610         B43_WARN_ON(!ring->tx);
1611         ring->ops->tx_suspend(ring);
1612 }
1613
1614 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1615 {
1616         B43_WARN_ON(!ring->tx);
1617         ring->ops->tx_resume(ring);
1618 }
1619
1620 void b43_dma_tx_suspend(struct b43_wldev *dev)
1621 {
1622         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1623         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1624         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1625         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1626         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1627         b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1628 }
1629
1630 void b43_dma_tx_resume(struct b43_wldev *dev)
1631 {
1632         b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1633         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1634         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1635         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1636         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1637         b43_power_saving_ctl_bits(dev, 0);
1638 }
1639
1640 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1641                            u16 mmio_base, bool enable)
1642 {
1643         u32 ctl;
1644
1645         if (type == B43_DMA_64BIT) {
1646                 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1647                 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1648                 if (enable)
1649                         ctl |= B43_DMA64_RXDIRECTFIFO;
1650                 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1651         } else {
1652                 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1653                 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1654                 if (enable)
1655                         ctl |= B43_DMA32_RXDIRECTFIFO;
1656                 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1657         }
1658 }
1659
1660 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1661  * This is called from PIO code, so DMA structures are not available. */
1662 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1663                             unsigned int engine_index, bool enable)
1664 {
1665         enum b43_dmatype type;
1666         u16 mmio_base;
1667
1668         type = dma_mask_to_engine_type(supported_dma_mask(dev));
1669
1670         mmio_base = b43_dmacontroller_base(type, engine_index);
1671         direct_fifo_rx(dev, type, mmio_base, enable);
1672 }