3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
88 static const struct ssb_device_id b43_ssb_tbl[] = {
89 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
90 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
91 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
92 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
99 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
101 /* Channel and ratetables are shared for all devices.
102 * They can't be const, because ieee80211 puts some precalculated
103 * data in there. This data is the same for all devices, so we don't
104 * get concurrency issues */
105 #define RATETAB_ENT(_rateid, _flags) \
107 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
108 .hw_value = (_rateid), \
113 * NOTE: When changing this, sync with xmit.c's
114 * b43_plcp_get_bitrate_idx_* functions!
116 static struct ieee80211_rate __b43_ratetable[] = {
117 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
118 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
119 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
120 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
122 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
123 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
124 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
125 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
131 #define b43_a_ratetable (__b43_ratetable + 4)
132 #define b43_a_ratetable_size 8
133 #define b43_b_ratetable (__b43_ratetable + 0)
134 #define b43_b_ratetable_size 4
135 #define b43_g_ratetable (__b43_ratetable + 0)
136 #define b43_g_ratetable_size 12
138 #define CHAN4G(_channel, _freq, _flags) { \
139 .band = IEEE80211_BAND_2GHZ, \
140 .center_freq = (_freq), \
141 .hw_value = (_channel), \
143 .max_antenna_gain = 0, \
146 static struct ieee80211_channel b43_2ghz_chantable[] = {
164 #define CHAN5G(_channel, _flags) { \
165 .band = IEEE80211_BAND_5GHZ, \
166 .center_freq = 5000 + (5 * (_channel)), \
167 .hw_value = (_channel), \
169 .max_antenna_gain = 0, \
172 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
173 CHAN5G(32, 0), CHAN5G(34, 0),
174 CHAN5G(36, 0), CHAN5G(38, 0),
175 CHAN5G(40, 0), CHAN5G(42, 0),
176 CHAN5G(44, 0), CHAN5G(46, 0),
177 CHAN5G(48, 0), CHAN5G(50, 0),
178 CHAN5G(52, 0), CHAN5G(54, 0),
179 CHAN5G(56, 0), CHAN5G(58, 0),
180 CHAN5G(60, 0), CHAN5G(62, 0),
181 CHAN5G(64, 0), CHAN5G(66, 0),
182 CHAN5G(68, 0), CHAN5G(70, 0),
183 CHAN5G(72, 0), CHAN5G(74, 0),
184 CHAN5G(76, 0), CHAN5G(78, 0),
185 CHAN5G(80, 0), CHAN5G(82, 0),
186 CHAN5G(84, 0), CHAN5G(86, 0),
187 CHAN5G(88, 0), CHAN5G(90, 0),
188 CHAN5G(92, 0), CHAN5G(94, 0),
189 CHAN5G(96, 0), CHAN5G(98, 0),
190 CHAN5G(100, 0), CHAN5G(102, 0),
191 CHAN5G(104, 0), CHAN5G(106, 0),
192 CHAN5G(108, 0), CHAN5G(110, 0),
193 CHAN5G(112, 0), CHAN5G(114, 0),
194 CHAN5G(116, 0), CHAN5G(118, 0),
195 CHAN5G(120, 0), CHAN5G(122, 0),
196 CHAN5G(124, 0), CHAN5G(126, 0),
197 CHAN5G(128, 0), CHAN5G(130, 0),
198 CHAN5G(132, 0), CHAN5G(134, 0),
199 CHAN5G(136, 0), CHAN5G(138, 0),
200 CHAN5G(140, 0), CHAN5G(142, 0),
201 CHAN5G(144, 0), CHAN5G(145, 0),
202 CHAN5G(146, 0), CHAN5G(147, 0),
203 CHAN5G(148, 0), CHAN5G(149, 0),
204 CHAN5G(150, 0), CHAN5G(151, 0),
205 CHAN5G(152, 0), CHAN5G(153, 0),
206 CHAN5G(154, 0), CHAN5G(155, 0),
207 CHAN5G(156, 0), CHAN5G(157, 0),
208 CHAN5G(158, 0), CHAN5G(159, 0),
209 CHAN5G(160, 0), CHAN5G(161, 0),
210 CHAN5G(162, 0), CHAN5G(163, 0),
211 CHAN5G(164, 0), CHAN5G(165, 0),
212 CHAN5G(166, 0), CHAN5G(168, 0),
213 CHAN5G(170, 0), CHAN5G(172, 0),
214 CHAN5G(174, 0), CHAN5G(176, 0),
215 CHAN5G(178, 0), CHAN5G(180, 0),
216 CHAN5G(182, 0), CHAN5G(184, 0),
217 CHAN5G(186, 0), CHAN5G(188, 0),
218 CHAN5G(190, 0), CHAN5G(192, 0),
219 CHAN5G(194, 0), CHAN5G(196, 0),
220 CHAN5G(198, 0), CHAN5G(200, 0),
221 CHAN5G(202, 0), CHAN5G(204, 0),
222 CHAN5G(206, 0), CHAN5G(208, 0),
223 CHAN5G(210, 0), CHAN5G(212, 0),
224 CHAN5G(214, 0), CHAN5G(216, 0),
225 CHAN5G(218, 0), CHAN5G(220, 0),
226 CHAN5G(222, 0), CHAN5G(224, 0),
227 CHAN5G(226, 0), CHAN5G(228, 0),
230 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
231 CHAN5G(34, 0), CHAN5G(36, 0),
232 CHAN5G(38, 0), CHAN5G(40, 0),
233 CHAN5G(42, 0), CHAN5G(44, 0),
234 CHAN5G(46, 0), CHAN5G(48, 0),
235 CHAN5G(52, 0), CHAN5G(56, 0),
236 CHAN5G(60, 0), CHAN5G(64, 0),
237 CHAN5G(100, 0), CHAN5G(104, 0),
238 CHAN5G(108, 0), CHAN5G(112, 0),
239 CHAN5G(116, 0), CHAN5G(120, 0),
240 CHAN5G(124, 0), CHAN5G(128, 0),
241 CHAN5G(132, 0), CHAN5G(136, 0),
242 CHAN5G(140, 0), CHAN5G(149, 0),
243 CHAN5G(153, 0), CHAN5G(157, 0),
244 CHAN5G(161, 0), CHAN5G(165, 0),
245 CHAN5G(184, 0), CHAN5G(188, 0),
246 CHAN5G(192, 0), CHAN5G(196, 0),
247 CHAN5G(200, 0), CHAN5G(204, 0),
248 CHAN5G(208, 0), CHAN5G(212, 0),
253 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
254 .band = IEEE80211_BAND_5GHZ,
255 .channels = b43_5ghz_nphy_chantable,
256 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
257 .bitrates = b43_a_ratetable,
258 .n_bitrates = b43_a_ratetable_size,
261 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
262 .band = IEEE80211_BAND_5GHZ,
263 .channels = b43_5ghz_aphy_chantable,
264 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
265 .bitrates = b43_a_ratetable,
266 .n_bitrates = b43_a_ratetable_size,
269 static struct ieee80211_supported_band b43_band_2GHz = {
270 .band = IEEE80211_BAND_2GHZ,
271 .channels = b43_2ghz_chantable,
272 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
273 .bitrates = b43_g_ratetable,
274 .n_bitrates = b43_g_ratetable_size,
277 static void b43_wireless_core_exit(struct b43_wldev *dev);
278 static int b43_wireless_core_init(struct b43_wldev *dev);
279 static void b43_wireless_core_stop(struct b43_wldev *dev);
280 static int b43_wireless_core_start(struct b43_wldev *dev);
282 static int b43_ratelimit(struct b43_wl *wl)
284 if (!wl || !wl->current_dev)
286 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
288 /* We are up and running.
289 * Ratelimit the messages to avoid DoS over the net. */
290 return net_ratelimit();
293 void b43info(struct b43_wl *wl, const char *fmt, ...)
297 if (!b43_ratelimit(wl))
300 printk(KERN_INFO "b43-%s: ",
301 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
306 void b43err(struct b43_wl *wl, const char *fmt, ...)
310 if (!b43_ratelimit(wl))
313 printk(KERN_ERR "b43-%s ERROR: ",
314 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
319 void b43warn(struct b43_wl *wl, const char *fmt, ...)
323 if (!b43_ratelimit(wl))
326 printk(KERN_WARNING "b43-%s warning: ",
327 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
333 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
338 printk(KERN_DEBUG "b43-%s debug: ",
339 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
345 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
349 B43_WARN_ON(offset % 4 != 0);
351 macctl = b43_read32(dev, B43_MMIO_MACCTL);
352 if (macctl & B43_MACCTL_BE)
355 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
357 b43_write32(dev, B43_MMIO_RAM_DATA, val);
360 static inline void b43_shm_control_word(struct b43_wldev *dev,
361 u16 routing, u16 offset)
365 /* "offset" is the WORD offset. */
369 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
372 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
374 struct b43_wl *wl = dev->wl;
378 spin_lock_irqsave(&wl->shm_lock, flags);
379 if (routing == B43_SHM_SHARED) {
380 B43_WARN_ON(offset & 0x0001);
381 if (offset & 0x0003) {
382 /* Unaligned access */
383 b43_shm_control_word(dev, routing, offset >> 2);
384 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
386 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
387 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
393 b43_shm_control_word(dev, routing, offset);
394 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
396 spin_unlock_irqrestore(&wl->shm_lock, flags);
401 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
403 struct b43_wl *wl = dev->wl;
407 spin_lock_irqsave(&wl->shm_lock, flags);
408 if (routing == B43_SHM_SHARED) {
409 B43_WARN_ON(offset & 0x0001);
410 if (offset & 0x0003) {
411 /* Unaligned access */
412 b43_shm_control_word(dev, routing, offset >> 2);
413 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
419 b43_shm_control_word(dev, routing, offset);
420 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
422 spin_unlock_irqrestore(&wl->shm_lock, flags);
427 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
429 struct b43_wl *wl = dev->wl;
432 spin_lock_irqsave(&wl->shm_lock, flags);
433 if (routing == B43_SHM_SHARED) {
434 B43_WARN_ON(offset & 0x0001);
435 if (offset & 0x0003) {
436 /* Unaligned access */
437 b43_shm_control_word(dev, routing, offset >> 2);
438 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
439 (value >> 16) & 0xffff);
440 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
441 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
446 b43_shm_control_word(dev, routing, offset);
447 b43_write32(dev, B43_MMIO_SHM_DATA, value);
449 spin_unlock_irqrestore(&wl->shm_lock, flags);
452 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
454 struct b43_wl *wl = dev->wl;
457 spin_lock_irqsave(&wl->shm_lock, flags);
458 if (routing == B43_SHM_SHARED) {
459 B43_WARN_ON(offset & 0x0001);
460 if (offset & 0x0003) {
461 /* Unaligned access */
462 b43_shm_control_word(dev, routing, offset >> 2);
463 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
468 b43_shm_control_word(dev, routing, offset);
469 b43_write16(dev, B43_MMIO_SHM_DATA, value);
471 spin_unlock_irqrestore(&wl->shm_lock, flags);
475 u64 b43_hf_read(struct b43_wldev * dev)
479 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
481 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
483 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
488 /* Write HostFlags */
489 void b43_hf_write(struct b43_wldev *dev, u64 value)
493 lo = (value & 0x00000000FFFFULL);
494 mi = (value & 0x0000FFFF0000ULL) >> 16;
495 hi = (value & 0xFFFF00000000ULL) >> 32;
496 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
497 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
498 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
501 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
503 /* We need to be careful. As we read the TSF from multiple
504 * registers, we should take care of register overflows.
505 * In theory, the whole tsf read process should be atomic.
506 * We try to be atomic here, by restaring the read process,
507 * if any of the high registers changed (overflew).
509 if (dev->dev->id.revision >= 3) {
510 u32 low, high, high2;
513 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
514 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
515 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
516 } while (unlikely(high != high2));
524 u16 test1, test2, test3;
527 v3 = b43_read16(dev, B43_MMIO_TSF_3);
528 v2 = b43_read16(dev, B43_MMIO_TSF_2);
529 v1 = b43_read16(dev, B43_MMIO_TSF_1);
530 v0 = b43_read16(dev, B43_MMIO_TSF_0);
532 test3 = b43_read16(dev, B43_MMIO_TSF_3);
533 test2 = b43_read16(dev, B43_MMIO_TSF_2);
534 test1 = b43_read16(dev, B43_MMIO_TSF_1);
535 } while (v3 != test3 || v2 != test2 || v1 != test1);
549 static void b43_time_lock(struct b43_wldev *dev)
553 macctl = b43_read32(dev, B43_MMIO_MACCTL);
554 macctl |= B43_MACCTL_TBTTHOLD;
555 b43_write32(dev, B43_MMIO_MACCTL, macctl);
556 /* Commit the write */
557 b43_read32(dev, B43_MMIO_MACCTL);
560 static void b43_time_unlock(struct b43_wldev *dev)
564 macctl = b43_read32(dev, B43_MMIO_MACCTL);
565 macctl &= ~B43_MACCTL_TBTTHOLD;
566 b43_write32(dev, B43_MMIO_MACCTL, macctl);
567 /* Commit the write */
568 b43_read32(dev, B43_MMIO_MACCTL);
571 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
573 /* Be careful with the in-progress timer.
574 * First zero out the low register, so we have a full
575 * register-overflow duration to complete the operation.
577 if (dev->dev->id.revision >= 3) {
578 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
579 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
581 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
583 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
585 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
587 u16 v0 = (tsf & 0x000000000000FFFFULL);
588 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
589 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
590 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
592 b43_write16(dev, B43_MMIO_TSF_0, 0);
594 b43_write16(dev, B43_MMIO_TSF_3, v3);
596 b43_write16(dev, B43_MMIO_TSF_2, v2);
598 b43_write16(dev, B43_MMIO_TSF_1, v1);
600 b43_write16(dev, B43_MMIO_TSF_0, v0);
604 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
607 b43_tsf_write_locked(dev, tsf);
608 b43_time_unlock(dev);
612 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
614 static const u8 zero_addr[ETH_ALEN] = { 0 };
621 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
625 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
631 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
634 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
638 u8 mac_bssid[ETH_ALEN * 2];
642 bssid = dev->wl->bssid;
643 mac = dev->wl->mac_addr;
645 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
647 memcpy(mac_bssid, mac, ETH_ALEN);
648 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
650 /* Write our MAC address and BSSID to template ram */
651 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
652 tmp = (u32) (mac_bssid[i + 0]);
653 tmp |= (u32) (mac_bssid[i + 1]) << 8;
654 tmp |= (u32) (mac_bssid[i + 2]) << 16;
655 tmp |= (u32) (mac_bssid[i + 3]) << 24;
656 b43_ram_write(dev, 0x20 + i, tmp);
660 static void b43_upload_card_macaddress(struct b43_wldev *dev)
662 b43_write_mac_bssid_templates(dev);
663 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
666 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
668 /* slot_time is in usec. */
669 if (dev->phy.type != B43_PHYTYPE_G)
671 b43_write16(dev, 0x684, 510 + slot_time);
672 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
675 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
677 b43_set_slot_time(dev, 9);
681 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
683 b43_set_slot_time(dev, 20);
687 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
688 * Returns the _previously_ enabled IRQ mask.
690 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
694 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
700 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
701 * Returns the _previously_ enabled IRQ mask.
703 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
707 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
708 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
713 /* Synchronize IRQ top- and bottom-half.
714 * IRQs must be masked before calling this.
715 * This must not be called with the irq_lock held.
717 static void b43_synchronize_irq(struct b43_wldev *dev)
719 synchronize_irq(dev->dev->irq);
720 tasklet_kill(&dev->isr_tasklet);
723 /* DummyTransmission function, as documented on
724 * http://bcm-specs.sipsolutions.net/DummyTransmission
726 void b43_dummy_transmission(struct b43_wldev *dev)
728 struct b43_phy *phy = &dev->phy;
729 unsigned int i, max_loop;
742 buffer[0] = 0x000201CC;
747 buffer[0] = 0x000B846E;
754 for (i = 0; i < 5; i++)
755 b43_ram_write(dev, i * 4, buffer[i]);
758 b43_read32(dev, B43_MMIO_MACCTL);
760 b43_write16(dev, 0x0568, 0x0000);
761 b43_write16(dev, 0x07C0, 0x0000);
762 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
763 b43_write16(dev, 0x050C, value);
764 b43_write16(dev, 0x0508, 0x0000);
765 b43_write16(dev, 0x050A, 0x0000);
766 b43_write16(dev, 0x054C, 0x0000);
767 b43_write16(dev, 0x056A, 0x0014);
768 b43_write16(dev, 0x0568, 0x0826);
769 b43_write16(dev, 0x0500, 0x0000);
770 b43_write16(dev, 0x0502, 0x0030);
772 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
773 b43_radio_write16(dev, 0x0051, 0x0017);
774 for (i = 0x00; i < max_loop; i++) {
775 value = b43_read16(dev, 0x050E);
780 for (i = 0x00; i < 0x0A; i++) {
781 value = b43_read16(dev, 0x050E);
786 for (i = 0x00; i < 0x0A; i++) {
787 value = b43_read16(dev, 0x0690);
788 if (!(value & 0x0100))
792 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
793 b43_radio_write16(dev, 0x0051, 0x0037);
796 static void key_write(struct b43_wldev *dev,
797 u8 index, u8 algorithm, const u8 * key)
804 /* Key index/algo block */
805 kidx = b43_kidx_to_fw(dev, index);
806 value = ((kidx << 4) | algorithm);
807 b43_shm_write16(dev, B43_SHM_SHARED,
808 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
810 /* Write the key to the Key Table Pointer offset */
811 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
812 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
814 value |= (u16) (key[i + 1]) << 8;
815 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
819 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
821 u32 addrtmp[2] = { 0, 0, };
822 u8 per_sta_keys_start = 8;
824 if (b43_new_kidx_api(dev))
825 per_sta_keys_start = 4;
827 B43_WARN_ON(index < per_sta_keys_start);
828 /* We have two default TX keys and possibly two default RX keys.
829 * Physical mac 0 is mapped to physical key 4 or 8, depending
830 * on the firmware version.
831 * So we must adjust the index here.
833 index -= per_sta_keys_start;
836 addrtmp[0] = addr[0];
837 addrtmp[0] |= ((u32) (addr[1]) << 8);
838 addrtmp[0] |= ((u32) (addr[2]) << 16);
839 addrtmp[0] |= ((u32) (addr[3]) << 24);
840 addrtmp[1] = addr[4];
841 addrtmp[1] |= ((u32) (addr[5]) << 8);
844 if (dev->dev->id.revision >= 5) {
845 /* Receive match transmitter address mechanism */
846 b43_shm_write32(dev, B43_SHM_RCMTA,
847 (index * 2) + 0, addrtmp[0]);
848 b43_shm_write16(dev, B43_SHM_RCMTA,
849 (index * 2) + 1, addrtmp[1]);
851 /* RXE (Receive Engine) and
852 * PSM (Programmable State Machine) mechanism
855 /* TODO write to RCM 16, 19, 22 and 25 */
857 b43_shm_write32(dev, B43_SHM_SHARED,
858 B43_SHM_SH_PSM + (index * 6) + 0,
860 b43_shm_write16(dev, B43_SHM_SHARED,
861 B43_SHM_SH_PSM + (index * 6) + 4,
867 static void do_key_write(struct b43_wldev *dev,
868 u8 index, u8 algorithm,
869 const u8 * key, size_t key_len, const u8 * mac_addr)
871 u8 buf[B43_SEC_KEYSIZE] = { 0, };
872 u8 per_sta_keys_start = 8;
874 if (b43_new_kidx_api(dev))
875 per_sta_keys_start = 4;
877 B43_WARN_ON(index >= dev->max_nr_keys);
878 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
880 if (index >= per_sta_keys_start)
881 keymac_write(dev, index, NULL); /* First zero out mac. */
883 memcpy(buf, key, key_len);
884 key_write(dev, index, algorithm, buf);
885 if (index >= per_sta_keys_start)
886 keymac_write(dev, index, mac_addr);
888 dev->key[index].algorithm = algorithm;
891 static int b43_key_write(struct b43_wldev *dev,
892 int index, u8 algorithm,
893 const u8 * key, size_t key_len,
895 struct ieee80211_key_conf *keyconf)
900 if (key_len > B43_SEC_KEYSIZE)
902 for (i = 0; i < dev->max_nr_keys; i++) {
903 /* Check that we don't already have this key. */
904 B43_WARN_ON(dev->key[i].keyconf == keyconf);
907 /* Either pairwise key or address is 00:00:00:00:00:00
908 * for transmit-only keys. Search the index. */
909 if (b43_new_kidx_api(dev))
913 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
914 if (!dev->key[i].keyconf) {
921 b43err(dev->wl, "Out of hardware key memory\n");
925 B43_WARN_ON(index > 3);
927 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
928 if ((index <= 3) && !b43_new_kidx_api(dev)) {
930 B43_WARN_ON(mac_addr);
931 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
933 keyconf->hw_key_idx = index;
934 dev->key[index].keyconf = keyconf;
939 static int b43_key_clear(struct b43_wldev *dev, int index)
941 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
943 do_key_write(dev, index, B43_SEC_ALGO_NONE,
944 NULL, B43_SEC_KEYSIZE, NULL);
945 if ((index <= 3) && !b43_new_kidx_api(dev)) {
946 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
947 NULL, B43_SEC_KEYSIZE, NULL);
949 dev->key[index].keyconf = NULL;
954 static void b43_clear_keys(struct b43_wldev *dev)
958 for (i = 0; i < dev->max_nr_keys; i++)
959 b43_key_clear(dev, i);
962 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
970 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
971 (ps_flags & B43_PS_DISABLED));
972 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
974 if (ps_flags & B43_PS_ENABLED) {
976 } else if (ps_flags & B43_PS_DISABLED) {
979 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
980 // and thus is not an AP and we are associated, set bit 25
982 if (ps_flags & B43_PS_AWAKE) {
984 } else if (ps_flags & B43_PS_ASLEEP) {
987 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
988 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
989 // successful, set bit26
992 /* FIXME: For now we force awake-on and hwps-off */
996 macctl = b43_read32(dev, B43_MMIO_MACCTL);
998 macctl |= B43_MACCTL_HWPS;
1000 macctl &= ~B43_MACCTL_HWPS;
1002 macctl |= B43_MACCTL_AWAKE;
1004 macctl &= ~B43_MACCTL_AWAKE;
1005 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1007 b43_read32(dev, B43_MMIO_MACCTL);
1008 if (awake && dev->dev->id.revision >= 5) {
1009 /* Wait for the microcode to wake up. */
1010 for (i = 0; i < 100; i++) {
1011 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1012 B43_SHM_SH_UCODESTAT);
1013 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1020 /* Turn the Analog ON/OFF */
1021 static void b43_switch_analog(struct b43_wldev *dev, int on)
1023 switch (dev->phy.type) {
1026 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
1029 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1037 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1042 flags |= B43_TMSLOW_PHYCLKEN;
1043 flags |= B43_TMSLOW_PHYRESET;
1044 ssb_device_enable(dev->dev, flags);
1045 msleep(2); /* Wait for the PLL to turn on. */
1047 /* Now take the PHY out of Reset again */
1048 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1049 tmslow |= SSB_TMSLOW_FGC;
1050 tmslow &= ~B43_TMSLOW_PHYRESET;
1051 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1052 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1054 tmslow &= ~SSB_TMSLOW_FGC;
1055 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1056 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1059 /* Turn Analog ON */
1060 b43_switch_analog(dev, 1);
1062 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1063 macctl &= ~B43_MACCTL_GMODE;
1064 if (flags & B43_TMSLOW_GMODE)
1065 macctl |= B43_MACCTL_GMODE;
1066 macctl |= B43_MACCTL_IHR_ENABLED;
1067 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1070 static void handle_irq_transmit_status(struct b43_wldev *dev)
1074 struct b43_txstatus stat;
1077 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1078 if (!(v0 & 0x00000001))
1080 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1082 stat.cookie = (v0 >> 16);
1083 stat.seq = (v1 & 0x0000FFFF);
1084 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1085 tmp = (v0 & 0x0000FFFF);
1086 stat.frame_count = ((tmp & 0xF000) >> 12);
1087 stat.rts_count = ((tmp & 0x0F00) >> 8);
1088 stat.supp_reason = ((tmp & 0x001C) >> 2);
1089 stat.pm_indicated = !!(tmp & 0x0080);
1090 stat.intermediate = !!(tmp & 0x0040);
1091 stat.for_ampdu = !!(tmp & 0x0020);
1092 stat.acked = !!(tmp & 0x0002);
1094 b43_handle_txstatus(dev, &stat);
1098 static void drain_txstatus_queue(struct b43_wldev *dev)
1102 if (dev->dev->id.revision < 5)
1104 /* Read all entries from the microcode TXstatus FIFO
1105 * and throw them away.
1108 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1109 if (!(dummy & 0x00000001))
1111 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1115 static u32 b43_jssi_read(struct b43_wldev *dev)
1119 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1121 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1126 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1128 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1129 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1132 static void b43_generate_noise_sample(struct b43_wldev *dev)
1134 b43_jssi_write(dev, 0x7F7F7F7F);
1135 b43_write32(dev, B43_MMIO_MACCMD,
1136 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1137 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1140 static void b43_calculate_link_quality(struct b43_wldev *dev)
1142 /* Top half of Link Quality calculation. */
1144 if (dev->noisecalc.calculation_running)
1146 dev->noisecalc.channel_at_start = dev->phy.channel;
1147 dev->noisecalc.calculation_running = 1;
1148 dev->noisecalc.nr_samples = 0;
1150 b43_generate_noise_sample(dev);
1153 static void handle_irq_noise(struct b43_wldev *dev)
1155 struct b43_phy *phy = &dev->phy;
1161 /* Bottom half of Link Quality calculation. */
1163 B43_WARN_ON(!dev->noisecalc.calculation_running);
1164 if (dev->noisecalc.channel_at_start != phy->channel)
1165 goto drop_calculation;
1166 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1167 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1168 noise[2] == 0x7F || noise[3] == 0x7F)
1171 /* Get the noise samples. */
1172 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1173 i = dev->noisecalc.nr_samples;
1174 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1175 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1176 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1177 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1178 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1179 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1180 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1181 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1182 dev->noisecalc.nr_samples++;
1183 if (dev->noisecalc.nr_samples == 8) {
1184 /* Calculate the Link Quality by the noise samples. */
1186 for (i = 0; i < 8; i++) {
1187 for (j = 0; j < 4; j++)
1188 average += dev->noisecalc.samples[i][j];
1194 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1195 tmp = (tmp / 128) & 0x1F;
1205 dev->stats.link_noise = average;
1207 dev->noisecalc.calculation_running = 0;
1211 b43_generate_noise_sample(dev);
1214 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1216 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1219 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1220 b43_power_saving_ctl_bits(dev, 0);
1222 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1226 static void handle_irq_atim_end(struct b43_wldev *dev)
1228 if (dev->dfq_valid) {
1229 b43_write32(dev, B43_MMIO_MACCMD,
1230 b43_read32(dev, B43_MMIO_MACCMD)
1231 | B43_MACCMD_DFQ_VALID);
1236 static void handle_irq_pmq(struct b43_wldev *dev)
1243 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1244 if (!(tmp & 0x00000008))
1247 /* 16bit write is odd, but correct. */
1248 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1251 static void b43_write_template_common(struct b43_wldev *dev,
1252 const u8 * data, u16 size,
1254 u16 shm_size_offset, u8 rate)
1257 struct b43_plcp_hdr4 plcp;
1260 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1261 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1262 ram_offset += sizeof(u32);
1263 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1264 * So leave the first two bytes of the next write blank.
1266 tmp = (u32) (data[0]) << 16;
1267 tmp |= (u32) (data[1]) << 24;
1268 b43_ram_write(dev, ram_offset, tmp);
1269 ram_offset += sizeof(u32);
1270 for (i = 2; i < size; i += sizeof(u32)) {
1271 tmp = (u32) (data[i + 0]);
1273 tmp |= (u32) (data[i + 1]) << 8;
1275 tmp |= (u32) (data[i + 2]) << 16;
1277 tmp |= (u32) (data[i + 3]) << 24;
1278 b43_ram_write(dev, ram_offset + i - 2, tmp);
1280 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1281 size + sizeof(struct b43_plcp_hdr6));
1284 static void b43_write_beacon_template(struct b43_wldev *dev,
1286 u16 shm_size_offset, u8 rate)
1288 unsigned int i, len, variable_len;
1289 const struct ieee80211_mgmt *bcn;
1293 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1294 len = min((size_t) dev->wl->current_beacon->len,
1295 0x200 - sizeof(struct b43_plcp_hdr6));
1297 b43_write_template_common(dev, (const u8 *)bcn,
1298 len, ram_offset, shm_size_offset, rate);
1300 /* Find the position of the TIM and the DTIM_period value
1301 * and write them to SHM. */
1302 ie = bcn->u.beacon.variable;
1303 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1304 for (i = 0; i < variable_len - 2; ) {
1305 uint8_t ie_id, ie_len;
1312 /* This is the TIM Information Element */
1314 /* Check whether the ie_len is in the beacon data range. */
1315 if (variable_len < ie_len + 2 + i)
1317 /* A valid TIM is at least 4 bytes long. */
1322 tim_position = sizeof(struct b43_plcp_hdr6);
1323 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1326 dtim_period = ie[i + 3];
1328 b43_shm_write16(dev, B43_SHM_SHARED,
1329 B43_SHM_SH_TIMBPOS, tim_position);
1330 b43_shm_write16(dev, B43_SHM_SHARED,
1331 B43_SHM_SH_DTIMPER, dtim_period);
1337 b43warn(dev->wl, "Did not find a valid TIM IE in "
1338 "the beacon template packet. AP or IBSS operation "
1339 "may be broken.\n");
1343 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1344 u16 shm_offset, u16 size,
1345 struct ieee80211_rate *rate)
1347 struct b43_plcp_hdr4 plcp;
1352 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1353 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1356 /* Write PLCP in two parts and timing for packet transfer */
1357 tmp = le32_to_cpu(plcp.data);
1358 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1359 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1360 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1363 /* Instead of using custom probe response template, this function
1364 * just patches custom beacon template by:
1365 * 1) Changing packet type
1366 * 2) Patching duration field
1369 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1371 struct ieee80211_rate *rate)
1375 u16 src_size, elem_size, src_pos, dest_pos;
1377 struct ieee80211_hdr *hdr;
1380 src_size = dev->wl->current_beacon->len;
1381 src_data = (const u8 *)dev->wl->current_beacon->data;
1383 /* Get the start offset of the variable IEs in the packet. */
1384 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1385 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1387 if (B43_WARN_ON(src_size < ie_start))
1390 dest_data = kmalloc(src_size, GFP_ATOMIC);
1391 if (unlikely(!dest_data))
1394 /* Copy the static data and all Information Elements, except the TIM. */
1395 memcpy(dest_data, src_data, ie_start);
1397 dest_pos = ie_start;
1398 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1399 elem_size = src_data[src_pos + 1] + 2;
1400 if (src_data[src_pos] == 5) {
1401 /* This is the TIM. */
1404 memcpy(dest_data + dest_pos, src_data + src_pos,
1406 dest_pos += elem_size;
1408 *dest_size = dest_pos;
1409 hdr = (struct ieee80211_hdr *)dest_data;
1411 /* Set the frame control. */
1412 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1413 IEEE80211_STYPE_PROBE_RESP);
1414 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1415 dev->wl->vif, *dest_size,
1417 hdr->duration_id = dur;
1422 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1424 u16 shm_size_offset,
1425 struct ieee80211_rate *rate)
1427 const u8 *probe_resp_data;
1430 size = dev->wl->current_beacon->len;
1431 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1432 if (unlikely(!probe_resp_data))
1435 /* Looks like PLCP headers plus packet timings are stored for
1436 * all possible basic rates
1438 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1439 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1440 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1441 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1443 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1444 b43_write_template_common(dev, probe_resp_data,
1445 size, ram_offset, shm_size_offset,
1447 kfree(probe_resp_data);
1450 /* Asynchronously update the packet templates in template RAM.
1451 * Locking: Requires wl->irq_lock to be locked. */
1452 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1454 /* This is the top half of the ansynchronous beacon update.
1455 * The bottom half is the beacon IRQ.
1456 * Beacon update must be asynchronous to avoid sending an
1457 * invalid beacon. This can happen for example, if the firmware
1458 * transmits a beacon while we are updating it. */
1460 if (wl->current_beacon)
1461 dev_kfree_skb_any(wl->current_beacon);
1462 wl->current_beacon = beacon;
1463 wl->beacon0_uploaded = 0;
1464 wl->beacon1_uploaded = 0;
1467 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1472 len = min((u16) ssid_len, (u16) 0x100);
1473 for (i = 0; i < len; i += sizeof(u32)) {
1474 tmp = (u32) (ssid[i + 0]);
1476 tmp |= (u32) (ssid[i + 1]) << 8;
1478 tmp |= (u32) (ssid[i + 2]) << 16;
1480 tmp |= (u32) (ssid[i + 3]) << 24;
1481 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1483 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1486 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1489 if (dev->dev->id.revision >= 3) {
1490 b43_write32(dev, 0x188, (beacon_int << 16));
1492 b43_write16(dev, 0x606, (beacon_int >> 6));
1493 b43_write16(dev, 0x610, beacon_int);
1495 b43_time_unlock(dev);
1498 static void handle_irq_beacon(struct b43_wldev *dev)
1500 struct b43_wl *wl = dev->wl;
1503 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1506 /* This is the bottom half of the asynchronous beacon update. */
1508 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1509 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1510 if (!wl->beacon0_uploaded) {
1511 b43_write_beacon_template(dev, 0x68, 0x18,
1513 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1514 &__b43_ratetable[3]);
1515 wl->beacon0_uploaded = 1;
1517 cmd |= B43_MACCMD_BEACON0_VALID;
1519 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1520 if (!wl->beacon1_uploaded) {
1521 b43_write_beacon_template(dev, 0x468, 0x1A,
1523 wl->beacon1_uploaded = 1;
1525 cmd |= B43_MACCMD_BEACON1_VALID;
1527 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1530 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1535 /* Interrupt handler bottom-half */
1536 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1539 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1540 u32 merged_dma_reason = 0;
1542 unsigned long flags;
1544 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1546 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1548 reason = dev->irq_reason;
1549 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1550 dma_reason[i] = dev->dma_reason[i];
1551 merged_dma_reason |= dma_reason[i];
1554 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1555 b43err(dev->wl, "MAC transmission error\n");
1557 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1558 b43err(dev->wl, "PHY transmission error\n");
1560 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1561 atomic_set(&dev->phy.txerr_cnt,
1562 B43_PHY_TX_BADNESS_LIMIT);
1563 b43err(dev->wl, "Too many PHY TX errors, "
1564 "restarting the controller\n");
1565 b43_controller_restart(dev, "PHY TX errors");
1569 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1570 B43_DMAIRQ_NONFATALMASK))) {
1571 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1572 b43err(dev->wl, "Fatal DMA error: "
1573 "0x%08X, 0x%08X, 0x%08X, "
1574 "0x%08X, 0x%08X, 0x%08X\n",
1575 dma_reason[0], dma_reason[1],
1576 dma_reason[2], dma_reason[3],
1577 dma_reason[4], dma_reason[5]);
1578 b43_controller_restart(dev, "DMA error");
1580 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1583 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1584 b43err(dev->wl, "DMA error: "
1585 "0x%08X, 0x%08X, 0x%08X, "
1586 "0x%08X, 0x%08X, 0x%08X\n",
1587 dma_reason[0], dma_reason[1],
1588 dma_reason[2], dma_reason[3],
1589 dma_reason[4], dma_reason[5]);
1593 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1594 handle_irq_ucode_debug(dev);
1595 if (reason & B43_IRQ_TBTT_INDI)
1596 handle_irq_tbtt_indication(dev);
1597 if (reason & B43_IRQ_ATIM_END)
1598 handle_irq_atim_end(dev);
1599 if (reason & B43_IRQ_BEACON)
1600 handle_irq_beacon(dev);
1601 if (reason & B43_IRQ_PMQ)
1602 handle_irq_pmq(dev);
1603 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1605 if (reason & B43_IRQ_NOISESAMPLE_OK)
1606 handle_irq_noise(dev);
1608 /* Check the DMA reason registers for received data. */
1609 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1610 if (b43_using_pio_transfers(dev))
1611 b43_pio_rx(dev->pio.rx_queue);
1613 b43_dma_rx(dev->dma.rx_ring);
1615 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1616 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1617 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1618 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1619 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1621 if (reason & B43_IRQ_TX_OK)
1622 handle_irq_transmit_status(dev);
1624 b43_interrupt_enable(dev, dev->irq_savedstate);
1626 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1629 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1631 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1633 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1634 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1635 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1636 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1637 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1638 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1641 /* Interrupt handler top-half */
1642 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1644 irqreturn_t ret = IRQ_NONE;
1645 struct b43_wldev *dev = dev_id;
1651 spin_lock(&dev->wl->irq_lock);
1653 if (b43_status(dev) < B43_STAT_STARTED)
1655 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1656 if (reason == 0xffffffff) /* shared IRQ */
1659 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1663 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1665 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1667 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1669 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1671 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1673 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1676 b43_interrupt_ack(dev, reason);
1677 /* disable all IRQs. They are enabled again in the bottom half. */
1678 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1679 /* save the reason code and call our bottom half. */
1680 dev->irq_reason = reason;
1681 tasklet_schedule(&dev->isr_tasklet);
1684 spin_unlock(&dev->wl->irq_lock);
1689 static void do_release_fw(struct b43_firmware_file *fw)
1691 release_firmware(fw->data);
1693 fw->filename = NULL;
1696 static void b43_release_firmware(struct b43_wldev *dev)
1698 do_release_fw(&dev->fw.ucode);
1699 do_release_fw(&dev->fw.pcm);
1700 do_release_fw(&dev->fw.initvals);
1701 do_release_fw(&dev->fw.initvals_band);
1704 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1708 text = "You must go to "
1709 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1710 "and download the latest firmware (version 4).\n";
1717 static int do_request_fw(struct b43_wldev *dev,
1719 struct b43_firmware_file *fw)
1721 char path[sizeof(modparam_fwpostfix) + 32];
1722 const struct firmware *blob;
1723 struct b43_fw_header *hdr;
1728 /* Don't fetch anything. Free possibly cached firmware. */
1733 if (strcmp(fw->filename, name) == 0)
1734 return 0; /* Already have this fw. */
1735 /* Free the cached firmware first. */
1739 snprintf(path, ARRAY_SIZE(path),
1741 modparam_fwpostfix, name);
1742 err = request_firmware(&blob, path, dev->dev->dev);
1744 b43err(dev->wl, "Firmware file \"%s\" not found "
1745 "or load failed.\n", path);
1748 if (blob->size < sizeof(struct b43_fw_header))
1750 hdr = (struct b43_fw_header *)(blob->data);
1751 switch (hdr->type) {
1752 case B43_FW_TYPE_UCODE:
1753 case B43_FW_TYPE_PCM:
1754 size = be32_to_cpu(hdr->size);
1755 if (size != blob->size - sizeof(struct b43_fw_header))
1758 case B43_FW_TYPE_IV:
1767 fw->filename = name;
1772 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1773 release_firmware(blob);
1778 static int b43_request_firmware(struct b43_wldev *dev)
1780 struct b43_firmware *fw = &dev->fw;
1781 const u8 rev = dev->dev->id.revision;
1782 const char *filename;
1787 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1788 if ((rev >= 5) && (rev <= 10))
1789 filename = "ucode5";
1790 else if ((rev >= 11) && (rev <= 12))
1791 filename = "ucode11";
1793 filename = "ucode13";
1796 err = do_request_fw(dev, filename, &fw->ucode);
1801 if ((rev >= 5) && (rev <= 10))
1807 err = do_request_fw(dev, filename, &fw->pcm);
1812 switch (dev->phy.type) {
1814 if ((rev >= 5) && (rev <= 10)) {
1815 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1816 filename = "a0g1initvals5";
1818 filename = "a0g0initvals5";
1820 goto err_no_initvals;
1823 if ((rev >= 5) && (rev <= 10))
1824 filename = "b0g0initvals5";
1826 filename = "lp0initvals13";
1828 goto err_no_initvals;
1831 if ((rev >= 11) && (rev <= 12))
1832 filename = "n0initvals11";
1834 goto err_no_initvals;
1837 goto err_no_initvals;
1839 err = do_request_fw(dev, filename, &fw->initvals);
1843 /* Get bandswitch initvals */
1844 switch (dev->phy.type) {
1846 if ((rev >= 5) && (rev <= 10)) {
1847 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1848 filename = "a0g1bsinitvals5";
1850 filename = "a0g0bsinitvals5";
1851 } else if (rev >= 11)
1854 goto err_no_initvals;
1857 if ((rev >= 5) && (rev <= 10))
1858 filename = "b0g0bsinitvals5";
1862 goto err_no_initvals;
1865 if ((rev >= 11) && (rev <= 12))
1866 filename = "n0bsinitvals11";
1868 goto err_no_initvals;
1871 goto err_no_initvals;
1873 err = do_request_fw(dev, filename, &fw->initvals_band);
1880 b43_print_fw_helptext(dev->wl, 1);
1885 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1890 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1895 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1896 "core rev %u\n", dev->phy.type, rev);
1900 b43_release_firmware(dev);
1904 static int b43_upload_microcode(struct b43_wldev *dev)
1906 const size_t hdr_len = sizeof(struct b43_fw_header);
1908 unsigned int i, len;
1909 u16 fwrev, fwpatch, fwdate, fwtime;
1913 /* Jump the microcode PSM to offset 0 */
1914 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1915 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1916 macctl |= B43_MACCTL_PSM_JMP0;
1917 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1918 /* Zero out all microcode PSM registers and shared memory. */
1919 for (i = 0; i < 64; i++)
1920 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1921 for (i = 0; i < 4096; i += 2)
1922 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1924 /* Upload Microcode. */
1925 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1926 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1927 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1928 for (i = 0; i < len; i++) {
1929 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1933 if (dev->fw.pcm.data) {
1934 /* Upload PCM data. */
1935 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1936 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1937 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1938 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1939 /* No need for autoinc bit in SHM_HW */
1940 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1941 for (i = 0; i < len; i++) {
1942 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1947 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1949 /* Start the microcode PSM */
1950 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1951 macctl &= ~B43_MACCTL_PSM_JMP0;
1952 macctl |= B43_MACCTL_PSM_RUN;
1953 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1955 /* Wait for the microcode to load and respond */
1958 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1959 if (tmp == B43_IRQ_MAC_SUSPENDED)
1963 b43err(dev->wl, "Microcode not responding\n");
1964 b43_print_fw_helptext(dev->wl, 1);
1968 msleep_interruptible(50);
1969 if (signal_pending(current)) {
1974 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1976 /* Get and check the revisions. */
1977 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1978 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1979 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1980 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1982 if (fwrev <= 0x128) {
1983 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1984 "binary drivers older than version 4.x is unsupported. "
1985 "You must upgrade your firmware files.\n");
1986 b43_print_fw_helptext(dev->wl, 1);
1990 b43info(dev->wl, "Loading firmware version %u.%u "
1991 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1993 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1994 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1996 dev->fw.rev = fwrev;
1997 dev->fw.patch = fwpatch;
1999 if (b43_is_old_txhdr_format(dev)) {
2000 b43warn(dev->wl, "You are using an old firmware image. "
2001 "Support for old firmware will be removed in July 2008.\n");
2002 b43_print_fw_helptext(dev->wl, 0);
2008 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2009 macctl &= ~B43_MACCTL_PSM_RUN;
2010 macctl |= B43_MACCTL_PSM_JMP0;
2011 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2016 static int b43_write_initvals(struct b43_wldev *dev,
2017 const struct b43_iv *ivals,
2021 const struct b43_iv *iv;
2026 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2028 for (i = 0; i < count; i++) {
2029 if (array_size < sizeof(iv->offset_size))
2031 array_size -= sizeof(iv->offset_size);
2032 offset = be16_to_cpu(iv->offset_size);
2033 bit32 = !!(offset & B43_IV_32BIT);
2034 offset &= B43_IV_OFFSET_MASK;
2035 if (offset >= 0x1000)
2040 if (array_size < sizeof(iv->data.d32))
2042 array_size -= sizeof(iv->data.d32);
2044 value = be32_to_cpu(get_unaligned(&iv->data.d32));
2045 b43_write32(dev, offset, value);
2047 iv = (const struct b43_iv *)((const uint8_t *)iv +
2053 if (array_size < sizeof(iv->data.d16))
2055 array_size -= sizeof(iv->data.d16);
2057 value = be16_to_cpu(iv->data.d16);
2058 b43_write16(dev, offset, value);
2060 iv = (const struct b43_iv *)((const uint8_t *)iv +
2071 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2072 b43_print_fw_helptext(dev->wl, 1);
2077 static int b43_upload_initvals(struct b43_wldev *dev)
2079 const size_t hdr_len = sizeof(struct b43_fw_header);
2080 const struct b43_fw_header *hdr;
2081 struct b43_firmware *fw = &dev->fw;
2082 const struct b43_iv *ivals;
2086 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2087 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2088 count = be32_to_cpu(hdr->size);
2089 err = b43_write_initvals(dev, ivals, count,
2090 fw->initvals.data->size - hdr_len);
2093 if (fw->initvals_band.data) {
2094 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2095 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2096 count = be32_to_cpu(hdr->size);
2097 err = b43_write_initvals(dev, ivals, count,
2098 fw->initvals_band.data->size - hdr_len);
2107 /* Initialize the GPIOs
2108 * http://bcm-specs.sipsolutions.net/GPIO
2110 static int b43_gpio_init(struct b43_wldev *dev)
2112 struct ssb_bus *bus = dev->dev->bus;
2113 struct ssb_device *gpiodev, *pcidev = NULL;
2116 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2117 & ~B43_MACCTL_GPOUTSMSK);
2119 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2124 if (dev->dev->bus->chip_id == 0x4301) {
2128 if (0 /* FIXME: conditional unknown */ ) {
2129 b43_write16(dev, B43_MMIO_GPIO_MASK,
2130 b43_read16(dev, B43_MMIO_GPIO_MASK)
2135 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2136 b43_write16(dev, B43_MMIO_GPIO_MASK,
2137 b43_read16(dev, B43_MMIO_GPIO_MASK)
2142 if (dev->dev->id.revision >= 2)
2143 mask |= 0x0010; /* FIXME: This is redundant. */
2145 #ifdef CONFIG_SSB_DRIVER_PCICORE
2146 pcidev = bus->pcicore.dev;
2148 gpiodev = bus->chipco.dev ? : pcidev;
2151 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2152 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2158 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2159 static void b43_gpio_cleanup(struct b43_wldev *dev)
2161 struct ssb_bus *bus = dev->dev->bus;
2162 struct ssb_device *gpiodev, *pcidev = NULL;
2164 #ifdef CONFIG_SSB_DRIVER_PCICORE
2165 pcidev = bus->pcicore.dev;
2167 gpiodev = bus->chipco.dev ? : pcidev;
2170 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2173 /* http://bcm-specs.sipsolutions.net/EnableMac */
2174 static void b43_mac_enable(struct b43_wldev *dev)
2176 dev->mac_suspended--;
2177 B43_WARN_ON(dev->mac_suspended < 0);
2178 if (dev->mac_suspended == 0) {
2179 b43_write32(dev, B43_MMIO_MACCTL,
2180 b43_read32(dev, B43_MMIO_MACCTL)
2181 | B43_MACCTL_ENABLED);
2182 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2183 B43_IRQ_MAC_SUSPENDED);
2185 b43_read32(dev, B43_MMIO_MACCTL);
2186 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2187 b43_power_saving_ctl_bits(dev, 0);
2189 /* Re-enable IRQs. */
2190 spin_lock_irq(&dev->wl->irq_lock);
2191 b43_interrupt_enable(dev, dev->irq_savedstate);
2192 spin_unlock_irq(&dev->wl->irq_lock);
2196 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2197 static void b43_mac_suspend(struct b43_wldev *dev)
2203 B43_WARN_ON(dev->mac_suspended < 0);
2205 if (dev->mac_suspended == 0) {
2206 /* Mask IRQs before suspending MAC. Otherwise
2207 * the MAC stays busy and won't suspend. */
2208 spin_lock_irq(&dev->wl->irq_lock);
2209 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2210 spin_unlock_irq(&dev->wl->irq_lock);
2211 b43_synchronize_irq(dev);
2212 dev->irq_savedstate = tmp;
2214 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2215 b43_write32(dev, B43_MMIO_MACCTL,
2216 b43_read32(dev, B43_MMIO_MACCTL)
2217 & ~B43_MACCTL_ENABLED);
2218 /* force pci to flush the write */
2219 b43_read32(dev, B43_MMIO_MACCTL);
2220 for (i = 40; i; i--) {
2221 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2222 if (tmp & B43_IRQ_MAC_SUSPENDED)
2226 b43err(dev->wl, "MAC suspend failed\n");
2229 dev->mac_suspended++;
2232 static void b43_adjust_opmode(struct b43_wldev *dev)
2234 struct b43_wl *wl = dev->wl;
2238 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2239 /* Reset status to STA infrastructure mode. */
2240 ctl &= ~B43_MACCTL_AP;
2241 ctl &= ~B43_MACCTL_KEEP_CTL;
2242 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2243 ctl &= ~B43_MACCTL_KEEP_BAD;
2244 ctl &= ~B43_MACCTL_PROMISC;
2245 ctl &= ~B43_MACCTL_BEACPROMISC;
2246 ctl |= B43_MACCTL_INFRA;
2248 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2249 ctl |= B43_MACCTL_AP;
2250 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2251 ctl &= ~B43_MACCTL_INFRA;
2253 if (wl->filter_flags & FIF_CONTROL)
2254 ctl |= B43_MACCTL_KEEP_CTL;
2255 if (wl->filter_flags & FIF_FCSFAIL)
2256 ctl |= B43_MACCTL_KEEP_BAD;
2257 if (wl->filter_flags & FIF_PLCPFAIL)
2258 ctl |= B43_MACCTL_KEEP_BADPLCP;
2259 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2260 ctl |= B43_MACCTL_PROMISC;
2261 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2262 ctl |= B43_MACCTL_BEACPROMISC;
2264 /* Workaround: On old hardware the HW-MAC-address-filter
2265 * doesn't work properly, so always run promisc in filter
2266 * it in software. */
2267 if (dev->dev->id.revision <= 4)
2268 ctl |= B43_MACCTL_PROMISC;
2270 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2273 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2274 if (dev->dev->bus->chip_id == 0x4306 &&
2275 dev->dev->bus->chip_rev == 3)
2280 b43_write16(dev, 0x612, cfp_pretbtt);
2283 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2289 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2292 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2294 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2295 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2298 static void b43_rate_memory_init(struct b43_wldev *dev)
2300 switch (dev->phy.type) {
2304 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2305 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2306 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2307 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2308 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2309 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2310 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2311 if (dev->phy.type == B43_PHYTYPE_A)
2315 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2316 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2317 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2318 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2325 /* Set the TX-Antenna for management frames sent by firmware. */
2326 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2333 ant |= B43_TXH_PHY_ANT0;
2336 ant |= B43_TXH_PHY_ANT1;
2339 ant |= B43_TXH_PHY_ANT2;
2342 ant |= B43_TXH_PHY_ANT3;
2344 case B43_ANTENNA_AUTO:
2345 ant |= B43_TXH_PHY_ANT01AUTO;
2351 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2354 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2355 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2356 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2358 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2359 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2360 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2361 /* For Probe Resposes */
2362 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2363 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2364 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2367 /* This is the opposite of b43_chip_init() */
2368 static void b43_chip_exit(struct b43_wldev *dev)
2370 b43_radio_turn_off(dev, 1);
2371 b43_gpio_cleanup(dev);
2372 /* firmware is released later */
2375 /* Initialize the chip
2376 * http://bcm-specs.sipsolutions.net/ChipInit
2378 static int b43_chip_init(struct b43_wldev *dev)
2380 struct b43_phy *phy = &dev->phy;
2382 u32 value32, macctl;
2385 /* Initialize the MAC control */
2386 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2388 macctl |= B43_MACCTL_GMODE;
2389 macctl |= B43_MACCTL_INFRA;
2390 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2392 err = b43_request_firmware(dev);
2395 err = b43_upload_microcode(dev);
2397 goto out; /* firmware is released later */
2399 err = b43_gpio_init(dev);
2401 goto out; /* firmware is released later */
2403 err = b43_upload_initvals(dev);
2405 goto err_gpio_clean;
2406 b43_radio_turn_on(dev);
2408 b43_write16(dev, 0x03E6, 0x0000);
2409 err = b43_phy_init(dev);
2413 /* Select initial Interference Mitigation. */
2414 tmp = phy->interfmode;
2415 phy->interfmode = B43_INTERFMODE_NONE;
2416 b43_radio_set_interference_mitigation(dev, tmp);
2418 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2419 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2421 if (phy->type == B43_PHYTYPE_B) {
2422 value16 = b43_read16(dev, 0x005E);
2424 b43_write16(dev, 0x005E, value16);
2426 b43_write32(dev, 0x0100, 0x01000000);
2427 if (dev->dev->id.revision < 5)
2428 b43_write32(dev, 0x010C, 0x01000000);
2430 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2431 & ~B43_MACCTL_INFRA);
2432 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2433 | B43_MACCTL_INFRA);
2435 /* Probe Response Timeout value */
2436 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2437 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2439 /* Initially set the wireless operation mode. */
2440 b43_adjust_opmode(dev);
2442 if (dev->dev->id.revision < 3) {
2443 b43_write16(dev, 0x060E, 0x0000);
2444 b43_write16(dev, 0x0610, 0x8000);
2445 b43_write16(dev, 0x0604, 0x0000);
2446 b43_write16(dev, 0x0606, 0x0200);
2448 b43_write32(dev, 0x0188, 0x80000000);
2449 b43_write32(dev, 0x018C, 0x02000000);
2451 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2452 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2453 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2454 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2455 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2456 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2457 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2459 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2460 value32 |= 0x00100000;
2461 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2463 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2464 dev->dev->bus->chipco.fast_pwrup_delay);
2467 b43dbg(dev->wl, "Chip initialized\n");
2472 b43_radio_turn_off(dev, 1);
2474 b43_gpio_cleanup(dev);
2478 static void b43_periodic_every120sec(struct b43_wldev *dev)
2480 struct b43_phy *phy = &dev->phy;
2482 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2485 b43_mac_suspend(dev);
2486 b43_lo_g_measure(dev);
2487 b43_mac_enable(dev);
2488 if (b43_has_hardware_pctl(phy))
2489 b43_lo_g_ctl_mark_all_unused(dev);
2492 static void b43_periodic_every60sec(struct b43_wldev *dev)
2494 struct b43_phy *phy = &dev->phy;
2496 if (phy->type != B43_PHYTYPE_G)
2498 if (!b43_has_hardware_pctl(phy))
2499 b43_lo_g_ctl_mark_all_unused(dev);
2500 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2501 b43_mac_suspend(dev);
2502 b43_calc_nrssi_slope(dev);
2503 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2504 u8 old_chan = phy->channel;
2506 /* VCO Calibration */
2508 b43_radio_selectchannel(dev, 1, 0);
2510 b43_radio_selectchannel(dev, 13, 0);
2511 b43_radio_selectchannel(dev, old_chan, 0);
2513 b43_mac_enable(dev);
2517 static void b43_periodic_every30sec(struct b43_wldev *dev)
2519 /* Update device statistics. */
2520 b43_calculate_link_quality(dev);
2523 static void b43_periodic_every15sec(struct b43_wldev *dev)
2525 struct b43_phy *phy = &dev->phy;
2527 if (phy->type == B43_PHYTYPE_G) {
2528 //TODO: update_aci_moving_average
2529 if (phy->aci_enable && phy->aci_wlan_automatic) {
2530 b43_mac_suspend(dev);
2531 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2532 if (0 /*TODO: bunch of conditions */ ) {
2533 b43_radio_set_interference_mitigation
2534 (dev, B43_INTERFMODE_MANUALWLAN);
2536 } else if (1 /*TODO*/) {
2538 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2539 b43_radio_set_interference_mitigation(dev,
2540 B43_INTERFMODE_NONE);
2544 b43_mac_enable(dev);
2545 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2547 //TODO: implement rev1 workaround
2550 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2551 //TODO for APHY (temperature?)
2553 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2557 static void do_periodic_work(struct b43_wldev *dev)
2561 state = dev->periodic_state;
2563 b43_periodic_every120sec(dev);
2565 b43_periodic_every60sec(dev);
2567 b43_periodic_every30sec(dev);
2568 b43_periodic_every15sec(dev);
2571 /* Periodic work locking policy:
2572 * The whole periodic work handler is protected by
2573 * wl->mutex. If another lock is needed somewhere in the
2574 * pwork callchain, it's aquired in-place, where it's needed.
2576 static void b43_periodic_work_handler(struct work_struct *work)
2578 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2579 periodic_work.work);
2580 struct b43_wl *wl = dev->wl;
2581 unsigned long delay;
2583 mutex_lock(&wl->mutex);
2585 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2587 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2590 do_periodic_work(dev);
2592 dev->periodic_state++;
2594 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2595 delay = msecs_to_jiffies(50);
2597 delay = round_jiffies_relative(HZ * 15);
2598 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2600 mutex_unlock(&wl->mutex);
2603 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2605 struct delayed_work *work = &dev->periodic_work;
2607 dev->periodic_state = 0;
2608 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2609 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2612 /* Check if communication with the device works correctly. */
2613 static int b43_validate_chipaccess(struct b43_wldev *dev)
2617 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2619 /* Check for read/write and endianness problems. */
2620 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2621 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2623 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2624 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2627 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2629 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2630 /* The 32bit register shadows the two 16bit registers
2631 * with update sideeffects. Validate this. */
2632 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2633 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2634 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2636 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2639 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2641 v = b43_read32(dev, B43_MMIO_MACCTL);
2642 v |= B43_MACCTL_GMODE;
2643 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2648 b43err(dev->wl, "Failed to validate the chipaccess\n");
2652 static void b43_security_init(struct b43_wldev *dev)
2654 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2655 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2656 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2657 /* KTP is a word address, but we address SHM bytewise.
2658 * So multiply by two.
2661 if (dev->dev->id.revision >= 5) {
2662 /* Number of RCMTA address slots */
2663 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2665 b43_clear_keys(dev);
2668 static int b43_rng_read(struct hwrng *rng, u32 * data)
2670 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2671 unsigned long flags;
2673 /* Don't take wl->mutex here, as it could deadlock with
2674 * hwrng internal locking. It's not needed to take
2675 * wl->mutex here, anyway. */
2677 spin_lock_irqsave(&wl->irq_lock, flags);
2678 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2679 spin_unlock_irqrestore(&wl->irq_lock, flags);
2681 return (sizeof(u16));
2684 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2686 if (wl->rng_initialized)
2687 __hwrng_unregister(&wl->rng, suspended);
2690 static int b43_rng_init(struct b43_wl *wl)
2694 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2695 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2696 wl->rng.name = wl->rng_name;
2697 wl->rng.data_read = b43_rng_read;
2698 wl->rng.priv = (unsigned long)wl;
2699 wl->rng_initialized = 1;
2700 err = hwrng_register(&wl->rng);
2702 wl->rng_initialized = 0;
2703 b43err(wl, "Failed to register the random "
2704 "number generator (%d)\n", err);
2710 static int b43_op_tx(struct ieee80211_hw *hw,
2711 struct sk_buff *skb,
2712 struct ieee80211_tx_control *ctl)
2714 struct b43_wl *wl = hw_to_b43_wl(hw);
2715 struct b43_wldev *dev = wl->current_dev;
2718 if (unlikely(skb->len < 2 + 2 + 6)) {
2719 /* Too short, this can't be a valid frame. */
2722 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2726 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2728 /* TX is done without a global lock. */
2729 if (b43_using_pio_transfers(dev))
2730 err = b43_pio_tx(dev, skb, ctl);
2732 err = b43_dma_tx(dev, skb, ctl);
2735 return NETDEV_TX_BUSY;
2736 return NETDEV_TX_OK;
2739 /* Locking: wl->irq_lock */
2740 static void b43_qos_params_upload(struct b43_wldev *dev,
2741 const struct ieee80211_tx_queue_params *p,
2744 u16 params[B43_NR_QOSPARAMS];
2745 int cw_min, cw_max, aifs, bslots, tmp;
2748 const u16 aCWmin = 0x0001;
2749 const u16 aCWmax = 0x03FF;
2751 /* Calculate the default values for the parameters, if needed. */
2752 switch (shm_offset) {
2754 aifs = (p->aifs == -1) ? 2 : p->aifs;
2755 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
2756 cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
2759 aifs = (p->aifs == -1) ? 2 : p->aifs;
2760 cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
2761 cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
2763 case B43_QOS_BESTEFFORT:
2764 aifs = (p->aifs == -1) ? 3 : p->aifs;
2765 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2766 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2768 case B43_QOS_BACKGROUND:
2769 aifs = (p->aifs == -1) ? 7 : p->aifs;
2770 cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
2771 cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
2781 bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
2783 memset(¶ms, 0, sizeof(params));
2785 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2786 params[B43_QOSPARAM_CWMIN] = cw_min;
2787 params[B43_QOSPARAM_CWMAX] = cw_max;
2788 params[B43_QOSPARAM_CWCUR] = cw_min;
2789 params[B43_QOSPARAM_AIFS] = aifs;
2790 params[B43_QOSPARAM_BSLOTS] = bslots;
2791 params[B43_QOSPARAM_REGGAP] = bslots + aifs;
2793 for (i = 0; i < ARRAY_SIZE(params); i++) {
2794 if (i == B43_QOSPARAM_STATUS) {
2795 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
2796 shm_offset + (i * 2));
2797 /* Mark the parameters as updated. */
2799 b43_shm_write16(dev, B43_SHM_SHARED,
2800 shm_offset + (i * 2),
2803 b43_shm_write16(dev, B43_SHM_SHARED,
2804 shm_offset + (i * 2),
2810 /* Update the QOS parameters in hardware. */
2811 static void b43_qos_update(struct b43_wldev *dev)
2813 struct b43_wl *wl = dev->wl;
2814 struct b43_qos_params *params;
2815 unsigned long flags;
2818 /* Mapping of mac80211 queues to b43 SHM offsets. */
2819 static const u16 qos_shm_offsets[] = {
2820 [0] = B43_QOS_VOICE,
2821 [1] = B43_QOS_VIDEO,
2822 [2] = B43_QOS_BESTEFFORT,
2823 [3] = B43_QOS_BACKGROUND,
2825 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
2827 b43_mac_suspend(dev);
2828 spin_lock_irqsave(&wl->irq_lock, flags);
2830 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2831 params = &(wl->qos_params[i]);
2832 if (params->need_hw_update) {
2833 b43_qos_params_upload(dev, &(params->p),
2834 qos_shm_offsets[i]);
2835 params->need_hw_update = 0;
2839 spin_unlock_irqrestore(&wl->irq_lock, flags);
2840 b43_mac_enable(dev);
2843 static void b43_qos_clear(struct b43_wl *wl)
2845 struct b43_qos_params *params;
2848 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
2849 params = &(wl->qos_params[i]);
2851 memset(&(params->p), 0, sizeof(params->p));
2852 params->p.aifs = -1;
2853 params->need_hw_update = 1;
2857 /* Initialize the core's QOS capabilities */
2858 static void b43_qos_init(struct b43_wldev *dev)
2860 struct b43_wl *wl = dev->wl;
2863 /* Upload the current QOS parameters. */
2864 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
2865 wl->qos_params[i].need_hw_update = 1;
2866 b43_qos_update(dev);
2868 /* Enable QOS support. */
2869 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
2870 b43_write16(dev, B43_MMIO_IFSCTL,
2871 b43_read16(dev, B43_MMIO_IFSCTL)
2872 | B43_MMIO_IFSCTL_USE_EDCF);
2875 static void b43_qos_update_work(struct work_struct *work)
2877 struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
2878 struct b43_wldev *dev;
2880 mutex_lock(&wl->mutex);
2881 dev = wl->current_dev;
2882 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
2883 b43_qos_update(dev);
2884 mutex_unlock(&wl->mutex);
2887 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2889 const struct ieee80211_tx_queue_params *params)
2891 struct b43_wl *wl = hw_to_b43_wl(hw);
2892 unsigned long flags;
2893 unsigned int queue = (unsigned int)_queue;
2894 struct b43_qos_params *p;
2896 if (queue >= ARRAY_SIZE(wl->qos_params)) {
2897 /* Queue not available or don't support setting
2898 * params on this queue. Return success to not
2899 * confuse mac80211. */
2903 spin_lock_irqsave(&wl->irq_lock, flags);
2904 p = &(wl->qos_params[queue]);
2905 memcpy(&(p->p), params, sizeof(p->p));
2906 p->need_hw_update = 1;
2907 spin_unlock_irqrestore(&wl->irq_lock, flags);
2909 queue_work(hw->workqueue, &wl->qos_update_work);
2914 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2915 struct ieee80211_tx_queue_stats *stats)
2917 struct b43_wl *wl = hw_to_b43_wl(hw);
2918 struct b43_wldev *dev = wl->current_dev;
2919 unsigned long flags;
2924 spin_lock_irqsave(&wl->irq_lock, flags);
2925 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2926 if (b43_using_pio_transfers(dev))
2927 b43_pio_get_tx_stats(dev, stats);
2929 b43_dma_get_tx_stats(dev, stats);
2932 spin_unlock_irqrestore(&wl->irq_lock, flags);
2937 static int b43_op_get_stats(struct ieee80211_hw *hw,
2938 struct ieee80211_low_level_stats *stats)
2940 struct b43_wl *wl = hw_to_b43_wl(hw);
2941 unsigned long flags;
2943 spin_lock_irqsave(&wl->irq_lock, flags);
2944 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2945 spin_unlock_irqrestore(&wl->irq_lock, flags);
2950 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2952 struct ssb_device *sdev = dev->dev;
2955 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2956 tmslow &= ~B43_TMSLOW_GMODE;
2957 tmslow |= B43_TMSLOW_PHYRESET;
2958 tmslow |= SSB_TMSLOW_FGC;
2959 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2962 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2963 tmslow &= ~SSB_TMSLOW_FGC;
2964 tmslow |= B43_TMSLOW_PHYRESET;
2965 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2969 static const char * band_to_string(enum ieee80211_band band)
2972 case IEEE80211_BAND_5GHZ:
2974 case IEEE80211_BAND_2GHZ:
2983 /* Expects wl->mutex locked */
2984 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
2986 struct b43_wldev *up_dev = NULL;
2987 struct b43_wldev *down_dev;
2988 struct b43_wldev *d;
2993 /* Find a device and PHY which supports the band. */
2994 list_for_each_entry(d, &wl->devlist, list) {
2995 switch (chan->band) {
2996 case IEEE80211_BAND_5GHZ:
2997 if (d->phy.supports_5ghz) {
3002 case IEEE80211_BAND_2GHZ:
3003 if (d->phy.supports_2ghz) {
3016 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3017 band_to_string(chan->band));
3020 if ((up_dev == wl->current_dev) &&
3021 (!!wl->current_dev->phy.gmode == !!gmode)) {
3022 /* This device is already running. */
3025 b43dbg(wl, "Switching to %s-GHz band\n",
3026 band_to_string(chan->band));
3027 down_dev = wl->current_dev;
3029 prev_status = b43_status(down_dev);
3030 /* Shutdown the currently running core. */
3031 if (prev_status >= B43_STAT_STARTED)
3032 b43_wireless_core_stop(down_dev);
3033 if (prev_status >= B43_STAT_INITIALIZED)
3034 b43_wireless_core_exit(down_dev);
3036 if (down_dev != up_dev) {
3037 /* We switch to a different core, so we put PHY into
3038 * RESET on the old core. */
3039 b43_put_phy_into_reset(down_dev);
3042 /* Now start the new core. */
3043 up_dev->phy.gmode = gmode;
3044 if (prev_status >= B43_STAT_INITIALIZED) {
3045 err = b43_wireless_core_init(up_dev);
3047 b43err(wl, "Fatal: Could not initialize device for "
3048 "selected %s-GHz band\n",
3049 band_to_string(chan->band));
3053 if (prev_status >= B43_STAT_STARTED) {
3054 err = b43_wireless_core_start(up_dev);
3056 b43err(wl, "Fatal: Coult not start device for "
3057 "selected %s-GHz band\n",
3058 band_to_string(chan->band));
3059 b43_wireless_core_exit(up_dev);
3063 B43_WARN_ON(b43_status(up_dev) != prev_status);
3065 wl->current_dev = up_dev;
3069 /* Whoops, failed to init the new core. No core is operating now. */
3070 wl->current_dev = NULL;
3074 /* Check if the use of the antenna that ieee80211 told us to
3075 * use is possible. This will fall back to DEFAULT.
3076 * "antenna_nr" is the antenna identifier we got from ieee80211. */
3077 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
3082 if (antenna_nr == 0) {
3083 /* Zero means "use default antenna". That's always OK. */
3087 /* Get the mask of available antennas. */
3089 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
3091 antenna_mask = dev->dev->bus->sprom.ant_available_a;
3093 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
3094 /* This antenna is not available. Fall back to default. */
3101 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
3103 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
3105 case 0: /* default/diversity */
3106 return B43_ANTENNA_DEFAULT;
3107 case 1: /* Antenna 0 */
3108 return B43_ANTENNA0;
3109 case 2: /* Antenna 1 */
3110 return B43_ANTENNA1;
3111 case 3: /* Antenna 2 */
3112 return B43_ANTENNA2;
3113 case 4: /* Antenna 3 */
3114 return B43_ANTENNA3;
3116 return B43_ANTENNA_DEFAULT;
3120 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3122 struct b43_wl *wl = hw_to_b43_wl(hw);
3123 struct b43_wldev *dev;
3124 struct b43_phy *phy;
3125 unsigned long flags;
3130 mutex_lock(&wl->mutex);
3132 /* Switch the band (if necessary). This might change the active core. */
3133 err = b43_switch_band(wl, conf->channel);
3135 goto out_unlock_mutex;
3136 dev = wl->current_dev;
3139 /* Disable IRQs while reconfiguring the device.
3140 * This makes it possible to drop the spinlock throughout
3141 * the reconfiguration process. */
3142 spin_lock_irqsave(&wl->irq_lock, flags);
3143 if (b43_status(dev) < B43_STAT_STARTED) {
3144 spin_unlock_irqrestore(&wl->irq_lock, flags);
3145 goto out_unlock_mutex;
3147 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3148 spin_unlock_irqrestore(&wl->irq_lock, flags);
3149 b43_synchronize_irq(dev);
3151 /* Switch to the requested channel.
3152 * The firmware takes care of races with the TX handler. */
3153 if (conf->channel->hw_value != phy->channel)
3154 b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
3156 /* Enable/Disable ShortSlot timing. */
3157 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3159 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3160 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3161 b43_short_slot_timing_enable(dev);
3163 b43_short_slot_timing_disable(dev);
3166 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3168 /* Adjust the desired TX power level. */
3169 if (conf->power_level != 0) {
3170 if (conf->power_level != phy->power_level) {
3171 phy->power_level = conf->power_level;
3172 b43_phy_xmitpower(dev);
3176 /* Antennas for RX and management frame TX. */
3177 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3178 b43_mgmtframe_txantenna(dev, antenna);
3179 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3180 b43_set_rx_antenna(dev, antenna);
3182 /* Update templates for AP mode. */
3183 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
3184 b43_set_beacon_int(dev, conf->beacon_int);
3186 if (!!conf->radio_enabled != phy->radio_on) {
3187 if (conf->radio_enabled) {
3188 b43_radio_turn_on(dev);
3189 b43info(dev->wl, "Radio turned on by software\n");
3190 if (!dev->radio_hw_enable) {
3191 b43info(dev->wl, "The hardware RF-kill button "
3192 "still turns the radio physically off. "
3193 "Press the button to turn it on.\n");
3196 b43_radio_turn_off(dev, 0);
3197 b43info(dev->wl, "Radio turned off by software\n");
3201 spin_lock_irqsave(&wl->irq_lock, flags);
3202 b43_interrupt_enable(dev, savedirqs);
3204 spin_unlock_irqrestore(&wl->irq_lock, flags);
3206 mutex_unlock(&wl->mutex);
3211 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3212 const u8 *local_addr, const u8 *addr,
3213 struct ieee80211_key_conf *key)
3215 struct b43_wl *wl = hw_to_b43_wl(hw);
3216 struct b43_wldev *dev;
3217 unsigned long flags;
3221 DECLARE_MAC_BUF(mac);
3223 if (modparam_nohwcrypt)
3224 return -ENOSPC; /* User disabled HW-crypto */
3226 mutex_lock(&wl->mutex);
3227 spin_lock_irqsave(&wl->irq_lock, flags);
3229 dev = wl->current_dev;
3231 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3237 if (key->keylen == 5)
3238 algorithm = B43_SEC_ALGO_WEP40;
3240 algorithm = B43_SEC_ALGO_WEP104;
3243 algorithm = B43_SEC_ALGO_TKIP;
3246 algorithm = B43_SEC_ALGO_AES;
3252 index = (u8) (key->keyidx);
3258 if (algorithm == B43_SEC_ALGO_TKIP) {
3259 /* FIXME: No TKIP hardware encryption for now. */
3264 if (is_broadcast_ether_addr(addr)) {
3265 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3266 err = b43_key_write(dev, index, algorithm,
3267 key->key, key->keylen, NULL, key);
3270 * either pairwise key or address is 00:00:00:00:00:00
3271 * for transmit-only keys
3273 err = b43_key_write(dev, -1, algorithm,
3274 key->key, key->keylen, addr, key);
3279 if (algorithm == B43_SEC_ALGO_WEP40 ||
3280 algorithm == B43_SEC_ALGO_WEP104) {
3281 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3284 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3286 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3289 err = b43_key_clear(dev, key->hw_key_idx);
3298 spin_unlock_irqrestore(&wl->irq_lock, flags);
3299 mutex_unlock(&wl->mutex);
3301 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3303 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3304 print_mac(mac, addr));
3309 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3310 unsigned int changed, unsigned int *fflags,
3311 int mc_count, struct dev_addr_list *mc_list)
3313 struct b43_wl *wl = hw_to_b43_wl(hw);
3314 struct b43_wldev *dev = wl->current_dev;
3315 unsigned long flags;
3322 spin_lock_irqsave(&wl->irq_lock, flags);
3323 *fflags &= FIF_PROMISC_IN_BSS |
3329 FIF_BCN_PRBRESP_PROMISC;
3331 changed &= FIF_PROMISC_IN_BSS |
3337 FIF_BCN_PRBRESP_PROMISC;
3339 wl->filter_flags = *fflags;
3341 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3342 b43_adjust_opmode(dev);
3343 spin_unlock_irqrestore(&wl->irq_lock, flags);
3346 static int b43_op_config_interface(struct ieee80211_hw *hw,
3347 struct ieee80211_vif *vif,
3348 struct ieee80211_if_conf *conf)
3350 struct b43_wl *wl = hw_to_b43_wl(hw);
3351 struct b43_wldev *dev = wl->current_dev;
3352 unsigned long flags;
3356 mutex_lock(&wl->mutex);
3357 spin_lock_irqsave(&wl->irq_lock, flags);
3358 B43_WARN_ON(wl->vif != vif);
3360 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3362 memset(wl->bssid, 0, ETH_ALEN);
3363 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3364 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3365 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3366 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3368 b43_update_templates(wl, conf->beacon);
3370 b43_write_mac_bssid_templates(dev);
3372 spin_unlock_irqrestore(&wl->irq_lock, flags);
3373 mutex_unlock(&wl->mutex);
3378 /* Locking: wl->mutex */
3379 static void b43_wireless_core_stop(struct b43_wldev *dev)
3381 struct b43_wl *wl = dev->wl;
3382 unsigned long flags;
3384 if (b43_status(dev) < B43_STAT_STARTED)
3387 /* Disable and sync interrupts. We must do this before than
3388 * setting the status to INITIALIZED, as the interrupt handler
3389 * won't care about IRQs then. */
3390 spin_lock_irqsave(&wl->irq_lock, flags);
3391 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3392 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3393 spin_unlock_irqrestore(&wl->irq_lock, flags);
3394 b43_synchronize_irq(dev);
3396 b43_set_status(dev, B43_STAT_INITIALIZED);
3399 mutex_unlock(&wl->mutex);
3400 /* Must unlock as it would otherwise deadlock. No races here.
3401 * Cancel the possibly running self-rearming periodic work. */
3402 cancel_delayed_work_sync(&dev->periodic_work);
3403 mutex_lock(&wl->mutex);
3405 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3407 b43_mac_suspend(dev);
3408 free_irq(dev->dev->irq, dev);
3409 b43dbg(wl, "Wireless interface stopped\n");
3412 /* Locking: wl->mutex */
3413 static int b43_wireless_core_start(struct b43_wldev *dev)
3417 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3419 drain_txstatus_queue(dev);
3420 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3421 IRQF_SHARED, KBUILD_MODNAME, dev);
3423 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3427 /* We are ready to run. */
3428 b43_set_status(dev, B43_STAT_STARTED);
3430 /* Start data flow (TX/RX). */
3431 b43_mac_enable(dev);
3432 b43_interrupt_enable(dev, dev->irq_savedstate);
3433 ieee80211_start_queues(dev->wl->hw);
3435 /* Start maintainance work */
3436 b43_periodic_tasks_setup(dev);
3438 b43dbg(dev->wl, "Wireless interface started\n");
3443 /* Get PHY and RADIO versioning numbers */
3444 static int b43_phy_versioning(struct b43_wldev *dev)
3446 struct b43_phy *phy = &dev->phy;
3454 int unsupported = 0;
3456 /* Get PHY versioning */
3457 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3458 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3459 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3460 phy_rev = (tmp & B43_PHYVER_VERSION);
3467 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3475 #ifdef CONFIG_B43_NPHY
3485 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3486 "(Analog %u, Type %u, Revision %u)\n",
3487 analog_type, phy_type, phy_rev);
3490 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3491 analog_type, phy_type, phy_rev);
3493 /* Get RADIO versioning */
3494 if (dev->dev->bus->chip_id == 0x4317) {
3495 if (dev->dev->bus->chip_rev == 0)
3497 else if (dev->dev->bus->chip_rev == 1)
3502 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3503 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3504 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3505 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3507 radio_manuf = (tmp & 0x00000FFF);
3508 radio_ver = (tmp & 0x0FFFF000) >> 12;
3509 radio_rev = (tmp & 0xF0000000) >> 28;
3510 if (radio_manuf != 0x17F /* Broadcom */)
3514 if (radio_ver != 0x2060)
3518 if (radio_manuf != 0x17F)
3522 if ((radio_ver & 0xFFF0) != 0x2050)
3526 if (radio_ver != 0x2050)
3530 if (radio_ver != 0x2055)
3537 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3538 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3539 radio_manuf, radio_ver, radio_rev);
3542 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3543 radio_manuf, radio_ver, radio_rev);
3545 phy->radio_manuf = radio_manuf;
3546 phy->radio_ver = radio_ver;
3547 phy->radio_rev = radio_rev;
3549 phy->analog = analog_type;
3550 phy->type = phy_type;
3556 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3557 struct b43_phy *phy)
3559 struct b43_txpower_lo_control *lo;
3562 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3563 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3565 phy->aci_enable = 0;
3566 phy->aci_wlan_automatic = 0;
3567 phy->aci_hw_rssi = 0;
3569 phy->radio_off_context.valid = 0;
3571 lo = phy->lo_control;
3573 memset(lo, 0, sizeof(*(phy->lo_control)));
3577 phy->max_lb_gain = 0;
3578 phy->trsw_rx_gain = 0;
3579 phy->txpwr_offset = 0;
3582 phy->nrssislope = 0;
3583 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3584 phy->nrssi[i] = -1000;
3585 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3586 phy->nrssi_lt[i] = i;
3588 phy->lofcal = 0xFFFF;
3589 phy->initval = 0xFFFF;
3591 phy->interfmode = B43_INTERFMODE_NONE;
3592 phy->channel = 0xFF;
3594 phy->hardware_power_control = !!modparam_hwpctl;
3596 /* PHY TX errors counter. */
3597 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3599 /* OFDM-table address caching. */
3600 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3603 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3607 /* Assume the radio is enabled. If it's not enabled, the state will
3608 * immediately get fixed on the first periodic work run. */
3609 dev->radio_hw_enable = 1;
3612 memset(&dev->stats, 0, sizeof(dev->stats));
3614 setup_struct_phy_for_init(dev, &dev->phy);
3616 /* IRQ related flags */
3617 dev->irq_reason = 0;
3618 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3619 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3621 dev->mac_suspended = 1;
3623 /* Noise calculation context */
3624 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3627 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3629 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3632 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3634 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3637 hf = b43_hf_read(dev);
3638 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3639 hf |= B43_HF_BTCOEXALT;
3641 hf |= B43_HF_BTCOEX;
3642 b43_hf_write(dev, hf);
3646 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3650 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3652 #ifdef CONFIG_SSB_DRIVER_PCICORE
3653 struct ssb_bus *bus = dev->dev->bus;
3656 if (bus->pcicore.dev &&
3657 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3658 bus->pcicore.dev->id.revision <= 5) {
3659 /* IMCFGLO timeouts workaround. */
3660 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3661 tmp &= ~SSB_IMCFGLO_REQTO;
3662 tmp &= ~SSB_IMCFGLO_SERTO;
3663 switch (bus->bustype) {
3664 case SSB_BUSTYPE_PCI:
3665 case SSB_BUSTYPE_PCMCIA:
3668 case SSB_BUSTYPE_SSB:
3672 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3674 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3677 /* Write the short and long frame retry limit values. */
3678 static void b43_set_retry_limits(struct b43_wldev *dev,
3679 unsigned int short_retry,
3680 unsigned int long_retry)
3682 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3683 * the chip-internal counter. */
3684 short_retry = min(short_retry, (unsigned int)0xF);
3685 long_retry = min(long_retry, (unsigned int)0xF);
3687 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3689 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3693 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3697 /* The time value is in microseconds. */
3698 if (dev->phy.type == B43_PHYTYPE_A)
3702 if ((dev->wl->if_type == IEEE80211_IF_TYPE_IBSS) || idle)
3704 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3705 pu_delay = max(pu_delay, (u16)2400);
3707 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3710 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3711 static void b43_set_pretbtt(struct b43_wldev *dev)
3715 /* The time value is in microseconds. */
3716 if (dev->wl->if_type == IEEE80211_IF_TYPE_IBSS) {
3719 if (dev->phy.type == B43_PHYTYPE_A)
3724 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3725 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3728 /* Shutdown a wireless core */
3729 /* Locking: wl->mutex */
3730 static void b43_wireless_core_exit(struct b43_wldev *dev)
3732 struct b43_phy *phy = &dev->phy;
3735 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3736 if (b43_status(dev) != B43_STAT_INITIALIZED)
3738 b43_set_status(dev, B43_STAT_UNINIT);
3740 /* Stop the microcode PSM. */
3741 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3742 macctl &= ~B43_MACCTL_PSM_RUN;
3743 macctl |= B43_MACCTL_PSM_JMP0;
3744 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3746 if (!dev->suspend_in_progress) {
3748 b43_rng_exit(dev->wl, false);
3753 b43_radio_turn_off(dev, 1);
3754 b43_switch_analog(dev, 0);
3755 if (phy->dyn_tssi_tbl)
3756 kfree(phy->tssi2dbm);
3757 kfree(phy->lo_control);
3758 phy->lo_control = NULL;
3759 if (dev->wl->current_beacon) {
3760 dev_kfree_skb_any(dev->wl->current_beacon);
3761 dev->wl->current_beacon = NULL;
3764 ssb_device_disable(dev->dev, 0);
3765 ssb_bus_may_powerdown(dev->dev->bus);
3768 /* Initialize a wireless core */
3769 static int b43_wireless_core_init(struct b43_wldev *dev)
3771 struct b43_wl *wl = dev->wl;
3772 struct ssb_bus *bus = dev->dev->bus;
3773 struct ssb_sprom *sprom = &bus->sprom;
3774 struct b43_phy *phy = &dev->phy;
3778 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3780 err = ssb_bus_powerup(bus, 0);
3783 if (!ssb_device_is_enabled(dev->dev)) {
3784 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3785 b43_wireless_core_reset(dev, tmp);
3788 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3790 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3791 if (!phy->lo_control) {
3796 setup_struct_wldev_for_init(dev);
3798 err = b43_phy_init_tssi2dbm_table(dev);
3800 goto err_kfree_lo_control;
3802 /* Enable IRQ routing to this device. */
3803 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3805 b43_imcfglo_timeouts_workaround(dev);
3806 b43_bluetooth_coext_disable(dev);
3807 b43_phy_early_init(dev);
3808 err = b43_chip_init(dev);
3810 goto err_kfree_tssitbl;
3811 b43_shm_write16(dev, B43_SHM_SHARED,
3812 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3813 hf = b43_hf_read(dev);
3814 if (phy->type == B43_PHYTYPE_G) {
3818 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3819 hf |= B43_HF_OFDMPABOOST;
3820 } else if (phy->type == B43_PHYTYPE_B) {
3822 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3825 b43_hf_write(dev, hf);
3827 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3828 B43_DEFAULT_LONG_RETRY_LIMIT);
3829 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3830 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3832 /* Disable sending probe responses from firmware.
3833 * Setting the MaxTime to one usec will always trigger
3834 * a timeout, so we never send any probe resp.
3835 * A timeout of zero is infinite. */
3836 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3838 b43_rate_memory_init(dev);
3840 /* Minimum Contention Window */
3841 if (phy->type == B43_PHYTYPE_B) {
3842 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3844 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3846 /* Maximum Contention Window */
3847 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3849 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
3850 dev->__using_pio_transfers = 1;
3851 err = b43_pio_init(dev);
3853 dev->__using_pio_transfers = 0;
3854 err = b43_dma_init(dev);
3859 b43_set_synth_pu_delay(dev, 1);
3860 b43_bluetooth_coext_enable(dev);
3862 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3863 b43_upload_card_macaddress(dev);
3864 b43_security_init(dev);
3865 if (!dev->suspend_in_progress)
3868 b43_set_status(dev, B43_STAT_INITIALIZED);
3870 if (!dev->suspend_in_progress)
3878 if (phy->dyn_tssi_tbl)
3879 kfree(phy->tssi2dbm);
3880 err_kfree_lo_control:
3881 kfree(phy->lo_control);
3882 phy->lo_control = NULL;
3884 ssb_bus_may_powerdown(bus);
3885 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3889 static int b43_op_add_interface(struct ieee80211_hw *hw,
3890 struct ieee80211_if_init_conf *conf)
3892 struct b43_wl *wl = hw_to_b43_wl(hw);
3893 struct b43_wldev *dev;
3894 unsigned long flags;
3895 int err = -EOPNOTSUPP;
3897 /* TODO: allow WDS/AP devices to coexist */
3899 if (conf->type != IEEE80211_IF_TYPE_AP &&
3900 conf->type != IEEE80211_IF_TYPE_STA &&
3901 conf->type != IEEE80211_IF_TYPE_WDS &&
3902 conf->type != IEEE80211_IF_TYPE_IBSS)
3905 mutex_lock(&wl->mutex);
3907 goto out_mutex_unlock;
3909 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3911 dev = wl->current_dev;
3913 wl->vif = conf->vif;
3914 wl->if_type = conf->type;
3915 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3917 spin_lock_irqsave(&wl->irq_lock, flags);
3918 b43_adjust_opmode(dev);
3919 b43_set_pretbtt(dev);
3920 b43_set_synth_pu_delay(dev, 0);
3921 b43_upload_card_macaddress(dev);
3922 spin_unlock_irqrestore(&wl->irq_lock, flags);
3926 mutex_unlock(&wl->mutex);
3931 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3932 struct ieee80211_if_init_conf *conf)
3934 struct b43_wl *wl = hw_to_b43_wl(hw);
3935 struct b43_wldev *dev = wl->current_dev;
3936 unsigned long flags;
3938 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3940 mutex_lock(&wl->mutex);
3942 B43_WARN_ON(!wl->operating);
3943 B43_WARN_ON(wl->vif != conf->vif);
3948 spin_lock_irqsave(&wl->irq_lock, flags);
3949 b43_adjust_opmode(dev);
3950 memset(wl->mac_addr, 0, ETH_ALEN);
3951 b43_upload_card_macaddress(dev);
3952 spin_unlock_irqrestore(&wl->irq_lock, flags);
3954 mutex_unlock(&wl->mutex);
3957 static int b43_op_start(struct ieee80211_hw *hw)
3959 struct b43_wl *wl = hw_to_b43_wl(hw);
3960 struct b43_wldev *dev = wl->current_dev;
3963 bool do_rfkill_exit = 0;
3965 /* Kill all old instance specific information to make sure
3966 * the card won't use it in the short timeframe between start
3967 * and mac80211 reconfiguring it. */
3968 memset(wl->bssid, 0, ETH_ALEN);
3969 memset(wl->mac_addr, 0, ETH_ALEN);
3970 wl->filter_flags = 0;
3971 wl->radiotap_enabled = 0;
3974 /* First register RFkill.
3975 * LEDs that are registered later depend on it. */
3976 b43_rfkill_init(dev);
3978 mutex_lock(&wl->mutex);
3980 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3981 err = b43_wireless_core_init(dev);
3984 goto out_mutex_unlock;
3989 if (b43_status(dev) < B43_STAT_STARTED) {
3990 err = b43_wireless_core_start(dev);
3993 b43_wireless_core_exit(dev);
3995 goto out_mutex_unlock;
4000 mutex_unlock(&wl->mutex);
4003 b43_rfkill_exit(dev);
4008 static void b43_op_stop(struct ieee80211_hw *hw)
4010 struct b43_wl *wl = hw_to_b43_wl(hw);
4011 struct b43_wldev *dev = wl->current_dev;
4013 b43_rfkill_exit(dev);
4014 cancel_work_sync(&(wl->qos_update_work));
4016 mutex_lock(&wl->mutex);
4017 if (b43_status(dev) >= B43_STAT_STARTED)
4018 b43_wireless_core_stop(dev);
4019 b43_wireless_core_exit(dev);
4020 mutex_unlock(&wl->mutex);
4023 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
4024 u32 short_retry_limit, u32 long_retry_limit)
4026 struct b43_wl *wl = hw_to_b43_wl(hw);
4027 struct b43_wldev *dev;
4030 mutex_lock(&wl->mutex);
4031 dev = wl->current_dev;
4032 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
4036 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
4038 mutex_unlock(&wl->mutex);
4043 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
4045 struct b43_wl *wl = hw_to_b43_wl(hw);
4046 struct sk_buff *beacon;
4047 unsigned long flags;
4049 /* We could modify the existing beacon and set the aid bit in
4050 * the TIM field, but that would probably require resizing and
4051 * moving of data within the beacon template.
4052 * Simply request a new beacon and let mac80211 do the hard work. */
4053 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
4054 if (unlikely(!beacon))
4056 spin_lock_irqsave(&wl->irq_lock, flags);
4057 b43_update_templates(wl, beacon);
4058 spin_unlock_irqrestore(&wl->irq_lock, flags);
4063 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
4064 struct sk_buff *beacon,
4065 struct ieee80211_tx_control *ctl)
4067 struct b43_wl *wl = hw_to_b43_wl(hw);
4068 unsigned long flags;
4070 spin_lock_irqsave(&wl->irq_lock, flags);
4071 b43_update_templates(wl, beacon);
4072 spin_unlock_irqrestore(&wl->irq_lock, flags);
4077 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4078 struct ieee80211_vif *vif,
4079 enum sta_notify_cmd notify_cmd,
4082 struct b43_wl *wl = hw_to_b43_wl(hw);
4084 B43_WARN_ON(!vif || wl->vif != vif);
4087 static const struct ieee80211_ops b43_hw_ops = {
4089 .conf_tx = b43_op_conf_tx,
4090 .add_interface = b43_op_add_interface,
4091 .remove_interface = b43_op_remove_interface,
4092 .config = b43_op_config,
4093 .config_interface = b43_op_config_interface,
4094 .configure_filter = b43_op_configure_filter,
4095 .set_key = b43_op_set_key,
4096 .get_stats = b43_op_get_stats,
4097 .get_tx_stats = b43_op_get_tx_stats,
4098 .start = b43_op_start,
4099 .stop = b43_op_stop,
4100 .set_retry_limit = b43_op_set_retry_limit,
4101 .set_tim = b43_op_beacon_set_tim,
4102 .beacon_update = b43_op_ibss_beacon_update,
4103 .sta_notify = b43_op_sta_notify,
4106 /* Hard-reset the chip. Do not call this directly.
4107 * Use b43_controller_restart()
4109 static void b43_chip_reset(struct work_struct *work)
4111 struct b43_wldev *dev =
4112 container_of(work, struct b43_wldev, restart_work);
4113 struct b43_wl *wl = dev->wl;
4117 mutex_lock(&wl->mutex);
4119 prev_status = b43_status(dev);
4120 /* Bring the device down... */
4121 if (prev_status >= B43_STAT_STARTED)
4122 b43_wireless_core_stop(dev);
4123 if (prev_status >= B43_STAT_INITIALIZED)
4124 b43_wireless_core_exit(dev);
4126 /* ...and up again. */
4127 if (prev_status >= B43_STAT_INITIALIZED) {
4128 err = b43_wireless_core_init(dev);
4132 if (prev_status >= B43_STAT_STARTED) {
4133 err = b43_wireless_core_start(dev);
4135 b43_wireless_core_exit(dev);
4140 mutex_unlock(&wl->mutex);
4142 b43err(wl, "Controller restart FAILED\n");
4144 b43info(wl, "Controller restarted\n");
4147 static int b43_setup_bands(struct b43_wldev *dev,
4148 bool have_2ghz_phy, bool have_5ghz_phy)
4150 struct ieee80211_hw *hw = dev->wl->hw;
4153 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4154 if (dev->phy.type == B43_PHYTYPE_N) {
4156 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4159 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4162 dev->phy.supports_2ghz = have_2ghz_phy;
4163 dev->phy.supports_5ghz = have_5ghz_phy;
4168 static void b43_wireless_core_detach(struct b43_wldev *dev)
4170 /* We release firmware that late to not be required to re-request
4171 * is all the time when we reinit the core. */
4172 b43_release_firmware(dev);
4175 static int b43_wireless_core_attach(struct b43_wldev *dev)
4177 struct b43_wl *wl = dev->wl;
4178 struct ssb_bus *bus = dev->dev->bus;
4179 struct pci_dev *pdev = bus->host_pci;
4181 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4184 /* Do NOT do any device initialization here.
4185 * Do it in wireless_core_init() instead.
4186 * This function is for gathering basic information about the HW, only.
4187 * Also some structs may be set up here. But most likely you want to have
4188 * that in core_init(), too.
4191 err = ssb_bus_powerup(bus, 0);
4193 b43err(wl, "Bus powerup failed\n");
4196 /* Get the PHY type. */
4197 if (dev->dev->id.revision >= 5) {
4200 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4201 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4202 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4206 dev->phy.gmode = have_2ghz_phy;
4207 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4208 b43_wireless_core_reset(dev, tmp);
4210 err = b43_phy_versioning(dev);
4213 /* Check if this device supports multiband. */
4215 (pdev->device != 0x4312 &&
4216 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4217 /* No multiband support. */
4220 switch (dev->phy.type) {
4232 if (dev->phy.type == B43_PHYTYPE_A) {
4234 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4238 dev->phy.gmode = have_2ghz_phy;
4239 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4240 b43_wireless_core_reset(dev, tmp);
4242 err = b43_validate_chipaccess(dev);
4245 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4249 /* Now set some default "current_dev" */
4250 if (!wl->current_dev)
4251 wl->current_dev = dev;
4252 INIT_WORK(&dev->restart_work, b43_chip_reset);
4254 b43_radio_turn_off(dev, 1);
4255 b43_switch_analog(dev, 0);
4256 ssb_device_disable(dev->dev, 0);
4257 ssb_bus_may_powerdown(bus);
4263 ssb_bus_may_powerdown(bus);
4267 static void b43_one_core_detach(struct ssb_device *dev)
4269 struct b43_wldev *wldev;
4272 wldev = ssb_get_drvdata(dev);
4274 cancel_work_sync(&wldev->restart_work);
4275 b43_debugfs_remove_device(wldev);
4276 b43_wireless_core_detach(wldev);
4277 list_del(&wldev->list);
4279 ssb_set_drvdata(dev, NULL);
4283 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4285 struct b43_wldev *wldev;
4286 struct pci_dev *pdev;
4289 if (!list_empty(&wl->devlist)) {
4290 /* We are not the first core on this chip. */
4291 pdev = dev->bus->host_pci;
4292 /* Only special chips support more than one wireless
4293 * core, although some of the other chips have more than
4294 * one wireless core as well. Check for this and
4298 ((pdev->device != 0x4321) &&
4299 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4300 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4305 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4311 b43_set_status(wldev, B43_STAT_UNINIT);
4312 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4313 tasklet_init(&wldev->isr_tasklet,
4314 (void (*)(unsigned long))b43_interrupt_tasklet,
4315 (unsigned long)wldev);
4316 INIT_LIST_HEAD(&wldev->list);
4318 err = b43_wireless_core_attach(wldev);
4320 goto err_kfree_wldev;
4322 list_add(&wldev->list, &wl->devlist);
4324 ssb_set_drvdata(dev, wldev);
4325 b43_debugfs_add_device(wldev);
4335 static void b43_sprom_fixup(struct ssb_bus *bus)
4337 /* boardflags workarounds */
4338 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4339 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4340 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4341 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4342 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4343 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4346 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4348 struct ieee80211_hw *hw = wl->hw;
4350 ssb_set_devtypedata(dev, NULL);
4351 ieee80211_free_hw(hw);
4354 static int b43_wireless_init(struct ssb_device *dev)
4356 struct ssb_sprom *sprom = &dev->bus->sprom;
4357 struct ieee80211_hw *hw;
4361 b43_sprom_fixup(dev->bus);
4363 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4365 b43err(NULL, "Could not allocate ieee80211 device\n");
4370 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4371 IEEE80211_HW_RX_INCLUDES_FCS;
4372 hw->max_signal = 100;
4373 hw->max_rssi = -110;
4374 hw->max_noise = -110;
4375 hw->queues = b43_modparam_qos ? 4 : 1;
4376 SET_IEEE80211_DEV(hw, dev->dev);
4377 if (is_valid_ether_addr(sprom->et1mac))
4378 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4380 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4382 /* Get and initialize struct b43_wl */
4383 wl = hw_to_b43_wl(hw);
4384 memset(wl, 0, sizeof(*wl));
4386 spin_lock_init(&wl->irq_lock);
4387 spin_lock_init(&wl->leds_lock);
4388 spin_lock_init(&wl->shm_lock);
4389 mutex_init(&wl->mutex);
4390 INIT_LIST_HEAD(&wl->devlist);
4391 INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
4393 ssb_set_devtypedata(dev, wl);
4394 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4400 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4406 wl = ssb_get_devtypedata(dev);
4408 /* Probing the first core. Must setup common struct b43_wl */
4410 err = b43_wireless_init(dev);
4413 wl = ssb_get_devtypedata(dev);
4416 err = b43_one_core_attach(dev, wl);
4418 goto err_wireless_exit;
4421 err = ieee80211_register_hw(wl->hw);
4423 goto err_one_core_detach;
4429 err_one_core_detach:
4430 b43_one_core_detach(dev);
4433 b43_wireless_exit(dev, wl);
4437 static void b43_remove(struct ssb_device *dev)
4439 struct b43_wl *wl = ssb_get_devtypedata(dev);
4440 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4443 if (wl->current_dev == wldev)
4444 ieee80211_unregister_hw(wl->hw);
4446 b43_one_core_detach(dev);
4448 if (list_empty(&wl->devlist)) {
4449 /* Last core on the chip unregistered.
4450 * We can destroy common struct b43_wl.
4452 b43_wireless_exit(dev, wl);
4456 /* Perform a hardware reset. This can be called from any context. */
4457 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4459 /* Must avoid requeueing, if we are in shutdown. */
4460 if (b43_status(dev) < B43_STAT_INITIALIZED)
4462 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4463 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4468 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4470 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4471 struct b43_wl *wl = wldev->wl;
4473 b43dbg(wl, "Suspending...\n");
4475 mutex_lock(&wl->mutex);
4476 wldev->suspend_in_progress = true;
4477 wldev->suspend_init_status = b43_status(wldev);
4478 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4479 b43_wireless_core_stop(wldev);
4480 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4481 b43_wireless_core_exit(wldev);
4482 mutex_unlock(&wl->mutex);
4484 b43dbg(wl, "Device suspended.\n");
4489 static int b43_resume(struct ssb_device *dev)
4491 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4492 struct b43_wl *wl = wldev->wl;
4495 b43dbg(wl, "Resuming...\n");
4497 mutex_lock(&wl->mutex);
4498 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4499 err = b43_wireless_core_init(wldev);
4501 b43err(wl, "Resume failed at core init\n");
4505 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4506 err = b43_wireless_core_start(wldev);
4508 b43_leds_exit(wldev);
4509 b43_rng_exit(wldev->wl, true);
4510 b43_wireless_core_exit(wldev);
4511 b43err(wl, "Resume failed at core start\n");
4515 b43dbg(wl, "Device resumed.\n");
4517 wldev->suspend_in_progress = false;
4518 mutex_unlock(&wl->mutex);
4522 #else /* CONFIG_PM */
4523 # define b43_suspend NULL
4524 # define b43_resume NULL
4525 #endif /* CONFIG_PM */
4527 static struct ssb_driver b43_ssb_driver = {
4528 .name = KBUILD_MODNAME,
4529 .id_table = b43_ssb_tbl,
4531 .remove = b43_remove,
4532 .suspend = b43_suspend,
4533 .resume = b43_resume,
4536 static void b43_print_driverinfo(void)
4538 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4539 *feat_leds = "", *feat_rfkill = "";
4541 #ifdef CONFIG_B43_PCI_AUTOSELECT
4544 #ifdef CONFIG_B43_PCMCIA
4547 #ifdef CONFIG_B43_NPHY
4550 #ifdef CONFIG_B43_LEDS
4553 #ifdef CONFIG_B43_RFKILL
4556 printk(KERN_INFO "Broadcom 43xx driver loaded "
4557 "[ Features: %s%s%s%s%s, Firmware-ID: "
4558 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4559 feat_pci, feat_pcmcia, feat_nphy,
4560 feat_leds, feat_rfkill);
4563 static int __init b43_init(void)
4568 err = b43_pcmcia_init();
4571 err = ssb_driver_register(&b43_ssb_driver);
4573 goto err_pcmcia_exit;
4574 b43_print_driverinfo();
4585 static void __exit b43_exit(void)
4587 ssb_driver_unregister(&b43_ssb_driver);
4592 module_init(b43_init)
4593 module_exit(b43_exit)