3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
13 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
15 Some parts of the code in this file are derived from the ipw2200
16 driver Copyright(c) 2003 - 2004 Intel Corporation.
18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; see the file COPYING. If not, write to
30 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31 Boston, MA 02110-1301, USA.
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
51 #include "phy_common.h"
61 #include <linux/mmc/sdio_func.h>
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82 "enable(1) / disable(0) Bad Frames Preemption");
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 #ifdef CONFIG_B43_BCMA_EXTRA
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
123 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
126 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
129 #ifdef CONFIG_B43_SSB
130 static const struct ssb_device_id b43_ssb_tbl[] = {
131 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
132 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
133 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
134 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
135 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
136 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
138 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
139 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
140 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
143 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
146 /* Channel and ratetables are shared for all devices.
147 * They can't be const, because ieee80211 puts some precalculated
148 * data in there. This data is the same for all devices, so we don't
149 * get concurrency issues */
150 #define RATETAB_ENT(_rateid, _flags) \
152 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
153 .hw_value = (_rateid), \
158 * NOTE: When changing this, sync with xmit.c's
159 * b43_plcp_get_bitrate_idx_* functions!
161 static struct ieee80211_rate __b43_ratetable[] = {
162 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
163 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
164 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
165 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
166 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
167 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
168 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
169 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
170 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
171 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
172 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
173 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
176 #define b43_a_ratetable (__b43_ratetable + 4)
177 #define b43_a_ratetable_size 8
178 #define b43_b_ratetable (__b43_ratetable + 0)
179 #define b43_b_ratetable_size 4
180 #define b43_g_ratetable (__b43_ratetable + 0)
181 #define b43_g_ratetable_size 12
183 #define CHAN4G(_channel, _freq, _flags) { \
184 .band = IEEE80211_BAND_2GHZ, \
185 .center_freq = (_freq), \
186 .hw_value = (_channel), \
188 .max_antenna_gain = 0, \
191 static struct ieee80211_channel b43_2ghz_chantable[] = {
209 #define CHAN5G(_channel, _flags) { \
210 .band = IEEE80211_BAND_5GHZ, \
211 .center_freq = 5000 + (5 * (_channel)), \
212 .hw_value = (_channel), \
214 .max_antenna_gain = 0, \
217 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
218 CHAN5G(32, 0), CHAN5G(34, 0),
219 CHAN5G(36, 0), CHAN5G(38, 0),
220 CHAN5G(40, 0), CHAN5G(42, 0),
221 CHAN5G(44, 0), CHAN5G(46, 0),
222 CHAN5G(48, 0), CHAN5G(50, 0),
223 CHAN5G(52, 0), CHAN5G(54, 0),
224 CHAN5G(56, 0), CHAN5G(58, 0),
225 CHAN5G(60, 0), CHAN5G(62, 0),
226 CHAN5G(64, 0), CHAN5G(66, 0),
227 CHAN5G(68, 0), CHAN5G(70, 0),
228 CHAN5G(72, 0), CHAN5G(74, 0),
229 CHAN5G(76, 0), CHAN5G(78, 0),
230 CHAN5G(80, 0), CHAN5G(82, 0),
231 CHAN5G(84, 0), CHAN5G(86, 0),
232 CHAN5G(88, 0), CHAN5G(90, 0),
233 CHAN5G(92, 0), CHAN5G(94, 0),
234 CHAN5G(96, 0), CHAN5G(98, 0),
235 CHAN5G(100, 0), CHAN5G(102, 0),
236 CHAN5G(104, 0), CHAN5G(106, 0),
237 CHAN5G(108, 0), CHAN5G(110, 0),
238 CHAN5G(112, 0), CHAN5G(114, 0),
239 CHAN5G(116, 0), CHAN5G(118, 0),
240 CHAN5G(120, 0), CHAN5G(122, 0),
241 CHAN5G(124, 0), CHAN5G(126, 0),
242 CHAN5G(128, 0), CHAN5G(130, 0),
243 CHAN5G(132, 0), CHAN5G(134, 0),
244 CHAN5G(136, 0), CHAN5G(138, 0),
245 CHAN5G(140, 0), CHAN5G(142, 0),
246 CHAN5G(144, 0), CHAN5G(145, 0),
247 CHAN5G(146, 0), CHAN5G(147, 0),
248 CHAN5G(148, 0), CHAN5G(149, 0),
249 CHAN5G(150, 0), CHAN5G(151, 0),
250 CHAN5G(152, 0), CHAN5G(153, 0),
251 CHAN5G(154, 0), CHAN5G(155, 0),
252 CHAN5G(156, 0), CHAN5G(157, 0),
253 CHAN5G(158, 0), CHAN5G(159, 0),
254 CHAN5G(160, 0), CHAN5G(161, 0),
255 CHAN5G(162, 0), CHAN5G(163, 0),
256 CHAN5G(164, 0), CHAN5G(165, 0),
257 CHAN5G(166, 0), CHAN5G(168, 0),
258 CHAN5G(170, 0), CHAN5G(172, 0),
259 CHAN5G(174, 0), CHAN5G(176, 0),
260 CHAN5G(178, 0), CHAN5G(180, 0),
261 CHAN5G(182, 0), CHAN5G(184, 0),
262 CHAN5G(186, 0), CHAN5G(188, 0),
263 CHAN5G(190, 0), CHAN5G(192, 0),
264 CHAN5G(194, 0), CHAN5G(196, 0),
265 CHAN5G(198, 0), CHAN5G(200, 0),
266 CHAN5G(202, 0), CHAN5G(204, 0),
267 CHAN5G(206, 0), CHAN5G(208, 0),
268 CHAN5G(210, 0), CHAN5G(212, 0),
269 CHAN5G(214, 0), CHAN5G(216, 0),
270 CHAN5G(218, 0), CHAN5G(220, 0),
271 CHAN5G(222, 0), CHAN5G(224, 0),
272 CHAN5G(226, 0), CHAN5G(228, 0),
275 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
276 CHAN5G(34, 0), CHAN5G(36, 0),
277 CHAN5G(38, 0), CHAN5G(40, 0),
278 CHAN5G(42, 0), CHAN5G(44, 0),
279 CHAN5G(46, 0), CHAN5G(48, 0),
280 CHAN5G(52, 0), CHAN5G(56, 0),
281 CHAN5G(60, 0), CHAN5G(64, 0),
282 CHAN5G(100, 0), CHAN5G(104, 0),
283 CHAN5G(108, 0), CHAN5G(112, 0),
284 CHAN5G(116, 0), CHAN5G(120, 0),
285 CHAN5G(124, 0), CHAN5G(128, 0),
286 CHAN5G(132, 0), CHAN5G(136, 0),
287 CHAN5G(140, 0), CHAN5G(149, 0),
288 CHAN5G(153, 0), CHAN5G(157, 0),
289 CHAN5G(161, 0), CHAN5G(165, 0),
290 CHAN5G(184, 0), CHAN5G(188, 0),
291 CHAN5G(192, 0), CHAN5G(196, 0),
292 CHAN5G(200, 0), CHAN5G(204, 0),
293 CHAN5G(208, 0), CHAN5G(212, 0),
298 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
299 .band = IEEE80211_BAND_5GHZ,
300 .channels = b43_5ghz_nphy_chantable,
301 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
302 .bitrates = b43_a_ratetable,
303 .n_bitrates = b43_a_ratetable_size,
306 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
307 .band = IEEE80211_BAND_5GHZ,
308 .channels = b43_5ghz_aphy_chantable,
309 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
310 .bitrates = b43_a_ratetable,
311 .n_bitrates = b43_a_ratetable_size,
314 static struct ieee80211_supported_band b43_band_2GHz = {
315 .band = IEEE80211_BAND_2GHZ,
316 .channels = b43_2ghz_chantable,
317 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
318 .bitrates = b43_g_ratetable,
319 .n_bitrates = b43_g_ratetable_size,
322 static void b43_wireless_core_exit(struct b43_wldev *dev);
323 static int b43_wireless_core_init(struct b43_wldev *dev);
324 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
325 static int b43_wireless_core_start(struct b43_wldev *dev);
326 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
327 struct ieee80211_vif *vif,
328 struct ieee80211_bss_conf *conf,
331 static int b43_ratelimit(struct b43_wl *wl)
333 if (!wl || !wl->current_dev)
335 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
337 /* We are up and running.
338 * Ratelimit the messages to avoid DoS over the net. */
339 return net_ratelimit();
342 void b43info(struct b43_wl *wl, const char *fmt, ...)
344 struct va_format vaf;
347 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
349 if (!b43_ratelimit(wl))
357 printk(KERN_INFO "b43-%s: %pV",
358 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
363 void b43err(struct b43_wl *wl, const char *fmt, ...)
365 struct va_format vaf;
368 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
370 if (!b43_ratelimit(wl))
378 printk(KERN_ERR "b43-%s ERROR: %pV",
379 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
384 void b43warn(struct b43_wl *wl, const char *fmt, ...)
386 struct va_format vaf;
389 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
391 if (!b43_ratelimit(wl))
399 printk(KERN_WARNING "b43-%s warning: %pV",
400 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
405 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
407 struct va_format vaf;
410 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
418 printk(KERN_DEBUG "b43-%s debug: %pV",
419 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
424 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
428 B43_WARN_ON(offset % 4 != 0);
430 macctl = b43_read32(dev, B43_MMIO_MACCTL);
431 if (macctl & B43_MACCTL_BE)
434 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
436 b43_write32(dev, B43_MMIO_RAM_DATA, val);
439 static inline void b43_shm_control_word(struct b43_wldev *dev,
440 u16 routing, u16 offset)
444 /* "offset" is the WORD offset. */
448 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
451 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
455 if (routing == B43_SHM_SHARED) {
456 B43_WARN_ON(offset & 0x0001);
457 if (offset & 0x0003) {
458 /* Unaligned access */
459 b43_shm_control_word(dev, routing, offset >> 2);
460 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
461 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
462 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
468 b43_shm_control_word(dev, routing, offset);
469 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
474 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
489 b43_shm_control_word(dev, routing, offset);
490 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
495 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
497 if (routing == B43_SHM_SHARED) {
498 B43_WARN_ON(offset & 0x0001);
499 if (offset & 0x0003) {
500 /* Unaligned access */
501 b43_shm_control_word(dev, routing, offset >> 2);
502 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
504 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505 b43_write16(dev, B43_MMIO_SHM_DATA,
506 (value >> 16) & 0xFFFF);
511 b43_shm_control_word(dev, routing, offset);
512 b43_write32(dev, B43_MMIO_SHM_DATA, value);
515 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
517 if (routing == B43_SHM_SHARED) {
518 B43_WARN_ON(offset & 0x0001);
519 if (offset & 0x0003) {
520 /* Unaligned access */
521 b43_shm_control_word(dev, routing, offset >> 2);
522 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
527 b43_shm_control_word(dev, routing, offset);
528 b43_write16(dev, B43_MMIO_SHM_DATA, value);
532 u64 b43_hf_read(struct b43_wldev *dev)
536 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
538 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
540 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
545 /* Write HostFlags */
546 void b43_hf_write(struct b43_wldev *dev, u64 value)
550 lo = (value & 0x00000000FFFFULL);
551 mi = (value & 0x0000FFFF0000ULL) >> 16;
552 hi = (value & 0xFFFF00000000ULL) >> 32;
553 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
554 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
555 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
558 /* Read the firmware capabilities bitmask (Opensource firmware only) */
559 static u16 b43_fwcapa_read(struct b43_wldev *dev)
561 B43_WARN_ON(!dev->fw.opensource);
562 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
565 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
569 B43_WARN_ON(dev->dev->core_rev < 3);
571 /* The hardware guarantees us an atomic read, if we
572 * read the low register first. */
573 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
574 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
581 static void b43_time_lock(struct b43_wldev *dev)
583 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
588 static void b43_time_unlock(struct b43_wldev *dev)
590 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
591 /* Commit the write */
592 b43_read32(dev, B43_MMIO_MACCTL);
595 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
599 B43_WARN_ON(dev->dev->core_rev < 3);
603 /* The hardware guarantees us an atomic write, if we
604 * write the low register first. */
605 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
607 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
611 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
614 b43_tsf_write_locked(dev, tsf);
615 b43_time_unlock(dev);
619 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
621 static const u8 zero_addr[ETH_ALEN] = { 0 };
628 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
632 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
635 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
638 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
641 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
645 u8 mac_bssid[ETH_ALEN * 2];
649 bssid = dev->wl->bssid;
650 mac = dev->wl->mac_addr;
652 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
654 memcpy(mac_bssid, mac, ETH_ALEN);
655 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
657 /* Write our MAC address and BSSID to template ram */
658 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
659 tmp = (u32) (mac_bssid[i + 0]);
660 tmp |= (u32) (mac_bssid[i + 1]) << 8;
661 tmp |= (u32) (mac_bssid[i + 2]) << 16;
662 tmp |= (u32) (mac_bssid[i + 3]) << 24;
663 b43_ram_write(dev, 0x20 + i, tmp);
667 static void b43_upload_card_macaddress(struct b43_wldev *dev)
669 b43_write_mac_bssid_templates(dev);
670 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
673 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
675 /* slot_time is in usec. */
676 /* This test used to exit for all but a G PHY. */
677 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
679 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
680 /* Shared memory location 0x0010 is the slot time and should be
681 * set to slot_time; however, this register is initially 0 and changing
682 * the value adversely affects the transmit rate for BCM4311
683 * devices. Until this behavior is unterstood, delete this step
685 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
689 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
691 b43_set_slot_time(dev, 9);
694 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
696 b43_set_slot_time(dev, 20);
699 /* DummyTransmission function, as documented on
700 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
702 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
704 struct b43_phy *phy = &dev->phy;
705 unsigned int i, max_loop;
717 buffer[0] = 0x000201CC;
720 buffer[0] = 0x000B846E;
723 for (i = 0; i < 5; i++)
724 b43_ram_write(dev, i * 4, buffer[i]);
726 b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
728 if (dev->dev->core_rev < 11)
729 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
731 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
733 value = (ofdm ? 0x41 : 0x40);
734 b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
735 if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
736 phy->type == B43_PHYTYPE_LCN)
737 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
739 b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
740 b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
742 b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
743 b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
744 b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
745 b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
747 if (!pa_on && phy->type == B43_PHYTYPE_N)
748 ; /*b43_nphy_pa_override(dev, false) */
752 case B43_PHYTYPE_LCN:
753 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
756 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
759 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
761 b43_read16(dev, B43_MMIO_TXE0_AUX);
763 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
764 b43_radio_write16(dev, 0x0051, 0x0017);
765 for (i = 0x00; i < max_loop; i++) {
766 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
771 for (i = 0x00; i < 0x0A; i++) {
772 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
777 for (i = 0x00; i < 0x19; i++) {
778 value = b43_read16(dev, B43_MMIO_IFSSTAT);
779 if (!(value & 0x0100))
783 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
784 b43_radio_write16(dev, 0x0051, 0x0037);
787 static void key_write(struct b43_wldev *dev,
788 u8 index, u8 algorithm, const u8 *key)
795 /* Key index/algo block */
796 kidx = b43_kidx_to_fw(dev, index);
797 value = ((kidx << 4) | algorithm);
798 b43_shm_write16(dev, B43_SHM_SHARED,
799 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
801 /* Write the key to the Key Table Pointer offset */
802 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
803 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
805 value |= (u16) (key[i + 1]) << 8;
806 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
810 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
812 u32 addrtmp[2] = { 0, 0, };
813 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
815 if (b43_new_kidx_api(dev))
816 pairwise_keys_start = B43_NR_GROUP_KEYS;
818 B43_WARN_ON(index < pairwise_keys_start);
819 /* We have four default TX keys and possibly four default RX keys.
820 * Physical mac 0 is mapped to physical key 4 or 8, depending
821 * on the firmware version.
822 * So we must adjust the index here.
824 index -= pairwise_keys_start;
825 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
828 addrtmp[0] = addr[0];
829 addrtmp[0] |= ((u32) (addr[1]) << 8);
830 addrtmp[0] |= ((u32) (addr[2]) << 16);
831 addrtmp[0] |= ((u32) (addr[3]) << 24);
832 addrtmp[1] = addr[4];
833 addrtmp[1] |= ((u32) (addr[5]) << 8);
836 /* Receive match transmitter address (RCMTA) mechanism */
837 b43_shm_write32(dev, B43_SHM_RCMTA,
838 (index * 2) + 0, addrtmp[0]);
839 b43_shm_write16(dev, B43_SHM_RCMTA,
840 (index * 2) + 1, addrtmp[1]);
843 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
844 * When a packet is received, the iv32 is checked.
845 * - if it doesn't the packet is returned without modification (and software
846 * decryption can be done). That's what happen when iv16 wrap.
847 * - if it does, the rc4 key is computed, and decryption is tried.
848 * Either it will success and B43_RX_MAC_DEC is returned,
849 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
850 * and the packet is not usable (it got modified by the ucode).
851 * So in order to never have B43_RX_MAC_DECERR, we should provide
852 * a iv32 and phase1key that match. Because we drop packets in case of
853 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
854 * packets will be lost without higher layer knowing (ie no resync possible
857 * NOTE : this should support 50 key like RCMTA because
858 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
860 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
865 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
867 if (!modparam_hwtkip)
870 if (b43_new_kidx_api(dev))
871 pairwise_keys_start = B43_NR_GROUP_KEYS;
873 B43_WARN_ON(index < pairwise_keys_start);
874 /* We have four default TX keys and possibly four default RX keys.
875 * Physical mac 0 is mapped to physical key 4 or 8, depending
876 * on the firmware version.
877 * So we must adjust the index here.
879 index -= pairwise_keys_start;
880 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
882 if (b43_debug(dev, B43_DBG_KEYS)) {
883 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
886 /* Write the key to the RX tkip shared mem */
887 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
888 for (i = 0; i < 10; i += 2) {
889 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
890 phase1key ? phase1key[i / 2] : 0);
892 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
893 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
896 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
897 struct ieee80211_vif *vif,
898 struct ieee80211_key_conf *keyconf,
899 struct ieee80211_sta *sta,
900 u32 iv32, u16 *phase1key)
902 struct b43_wl *wl = hw_to_b43_wl(hw);
903 struct b43_wldev *dev;
904 int index = keyconf->hw_key_idx;
906 if (B43_WARN_ON(!modparam_hwtkip))
909 /* This is only called from the RX path through mac80211, where
910 * our mutex is already locked. */
911 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
912 dev = wl->current_dev;
913 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
915 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
917 rx_tkip_phase1_write(dev, index, iv32, phase1key);
918 /* only pairwise TKIP keys are supported right now */
921 keymac_write(dev, index, sta->addr);
924 static void do_key_write(struct b43_wldev *dev,
925 u8 index, u8 algorithm,
926 const u8 *key, size_t key_len, const u8 *mac_addr)
928 u8 buf[B43_SEC_KEYSIZE] = { 0, };
929 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
931 if (b43_new_kidx_api(dev))
932 pairwise_keys_start = B43_NR_GROUP_KEYS;
934 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
935 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
937 if (index >= pairwise_keys_start)
938 keymac_write(dev, index, NULL); /* First zero out mac. */
939 if (algorithm == B43_SEC_ALGO_TKIP) {
941 * We should provide an initial iv32, phase1key pair.
942 * We could start with iv32=0 and compute the corresponding
943 * phase1key, but this means calling ieee80211_get_tkip_key
944 * with a fake skb (or export other tkip function).
945 * Because we are lazy we hope iv32 won't start with
946 * 0xffffffff and let's b43_op_update_tkip_key provide a
949 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
950 } else if (index >= pairwise_keys_start) /* clear it */
951 rx_tkip_phase1_write(dev, index, 0, NULL);
953 memcpy(buf, key, key_len);
954 key_write(dev, index, algorithm, buf);
955 if (index >= pairwise_keys_start)
956 keymac_write(dev, index, mac_addr);
958 dev->key[index].algorithm = algorithm;
961 static int b43_key_write(struct b43_wldev *dev,
962 int index, u8 algorithm,
963 const u8 *key, size_t key_len,
965 struct ieee80211_key_conf *keyconf)
968 int pairwise_keys_start;
970 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
971 * - Temporal Encryption Key (128 bits)
972 * - Temporal Authenticator Tx MIC Key (64 bits)
973 * - Temporal Authenticator Rx MIC Key (64 bits)
975 * Hardware only store TEK
977 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
979 if (key_len > B43_SEC_KEYSIZE)
981 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
982 /* Check that we don't already have this key. */
983 B43_WARN_ON(dev->key[i].keyconf == keyconf);
986 /* Pairwise key. Get an empty slot for the key. */
987 if (b43_new_kidx_api(dev))
988 pairwise_keys_start = B43_NR_GROUP_KEYS;
990 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
991 for (i = pairwise_keys_start;
992 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
994 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
995 if (!dev->key[i].keyconf) {
1002 b43warn(dev->wl, "Out of hardware key memory\n");
1006 B43_WARN_ON(index > 3);
1008 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010 /* Default RX key */
1011 B43_WARN_ON(mac_addr);
1012 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1014 keyconf->hw_key_idx = index;
1015 dev->key[index].keyconf = keyconf;
1020 static int b43_key_clear(struct b43_wldev *dev, int index)
1022 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1024 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025 NULL, B43_SEC_KEYSIZE, NULL);
1026 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028 NULL, B43_SEC_KEYSIZE, NULL);
1030 dev->key[index].keyconf = NULL;
1035 static void b43_clear_keys(struct b43_wldev *dev)
1039 if (b43_new_kidx_api(dev))
1040 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1042 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043 for (i = 0; i < count; i++)
1044 b43_key_clear(dev, i);
1047 static void b43_dump_keymemory(struct b43_wldev *dev)
1049 unsigned int i, index, count, offset, pairwise_keys_start;
1055 struct b43_key *key;
1057 if (!b43_debug(dev, B43_DBG_KEYS))
1060 hf = b43_hf_read(dev);
1061 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1062 !!(hf & B43_HF_USEDEFKEYS));
1063 if (b43_new_kidx_api(dev)) {
1064 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1067 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1070 for (index = 0; index < count; index++) {
1071 key = &(dev->key[index]);
1072 printk(KERN_DEBUG "Key slot %02u: %s",
1073 index, (key->keyconf == NULL) ? " " : "*");
1074 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1080 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082 printk(" Algo: %04X/%02X", algo, key->algorithm);
1084 if (index >= pairwise_keys_start) {
1085 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1087 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088 for (i = 0; i < 14; i += 2) {
1089 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1093 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1094 ((index - pairwise_keys_start) * 2) + 0);
1095 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1096 ((index - pairwise_keys_start) * 2) + 1);
1097 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1099 printk(" MAC: %pM", mac);
1101 printk(" DEFAULT KEY");
1106 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1114 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115 (ps_flags & B43_PS_DISABLED));
1116 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1118 if (ps_flags & B43_PS_ENABLED) {
1120 } else if (ps_flags & B43_PS_DISABLED) {
1123 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124 // and thus is not an AP and we are associated, set bit 25
1126 if (ps_flags & B43_PS_AWAKE) {
1128 } else if (ps_flags & B43_PS_ASLEEP) {
1131 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133 // successful, set bit26
1136 /* FIXME: For now we force awake-on and hwps-off */
1140 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1142 macctl |= B43_MACCTL_HWPS;
1144 macctl &= ~B43_MACCTL_HWPS;
1146 macctl |= B43_MACCTL_AWAKE;
1148 macctl &= ~B43_MACCTL_AWAKE;
1149 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1151 b43_read32(dev, B43_MMIO_MACCTL);
1152 if (awake && dev->dev->core_rev >= 5) {
1153 /* Wait for the microcode to wake up. */
1154 for (i = 0; i < 100; i++) {
1155 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156 B43_SHM_SH_UCODESTAT);
1157 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1164 #ifdef CONFIG_B43_BCMA
1165 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1169 /* Put PHY into reset */
1170 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171 flags |= B43_BCMA_IOCTL_PHY_RESET;
1172 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1173 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1176 /* Take PHY out of reset */
1177 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179 flags |= BCMA_IOCTL_FGC;
1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1183 /* Do not force clock anymore */
1184 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185 flags &= ~BCMA_IOCTL_FGC;
1186 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1190 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1192 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194 b43_bcma_phy_reset(dev);
1195 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1199 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1201 struct ssb_device *sdev = dev->dev->sdev;
1206 flags |= B43_TMSLOW_GMODE;
1207 flags |= B43_TMSLOW_PHYCLKEN;
1208 flags |= B43_TMSLOW_PHYRESET;
1209 if (dev->phy.type == B43_PHYTYPE_N)
1210 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1211 b43_device_enable(dev, flags);
1212 msleep(2); /* Wait for the PLL to turn on. */
1214 /* Now take the PHY out of Reset again */
1215 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1216 tmslow |= SSB_TMSLOW_FGC;
1217 tmslow &= ~B43_TMSLOW_PHYRESET;
1218 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1219 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1221 tmslow &= ~SSB_TMSLOW_FGC;
1222 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1223 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1227 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1231 switch (dev->dev->bus_type) {
1232 #ifdef CONFIG_B43_BCMA
1234 b43_bcma_wireless_core_reset(dev, gmode);
1237 #ifdef CONFIG_B43_SSB
1239 b43_ssb_wireless_core_reset(dev, gmode);
1244 /* Turn Analog ON, but only if we already know the PHY-type.
1245 * This protects against very early setup where we don't know the
1246 * PHY-type, yet. wireless_core_reset will be called once again later,
1247 * when we know the PHY-type. */
1249 dev->phy.ops->switch_analog(dev, 1);
1251 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1252 macctl &= ~B43_MACCTL_GMODE;
1254 macctl |= B43_MACCTL_GMODE;
1255 macctl |= B43_MACCTL_IHR_ENABLED;
1256 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1259 static void handle_irq_transmit_status(struct b43_wldev *dev)
1263 struct b43_txstatus stat;
1266 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1267 if (!(v0 & 0x00000001))
1269 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1271 stat.cookie = (v0 >> 16);
1272 stat.seq = (v1 & 0x0000FFFF);
1273 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1274 tmp = (v0 & 0x0000FFFF);
1275 stat.frame_count = ((tmp & 0xF000) >> 12);
1276 stat.rts_count = ((tmp & 0x0F00) >> 8);
1277 stat.supp_reason = ((tmp & 0x001C) >> 2);
1278 stat.pm_indicated = !!(tmp & 0x0080);
1279 stat.intermediate = !!(tmp & 0x0040);
1280 stat.for_ampdu = !!(tmp & 0x0020);
1281 stat.acked = !!(tmp & 0x0002);
1283 b43_handle_txstatus(dev, &stat);
1287 static void drain_txstatus_queue(struct b43_wldev *dev)
1291 if (dev->dev->core_rev < 5)
1293 /* Read all entries from the microcode TXstatus FIFO
1294 * and throw them away.
1297 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1298 if (!(dummy & 0x00000001))
1300 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1304 static u32 b43_jssi_read(struct b43_wldev *dev)
1308 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1310 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1315 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1318 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1321 static void b43_generate_noise_sample(struct b43_wldev *dev)
1323 b43_jssi_write(dev, 0x7F7F7F7F);
1324 b43_write32(dev, B43_MMIO_MACCMD,
1325 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1328 static void b43_calculate_link_quality(struct b43_wldev *dev)
1330 /* Top half of Link Quality calculation. */
1332 if (dev->phy.type != B43_PHYTYPE_G)
1334 if (dev->noisecalc.calculation_running)
1336 dev->noisecalc.calculation_running = true;
1337 dev->noisecalc.nr_samples = 0;
1339 b43_generate_noise_sample(dev);
1342 static void handle_irq_noise(struct b43_wldev *dev)
1344 struct b43_phy_g *phy = dev->phy.g;
1350 /* Bottom half of Link Quality calculation. */
1352 if (dev->phy.type != B43_PHYTYPE_G)
1355 /* Possible race condition: It might be possible that the user
1356 * changed to a different channel in the meantime since we
1357 * started the calculation. We ignore that fact, since it's
1358 * not really that much of a problem. The background noise is
1359 * an estimation only anyway. Slightly wrong results will get damped
1360 * by the averaging of the 8 sample rounds. Additionally the
1361 * value is shortlived. So it will be replaced by the next noise
1362 * calculation round soon. */
1364 B43_WARN_ON(!dev->noisecalc.calculation_running);
1365 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1366 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1367 noise[2] == 0x7F || noise[3] == 0x7F)
1370 /* Get the noise samples. */
1371 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1372 i = dev->noisecalc.nr_samples;
1373 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1378 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1379 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1380 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1381 dev->noisecalc.nr_samples++;
1382 if (dev->noisecalc.nr_samples == 8) {
1383 /* Calculate the Link Quality by the noise samples. */
1385 for (i = 0; i < 8; i++) {
1386 for (j = 0; j < 4; j++)
1387 average += dev->noisecalc.samples[i][j];
1393 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1394 tmp = (tmp / 128) & 0x1F;
1404 dev->stats.link_noise = average;
1405 dev->noisecalc.calculation_running = false;
1409 b43_generate_noise_sample(dev);
1412 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1414 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1417 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1418 b43_power_saving_ctl_bits(dev, 0);
1420 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1421 dev->dfq_valid = true;
1424 static void handle_irq_atim_end(struct b43_wldev *dev)
1426 if (dev->dfq_valid) {
1427 b43_write32(dev, B43_MMIO_MACCMD,
1428 b43_read32(dev, B43_MMIO_MACCMD)
1429 | B43_MACCMD_DFQ_VALID);
1430 dev->dfq_valid = false;
1434 static void handle_irq_pmq(struct b43_wldev *dev)
1441 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1442 if (!(tmp & 0x00000008))
1445 /* 16bit write is odd, but correct. */
1446 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1449 static void b43_write_template_common(struct b43_wldev *dev,
1450 const u8 *data, u16 size,
1452 u16 shm_size_offset, u8 rate)
1455 struct b43_plcp_hdr4 plcp;
1458 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1459 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1460 ram_offset += sizeof(u32);
1461 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1462 * So leave the first two bytes of the next write blank.
1464 tmp = (u32) (data[0]) << 16;
1465 tmp |= (u32) (data[1]) << 24;
1466 b43_ram_write(dev, ram_offset, tmp);
1467 ram_offset += sizeof(u32);
1468 for (i = 2; i < size; i += sizeof(u32)) {
1469 tmp = (u32) (data[i + 0]);
1471 tmp |= (u32) (data[i + 1]) << 8;
1473 tmp |= (u32) (data[i + 2]) << 16;
1475 tmp |= (u32) (data[i + 3]) << 24;
1476 b43_ram_write(dev, ram_offset + i - 2, tmp);
1478 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1479 size + sizeof(struct b43_plcp_hdr6));
1482 /* Check if the use of the antenna that ieee80211 told us to
1483 * use is possible. This will fall back to DEFAULT.
1484 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1485 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1490 if (antenna_nr == 0) {
1491 /* Zero means "use default antenna". That's always OK. */
1495 /* Get the mask of available antennas. */
1497 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1499 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1501 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1502 /* This antenna is not available. Fall back to default. */
1509 /* Convert a b43 antenna number value to the PHY TX control value. */
1510 static u16 b43_antenna_to_phyctl(int antenna)
1514 return B43_TXH_PHY_ANT0;
1516 return B43_TXH_PHY_ANT1;
1518 return B43_TXH_PHY_ANT2;
1520 return B43_TXH_PHY_ANT3;
1521 case B43_ANTENNA_AUTO0:
1522 case B43_ANTENNA_AUTO1:
1523 return B43_TXH_PHY_ANT01AUTO;
1529 static void b43_write_beacon_template(struct b43_wldev *dev,
1531 u16 shm_size_offset)
1533 unsigned int i, len, variable_len;
1534 const struct ieee80211_mgmt *bcn;
1536 bool tim_found = false;
1540 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1542 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1543 len = min((size_t) dev->wl->current_beacon->len,
1544 0x200 - sizeof(struct b43_plcp_hdr6));
1545 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1547 b43_write_template_common(dev, (const u8 *)bcn,
1548 len, ram_offset, shm_size_offset, rate);
1550 /* Write the PHY TX control parameters. */
1551 antenna = B43_ANTENNA_DEFAULT;
1552 antenna = b43_antenna_to_phyctl(antenna);
1553 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1554 /* We can't send beacons with short preamble. Would get PHY errors. */
1555 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1556 ctl &= ~B43_TXH_PHY_ANT;
1557 ctl &= ~B43_TXH_PHY_ENC;
1559 if (b43_is_cck_rate(rate))
1560 ctl |= B43_TXH_PHY_ENC_CCK;
1562 ctl |= B43_TXH_PHY_ENC_OFDM;
1563 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1565 /* Find the position of the TIM and the DTIM_period value
1566 * and write them to SHM. */
1567 ie = bcn->u.beacon.variable;
1568 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1569 for (i = 0; i < variable_len - 2; ) {
1570 uint8_t ie_id, ie_len;
1577 /* This is the TIM Information Element */
1579 /* Check whether the ie_len is in the beacon data range. */
1580 if (variable_len < ie_len + 2 + i)
1582 /* A valid TIM is at least 4 bytes long. */
1587 tim_position = sizeof(struct b43_plcp_hdr6);
1588 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1591 dtim_period = ie[i + 3];
1593 b43_shm_write16(dev, B43_SHM_SHARED,
1594 B43_SHM_SH_TIMBPOS, tim_position);
1595 b43_shm_write16(dev, B43_SHM_SHARED,
1596 B43_SHM_SH_DTIMPER, dtim_period);
1603 * If ucode wants to modify TIM do it behind the beacon, this
1604 * will happen, for example, when doing mesh networking.
1606 b43_shm_write16(dev, B43_SHM_SHARED,
1608 len + sizeof(struct b43_plcp_hdr6));
1609 b43_shm_write16(dev, B43_SHM_SHARED,
1610 B43_SHM_SH_DTIMPER, 0);
1612 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1615 static void b43_upload_beacon0(struct b43_wldev *dev)
1617 struct b43_wl *wl = dev->wl;
1619 if (wl->beacon0_uploaded)
1621 b43_write_beacon_template(dev, 0x68, 0x18);
1622 wl->beacon0_uploaded = true;
1625 static void b43_upload_beacon1(struct b43_wldev *dev)
1627 struct b43_wl *wl = dev->wl;
1629 if (wl->beacon1_uploaded)
1631 b43_write_beacon_template(dev, 0x468, 0x1A);
1632 wl->beacon1_uploaded = true;
1635 static void handle_irq_beacon(struct b43_wldev *dev)
1637 struct b43_wl *wl = dev->wl;
1638 u32 cmd, beacon0_valid, beacon1_valid;
1640 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1641 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1642 !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1645 /* This is the bottom half of the asynchronous beacon update. */
1647 /* Ignore interrupt in the future. */
1648 dev->irq_mask &= ~B43_IRQ_BEACON;
1650 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1651 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1652 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1654 /* Schedule interrupt manually, if busy. */
1655 if (beacon0_valid && beacon1_valid) {
1656 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1657 dev->irq_mask |= B43_IRQ_BEACON;
1661 if (unlikely(wl->beacon_templates_virgin)) {
1662 /* We never uploaded a beacon before.
1663 * Upload both templates now, but only mark one valid. */
1664 wl->beacon_templates_virgin = false;
1665 b43_upload_beacon0(dev);
1666 b43_upload_beacon1(dev);
1667 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1668 cmd |= B43_MACCMD_BEACON0_VALID;
1669 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1671 if (!beacon0_valid) {
1672 b43_upload_beacon0(dev);
1673 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1674 cmd |= B43_MACCMD_BEACON0_VALID;
1675 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1676 } else if (!beacon1_valid) {
1677 b43_upload_beacon1(dev);
1678 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1679 cmd |= B43_MACCMD_BEACON1_VALID;
1680 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1685 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1687 u32 old_irq_mask = dev->irq_mask;
1689 /* update beacon right away or defer to irq */
1690 handle_irq_beacon(dev);
1691 if (old_irq_mask != dev->irq_mask) {
1692 /* The handler updated the IRQ mask. */
1693 B43_WARN_ON(!dev->irq_mask);
1694 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1695 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1697 /* Device interrupts are currently disabled. That means
1698 * we just ran the hardirq handler and scheduled the
1699 * IRQ thread. The thread will write the IRQ mask when
1700 * it finished, so there's nothing to do here. Writing
1701 * the mask _here_ would incorrectly re-enable IRQs. */
1706 static void b43_beacon_update_trigger_work(struct work_struct *work)
1708 struct b43_wl *wl = container_of(work, struct b43_wl,
1709 beacon_update_trigger);
1710 struct b43_wldev *dev;
1712 mutex_lock(&wl->mutex);
1713 dev = wl->current_dev;
1714 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1715 if (b43_bus_host_is_sdio(dev->dev)) {
1716 /* wl->mutex is enough. */
1717 b43_do_beacon_update_trigger_work(dev);
1720 spin_lock_irq(&wl->hardirq_lock);
1721 b43_do_beacon_update_trigger_work(dev);
1723 spin_unlock_irq(&wl->hardirq_lock);
1726 mutex_unlock(&wl->mutex);
1729 /* Asynchronously update the packet templates in template RAM.
1730 * Locking: Requires wl->mutex to be locked. */
1731 static void b43_update_templates(struct b43_wl *wl)
1733 struct sk_buff *beacon;
1735 /* This is the top half of the ansynchronous beacon update.
1736 * The bottom half is the beacon IRQ.
1737 * Beacon update must be asynchronous to avoid sending an
1738 * invalid beacon. This can happen for example, if the firmware
1739 * transmits a beacon while we are updating it. */
1741 /* We could modify the existing beacon and set the aid bit in
1742 * the TIM field, but that would probably require resizing and
1743 * moving of data within the beacon template.
1744 * Simply request a new beacon and let mac80211 do the hard work. */
1745 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1746 if (unlikely(!beacon))
1749 if (wl->current_beacon)
1750 dev_kfree_skb_any(wl->current_beacon);
1751 wl->current_beacon = beacon;
1752 wl->beacon0_uploaded = false;
1753 wl->beacon1_uploaded = false;
1754 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1757 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1760 if (dev->dev->core_rev >= 3) {
1761 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1762 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1764 b43_write16(dev, 0x606, (beacon_int >> 6));
1765 b43_write16(dev, 0x610, beacon_int);
1767 b43_time_unlock(dev);
1768 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1771 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1775 /* Read the register that contains the reason code for the panic. */
1776 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1777 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1781 b43dbg(dev->wl, "The panic reason is unknown.\n");
1783 case B43_FWPANIC_DIE:
1784 /* Do not restart the controller or firmware.
1785 * The device is nonfunctional from now on.
1786 * Restarting would result in this panic to trigger again,
1787 * so we avoid that recursion. */
1789 case B43_FWPANIC_RESTART:
1790 b43_controller_restart(dev, "Microcode panic");
1795 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1797 unsigned int i, cnt;
1798 u16 reason, marker_id, marker_line;
1801 /* The proprietary firmware doesn't have this IRQ. */
1802 if (!dev->fw.opensource)
1805 /* Read the register that contains the reason code for this IRQ. */
1806 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1809 case B43_DEBUGIRQ_PANIC:
1810 b43_handle_firmware_panic(dev);
1812 case B43_DEBUGIRQ_DUMP_SHM:
1814 break; /* Only with driver debugging enabled. */
1815 buf = kmalloc(4096, GFP_ATOMIC);
1817 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1820 for (i = 0; i < 4096; i += 2) {
1821 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1822 buf[i / 2] = cpu_to_le16(tmp);
1824 b43info(dev->wl, "Shared memory dump:\n");
1825 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1826 16, 2, buf, 4096, 1);
1829 case B43_DEBUGIRQ_DUMP_REGS:
1831 break; /* Only with driver debugging enabled. */
1832 b43info(dev->wl, "Microcode register dump:\n");
1833 for (i = 0, cnt = 0; i < 64; i++) {
1834 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1837 printk("r%02u: 0x%04X ", i, tmp);
1846 case B43_DEBUGIRQ_MARKER:
1848 break; /* Only with driver debugging enabled. */
1849 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1851 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1852 B43_MARKER_LINE_REG);
1853 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1854 "at line number %u\n",
1855 marker_id, marker_line);
1858 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1862 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1863 b43_shm_write16(dev, B43_SHM_SCRATCH,
1864 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1867 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1870 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1871 u32 merged_dma_reason = 0;
1874 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1877 reason = dev->irq_reason;
1878 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1879 dma_reason[i] = dev->dma_reason[i];
1880 merged_dma_reason |= dma_reason[i];
1883 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1884 b43err(dev->wl, "MAC transmission error\n");
1886 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1887 b43err(dev->wl, "PHY transmission error\n");
1889 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1890 atomic_set(&dev->phy.txerr_cnt,
1891 B43_PHY_TX_BADNESS_LIMIT);
1892 b43err(dev->wl, "Too many PHY TX errors, "
1893 "restarting the controller\n");
1894 b43_controller_restart(dev, "PHY TX errors");
1898 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1899 B43_DMAIRQ_NONFATALMASK))) {
1900 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1901 b43err(dev->wl, "Fatal DMA error: "
1902 "0x%08X, 0x%08X, 0x%08X, "
1903 "0x%08X, 0x%08X, 0x%08X\n",
1904 dma_reason[0], dma_reason[1],
1905 dma_reason[2], dma_reason[3],
1906 dma_reason[4], dma_reason[5]);
1907 b43err(dev->wl, "This device does not support DMA "
1908 "on your system. It will now be switched to PIO.\n");
1909 /* Fall back to PIO transfers if we get fatal DMA errors! */
1910 dev->use_pio = true;
1911 b43_controller_restart(dev, "DMA error");
1914 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1915 b43err(dev->wl, "DMA error: "
1916 "0x%08X, 0x%08X, 0x%08X, "
1917 "0x%08X, 0x%08X, 0x%08X\n",
1918 dma_reason[0], dma_reason[1],
1919 dma_reason[2], dma_reason[3],
1920 dma_reason[4], dma_reason[5]);
1924 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1925 handle_irq_ucode_debug(dev);
1926 if (reason & B43_IRQ_TBTT_INDI)
1927 handle_irq_tbtt_indication(dev);
1928 if (reason & B43_IRQ_ATIM_END)
1929 handle_irq_atim_end(dev);
1930 if (reason & B43_IRQ_BEACON)
1931 handle_irq_beacon(dev);
1932 if (reason & B43_IRQ_PMQ)
1933 handle_irq_pmq(dev);
1934 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1936 if (reason & B43_IRQ_NOISESAMPLE_OK)
1937 handle_irq_noise(dev);
1939 /* Check the DMA reason registers for received data. */
1940 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1941 if (b43_using_pio_transfers(dev))
1942 b43_pio_rx(dev->pio.rx_queue);
1944 b43_dma_rx(dev->dma.rx_ring);
1946 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1947 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1948 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1949 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1950 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1952 if (reason & B43_IRQ_TX_OK)
1953 handle_irq_transmit_status(dev);
1955 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1956 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1959 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1961 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1962 if (reason & (1 << i))
1963 dev->irq_bit_count[i]++;
1969 /* Interrupt thread handler. Handles device interrupts in thread context. */
1970 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1972 struct b43_wldev *dev = dev_id;
1974 mutex_lock(&dev->wl->mutex);
1975 b43_do_interrupt_thread(dev);
1977 mutex_unlock(&dev->wl->mutex);
1982 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1986 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1987 * On SDIO, this runs under wl->mutex. */
1989 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990 if (reason == 0xffffffff) /* shared IRQ */
1992 reason &= dev->irq_mask;
1996 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1998 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
2000 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2002 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2004 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2007 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2011 /* ACK the interrupt. */
2012 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2013 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2014 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2015 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2016 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2017 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2019 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2022 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2023 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2024 /* Save the reason bitmasks for the IRQ thread handler. */
2025 dev->irq_reason = reason;
2027 return IRQ_WAKE_THREAD;
2030 /* Interrupt handler top-half. This runs with interrupts disabled. */
2031 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2033 struct b43_wldev *dev = dev_id;
2036 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2039 spin_lock(&dev->wl->hardirq_lock);
2040 ret = b43_do_interrupt(dev);
2042 spin_unlock(&dev->wl->hardirq_lock);
2047 /* SDIO interrupt handler. This runs in process context. */
2048 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2050 struct b43_wl *wl = dev->wl;
2053 mutex_lock(&wl->mutex);
2055 ret = b43_do_interrupt(dev);
2056 if (ret == IRQ_WAKE_THREAD)
2057 b43_do_interrupt_thread(dev);
2059 mutex_unlock(&wl->mutex);
2062 void b43_do_release_fw(struct b43_firmware_file *fw)
2064 release_firmware(fw->data);
2066 fw->filename = NULL;
2069 static void b43_release_firmware(struct b43_wldev *dev)
2071 b43_do_release_fw(&dev->fw.ucode);
2072 b43_do_release_fw(&dev->fw.pcm);
2073 b43_do_release_fw(&dev->fw.initvals);
2074 b43_do_release_fw(&dev->fw.initvals_band);
2077 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2081 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2082 "and download the correct firmware for this driver version. " \
2083 "Please carefully read all instructions on this website.\n";
2091 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2093 struct b43_firmware_file *fw)
2095 const struct firmware *blob;
2096 struct b43_fw_header *hdr;
2101 /* Don't fetch anything. Free possibly cached firmware. */
2102 /* FIXME: We should probably keep it anyway, to save some headache
2103 * on suspend/resume with multiband devices. */
2104 b43_do_release_fw(fw);
2108 if ((fw->type == ctx->req_type) &&
2109 (strcmp(fw->filename, name) == 0))
2110 return 0; /* Already have this fw. */
2111 /* Free the cached firmware first. */
2112 /* FIXME: We should probably do this later after we successfully
2113 * got the new fw. This could reduce headache with multiband devices.
2114 * We could also redesign this to cache the firmware for all possible
2115 * bands all the time. */
2116 b43_do_release_fw(fw);
2119 switch (ctx->req_type) {
2120 case B43_FWTYPE_PROPRIETARY:
2121 snprintf(ctx->fwname, sizeof(ctx->fwname),
2123 modparam_fwpostfix, name);
2125 case B43_FWTYPE_OPENSOURCE:
2126 snprintf(ctx->fwname, sizeof(ctx->fwname),
2128 modparam_fwpostfix, name);
2134 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2135 if (err == -ENOENT) {
2136 snprintf(ctx->errors[ctx->req_type],
2137 sizeof(ctx->errors[ctx->req_type]),
2138 "Firmware file \"%s\" not found\n", ctx->fwname);
2141 snprintf(ctx->errors[ctx->req_type],
2142 sizeof(ctx->errors[ctx->req_type]),
2143 "Firmware file \"%s\" request failed (err=%d)\n",
2147 if (blob->size < sizeof(struct b43_fw_header))
2149 hdr = (struct b43_fw_header *)(blob->data);
2150 switch (hdr->type) {
2151 case B43_FW_TYPE_UCODE:
2152 case B43_FW_TYPE_PCM:
2153 size = be32_to_cpu(hdr->size);
2154 if (size != blob->size - sizeof(struct b43_fw_header))
2157 case B43_FW_TYPE_IV:
2166 fw->filename = name;
2167 fw->type = ctx->req_type;
2172 snprintf(ctx->errors[ctx->req_type],
2173 sizeof(ctx->errors[ctx->req_type]),
2174 "Firmware file \"%s\" format error.\n", ctx->fwname);
2175 release_firmware(blob);
2180 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2182 struct b43_wldev *dev = ctx->dev;
2183 struct b43_firmware *fw = &ctx->dev->fw;
2184 const u8 rev = ctx->dev->dev->core_rev;
2185 const char *filename;
2189 /* Files for HT and LCN were found by trying one by one */
2192 if ((rev >= 5) && (rev <= 10)) {
2193 filename = "ucode5";
2194 } else if ((rev >= 11) && (rev <= 12)) {
2195 filename = "ucode11";
2196 } else if (rev == 13) {
2197 filename = "ucode13";
2198 } else if (rev == 14) {
2199 filename = "ucode14";
2200 } else if (rev == 15) {
2201 filename = "ucode15";
2203 switch (dev->phy.type) {
2206 filename = "ucode16_mimo";
2210 case B43_PHYTYPE_HT:
2212 filename = "ucode29_mimo";
2216 case B43_PHYTYPE_LCN:
2218 filename = "ucode24_mimo";
2226 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2231 if ((rev >= 5) && (rev <= 10))
2237 fw->pcm_request_failed = false;
2238 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2239 if (err == -ENOENT) {
2240 /* We did not find a PCM file? Not fatal, but
2241 * core rev <= 10 must do without hwcrypto then. */
2242 fw->pcm_request_failed = true;
2247 switch (dev->phy.type) {
2249 if ((rev >= 5) && (rev <= 10)) {
2250 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2251 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2252 filename = "a0g1initvals5";
2254 filename = "a0g0initvals5";
2256 goto err_no_initvals;
2259 if ((rev >= 5) && (rev <= 10))
2260 filename = "b0g0initvals5";
2262 filename = "b0g0initvals13";
2264 goto err_no_initvals;
2268 filename = "n0initvals16";
2269 else if ((rev >= 11) && (rev <= 12))
2270 filename = "n0initvals11";
2272 goto err_no_initvals;
2274 case B43_PHYTYPE_LP:
2276 filename = "lp0initvals13";
2278 filename = "lp0initvals14";
2280 filename = "lp0initvals15";
2282 goto err_no_initvals;
2284 case B43_PHYTYPE_HT:
2286 filename = "ht0initvals29";
2288 goto err_no_initvals;
2290 case B43_PHYTYPE_LCN:
2292 filename = "lcn0initvals24";
2294 goto err_no_initvals;
2297 goto err_no_initvals;
2299 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2303 /* Get bandswitch initvals */
2304 switch (dev->phy.type) {
2306 if ((rev >= 5) && (rev <= 10)) {
2307 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2308 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2309 filename = "a0g1bsinitvals5";
2311 filename = "a0g0bsinitvals5";
2312 } else if (rev >= 11)
2315 goto err_no_initvals;
2318 if ((rev >= 5) && (rev <= 10))
2319 filename = "b0g0bsinitvals5";
2323 goto err_no_initvals;
2327 filename = "n0bsinitvals16";
2328 else if ((rev >= 11) && (rev <= 12))
2329 filename = "n0bsinitvals11";
2331 goto err_no_initvals;
2333 case B43_PHYTYPE_LP:
2335 filename = "lp0bsinitvals13";
2337 filename = "lp0bsinitvals14";
2339 filename = "lp0bsinitvals15";
2341 goto err_no_initvals;
2343 case B43_PHYTYPE_HT:
2345 filename = "ht0bsinitvals29";
2347 goto err_no_initvals;
2349 case B43_PHYTYPE_LCN:
2351 filename = "lcn0bsinitvals24";
2353 goto err_no_initvals;
2356 goto err_no_initvals;
2358 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2365 err = ctx->fatal_failure = -EOPNOTSUPP;
2366 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2367 "is required for your device (wl-core rev %u)\n", rev);
2371 err = ctx->fatal_failure = -EOPNOTSUPP;
2372 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2373 "is required for your device (wl-core rev %u)\n", rev);
2377 err = ctx->fatal_failure = -EOPNOTSUPP;
2378 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2379 "is required for your device (wl-core rev %u)\n", rev);
2383 /* We failed to load this firmware image. The error message
2384 * already is in ctx->errors. Return and let our caller decide
2389 b43_release_firmware(dev);
2393 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2394 static void b43_one_core_detach(struct b43_bus_dev *dev);
2396 static void b43_request_firmware(struct work_struct *work)
2398 struct b43_wl *wl = container_of(work,
2399 struct b43_wl, firmware_load);
2400 struct b43_wldev *dev = wl->current_dev;
2401 struct b43_request_fw_context *ctx;
2406 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2411 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2412 err = b43_try_request_fw(ctx);
2414 goto start_ieee80211; /* Successfully loaded it. */
2415 /* Was fw version known? */
2416 if (ctx->fatal_failure)
2419 /* proprietary fw not found, try open source */
2420 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2421 err = b43_try_request_fw(ctx);
2423 goto start_ieee80211; /* Successfully loaded it. */
2424 if(ctx->fatal_failure)
2427 /* Could not find a usable firmware. Print the errors. */
2428 for (i = 0; i < B43_NR_FWTYPES; i++) {
2429 errmsg = ctx->errors[i];
2431 b43err(dev->wl, errmsg);
2433 b43_print_fw_helptext(dev->wl, 1);
2437 err = ieee80211_register_hw(wl->hw);
2439 goto err_one_core_detach;
2440 wl->hw_registred = true;
2441 b43_leds_register(wl->current_dev);
2444 err_one_core_detach:
2445 b43_one_core_detach(dev->dev);
2451 static int b43_upload_microcode(struct b43_wldev *dev)
2453 struct wiphy *wiphy = dev->wl->hw->wiphy;
2454 const size_t hdr_len = sizeof(struct b43_fw_header);
2456 unsigned int i, len;
2457 u16 fwrev, fwpatch, fwdate, fwtime;
2461 /* Jump the microcode PSM to offset 0 */
2462 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2463 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2464 macctl |= B43_MACCTL_PSM_JMP0;
2465 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2466 /* Zero out all microcode PSM registers and shared memory. */
2467 for (i = 0; i < 64; i++)
2468 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2469 for (i = 0; i < 4096; i += 2)
2470 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2472 /* Upload Microcode. */
2473 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2474 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2475 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2476 for (i = 0; i < len; i++) {
2477 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2481 if (dev->fw.pcm.data) {
2482 /* Upload PCM data. */
2483 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2484 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2485 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2486 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2487 /* No need for autoinc bit in SHM_HW */
2488 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2489 for (i = 0; i < len; i++) {
2490 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2495 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2497 /* Start the microcode PSM */
2498 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2499 B43_MACCTL_PSM_RUN);
2501 /* Wait for the microcode to load and respond */
2504 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2505 if (tmp == B43_IRQ_MAC_SUSPENDED)
2509 b43err(dev->wl, "Microcode not responding\n");
2510 b43_print_fw_helptext(dev->wl, 1);
2516 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2518 /* Get and check the revisions. */
2519 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2520 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2521 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2522 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2524 if (fwrev <= 0x128) {
2525 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2526 "binary drivers older than version 4.x is unsupported. "
2527 "You must upgrade your firmware files.\n");
2528 b43_print_fw_helptext(dev->wl, 1);
2532 dev->fw.rev = fwrev;
2533 dev->fw.patch = fwpatch;
2534 if (dev->fw.rev >= 598)
2535 dev->fw.hdr_format = B43_FW_HDR_598;
2536 else if (dev->fw.rev >= 410)
2537 dev->fw.hdr_format = B43_FW_HDR_410;
2539 dev->fw.hdr_format = B43_FW_HDR_351;
2540 dev->fw.opensource = (fwdate == 0xFFFF);
2542 /* Default to use-all-queues. */
2543 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2544 dev->qos_enabled = !!modparam_qos;
2545 /* Default to firmware/hardware crypto acceleration. */
2546 dev->hwcrypto_enabled = true;
2548 if (dev->fw.opensource) {
2551 /* Patchlevel info is encoded in the "time" field. */
2552 dev->fw.patch = fwtime;
2553 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2554 dev->fw.rev, dev->fw.patch);
2556 fwcapa = b43_fwcapa_read(dev);
2557 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2558 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2559 /* Disable hardware crypto and fall back to software crypto. */
2560 dev->hwcrypto_enabled = false;
2562 if (!(fwcapa & B43_FWCAPA_QOS)) {
2563 b43info(dev->wl, "QoS not supported by firmware\n");
2564 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2565 * ieee80211_unregister to make sure the networking core can
2566 * properly free possible resources. */
2567 dev->wl->hw->queues = 1;
2568 dev->qos_enabled = false;
2571 b43info(dev->wl, "Loading firmware version %u.%u "
2572 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2574 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2575 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2576 if (dev->fw.pcm_request_failed) {
2577 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2578 "Hardware accelerated cryptography is disabled.\n");
2579 b43_print_fw_helptext(dev->wl, 0);
2583 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2584 dev->fw.rev, dev->fw.patch);
2585 wiphy->hw_version = dev->dev->core_id;
2587 if (dev->fw.hdr_format == B43_FW_HDR_351) {
2588 /* We're over the deadline, but we keep support for old fw
2589 * until it turns out to be in major conflict with something new. */
2590 b43warn(dev->wl, "You are using an old firmware image. "
2591 "Support for old firmware will be removed soon "
2592 "(official deadline was July 2008).\n");
2593 b43_print_fw_helptext(dev->wl, 0);
2599 /* Stop the microcode PSM. */
2600 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2601 B43_MACCTL_PSM_JMP0);
2606 static int b43_write_initvals(struct b43_wldev *dev,
2607 const struct b43_iv *ivals,
2611 const struct b43_iv *iv;
2616 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2618 for (i = 0; i < count; i++) {
2619 if (array_size < sizeof(iv->offset_size))
2621 array_size -= sizeof(iv->offset_size);
2622 offset = be16_to_cpu(iv->offset_size);
2623 bit32 = !!(offset & B43_IV_32BIT);
2624 offset &= B43_IV_OFFSET_MASK;
2625 if (offset >= 0x1000)
2630 if (array_size < sizeof(iv->data.d32))
2632 array_size -= sizeof(iv->data.d32);
2634 value = get_unaligned_be32(&iv->data.d32);
2635 b43_write32(dev, offset, value);
2637 iv = (const struct b43_iv *)((const uint8_t *)iv +
2643 if (array_size < sizeof(iv->data.d16))
2645 array_size -= sizeof(iv->data.d16);
2647 value = be16_to_cpu(iv->data.d16);
2648 b43_write16(dev, offset, value);
2650 iv = (const struct b43_iv *)((const uint8_t *)iv +
2661 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2662 b43_print_fw_helptext(dev->wl, 1);
2667 static int b43_upload_initvals(struct b43_wldev *dev)
2669 const size_t hdr_len = sizeof(struct b43_fw_header);
2670 const struct b43_fw_header *hdr;
2671 struct b43_firmware *fw = &dev->fw;
2672 const struct b43_iv *ivals;
2676 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2677 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2678 count = be32_to_cpu(hdr->size);
2679 err = b43_write_initvals(dev, ivals, count,
2680 fw->initvals.data->size - hdr_len);
2683 if (fw->initvals_band.data) {
2684 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2685 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2686 count = be32_to_cpu(hdr->size);
2687 err = b43_write_initvals(dev, ivals, count,
2688 fw->initvals_band.data->size - hdr_len);
2697 /* Initialize the GPIOs
2698 * http://bcm-specs.sipsolutions.net/GPIO
2700 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2702 struct ssb_bus *bus = dev->dev->sdev->bus;
2704 #ifdef CONFIG_SSB_DRIVER_PCICORE
2705 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2707 return bus->chipco.dev;
2711 static int b43_gpio_init(struct b43_wldev *dev)
2713 struct ssb_device *gpiodev;
2716 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2717 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2721 if (dev->dev->chip_id == 0x4301) {
2725 if (dev->dev->chip_id == 0x5354)
2727 if (0 /* FIXME: conditional unknown */ ) {
2728 b43_write16(dev, B43_MMIO_GPIO_MASK,
2729 b43_read16(dev, B43_MMIO_GPIO_MASK)
2734 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2735 b43_write16(dev, B43_MMIO_GPIO_MASK,
2736 b43_read16(dev, B43_MMIO_GPIO_MASK)
2741 if (dev->dev->core_rev >= 2)
2742 mask |= 0x0010; /* FIXME: This is redundant. */
2744 switch (dev->dev->bus_type) {
2745 #ifdef CONFIG_B43_BCMA
2747 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2748 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2749 BCMA_CC_GPIOCTL) & mask) | set);
2752 #ifdef CONFIG_B43_SSB
2754 gpiodev = b43_ssb_gpio_dev(dev);
2756 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2757 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2766 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2767 static void b43_gpio_cleanup(struct b43_wldev *dev)
2769 struct ssb_device *gpiodev;
2771 switch (dev->dev->bus_type) {
2772 #ifdef CONFIG_B43_BCMA
2774 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2778 #ifdef CONFIG_B43_SSB
2780 gpiodev = b43_ssb_gpio_dev(dev);
2782 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2788 /* http://bcm-specs.sipsolutions.net/EnableMac */
2789 void b43_mac_enable(struct b43_wldev *dev)
2791 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2794 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2795 B43_SHM_SH_UCODESTAT);
2796 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2797 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2798 b43err(dev->wl, "b43_mac_enable(): The firmware "
2799 "should be suspended, but current state is %u\n",
2804 dev->mac_suspended--;
2805 B43_WARN_ON(dev->mac_suspended < 0);
2806 if (dev->mac_suspended == 0) {
2807 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2808 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2809 B43_IRQ_MAC_SUSPENDED);
2811 b43_read32(dev, B43_MMIO_MACCTL);
2812 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2813 b43_power_saving_ctl_bits(dev, 0);
2817 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2818 void b43_mac_suspend(struct b43_wldev *dev)
2824 B43_WARN_ON(dev->mac_suspended < 0);
2826 if (dev->mac_suspended == 0) {
2827 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2828 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2829 /* force pci to flush the write */
2830 b43_read32(dev, B43_MMIO_MACCTL);
2831 for (i = 35; i; i--) {
2832 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2833 if (tmp & B43_IRQ_MAC_SUSPENDED)
2837 /* Hm, it seems this will take some time. Use msleep(). */
2838 for (i = 40; i; i--) {
2839 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2840 if (tmp & B43_IRQ_MAC_SUSPENDED)
2844 b43err(dev->wl, "MAC suspend failed\n");
2847 dev->mac_suspended++;
2850 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2851 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2855 switch (dev->dev->bus_type) {
2856 #ifdef CONFIG_B43_BCMA
2858 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2860 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2862 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2863 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2866 #ifdef CONFIG_B43_SSB
2868 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2870 tmp |= B43_TMSLOW_MACPHYCLKEN;
2872 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2873 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2879 static void b43_adjust_opmode(struct b43_wldev *dev)
2881 struct b43_wl *wl = dev->wl;
2885 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2886 /* Reset status to STA infrastructure mode. */
2887 ctl &= ~B43_MACCTL_AP;
2888 ctl &= ~B43_MACCTL_KEEP_CTL;
2889 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2890 ctl &= ~B43_MACCTL_KEEP_BAD;
2891 ctl &= ~B43_MACCTL_PROMISC;
2892 ctl &= ~B43_MACCTL_BEACPROMISC;
2893 ctl |= B43_MACCTL_INFRA;
2895 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2896 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2897 ctl |= B43_MACCTL_AP;
2898 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2899 ctl &= ~B43_MACCTL_INFRA;
2901 if (wl->filter_flags & FIF_CONTROL)
2902 ctl |= B43_MACCTL_KEEP_CTL;
2903 if (wl->filter_flags & FIF_FCSFAIL)
2904 ctl |= B43_MACCTL_KEEP_BAD;
2905 if (wl->filter_flags & FIF_PLCPFAIL)
2906 ctl |= B43_MACCTL_KEEP_BADPLCP;
2907 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2908 ctl |= B43_MACCTL_PROMISC;
2909 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2910 ctl |= B43_MACCTL_BEACPROMISC;
2912 /* Workaround: On old hardware the HW-MAC-address-filter
2913 * doesn't work properly, so always run promisc in filter
2914 * it in software. */
2915 if (dev->dev->core_rev <= 4)
2916 ctl |= B43_MACCTL_PROMISC;
2918 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2921 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2922 if (dev->dev->chip_id == 0x4306 &&
2923 dev->dev->chip_rev == 3)
2928 b43_write16(dev, 0x612, cfp_pretbtt);
2930 /* FIXME: We don't currently implement the PMQ mechanism,
2931 * so always disable it. If we want to implement PMQ,
2932 * we need to enable it here (clear DISCPMQ) in AP mode.
2934 if (0 /* ctl & B43_MACCTL_AP */)
2935 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2937 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2940 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2946 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2949 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2951 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2952 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2955 static void b43_rate_memory_init(struct b43_wldev *dev)
2957 switch (dev->phy.type) {
2961 case B43_PHYTYPE_LP:
2962 case B43_PHYTYPE_HT:
2963 case B43_PHYTYPE_LCN:
2964 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2965 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2966 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2967 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2968 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2969 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2970 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2971 if (dev->phy.type == B43_PHYTYPE_A)
2975 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2976 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2977 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2978 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2985 /* Set the default values for the PHY TX Control Words. */
2986 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2990 ctl |= B43_TXH_PHY_ENC_CCK;
2991 ctl |= B43_TXH_PHY_ANT01AUTO;
2992 ctl |= B43_TXH_PHY_TXPWR;
2994 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2995 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2996 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2999 /* Set the TX-Antenna for management frames sent by firmware. */
3000 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3005 ant = b43_antenna_to_phyctl(antenna);
3008 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3009 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3011 /* For Probe Resposes */
3012 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3013 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3014 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3017 /* This is the opposite of b43_chip_init() */
3018 static void b43_chip_exit(struct b43_wldev *dev)
3021 b43_gpio_cleanup(dev);
3022 /* firmware is released later */
3025 /* Initialize the chip
3026 * http://bcm-specs.sipsolutions.net/ChipInit
3028 static int b43_chip_init(struct b43_wldev *dev)
3030 struct b43_phy *phy = &dev->phy;
3035 /* Initialize the MAC control */
3036 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3038 macctl |= B43_MACCTL_GMODE;
3039 macctl |= B43_MACCTL_INFRA;
3040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3042 err = b43_upload_microcode(dev);
3044 goto out; /* firmware is released later */
3046 err = b43_gpio_init(dev);
3048 goto out; /* firmware is released later */
3050 err = b43_upload_initvals(dev);
3052 goto err_gpio_clean;
3054 /* Turn the Analog on and initialize the PHY. */
3055 phy->ops->switch_analog(dev, 1);
3056 err = b43_phy_init(dev);
3058 goto err_gpio_clean;
3060 /* Disable Interference Mitigation. */
3061 if (phy->ops->interf_mitigation)
3062 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3064 /* Select the antennae */
3065 if (phy->ops->set_rx_antenna)
3066 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3067 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3069 if (phy->type == B43_PHYTYPE_B) {
3070 value16 = b43_read16(dev, 0x005E);
3072 b43_write16(dev, 0x005E, value16);
3074 b43_write32(dev, 0x0100, 0x01000000);
3075 if (dev->dev->core_rev < 5)
3076 b43_write32(dev, 0x010C, 0x01000000);
3078 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3079 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3081 /* Probe Response Timeout value */
3082 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3083 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3085 /* Initially set the wireless operation mode. */
3086 b43_adjust_opmode(dev);
3088 if (dev->dev->core_rev < 3) {
3089 b43_write16(dev, 0x060E, 0x0000);
3090 b43_write16(dev, 0x0610, 0x8000);
3091 b43_write16(dev, 0x0604, 0x0000);
3092 b43_write16(dev, 0x0606, 0x0200);
3094 b43_write32(dev, 0x0188, 0x80000000);
3095 b43_write32(dev, 0x018C, 0x02000000);
3097 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3098 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3099 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3100 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3101 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3102 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3103 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3105 b43_mac_phy_clock_set(dev, true);
3107 switch (dev->dev->bus_type) {
3108 #ifdef CONFIG_B43_BCMA
3110 /* FIXME: 0xE74 is quite common, but should be read from CC */
3111 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3114 #ifdef CONFIG_B43_SSB
3116 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3117 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3123 b43dbg(dev->wl, "Chip initialized\n");
3128 b43_gpio_cleanup(dev);
3132 static void b43_periodic_every60sec(struct b43_wldev *dev)
3134 const struct b43_phy_operations *ops = dev->phy.ops;
3136 if (ops->pwork_60sec)
3137 ops->pwork_60sec(dev);
3139 /* Force check the TX power emission now. */
3140 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3143 static void b43_periodic_every30sec(struct b43_wldev *dev)
3145 /* Update device statistics. */
3146 b43_calculate_link_quality(dev);
3149 static void b43_periodic_every15sec(struct b43_wldev *dev)
3151 struct b43_phy *phy = &dev->phy;
3154 if (dev->fw.opensource) {
3155 /* Check if the firmware is still alive.
3156 * It will reset the watchdog counter to 0 in its idle loop. */
3157 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3158 if (unlikely(wdr)) {
3159 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3160 b43_controller_restart(dev, "Firmware watchdog");
3163 b43_shm_write16(dev, B43_SHM_SCRATCH,
3164 B43_WATCHDOG_REG, 1);
3168 if (phy->ops->pwork_15sec)
3169 phy->ops->pwork_15sec(dev);
3171 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3175 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3178 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3179 dev->irq_count / 15,
3181 dev->rx_count / 15);
3185 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3186 if (dev->irq_bit_count[i]) {
3187 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3188 dev->irq_bit_count[i] / 15, i, (1 << i));
3189 dev->irq_bit_count[i] = 0;
3196 static void do_periodic_work(struct b43_wldev *dev)
3200 state = dev->periodic_state;
3202 b43_periodic_every60sec(dev);
3204 b43_periodic_every30sec(dev);
3205 b43_periodic_every15sec(dev);
3208 /* Periodic work locking policy:
3209 * The whole periodic work handler is protected by
3210 * wl->mutex. If another lock is needed somewhere in the
3211 * pwork callchain, it's acquired in-place, where it's needed.
3213 static void b43_periodic_work_handler(struct work_struct *work)
3215 struct b43_wldev *dev = container_of(work, struct b43_wldev,
3216 periodic_work.work);
3217 struct b43_wl *wl = dev->wl;
3218 unsigned long delay;
3220 mutex_lock(&wl->mutex);
3222 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3224 if (b43_debug(dev, B43_DBG_PWORK_STOP))
3227 do_periodic_work(dev);
3229 dev->periodic_state++;
3231 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3232 delay = msecs_to_jiffies(50);
3234 delay = round_jiffies_relative(HZ * 15);
3235 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3237 mutex_unlock(&wl->mutex);
3240 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3242 struct delayed_work *work = &dev->periodic_work;
3244 dev->periodic_state = 0;
3245 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3246 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3249 /* Check if communication with the device works correctly. */
3250 static int b43_validate_chipaccess(struct b43_wldev *dev)
3252 u32 v, backup0, backup4;
3254 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3255 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3257 /* Check for read/write and endianness problems. */
3258 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3259 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3261 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3262 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3265 /* Check if unaligned 32bit SHM_SHARED access works properly.
3266 * However, don't bail out on failure, because it's noncritical. */
3267 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3268 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3269 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3270 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3271 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3272 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3273 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3274 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3275 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3276 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3277 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3278 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3280 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3281 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3283 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3284 /* The 32bit register shadows the two 16bit registers
3285 * with update sideeffects. Validate this. */
3286 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3287 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3288 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3290 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3293 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3295 v = b43_read32(dev, B43_MMIO_MACCTL);
3296 v |= B43_MACCTL_GMODE;
3297 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3302 b43err(dev->wl, "Failed to validate the chipaccess\n");
3306 static void b43_security_init(struct b43_wldev *dev)
3308 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3309 /* KTP is a word address, but we address SHM bytewise.
3310 * So multiply by two.
3313 /* Number of RCMTA address slots */
3314 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3315 /* Clear the key memory. */
3316 b43_clear_keys(dev);
3319 #ifdef CONFIG_B43_HWRNG
3320 static int b43_rng_read(struct hwrng *rng, u32 *data)
3322 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3323 struct b43_wldev *dev;
3324 int count = -ENODEV;
3326 mutex_lock(&wl->mutex);
3327 dev = wl->current_dev;
3328 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3329 *data = b43_read16(dev, B43_MMIO_RNG);
3330 count = sizeof(u16);
3332 mutex_unlock(&wl->mutex);
3336 #endif /* CONFIG_B43_HWRNG */
3338 static void b43_rng_exit(struct b43_wl *wl)
3340 #ifdef CONFIG_B43_HWRNG
3341 if (wl->rng_initialized)
3342 hwrng_unregister(&wl->rng);
3343 #endif /* CONFIG_B43_HWRNG */
3346 static int b43_rng_init(struct b43_wl *wl)
3350 #ifdef CONFIG_B43_HWRNG
3351 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3352 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3353 wl->rng.name = wl->rng_name;
3354 wl->rng.data_read = b43_rng_read;
3355 wl->rng.priv = (unsigned long)wl;
3356 wl->rng_initialized = true;
3357 err = hwrng_register(&wl->rng);
3359 wl->rng_initialized = false;
3360 b43err(wl, "Failed to register the random "
3361 "number generator (%d)\n", err);
3363 #endif /* CONFIG_B43_HWRNG */
3368 static void b43_tx_work(struct work_struct *work)
3370 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3371 struct b43_wldev *dev;
3372 struct sk_buff *skb;
3376 mutex_lock(&wl->mutex);
3377 dev = wl->current_dev;
3378 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3379 mutex_unlock(&wl->mutex);
3383 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3384 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3385 skb = skb_dequeue(&wl->tx_queue[queue_num]);
3386 if (b43_using_pio_transfers(dev))
3387 err = b43_pio_tx(dev, skb);
3389 err = b43_dma_tx(dev, skb);
3390 if (err == -ENOSPC) {
3391 wl->tx_queue_stopped[queue_num] = 1;
3392 ieee80211_stop_queue(wl->hw, queue_num);
3393 skb_queue_head(&wl->tx_queue[queue_num], skb);
3397 dev_kfree_skb(skb); /* Drop it */
3402 wl->tx_queue_stopped[queue_num] = 0;
3408 mutex_unlock(&wl->mutex);
3411 static void b43_op_tx(struct ieee80211_hw *hw,
3412 struct sk_buff *skb)
3414 struct b43_wl *wl = hw_to_b43_wl(hw);
3416 if (unlikely(skb->len < 2 + 2 + 6)) {
3417 /* Too short, this can't be a valid frame. */
3418 dev_kfree_skb_any(skb);
3421 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3423 skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3424 if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3425 ieee80211_queue_work(wl->hw, &wl->tx_work);
3427 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3431 static void b43_qos_params_upload(struct b43_wldev *dev,
3432 const struct ieee80211_tx_queue_params *p,
3435 u16 params[B43_NR_QOSPARAMS];
3439 if (!dev->qos_enabled)
3442 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3444 memset(¶ms, 0, sizeof(params));
3446 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3447 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3448 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3449 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3450 params[B43_QOSPARAM_AIFS] = p->aifs;
3451 params[B43_QOSPARAM_BSLOTS] = bslots;
3452 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3454 for (i = 0; i < ARRAY_SIZE(params); i++) {
3455 if (i == B43_QOSPARAM_STATUS) {
3456 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3457 shm_offset + (i * 2));
3458 /* Mark the parameters as updated. */
3460 b43_shm_write16(dev, B43_SHM_SHARED,
3461 shm_offset + (i * 2),
3464 b43_shm_write16(dev, B43_SHM_SHARED,
3465 shm_offset + (i * 2),
3471 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3472 static const u16 b43_qos_shm_offsets[] = {
3473 /* [mac80211-queue-nr] = SHM_OFFSET, */
3474 [0] = B43_QOS_VOICE,
3475 [1] = B43_QOS_VIDEO,
3476 [2] = B43_QOS_BESTEFFORT,
3477 [3] = B43_QOS_BACKGROUND,
3480 /* Update all QOS parameters in hardware. */
3481 static void b43_qos_upload_all(struct b43_wldev *dev)
3483 struct b43_wl *wl = dev->wl;
3484 struct b43_qos_params *params;
3487 if (!dev->qos_enabled)
3490 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3491 ARRAY_SIZE(wl->qos_params));
3493 b43_mac_suspend(dev);
3494 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3495 params = &(wl->qos_params[i]);
3496 b43_qos_params_upload(dev, &(params->p),
3497 b43_qos_shm_offsets[i]);
3499 b43_mac_enable(dev);
3502 static void b43_qos_clear(struct b43_wl *wl)
3504 struct b43_qos_params *params;
3507 /* Initialize QoS parameters to sane defaults. */
3509 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3510 ARRAY_SIZE(wl->qos_params));
3512 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3513 params = &(wl->qos_params[i]);
3515 switch (b43_qos_shm_offsets[i]) {
3519 params->p.cw_min = 0x0001;
3520 params->p.cw_max = 0x0001;
3525 params->p.cw_min = 0x0001;
3526 params->p.cw_max = 0x0001;
3528 case B43_QOS_BESTEFFORT:
3531 params->p.cw_min = 0x0001;
3532 params->p.cw_max = 0x03FF;
3534 case B43_QOS_BACKGROUND:
3537 params->p.cw_min = 0x0001;
3538 params->p.cw_max = 0x03FF;
3546 /* Initialize the core's QOS capabilities */
3547 static void b43_qos_init(struct b43_wldev *dev)
3549 if (!dev->qos_enabled) {
3550 /* Disable QOS support. */
3551 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3552 b43_write16(dev, B43_MMIO_IFSCTL,
3553 b43_read16(dev, B43_MMIO_IFSCTL)
3554 & ~B43_MMIO_IFSCTL_USE_EDCF);
3555 b43dbg(dev->wl, "QoS disabled\n");
3559 /* Upload the current QOS parameters. */
3560 b43_qos_upload_all(dev);
3562 /* Enable QOS support. */
3563 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3564 b43_write16(dev, B43_MMIO_IFSCTL,
3565 b43_read16(dev, B43_MMIO_IFSCTL)
3566 | B43_MMIO_IFSCTL_USE_EDCF);
3567 b43dbg(dev->wl, "QoS enabled\n");
3570 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3571 struct ieee80211_vif *vif, u16 _queue,
3572 const struct ieee80211_tx_queue_params *params)
3574 struct b43_wl *wl = hw_to_b43_wl(hw);
3575 struct b43_wldev *dev;
3576 unsigned int queue = (unsigned int)_queue;
3579 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3580 /* Queue not available or don't support setting
3581 * params on this queue. Return success to not
3582 * confuse mac80211. */
3585 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3586 ARRAY_SIZE(wl->qos_params));
3588 mutex_lock(&wl->mutex);
3589 dev = wl->current_dev;
3590 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3593 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3594 b43_mac_suspend(dev);
3595 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3596 b43_qos_shm_offsets[queue]);
3597 b43_mac_enable(dev);
3601 mutex_unlock(&wl->mutex);
3606 static int b43_op_get_stats(struct ieee80211_hw *hw,
3607 struct ieee80211_low_level_stats *stats)
3609 struct b43_wl *wl = hw_to_b43_wl(hw);
3611 mutex_lock(&wl->mutex);
3612 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3613 mutex_unlock(&wl->mutex);
3618 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3620 struct b43_wl *wl = hw_to_b43_wl(hw);
3621 struct b43_wldev *dev;
3624 mutex_lock(&wl->mutex);
3625 dev = wl->current_dev;
3627 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3628 b43_tsf_read(dev, &tsf);
3632 mutex_unlock(&wl->mutex);
3637 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3638 struct ieee80211_vif *vif, u64 tsf)
3640 struct b43_wl *wl = hw_to_b43_wl(hw);
3641 struct b43_wldev *dev;
3643 mutex_lock(&wl->mutex);
3644 dev = wl->current_dev;
3646 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3647 b43_tsf_write(dev, tsf);
3649 mutex_unlock(&wl->mutex);
3652 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3656 switch (dev->dev->bus_type) {
3657 #ifdef CONFIG_B43_BCMA
3660 "Putting PHY into reset not supported on BCMA\n");
3663 #ifdef CONFIG_B43_SSB
3665 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3666 tmp &= ~B43_TMSLOW_GMODE;
3667 tmp |= B43_TMSLOW_PHYRESET;
3668 tmp |= SSB_TMSLOW_FGC;
3669 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3672 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3673 tmp &= ~SSB_TMSLOW_FGC;
3674 tmp |= B43_TMSLOW_PHYRESET;
3675 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3683 static const char *band_to_string(enum ieee80211_band band)
3686 case IEEE80211_BAND_5GHZ:
3688 case IEEE80211_BAND_2GHZ:
3697 /* Expects wl->mutex locked */
3698 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3700 struct b43_wldev *up_dev = NULL;
3701 struct b43_wldev *down_dev;
3702 struct b43_wldev *d;
3704 bool uninitialized_var(gmode);
3707 /* Find a device and PHY which supports the band. */
3708 list_for_each_entry(d, &wl->devlist, list) {
3709 switch (chan->band) {
3710 case IEEE80211_BAND_5GHZ:
3711 if (d->phy.supports_5ghz) {
3716 case IEEE80211_BAND_2GHZ:
3717 if (d->phy.supports_2ghz) {
3730 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3731 band_to_string(chan->band));
3734 if ((up_dev == wl->current_dev) &&
3735 (!!wl->current_dev->phy.gmode == !!gmode)) {
3736 /* This device is already running. */
3739 b43dbg(wl, "Switching to %s-GHz band\n",
3740 band_to_string(chan->band));
3741 down_dev = wl->current_dev;
3743 prev_status = b43_status(down_dev);
3744 /* Shutdown the currently running core. */
3745 if (prev_status >= B43_STAT_STARTED)
3746 down_dev = b43_wireless_core_stop(down_dev);
3747 if (prev_status >= B43_STAT_INITIALIZED)
3748 b43_wireless_core_exit(down_dev);
3750 if (down_dev != up_dev) {
3751 /* We switch to a different core, so we put PHY into
3752 * RESET on the old core. */
3753 b43_put_phy_into_reset(down_dev);
3756 /* Now start the new core. */
3757 up_dev->phy.gmode = gmode;
3758 if (prev_status >= B43_STAT_INITIALIZED) {
3759 err = b43_wireless_core_init(up_dev);
3761 b43err(wl, "Fatal: Could not initialize device for "
3762 "selected %s-GHz band\n",
3763 band_to_string(chan->band));
3767 if (prev_status >= B43_STAT_STARTED) {
3768 err = b43_wireless_core_start(up_dev);
3770 b43err(wl, "Fatal: Coult not start device for "
3771 "selected %s-GHz band\n",
3772 band_to_string(chan->band));
3773 b43_wireless_core_exit(up_dev);
3777 B43_WARN_ON(b43_status(up_dev) != prev_status);
3779 wl->current_dev = up_dev;
3783 /* Whoops, failed to init the new core. No core is operating now. */
3784 wl->current_dev = NULL;
3788 /* Write the short and long frame retry limit values. */
3789 static void b43_set_retry_limits(struct b43_wldev *dev,
3790 unsigned int short_retry,
3791 unsigned int long_retry)
3793 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3794 * the chip-internal counter. */
3795 short_retry = min(short_retry, (unsigned int)0xF);
3796 long_retry = min(long_retry, (unsigned int)0xF);
3798 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3800 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3804 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3806 struct b43_wl *wl = hw_to_b43_wl(hw);
3807 struct b43_wldev *dev;
3808 struct b43_phy *phy;
3809 struct ieee80211_conf *conf = &hw->conf;
3812 bool reload_bss = false;
3814 mutex_lock(&wl->mutex);
3816 dev = wl->current_dev;
3818 /* Switch the band (if necessary). This might change the active core. */
3819 err = b43_switch_band(wl, conf->channel);
3821 goto out_unlock_mutex;
3823 /* Need to reload all settings if the core changed */
3824 if (dev != wl->current_dev) {
3825 dev = wl->current_dev;
3832 if (conf_is_ht(conf))
3834 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3836 phy->is_40mhz = false;
3838 b43_mac_suspend(dev);
3840 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3841 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3842 conf->long_frame_max_tx_count);
3843 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3845 goto out_mac_enable;
3847 /* Switch to the requested channel.
3848 * The firmware takes care of races with the TX handler. */
3849 if (conf->channel->hw_value != phy->channel)
3850 b43_switch_channel(dev, conf->channel->hw_value);
3852 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3854 /* Adjust the desired TX power level. */
3855 if (conf->power_level != 0) {
3856 if (conf->power_level != phy->desired_txpower) {
3857 phy->desired_txpower = conf->power_level;
3858 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3859 B43_TXPWR_IGNORE_TSSI);
3863 /* Antennas for RX and management frame TX. */
3864 antenna = B43_ANTENNA_DEFAULT;
3865 b43_mgmtframe_txantenna(dev, antenna);
3866 antenna = B43_ANTENNA_DEFAULT;
3867 if (phy->ops->set_rx_antenna)
3868 phy->ops->set_rx_antenna(dev, antenna);
3870 if (wl->radio_enabled != phy->radio_on) {
3871 if (wl->radio_enabled) {
3872 b43_software_rfkill(dev, false);
3873 b43info(dev->wl, "Radio turned on by software\n");
3874 if (!dev->radio_hw_enable) {
3875 b43info(dev->wl, "The hardware RF-kill button "
3876 "still turns the radio physically off. "
3877 "Press the button to turn it on.\n");
3880 b43_software_rfkill(dev, true);
3881 b43info(dev->wl, "Radio turned off by software\n");
3886 b43_mac_enable(dev);
3888 mutex_unlock(&wl->mutex);
3890 if (wl->vif && reload_bss)
3891 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3896 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3898 struct ieee80211_supported_band *sband =
3899 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3900 struct ieee80211_rate *rate;
3902 u16 basic, direct, offset, basic_offset, rateptr;
3904 for (i = 0; i < sband->n_bitrates; i++) {
3905 rate = &sband->bitrates[i];
3907 if (b43_is_cck_rate(rate->hw_value)) {
3908 direct = B43_SHM_SH_CCKDIRECT;
3909 basic = B43_SHM_SH_CCKBASIC;
3910 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3913 direct = B43_SHM_SH_OFDMDIRECT;
3914 basic = B43_SHM_SH_OFDMBASIC;
3915 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3919 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3921 if (b43_is_cck_rate(rate->hw_value)) {
3922 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3923 basic_offset &= 0xF;
3925 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3926 basic_offset &= 0xF;
3930 * Get the pointer that we need to point to
3931 * from the direct map
3933 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3934 direct + 2 * basic_offset);
3935 /* and write it to the basic map */
3936 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3941 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3942 struct ieee80211_vif *vif,
3943 struct ieee80211_bss_conf *conf,
3946 struct b43_wl *wl = hw_to_b43_wl(hw);
3947 struct b43_wldev *dev;
3949 mutex_lock(&wl->mutex);
3951 dev = wl->current_dev;
3952 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3953 goto out_unlock_mutex;
3955 B43_WARN_ON(wl->vif != vif);
3957 if (changed & BSS_CHANGED_BSSID) {
3959 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3961 memset(wl->bssid, 0, ETH_ALEN);
3964 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3965 if (changed & BSS_CHANGED_BEACON &&
3966 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3967 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3968 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3969 b43_update_templates(wl);
3971 if (changed & BSS_CHANGED_BSSID)
3972 b43_write_mac_bssid_templates(dev);
3975 b43_mac_suspend(dev);
3977 /* Update templates for AP/mesh mode. */
3978 if (changed & BSS_CHANGED_BEACON_INT &&
3979 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3980 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3981 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
3983 b43_set_beacon_int(dev, conf->beacon_int);
3985 if (changed & BSS_CHANGED_BASIC_RATES)
3986 b43_update_basic_rates(dev, conf->basic_rates);
3988 if (changed & BSS_CHANGED_ERP_SLOT) {
3989 if (conf->use_short_slot)
3990 b43_short_slot_timing_enable(dev);
3992 b43_short_slot_timing_disable(dev);
3995 b43_mac_enable(dev);
3997 mutex_unlock(&wl->mutex);
4000 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4001 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4002 struct ieee80211_key_conf *key)
4004 struct b43_wl *wl = hw_to_b43_wl(hw);
4005 struct b43_wldev *dev;
4009 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4011 if (modparam_nohwcrypt)
4012 return -ENOSPC; /* User disabled HW-crypto */
4014 if ((vif->type == NL80211_IFTYPE_ADHOC ||
4015 vif->type == NL80211_IFTYPE_MESH_POINT) &&
4016 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
4017 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
4018 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
4020 * For now, disable hw crypto for the RSN IBSS group keys. This
4021 * could be optimized in the future, but until that gets
4022 * implemented, use of software crypto for group addressed
4023 * frames is a acceptable to allow RSN IBSS to be used.
4028 mutex_lock(&wl->mutex);
4030 dev = wl->current_dev;
4032 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4035 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4036 /* We don't have firmware for the crypto engine.
4037 * Must use software-crypto. */
4043 switch (key->cipher) {
4044 case WLAN_CIPHER_SUITE_WEP40:
4045 algorithm = B43_SEC_ALGO_WEP40;
4047 case WLAN_CIPHER_SUITE_WEP104:
4048 algorithm = B43_SEC_ALGO_WEP104;
4050 case WLAN_CIPHER_SUITE_TKIP:
4051 algorithm = B43_SEC_ALGO_TKIP;
4053 case WLAN_CIPHER_SUITE_CCMP:
4054 algorithm = B43_SEC_ALGO_AES;
4060 index = (u8) (key->keyidx);
4066 if (algorithm == B43_SEC_ALGO_TKIP &&
4067 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4068 !modparam_hwtkip)) {
4069 /* We support only pairwise key */
4074 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4075 if (WARN_ON(!sta)) {
4079 /* Pairwise key with an assigned MAC address. */
4080 err = b43_key_write(dev, -1, algorithm,
4081 key->key, key->keylen,
4085 err = b43_key_write(dev, index, algorithm,
4086 key->key, key->keylen, NULL, key);
4091 if (algorithm == B43_SEC_ALGO_WEP40 ||
4092 algorithm == B43_SEC_ALGO_WEP104) {
4093 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4096 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4098 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4099 if (algorithm == B43_SEC_ALGO_TKIP)
4100 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4103 err = b43_key_clear(dev, key->hw_key_idx);
4114 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4116 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4117 sta ? sta->addr : bcast_addr);
4118 b43_dump_keymemory(dev);
4120 mutex_unlock(&wl->mutex);
4125 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4126 unsigned int changed, unsigned int *fflags,
4129 struct b43_wl *wl = hw_to_b43_wl(hw);
4130 struct b43_wldev *dev;
4132 mutex_lock(&wl->mutex);
4133 dev = wl->current_dev;
4139 *fflags &= FIF_PROMISC_IN_BSS |
4145 FIF_BCN_PRBRESP_PROMISC;
4147 changed &= FIF_PROMISC_IN_BSS |
4153 FIF_BCN_PRBRESP_PROMISC;
4155 wl->filter_flags = *fflags;
4157 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4158 b43_adjust_opmode(dev);
4161 mutex_unlock(&wl->mutex);
4164 /* Locking: wl->mutex
4165 * Returns the current dev. This might be different from the passed in dev,
4166 * because the core might be gone away while we unlocked the mutex. */
4167 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4170 struct b43_wldev *orig_dev;
4178 if (!dev || b43_status(dev) < B43_STAT_STARTED)
4181 /* Cancel work. Unlock to avoid deadlocks. */
4182 mutex_unlock(&wl->mutex);
4183 cancel_delayed_work_sync(&dev->periodic_work);
4184 cancel_work_sync(&wl->tx_work);
4185 cancel_work_sync(&wl->firmware_load);
4186 mutex_lock(&wl->mutex);
4187 dev = wl->current_dev;
4188 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4189 /* Whoops, aliens ate up the device while we were unlocked. */
4193 /* Disable interrupts on the device. */
4194 b43_set_status(dev, B43_STAT_INITIALIZED);
4195 if (b43_bus_host_is_sdio(dev->dev)) {
4196 /* wl->mutex is locked. That is enough. */
4197 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4198 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4200 spin_lock_irq(&wl->hardirq_lock);
4201 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4202 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4203 spin_unlock_irq(&wl->hardirq_lock);
4205 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4207 mutex_unlock(&wl->mutex);
4208 if (b43_bus_host_is_sdio(dev->dev)) {
4209 b43_sdio_free_irq(dev);
4211 synchronize_irq(dev->dev->irq);
4212 free_irq(dev->dev->irq, dev);
4214 mutex_lock(&wl->mutex);
4215 dev = wl->current_dev;
4218 if (dev != orig_dev) {
4219 if (b43_status(dev) >= B43_STAT_STARTED)
4223 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4224 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4226 /* Drain all TX queues. */
4227 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4228 while (skb_queue_len(&wl->tx_queue[queue_num]))
4229 dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
4232 b43_mac_suspend(dev);
4234 b43dbg(wl, "Wireless interface stopped\n");
4239 /* Locking: wl->mutex */
4240 static int b43_wireless_core_start(struct b43_wldev *dev)
4244 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4246 drain_txstatus_queue(dev);
4247 if (b43_bus_host_is_sdio(dev->dev)) {
4248 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4250 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4254 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4255 b43_interrupt_thread_handler,
4256 IRQF_SHARED, KBUILD_MODNAME, dev);
4258 b43err(dev->wl, "Cannot request IRQ-%d\n",
4264 /* We are ready to run. */
4265 ieee80211_wake_queues(dev->wl->hw);
4266 b43_set_status(dev, B43_STAT_STARTED);
4268 /* Start data flow (TX/RX). */
4269 b43_mac_enable(dev);
4270 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4272 /* Start maintenance work */
4273 b43_periodic_tasks_setup(dev);
4277 b43dbg(dev->wl, "Wireless interface started\n");
4282 /* Get PHY and RADIO versioning numbers */
4283 static int b43_phy_versioning(struct b43_wldev *dev)
4285 struct b43_phy *phy = &dev->phy;
4293 int unsupported = 0;
4295 /* Get PHY versioning */
4296 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4297 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4298 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4299 phy_rev = (tmp & B43_PHYVER_VERSION);
4306 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4314 #ifdef CONFIG_B43_PHY_N
4320 #ifdef CONFIG_B43_PHY_LP
4321 case B43_PHYTYPE_LP:
4326 #ifdef CONFIG_B43_PHY_HT
4327 case B43_PHYTYPE_HT:
4332 #ifdef CONFIG_B43_PHY_LCN
4333 case B43_PHYTYPE_LCN:
4342 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4343 "(Analog %u, Type %u, Revision %u)\n",
4344 analog_type, phy_type, phy_rev);
4347 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4348 analog_type, phy_type, phy_rev);
4350 /* Get RADIO versioning */
4351 if (dev->dev->core_rev >= 24) {
4354 for (tmp = 0; tmp < 3; tmp++) {
4355 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4356 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4359 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4360 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4362 radio_manuf = 0x17F;
4363 radio_ver = (radio24[2] << 8) | radio24[1];
4364 radio_rev = (radio24[0] & 0xF);
4366 if (dev->dev->chip_id == 0x4317) {
4367 if (dev->dev->chip_rev == 0)
4369 else if (dev->dev->chip_rev == 1)
4374 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4376 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4377 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4379 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4382 radio_manuf = (tmp & 0x00000FFF);
4383 radio_ver = (tmp & 0x0FFFF000) >> 12;
4384 radio_rev = (tmp & 0xF0000000) >> 28;
4387 if (radio_manuf != 0x17F /* Broadcom */)
4391 if (radio_ver != 0x2060)
4395 if (radio_manuf != 0x17F)
4399 if ((radio_ver & 0xFFF0) != 0x2050)
4403 if (radio_ver != 0x2050)
4407 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4410 case B43_PHYTYPE_LP:
4411 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4414 case B43_PHYTYPE_HT:
4415 if (radio_ver != 0x2059)
4418 case B43_PHYTYPE_LCN:
4419 if (radio_ver != 0x2064)
4426 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4427 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4428 radio_manuf, radio_ver, radio_rev);
4431 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4432 radio_manuf, radio_ver, radio_rev);
4434 phy->radio_manuf = radio_manuf;
4435 phy->radio_ver = radio_ver;
4436 phy->radio_rev = radio_rev;
4438 phy->analog = analog_type;
4439 phy->type = phy_type;
4445 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4446 struct b43_phy *phy)
4448 phy->hardware_power_control = !!modparam_hwpctl;
4449 phy->next_txpwr_check_time = jiffies;
4450 /* PHY TX errors counter. */
4451 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4454 phy->phy_locked = false;
4455 phy->radio_locked = false;
4459 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4461 dev->dfq_valid = false;
4463 /* Assume the radio is enabled. If it's not enabled, the state will
4464 * immediately get fixed on the first periodic work run. */
4465 dev->radio_hw_enable = true;
4468 memset(&dev->stats, 0, sizeof(dev->stats));
4470 setup_struct_phy_for_init(dev, &dev->phy);
4472 /* IRQ related flags */
4473 dev->irq_reason = 0;
4474 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4475 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4476 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4477 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4479 dev->mac_suspended = 1;
4481 /* Noise calculation context */
4482 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4485 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4487 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4490 if (!modparam_btcoex)
4492 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4494 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4497 hf = b43_hf_read(dev);
4498 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4499 hf |= B43_HF_BTCOEXALT;
4501 hf |= B43_HF_BTCOEX;
4502 b43_hf_write(dev, hf);
4505 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4507 if (!modparam_btcoex)
4512 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4514 struct ssb_bus *bus;
4517 if (dev->dev->bus_type != B43_BUS_SSB)
4520 bus = dev->dev->sdev->bus;
4522 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4523 (bus->chip_id == 0x4312)) {
4524 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4525 tmp &= ~SSB_IMCFGLO_REQTO;
4526 tmp &= ~SSB_IMCFGLO_SERTO;
4528 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4529 ssb_commit_settings(bus);
4533 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4537 /* The time value is in microseconds. */
4538 if (dev->phy.type == B43_PHYTYPE_A)
4542 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4544 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4545 pu_delay = max(pu_delay, (u16)2400);
4547 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4550 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4551 static void b43_set_pretbtt(struct b43_wldev *dev)
4555 /* The time value is in microseconds. */
4556 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4559 if (dev->phy.type == B43_PHYTYPE_A)
4564 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4565 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4568 /* Shutdown a wireless core */
4569 /* Locking: wl->mutex */
4570 static void b43_wireless_core_exit(struct b43_wldev *dev)
4572 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4573 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4576 /* Unregister HW RNG driver */
4577 b43_rng_exit(dev->wl);
4579 b43_set_status(dev, B43_STAT_UNINIT);
4581 /* Stop the microcode PSM. */
4582 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4583 B43_MACCTL_PSM_JMP0);
4588 dev->phy.ops->switch_analog(dev, 0);
4589 if (dev->wl->current_beacon) {
4590 dev_kfree_skb_any(dev->wl->current_beacon);
4591 dev->wl->current_beacon = NULL;
4594 b43_device_disable(dev, 0);
4595 b43_bus_may_powerdown(dev);
4598 /* Initialize a wireless core */
4599 static int b43_wireless_core_init(struct b43_wldev *dev)
4601 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4602 struct b43_phy *phy = &dev->phy;
4606 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4608 err = b43_bus_powerup(dev, 0);
4611 if (!b43_device_is_enabled(dev))
4612 b43_wireless_core_reset(dev, phy->gmode);
4614 /* Reset all data structures. */
4615 setup_struct_wldev_for_init(dev);
4616 phy->ops->prepare_structs(dev);
4618 /* Enable IRQ routing to this device. */
4619 switch (dev->dev->bus_type) {
4620 #ifdef CONFIG_B43_BCMA
4622 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4623 dev->dev->bdev, true);
4626 #ifdef CONFIG_B43_SSB
4628 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4634 b43_imcfglo_timeouts_workaround(dev);
4635 b43_bluetooth_coext_disable(dev);
4636 if (phy->ops->prepare_hardware) {
4637 err = phy->ops->prepare_hardware(dev);
4641 err = b43_chip_init(dev);
4644 b43_shm_write16(dev, B43_SHM_SHARED,
4645 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4646 hf = b43_hf_read(dev);
4647 if (phy->type == B43_PHYTYPE_G) {
4651 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4652 hf |= B43_HF_OFDMPABOOST;
4654 if (phy->radio_ver == 0x2050) {
4655 if (phy->radio_rev == 6)
4656 hf |= B43_HF_4318TSSI;
4657 if (phy->radio_rev < 6)
4658 hf |= B43_HF_VCORECALC;
4660 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4661 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4662 #ifdef CONFIG_SSB_DRIVER_PCICORE
4663 if (dev->dev->bus_type == B43_BUS_SSB &&
4664 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4665 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4666 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4668 hf &= ~B43_HF_SKCFPUP;
4669 b43_hf_write(dev, hf);
4671 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4672 B43_DEFAULT_LONG_RETRY_LIMIT);
4673 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4674 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4676 /* Disable sending probe responses from firmware.
4677 * Setting the MaxTime to one usec will always trigger
4678 * a timeout, so we never send any probe resp.
4679 * A timeout of zero is infinite. */
4680 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4682 b43_rate_memory_init(dev);
4683 b43_set_phytxctl_defaults(dev);
4685 /* Minimum Contention Window */
4686 if (phy->type == B43_PHYTYPE_B)
4687 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4689 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4690 /* Maximum Contention Window */
4691 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4693 if (b43_bus_host_is_pcmcia(dev->dev) ||
4694 b43_bus_host_is_sdio(dev->dev)) {
4695 dev->__using_pio_transfers = true;
4696 err = b43_pio_init(dev);
4697 } else if (dev->use_pio) {
4698 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4699 "This should not be needed and will result in lower "
4701 dev->__using_pio_transfers = true;
4702 err = b43_pio_init(dev);
4704 dev->__using_pio_transfers = false;
4705 err = b43_dma_init(dev);
4710 b43_set_synth_pu_delay(dev, 1);
4711 b43_bluetooth_coext_enable(dev);
4713 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4714 b43_upload_card_macaddress(dev);
4715 b43_security_init(dev);
4717 ieee80211_wake_queues(dev->wl->hw);
4719 b43_set_status(dev, B43_STAT_INITIALIZED);
4721 /* Register HW RNG driver */
4722 b43_rng_init(dev->wl);
4730 b43_bus_may_powerdown(dev);
4731 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4735 static int b43_op_add_interface(struct ieee80211_hw *hw,
4736 struct ieee80211_vif *vif)
4738 struct b43_wl *wl = hw_to_b43_wl(hw);
4739 struct b43_wldev *dev;
4740 int err = -EOPNOTSUPP;
4742 /* TODO: allow WDS/AP devices to coexist */
4744 if (vif->type != NL80211_IFTYPE_AP &&
4745 vif->type != NL80211_IFTYPE_MESH_POINT &&
4746 vif->type != NL80211_IFTYPE_STATION &&
4747 vif->type != NL80211_IFTYPE_WDS &&
4748 vif->type != NL80211_IFTYPE_ADHOC)
4751 mutex_lock(&wl->mutex);
4753 goto out_mutex_unlock;
4755 b43dbg(wl, "Adding Interface type %d\n", vif->type);
4757 dev = wl->current_dev;
4758 wl->operating = true;
4760 wl->if_type = vif->type;
4761 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4763 b43_adjust_opmode(dev);
4764 b43_set_pretbtt(dev);
4765 b43_set_synth_pu_delay(dev, 0);
4766 b43_upload_card_macaddress(dev);
4770 mutex_unlock(&wl->mutex);
4773 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4778 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4779 struct ieee80211_vif *vif)
4781 struct b43_wl *wl = hw_to_b43_wl(hw);
4782 struct b43_wldev *dev = wl->current_dev;
4784 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4786 mutex_lock(&wl->mutex);
4788 B43_WARN_ON(!wl->operating);
4789 B43_WARN_ON(wl->vif != vif);
4792 wl->operating = false;
4794 b43_adjust_opmode(dev);
4795 memset(wl->mac_addr, 0, ETH_ALEN);
4796 b43_upload_card_macaddress(dev);
4798 mutex_unlock(&wl->mutex);
4801 static int b43_op_start(struct ieee80211_hw *hw)
4803 struct b43_wl *wl = hw_to_b43_wl(hw);
4804 struct b43_wldev *dev = wl->current_dev;
4808 /* Kill all old instance specific information to make sure
4809 * the card won't use it in the short timeframe between start
4810 * and mac80211 reconfiguring it. */
4811 memset(wl->bssid, 0, ETH_ALEN);
4812 memset(wl->mac_addr, 0, ETH_ALEN);
4813 wl->filter_flags = 0;
4814 wl->radiotap_enabled = false;
4816 wl->beacon0_uploaded = false;
4817 wl->beacon1_uploaded = false;
4818 wl->beacon_templates_virgin = true;
4819 wl->radio_enabled = true;
4821 mutex_lock(&wl->mutex);
4823 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4824 err = b43_wireless_core_init(dev);
4826 goto out_mutex_unlock;
4830 if (b43_status(dev) < B43_STAT_STARTED) {
4831 err = b43_wireless_core_start(dev);
4834 b43_wireless_core_exit(dev);
4835 goto out_mutex_unlock;
4839 /* XXX: only do if device doesn't support rfkill irq */
4840 wiphy_rfkill_start_polling(hw->wiphy);
4843 mutex_unlock(&wl->mutex);
4846 * Configuration may have been overwritten during initialization.
4847 * Reload the configuration, but only if initialization was
4848 * successful. Reloading the configuration after a failed init
4849 * may hang the system.
4852 b43_op_config(hw, ~0);
4857 static void b43_op_stop(struct ieee80211_hw *hw)
4859 struct b43_wl *wl = hw_to_b43_wl(hw);
4860 struct b43_wldev *dev = wl->current_dev;
4862 cancel_work_sync(&(wl->beacon_update_trigger));
4867 mutex_lock(&wl->mutex);
4868 if (b43_status(dev) >= B43_STAT_STARTED) {
4869 dev = b43_wireless_core_stop(dev);
4873 b43_wireless_core_exit(dev);
4874 wl->radio_enabled = false;
4877 mutex_unlock(&wl->mutex);
4879 cancel_work_sync(&(wl->txpower_adjust_work));
4882 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4883 struct ieee80211_sta *sta, bool set)
4885 struct b43_wl *wl = hw_to_b43_wl(hw);
4887 /* FIXME: add locking */
4888 b43_update_templates(wl);
4893 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4894 struct ieee80211_vif *vif,
4895 enum sta_notify_cmd notify_cmd,
4896 struct ieee80211_sta *sta)
4898 struct b43_wl *wl = hw_to_b43_wl(hw);
4900 B43_WARN_ON(!vif || wl->vif != vif);
4903 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4905 struct b43_wl *wl = hw_to_b43_wl(hw);
4906 struct b43_wldev *dev;
4908 mutex_lock(&wl->mutex);
4909 dev = wl->current_dev;
4910 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4911 /* Disable CFP update during scan on other channels. */
4912 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4914 mutex_unlock(&wl->mutex);
4917 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4919 struct b43_wl *wl = hw_to_b43_wl(hw);
4920 struct b43_wldev *dev;
4922 mutex_lock(&wl->mutex);
4923 dev = wl->current_dev;
4924 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4925 /* Re-enable CFP update. */
4926 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4928 mutex_unlock(&wl->mutex);
4931 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4932 struct survey_info *survey)
4934 struct b43_wl *wl = hw_to_b43_wl(hw);
4935 struct b43_wldev *dev = wl->current_dev;
4936 struct ieee80211_conf *conf = &hw->conf;
4941 survey->channel = conf->channel;
4942 survey->filled = SURVEY_INFO_NOISE_DBM;
4943 survey->noise = dev->stats.link_noise;
4948 static const struct ieee80211_ops b43_hw_ops = {
4950 .conf_tx = b43_op_conf_tx,
4951 .add_interface = b43_op_add_interface,
4952 .remove_interface = b43_op_remove_interface,
4953 .config = b43_op_config,
4954 .bss_info_changed = b43_op_bss_info_changed,
4955 .configure_filter = b43_op_configure_filter,
4956 .set_key = b43_op_set_key,
4957 .update_tkip_key = b43_op_update_tkip_key,
4958 .get_stats = b43_op_get_stats,
4959 .get_tsf = b43_op_get_tsf,
4960 .set_tsf = b43_op_set_tsf,
4961 .start = b43_op_start,
4962 .stop = b43_op_stop,
4963 .set_tim = b43_op_beacon_set_tim,
4964 .sta_notify = b43_op_sta_notify,
4965 .sw_scan_start = b43_op_sw_scan_start_notifier,
4966 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4967 .get_survey = b43_op_get_survey,
4968 .rfkill_poll = b43_rfkill_poll,
4971 /* Hard-reset the chip. Do not call this directly.
4972 * Use b43_controller_restart()
4974 static void b43_chip_reset(struct work_struct *work)
4976 struct b43_wldev *dev =
4977 container_of(work, struct b43_wldev, restart_work);
4978 struct b43_wl *wl = dev->wl;
4982 mutex_lock(&wl->mutex);
4984 prev_status = b43_status(dev);
4985 /* Bring the device down... */
4986 if (prev_status >= B43_STAT_STARTED) {
4987 dev = b43_wireless_core_stop(dev);
4993 if (prev_status >= B43_STAT_INITIALIZED)
4994 b43_wireless_core_exit(dev);
4996 /* ...and up again. */
4997 if (prev_status >= B43_STAT_INITIALIZED) {
4998 err = b43_wireless_core_init(dev);
5002 if (prev_status >= B43_STAT_STARTED) {
5003 err = b43_wireless_core_start(dev);
5005 b43_wireless_core_exit(dev);
5011 wl->current_dev = NULL; /* Failed to init the dev. */
5012 mutex_unlock(&wl->mutex);
5015 b43err(wl, "Controller restart FAILED\n");
5019 /* reload configuration */
5020 b43_op_config(wl->hw, ~0);
5022 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5024 b43info(wl, "Controller restarted\n");
5027 static int b43_setup_bands(struct b43_wldev *dev,
5028 bool have_2ghz_phy, bool have_5ghz_phy)
5030 struct ieee80211_hw *hw = dev->wl->hw;
5033 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5034 if (dev->phy.type == B43_PHYTYPE_N) {
5036 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5039 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5042 dev->phy.supports_2ghz = have_2ghz_phy;
5043 dev->phy.supports_5ghz = have_5ghz_phy;
5048 static void b43_wireless_core_detach(struct b43_wldev *dev)
5050 /* We release firmware that late to not be required to re-request
5051 * is all the time when we reinit the core. */
5052 b43_release_firmware(dev);
5056 static int b43_wireless_core_attach(struct b43_wldev *dev)
5058 struct b43_wl *wl = dev->wl;
5059 struct pci_dev *pdev = NULL;
5062 bool have_2ghz_phy = false, have_5ghz_phy = false;
5064 /* Do NOT do any device initialization here.
5065 * Do it in wireless_core_init() instead.
5066 * This function is for gathering basic information about the HW, only.
5067 * Also some structs may be set up here. But most likely you want to have
5068 * that in core_init(), too.
5071 #ifdef CONFIG_B43_SSB
5072 if (dev->dev->bus_type == B43_BUS_SSB &&
5073 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5074 pdev = dev->dev->sdev->bus->host_pci;
5077 err = b43_bus_powerup(dev, 0);
5079 b43err(wl, "Bus powerup failed\n");
5083 /* Get the PHY type. */
5084 switch (dev->dev->bus_type) {
5085 #ifdef CONFIG_B43_BCMA
5087 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5088 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5089 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5092 #ifdef CONFIG_B43_SSB
5094 if (dev->dev->core_rev >= 5) {
5095 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5096 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5097 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5104 dev->phy.gmode = have_2ghz_phy;
5105 dev->phy.radio_on = true;
5106 b43_wireless_core_reset(dev, dev->phy.gmode);
5108 err = b43_phy_versioning(dev);
5111 /* Check if this device supports multiband. */
5113 (pdev->device != 0x4312 &&
5114 pdev->device != 0x4319 && pdev->device != 0x4324)) {
5115 /* No multiband support. */
5116 have_2ghz_phy = false;
5117 have_5ghz_phy = false;
5118 switch (dev->phy.type) {
5120 have_5ghz_phy = true;
5122 case B43_PHYTYPE_LP: //FIXME not always!
5123 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5128 case B43_PHYTYPE_HT:
5129 case B43_PHYTYPE_LCN:
5130 have_2ghz_phy = true;
5136 if (dev->phy.type == B43_PHYTYPE_A) {
5138 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5142 if (1 /* disable A-PHY */) {
5143 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5144 if (dev->phy.type != B43_PHYTYPE_N &&
5145 dev->phy.type != B43_PHYTYPE_LP) {
5146 have_2ghz_phy = true;
5147 have_5ghz_phy = false;
5151 err = b43_phy_allocate(dev);
5155 dev->phy.gmode = have_2ghz_phy;
5156 b43_wireless_core_reset(dev, dev->phy.gmode);
5158 err = b43_validate_chipaccess(dev);
5161 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5165 /* Now set some default "current_dev" */
5166 if (!wl->current_dev)
5167 wl->current_dev = dev;
5168 INIT_WORK(&dev->restart_work, b43_chip_reset);
5170 dev->phy.ops->switch_analog(dev, 0);
5171 b43_device_disable(dev, 0);
5172 b43_bus_may_powerdown(dev);
5180 b43_bus_may_powerdown(dev);
5184 static void b43_one_core_detach(struct b43_bus_dev *dev)
5186 struct b43_wldev *wldev;
5189 /* Do not cancel ieee80211-workqueue based work here.
5190 * See comment in b43_remove(). */
5192 wldev = b43_bus_get_wldev(dev);
5194 b43_debugfs_remove_device(wldev);
5195 b43_wireless_core_detach(wldev);
5196 list_del(&wldev->list);
5198 b43_bus_set_wldev(dev, NULL);
5202 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5204 struct b43_wldev *wldev;
5207 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5211 wldev->use_pio = b43_modparam_pio;
5214 b43_set_status(wldev, B43_STAT_UNINIT);
5215 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5216 INIT_LIST_HEAD(&wldev->list);
5218 err = b43_wireless_core_attach(wldev);
5220 goto err_kfree_wldev;
5222 list_add(&wldev->list, &wl->devlist);
5224 b43_bus_set_wldev(dev, wldev);
5225 b43_debugfs_add_device(wldev);
5235 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
5236 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
5237 (pdev->device == _device) && \
5238 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
5239 (pdev->subsystem_device == _subdevice) )
5241 static void b43_sprom_fixup(struct ssb_bus *bus)
5243 struct pci_dev *pdev;
5245 /* boardflags workarounds */
5246 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5247 bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
5248 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5249 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5250 bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
5251 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5252 if (bus->bustype == SSB_BUSTYPE_PCI) {
5253 pdev = bus->host_pci;
5254 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5255 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
5256 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
5257 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5258 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5259 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5260 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5261 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5265 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5267 struct ieee80211_hw *hw = wl->hw;
5269 ssb_set_devtypedata(dev->sdev, NULL);
5270 ieee80211_free_hw(hw);
5273 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5275 struct ssb_sprom *sprom = dev->bus_sprom;
5276 struct ieee80211_hw *hw;
5281 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5283 b43err(NULL, "Could not allocate ieee80211 device\n");
5284 return ERR_PTR(-ENOMEM);
5286 wl = hw_to_b43_wl(hw);
5289 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5290 IEEE80211_HW_SIGNAL_DBM;
5292 hw->wiphy->interface_modes =
5293 BIT(NL80211_IFTYPE_AP) |
5294 BIT(NL80211_IFTYPE_MESH_POINT) |
5295 BIT(NL80211_IFTYPE_STATION) |
5296 BIT(NL80211_IFTYPE_WDS) |
5297 BIT(NL80211_IFTYPE_ADHOC);
5299 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
5301 hw->queues = modparam_qos ? B43_QOS_QUEUE_NUM : 1;
5302 wl->mac80211_initially_registered_queues = hw->queues;
5303 wl->hw_registred = false;
5305 SET_IEEE80211_DEV(hw, dev->dev);
5306 if (is_valid_ether_addr(sprom->et1mac))
5307 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5309 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5311 /* Initialize struct b43_wl */
5313 mutex_init(&wl->mutex);
5314 spin_lock_init(&wl->hardirq_lock);
5315 INIT_LIST_HEAD(&wl->devlist);
5316 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5317 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5318 INIT_WORK(&wl->tx_work, b43_tx_work);
5320 /* Initialize queues and flags. */
5321 for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5322 skb_queue_head_init(&wl->tx_queue[queue_num]);
5323 wl->tx_queue_stopped[queue_num] = 0;
5326 snprintf(chip_name, ARRAY_SIZE(chip_name),
5327 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5328 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5333 #ifdef CONFIG_B43_BCMA
5334 static int b43_bcma_probe(struct bcma_device *core)
5336 struct b43_bus_dev *dev;
5340 dev = b43_bus_dev_bcma_init(core);
5344 wl = b43_wireless_init(dev);
5350 err = b43_one_core_attach(dev, wl);
5352 goto bcma_err_wireless_exit;
5354 /* setup and start work to load firmware */
5355 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5356 schedule_work(&wl->firmware_load);
5361 bcma_err_wireless_exit:
5362 ieee80211_free_hw(wl->hw);
5366 static void b43_bcma_remove(struct bcma_device *core)
5368 struct b43_wldev *wldev = bcma_get_drvdata(core);
5369 struct b43_wl *wl = wldev->wl;
5371 /* We must cancel any work here before unregistering from ieee80211,
5372 * as the ieee80211 unreg will destroy the workqueue. */
5373 cancel_work_sync(&wldev->restart_work);
5376 if (wl->current_dev == wldev && wl->hw_registred) {
5377 /* Restore the queues count before unregistering, because firmware detect
5378 * might have modified it. Restoring is important, so the networking
5379 * stack can properly free resources. */
5380 wl->hw->queues = wl->mac80211_initially_registered_queues;
5381 b43_leds_stop(wldev);
5382 ieee80211_unregister_hw(wl->hw);
5385 b43_one_core_detach(wldev->dev);
5387 b43_leds_unregister(wl);
5389 ieee80211_free_hw(wl->hw);
5392 static struct bcma_driver b43_bcma_driver = {
5393 .name = KBUILD_MODNAME,
5394 .id_table = b43_bcma_tbl,
5395 .probe = b43_bcma_probe,
5396 .remove = b43_bcma_remove,
5400 #ifdef CONFIG_B43_SSB
5402 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5404 struct b43_bus_dev *dev;
5409 dev = b43_bus_dev_ssb_init(sdev);
5413 wl = ssb_get_devtypedata(sdev);
5415 /* Probing the first core. Must setup common struct b43_wl */
5417 b43_sprom_fixup(sdev->bus);
5418 wl = b43_wireless_init(dev);
5423 ssb_set_devtypedata(sdev, wl);
5424 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5426 err = b43_one_core_attach(dev, wl);
5428 goto err_wireless_exit;
5430 /* setup and start work to load firmware */
5431 INIT_WORK(&wl->firmware_load, b43_request_firmware);
5432 schedule_work(&wl->firmware_load);
5439 b43_wireless_exit(dev, wl);
5443 static void b43_ssb_remove(struct ssb_device *sdev)
5445 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5446 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5447 struct b43_bus_dev *dev = wldev->dev;
5449 /* We must cancel any work here before unregistering from ieee80211,
5450 * as the ieee80211 unreg will destroy the workqueue. */
5451 cancel_work_sync(&wldev->restart_work);
5454 if (wl->current_dev == wldev && wl->hw_registred) {
5455 /* Restore the queues count before unregistering, because firmware detect
5456 * might have modified it. Restoring is important, so the networking
5457 * stack can properly free resources. */
5458 wl->hw->queues = wl->mac80211_initially_registered_queues;
5459 b43_leds_stop(wldev);
5460 ieee80211_unregister_hw(wl->hw);
5463 b43_one_core_detach(dev);
5465 if (list_empty(&wl->devlist)) {
5466 b43_leds_unregister(wl);
5467 /* Last core on the chip unregistered.
5468 * We can destroy common struct b43_wl.
5470 b43_wireless_exit(dev, wl);
5474 static struct ssb_driver b43_ssb_driver = {
5475 .name = KBUILD_MODNAME,
5476 .id_table = b43_ssb_tbl,
5477 .probe = b43_ssb_probe,
5478 .remove = b43_ssb_remove,
5480 #endif /* CONFIG_B43_SSB */
5482 /* Perform a hardware reset. This can be called from any context. */
5483 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5485 /* Must avoid requeueing, if we are in shutdown. */
5486 if (b43_status(dev) < B43_STAT_INITIALIZED)
5488 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5489 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5492 static void b43_print_driverinfo(void)
5494 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5495 *feat_leds = "", *feat_sdio = "";
5497 #ifdef CONFIG_B43_PCI_AUTOSELECT
5500 #ifdef CONFIG_B43_PCMCIA
5503 #ifdef CONFIG_B43_PHY_N
5506 #ifdef CONFIG_B43_LEDS
5509 #ifdef CONFIG_B43_SDIO
5512 printk(KERN_INFO "Broadcom 43xx driver loaded "
5513 "[ Features: %s%s%s%s%s ]\n",
5514 feat_pci, feat_pcmcia, feat_nphy,
5515 feat_leds, feat_sdio);
5518 static int __init b43_init(void)
5523 err = b43_pcmcia_init();
5526 err = b43_sdio_init();
5528 goto err_pcmcia_exit;
5529 #ifdef CONFIG_B43_BCMA
5530 err = bcma_driver_register(&b43_bcma_driver);
5534 #ifdef CONFIG_B43_SSB
5535 err = ssb_driver_register(&b43_ssb_driver);
5537 goto err_bcma_driver_exit;
5539 b43_print_driverinfo();
5543 #ifdef CONFIG_B43_SSB
5544 err_bcma_driver_exit:
5546 #ifdef CONFIG_B43_BCMA
5547 bcma_driver_unregister(&b43_bcma_driver);
5558 static void __exit b43_exit(void)
5560 #ifdef CONFIG_B43_SSB
5561 ssb_driver_unregister(&b43_ssb_driver);
5563 #ifdef CONFIG_B43_BCMA
5564 bcma_driver_unregister(&b43_bcma_driver);
5571 module_init(b43_init)
5572 module_exit(b43_exit)