3 Broadcom B43 wireless driver
4 IEEE 802.11g PHY driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
31 #include "phy_common.h"
35 #include <linux/bitrev.h>
36 #include <linux/slab.h>
39 static const s8 b43_tssi2dbm_g_table[] = {
58 static const u8 b43_radio_channel_codes_bg[] = {
66 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
69 #define bitrev4(tmp) (bitrev8(tmp) >> 4)
72 /* Get the freq, as it has to be written to the device. */
73 static inline u16 channel2freq_bg(u8 channel)
75 B43_WARN_ON(!(channel >= 1 && channel <= 14));
77 return b43_radio_channel_codes_bg[channel - 1];
80 static void generate_rfatt_list(struct b43_wldev *dev,
81 struct b43_rfatt_list *list)
83 struct b43_phy *phy = &dev->phy;
85 /* APHY.rev < 5 || GPHY.rev < 6 */
86 static const struct b43_rfatt rfatt_0[] = {
87 {.att = 3,.with_padmix = 0,},
88 {.att = 1,.with_padmix = 0,},
89 {.att = 5,.with_padmix = 0,},
90 {.att = 7,.with_padmix = 0,},
91 {.att = 9,.with_padmix = 0,},
92 {.att = 2,.with_padmix = 0,},
93 {.att = 0,.with_padmix = 0,},
94 {.att = 4,.with_padmix = 0,},
95 {.att = 6,.with_padmix = 0,},
96 {.att = 8,.with_padmix = 0,},
97 {.att = 1,.with_padmix = 1,},
98 {.att = 2,.with_padmix = 1,},
99 {.att = 3,.with_padmix = 1,},
100 {.att = 4,.with_padmix = 1,},
102 /* Radio.rev == 8 && Radio.version == 0x2050 */
103 static const struct b43_rfatt rfatt_1[] = {
104 {.att = 2,.with_padmix = 1,},
105 {.att = 4,.with_padmix = 1,},
106 {.att = 6,.with_padmix = 1,},
107 {.att = 8,.with_padmix = 1,},
108 {.att = 10,.with_padmix = 1,},
109 {.att = 12,.with_padmix = 1,},
110 {.att = 14,.with_padmix = 1,},
113 static const struct b43_rfatt rfatt_2[] = {
114 {.att = 0,.with_padmix = 1,},
115 {.att = 2,.with_padmix = 1,},
116 {.att = 4,.with_padmix = 1,},
117 {.att = 6,.with_padmix = 1,},
118 {.att = 8,.with_padmix = 1,},
119 {.att = 9,.with_padmix = 1,},
120 {.att = 9,.with_padmix = 1,},
123 if (!b43_has_hardware_pctl(dev)) {
125 list->list = rfatt_0;
126 list->len = ARRAY_SIZE(rfatt_0);
131 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
133 list->list = rfatt_1;
134 list->len = ARRAY_SIZE(rfatt_1);
140 list->list = rfatt_2;
141 list->len = ARRAY_SIZE(rfatt_2);
146 static void generate_bbatt_list(struct b43_wldev *dev,
147 struct b43_bbatt_list *list)
149 static const struct b43_bbatt bbatt_0[] = {
161 list->list = bbatt_0;
162 list->len = ARRAY_SIZE(bbatt_0);
167 static void b43_shm_clear_tssi(struct b43_wldev *dev)
169 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
170 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
171 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
172 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
175 /* Synthetic PU workaround */
176 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
178 struct b43_phy *phy = &dev->phy;
182 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
183 /* We do not need the workaround. */
188 b43_write16(dev, B43_MMIO_CHANNEL,
189 channel2freq_bg(channel + 4));
191 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
194 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
197 /* Set the baseband attenuation value on chip. */
198 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
199 u16 baseband_attenuation)
201 struct b43_phy *phy = &dev->phy;
203 if (phy->analog == 0) {
204 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
206 baseband_attenuation);
207 } else if (phy->analog > 1) {
208 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2));
210 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3));
214 /* Adjust the transmission power output (G-PHY) */
215 static void b43_set_txpower_g(struct b43_wldev *dev,
216 const struct b43_bbatt *bbatt,
217 const struct b43_rfatt *rfatt, u8 tx_control)
219 struct b43_phy *phy = &dev->phy;
220 struct b43_phy_g *gphy = phy->g;
221 struct b43_txpower_lo_control *lo = gphy->lo_control;
223 u16 tx_bias, tx_magn;
227 tx_bias = lo->tx_bias;
228 tx_magn = lo->tx_magn;
229 if (unlikely(tx_bias == 0xFF))
232 /* Save the values for later. Use memmove, because it's valid
233 * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */
234 gphy->tx_control = tx_control;
235 memmove(&gphy->rfatt, rfatt, sizeof(*rfatt));
236 gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
237 memmove(&gphy->bbatt, bbatt, sizeof(*bbatt));
239 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
240 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
241 "rfatt(%u), tx_control(0x%02X), "
242 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
243 bb, rf, tx_control, tx_bias, tx_magn);
246 b43_gphy_set_baseband_attenuation(dev, bb);
247 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
248 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
249 b43_radio_write16(dev, 0x43,
250 (rf & 0x000F) | (tx_control & 0x0070));
252 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F));
253 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070));
255 if (has_tx_magnification(phy)) {
256 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
258 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F));
260 b43_lo_g_adjust(dev);
263 /* GPHY_TSSI_Power_Lookup_Table_Init */
264 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
266 struct b43_phy_g *gphy = dev->phy.g;
270 for (i = 0; i < 32; i++)
271 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
272 for (i = 32; i < 64; i++)
273 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
274 for (i = 0; i < 64; i += 2) {
275 value = (u16) gphy->tssi2dbm[i];
276 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
277 b43_phy_write(dev, 0x380 + (i / 2), value);
281 /* GPHY_Gain_Lookup_Table_Init */
282 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
284 struct b43_phy *phy = &dev->phy;
285 struct b43_phy_g *gphy = phy->g;
286 struct b43_txpower_lo_control *lo = gphy->lo_control;
291 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
292 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
293 if (nr_written >= 0x40)
295 tmp = lo->bbatt_list.list[bb].att;
297 if (phy->radio_rev == 8)
301 tmp |= lo->rfatt_list.list[rf].att;
302 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
308 static void b43_set_all_gains(struct b43_wldev *dev,
309 s16 first, s16 second, s16 third)
311 struct b43_phy *phy = &dev->phy;
313 u16 start = 0x08, end = 0x18;
322 table = B43_OFDMTAB_GAINX;
324 table = B43_OFDMTAB_GAINX_R1;
325 for (i = 0; i < 4; i++)
326 b43_ofdmtab_write16(dev, table, i, first);
328 for (i = start; i < end; i++)
329 b43_ofdmtab_write16(dev, table, i, second);
332 tmp = ((u16) third << 14) | ((u16) third << 6);
333 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp);
334 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp);
335 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp);
337 b43_dummy_transmission(dev, false, true);
340 static void b43_set_original_gains(struct b43_wldev *dev)
342 struct b43_phy *phy = &dev->phy;
345 u16 start = 0x0008, end = 0x0018;
352 table = B43_OFDMTAB_GAINX;
354 table = B43_OFDMTAB_GAINX_R1;
355 for (i = 0; i < 4; i++) {
357 tmp |= (i & 0x0001) << 1;
358 tmp |= (i & 0x0002) >> 1;
360 b43_ofdmtab_write16(dev, table, i, tmp);
363 for (i = start; i < end; i++)
364 b43_ofdmtab_write16(dev, table, i, i - start);
366 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040);
367 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040);
368 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000);
369 b43_dummy_transmission(dev, false, true);
372 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
373 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
375 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
376 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
379 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
380 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
384 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
385 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
390 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
391 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
396 for (i = 0; i < 64; i++) {
397 tmp = b43_nrssi_hw_read(dev, i);
399 tmp = clamp_val(tmp, -32, 31);
400 b43_nrssi_hw_write(dev, i, tmp);
404 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
405 static void b43_nrssi_mem_update(struct b43_wldev *dev)
407 struct b43_phy_g *gphy = dev->phy.g;
411 delta = 0x1F - gphy->nrssi[0];
412 for (i = 0; i < 64; i++) {
413 tmp = (i - delta) * gphy->nrssislope;
416 tmp = clamp_val(tmp, 0, 0x3F);
417 gphy->nrssi_lt[i] = tmp;
421 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
423 struct b43_phy *phy = &dev->phy;
424 u16 backup[20] = { 0 };
429 backup[0] = b43_phy_read(dev, 0x0001);
430 backup[1] = b43_phy_read(dev, 0x0811);
431 backup[2] = b43_phy_read(dev, 0x0812);
432 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
433 backup[3] = b43_phy_read(dev, 0x0814);
434 backup[4] = b43_phy_read(dev, 0x0815);
436 backup[5] = b43_phy_read(dev, 0x005A);
437 backup[6] = b43_phy_read(dev, 0x0059);
438 backup[7] = b43_phy_read(dev, 0x0058);
439 backup[8] = b43_phy_read(dev, 0x000A);
440 backup[9] = b43_phy_read(dev, 0x0003);
441 backup[10] = b43_radio_read16(dev, 0x007A);
442 backup[11] = b43_radio_read16(dev, 0x0043);
444 b43_phy_mask(dev, 0x0429, 0x7FFF);
445 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000);
446 b43_phy_set(dev, 0x0811, 0x000C);
447 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004);
448 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
450 backup[12] = b43_phy_read(dev, 0x002E);
451 backup[13] = b43_phy_read(dev, 0x002F);
452 backup[14] = b43_phy_read(dev, 0x080F);
453 backup[15] = b43_phy_read(dev, 0x0810);
454 backup[16] = b43_phy_read(dev, 0x0801);
455 backup[17] = b43_phy_read(dev, 0x0060);
456 backup[18] = b43_phy_read(dev, 0x0014);
457 backup[19] = b43_phy_read(dev, 0x0478);
459 b43_phy_write(dev, 0x002E, 0);
460 b43_phy_write(dev, 0x002F, 0);
461 b43_phy_write(dev, 0x080F, 0);
462 b43_phy_write(dev, 0x0810, 0);
463 b43_phy_set(dev, 0x0478, 0x0100);
464 b43_phy_set(dev, 0x0801, 0x0040);
465 b43_phy_set(dev, 0x0060, 0x0040);
466 b43_phy_set(dev, 0x0014, 0x0200);
468 b43_radio_set(dev, 0x007A, 0x0070);
469 b43_radio_set(dev, 0x007A, 0x0080);
472 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
476 for (i = 7; i >= 4; i--) {
477 b43_radio_write16(dev, 0x007B, i);
480 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
483 if (v47F < 31 && saved == 0xFFFF)
489 b43_radio_mask(dev, 0x007A, 0x007F);
490 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
491 b43_phy_set(dev, 0x0814, 0x0001);
492 b43_phy_mask(dev, 0x0815, 0xFFFE);
494 b43_phy_set(dev, 0x0811, 0x000C);
495 b43_phy_set(dev, 0x0812, 0x000C);
496 b43_phy_set(dev, 0x0811, 0x0030);
497 b43_phy_set(dev, 0x0812, 0x0030);
498 b43_phy_write(dev, 0x005A, 0x0480);
499 b43_phy_write(dev, 0x0059, 0x0810);
500 b43_phy_write(dev, 0x0058, 0x000D);
502 b43_phy_write(dev, 0x0003, 0x0122);
504 b43_phy_set(dev, 0x000A, 0x2000);
506 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
507 b43_phy_set(dev, 0x0814, 0x0004);
508 b43_phy_mask(dev, 0x0815, 0xFFFB);
510 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
511 b43_radio_set(dev, 0x007A, 0x000F);
512 b43_set_all_gains(dev, 3, 0, 1);
513 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F);
515 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
519 for (i = 0; i < 4; i++) {
520 b43_radio_write16(dev, 0x007B, i);
523 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
527 if (v47F > -31 && saved == 0xFFFF)
535 b43_radio_write16(dev, 0x007B, saved);
538 b43_phy_write(dev, 0x002E, backup[12]);
539 b43_phy_write(dev, 0x002F, backup[13]);
540 b43_phy_write(dev, 0x080F, backup[14]);
541 b43_phy_write(dev, 0x0810, backup[15]);
543 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
544 b43_phy_write(dev, 0x0814, backup[3]);
545 b43_phy_write(dev, 0x0815, backup[4]);
547 b43_phy_write(dev, 0x005A, backup[5]);
548 b43_phy_write(dev, 0x0059, backup[6]);
549 b43_phy_write(dev, 0x0058, backup[7]);
550 b43_phy_write(dev, 0x000A, backup[8]);
551 b43_phy_write(dev, 0x0003, backup[9]);
552 b43_radio_write16(dev, 0x0043, backup[11]);
553 b43_radio_write16(dev, 0x007A, backup[10]);
554 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
555 b43_phy_set(dev, 0x0429, 0x8000);
556 b43_set_original_gains(dev);
558 b43_phy_write(dev, 0x0801, backup[16]);
559 b43_phy_write(dev, 0x0060, backup[17]);
560 b43_phy_write(dev, 0x0014, backup[18]);
561 b43_phy_write(dev, 0x0478, backup[19]);
563 b43_phy_write(dev, 0x0001, backup[0]);
564 b43_phy_write(dev, 0x0812, backup[2]);
565 b43_phy_write(dev, 0x0811, backup[1]);
568 static void b43_calc_nrssi_slope(struct b43_wldev *dev)
570 struct b43_phy *phy = &dev->phy;
571 struct b43_phy_g *gphy = phy->g;
572 u16 backup[18] = { 0 };
576 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
578 if (phy->radio_rev >= 9)
580 if (phy->radio_rev == 8)
581 b43_calc_nrssi_offset(dev);
583 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
584 b43_phy_mask(dev, 0x0802, 0xFFFC);
585 backup[7] = b43_read16(dev, 0x03E2);
586 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
587 backup[0] = b43_radio_read16(dev, 0x007A);
588 backup[1] = b43_radio_read16(dev, 0x0052);
589 backup[2] = b43_radio_read16(dev, 0x0043);
590 backup[3] = b43_phy_read(dev, 0x0015);
591 backup[4] = b43_phy_read(dev, 0x005A);
592 backup[5] = b43_phy_read(dev, 0x0059);
593 backup[6] = b43_phy_read(dev, 0x0058);
594 backup[8] = b43_read16(dev, 0x03E6);
595 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
597 backup[10] = b43_phy_read(dev, 0x002E);
598 backup[11] = b43_phy_read(dev, 0x002F);
599 backup[12] = b43_phy_read(dev, 0x080F);
600 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
601 backup[14] = b43_phy_read(dev, 0x0801);
602 backup[15] = b43_phy_read(dev, 0x0060);
603 backup[16] = b43_phy_read(dev, 0x0014);
604 backup[17] = b43_phy_read(dev, 0x0478);
605 b43_phy_write(dev, 0x002E, 0);
606 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
611 b43_phy_set(dev, 0x0478, 0x0100);
612 b43_phy_set(dev, 0x0801, 0x0040);
616 b43_phy_mask(dev, 0x0801, 0xFFBF);
619 b43_phy_set(dev, 0x0060, 0x0040);
620 b43_phy_set(dev, 0x0014, 0x0200);
622 b43_radio_set(dev, 0x007A, 0x0070);
623 b43_set_all_gains(dev, 0, 8, 0);
624 b43_radio_mask(dev, 0x007A, 0x00F7);
626 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030);
627 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010);
629 b43_radio_set(dev, 0x007A, 0x0080);
632 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
633 if (nrssi0 >= 0x0020)
636 b43_radio_mask(dev, 0x007A, 0x007F);
638 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
641 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
642 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
644 b43_radio_set(dev, 0x007A, 0x000F);
645 b43_phy_write(dev, 0x0015, 0xF330);
647 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020);
648 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020);
651 b43_set_all_gains(dev, 3, 0, 1);
652 if (phy->radio_rev == 8) {
653 b43_radio_write16(dev, 0x0043, 0x001F);
655 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
656 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
657 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
658 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
660 b43_phy_write(dev, 0x005A, 0x0480);
661 b43_phy_write(dev, 0x0059, 0x0810);
662 b43_phy_write(dev, 0x0058, 0x000D);
664 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
665 if (nrssi1 >= 0x0020)
667 if (nrssi0 == nrssi1)
668 gphy->nrssislope = 0x00010000;
670 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
672 gphy->nrssi[0] = nrssi1;
673 gphy->nrssi[1] = nrssi0;
676 b43_phy_write(dev, 0x002E, backup[10]);
677 b43_phy_write(dev, 0x002F, backup[11]);
678 b43_phy_write(dev, 0x080F, backup[12]);
679 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
682 b43_phy_mask(dev, 0x0812, 0xFFCF);
683 b43_phy_mask(dev, 0x0811, 0xFFCF);
686 b43_radio_write16(dev, 0x007A, backup[0]);
687 b43_radio_write16(dev, 0x0052, backup[1]);
688 b43_radio_write16(dev, 0x0043, backup[2]);
689 b43_write16(dev, 0x03E2, backup[7]);
690 b43_write16(dev, 0x03E6, backup[8]);
691 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
692 b43_phy_write(dev, 0x0015, backup[3]);
693 b43_phy_write(dev, 0x005A, backup[4]);
694 b43_phy_write(dev, 0x0059, backup[5]);
695 b43_phy_write(dev, 0x0058, backup[6]);
696 b43_synth_pu_workaround(dev, phy->channel);
697 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002));
698 b43_set_original_gains(dev);
699 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
701 b43_phy_write(dev, 0x0801, backup[14]);
702 b43_phy_write(dev, 0x0060, backup[15]);
703 b43_phy_write(dev, 0x0014, backup[16]);
704 b43_phy_write(dev, 0x0478, backup[17]);
706 b43_nrssi_mem_update(dev);
707 b43_calc_nrssi_threshold(dev);
710 static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
712 struct b43_phy *phy = &dev->phy;
713 struct b43_phy_g *gphy = phy->g;
718 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
721 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) {
722 tmp16 = b43_nrssi_hw_read(dev, 0x20);
726 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB);
728 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED);
731 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
734 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
742 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
743 a += (gphy->nrssi[0] << 6);
749 a = clamp_val(a, -31, 31);
751 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
752 b += (gphy->nrssi[0] << 6);
758 b = clamp_val(b, -31, 31);
760 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
761 tmp_u16 |= ((u32) b & 0x0000003F);
762 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
763 b43_phy_write(dev, 0x048A, tmp_u16);
767 /* Stack implementation to save/restore values from the
768 * interference mitigation code.
769 * It is save to restore values in random order.
771 static void _stack_save(u32 *_stackptr, size_t *stackidx,
772 u8 id, u16 offset, u16 value)
774 u32 *stackptr = &(_stackptr[*stackidx]);
776 B43_WARN_ON(offset & 0xF000);
777 B43_WARN_ON(id & 0xF0);
779 *stackptr |= ((u32) id) << 12;
780 *stackptr |= ((u32) value) << 16;
782 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
785 static u16 _stack_restore(u32 *stackptr, u8 id, u16 offset)
789 B43_WARN_ON(offset & 0xF000);
790 B43_WARN_ON(id & 0xF0);
791 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
792 if ((*stackptr & 0x00000FFF) != offset)
794 if (((*stackptr & 0x0000F000) >> 12) != id)
796 return ((*stackptr & 0xFFFF0000) >> 16);
803 #define phy_stacksave(offset) \
805 _stack_save(stack, &stackidx, 0x1, (offset), \
806 b43_phy_read(dev, (offset))); \
808 #define phy_stackrestore(offset) \
810 b43_phy_write(dev, (offset), \
811 _stack_restore(stack, 0x1, \
814 #define radio_stacksave(offset) \
816 _stack_save(stack, &stackidx, 0x2, (offset), \
817 b43_radio_read16(dev, (offset))); \
819 #define radio_stackrestore(offset) \
821 b43_radio_write16(dev, (offset), \
822 _stack_restore(stack, 0x2, \
825 #define ofdmtab_stacksave(table, offset) \
827 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
828 b43_ofdmtab_read16(dev, (table), (offset))); \
830 #define ofdmtab_stackrestore(table, offset) \
832 b43_ofdmtab_write16(dev, (table), (offset), \
833 _stack_restore(stack, 0x3, \
834 (offset)|(table))); \
838 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
840 struct b43_phy *phy = &dev->phy;
841 struct b43_phy_g *gphy = phy->g;
844 u32 *stack = gphy->interfstack;
847 case B43_INTERFMODE_NONWLAN:
849 b43_phy_set(dev, 0x042B, 0x0800);
850 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
853 radio_stacksave(0x0078);
854 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
855 B43_WARN_ON(tmp > 15);
856 flipped = bitrev4(tmp);
857 if (flipped < 10 && flipped >= 8)
859 else if (flipped >= 10)
861 flipped = (bitrev4(flipped) << 1) | 0x0020;
862 b43_radio_write16(dev, 0x0078, flipped);
864 b43_calc_nrssi_threshold(dev);
866 phy_stacksave(0x0406);
867 b43_phy_write(dev, 0x0406, 0x7E28);
869 b43_phy_set(dev, 0x042B, 0x0800);
870 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
872 phy_stacksave(0x04A0);
873 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008);
874 phy_stacksave(0x04A1);
875 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605);
876 phy_stacksave(0x04A2);
877 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204);
878 phy_stacksave(0x04A8);
879 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803);
880 phy_stacksave(0x04AB);
881 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605);
883 phy_stacksave(0x04A7);
884 b43_phy_write(dev, 0x04A7, 0x0002);
885 phy_stacksave(0x04A3);
886 b43_phy_write(dev, 0x04A3, 0x287A);
887 phy_stacksave(0x04A9);
888 b43_phy_write(dev, 0x04A9, 0x2027);
889 phy_stacksave(0x0493);
890 b43_phy_write(dev, 0x0493, 0x32F5);
891 phy_stacksave(0x04AA);
892 b43_phy_write(dev, 0x04AA, 0x2027);
893 phy_stacksave(0x04AC);
894 b43_phy_write(dev, 0x04AC, 0x32F5);
896 case B43_INTERFMODE_MANUALWLAN:
897 if (b43_phy_read(dev, 0x0033) & 0x0800)
900 gphy->aci_enable = 1;
902 phy_stacksave(B43_PHY_RADIO_BITFIELD);
903 phy_stacksave(B43_PHY_G_CRS);
905 phy_stacksave(0x0406);
907 phy_stacksave(0x04C0);
908 phy_stacksave(0x04C1);
910 phy_stacksave(0x0033);
911 phy_stacksave(0x04A7);
912 phy_stacksave(0x04A3);
913 phy_stacksave(0x04A9);
914 phy_stacksave(0x04AA);
915 phy_stacksave(0x04AC);
916 phy_stacksave(0x0493);
917 phy_stacksave(0x04A1);
918 phy_stacksave(0x04A0);
919 phy_stacksave(0x04A2);
920 phy_stacksave(0x048A);
921 phy_stacksave(0x04A8);
922 phy_stacksave(0x04AB);
924 phy_stacksave(0x04AD);
925 phy_stacksave(0x04AE);
926 } else if (phy->rev >= 3) {
927 phy_stacksave(0x04AD);
928 phy_stacksave(0x0415);
929 phy_stacksave(0x0416);
930 phy_stacksave(0x0417);
931 ofdmtab_stacksave(0x1A00, 0x2);
932 ofdmtab_stacksave(0x1A00, 0x3);
934 phy_stacksave(0x042B);
935 phy_stacksave(0x048C);
937 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
938 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002);
940 b43_phy_write(dev, 0x0033, 0x0800);
941 b43_phy_write(dev, 0x04A3, 0x2027);
942 b43_phy_write(dev, 0x04A9, 0x1CA8);
943 b43_phy_write(dev, 0x0493, 0x287A);
944 b43_phy_write(dev, 0x04AA, 0x1CA8);
945 b43_phy_write(dev, 0x04AC, 0x287A);
947 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A);
948 b43_phy_write(dev, 0x04A7, 0x000D);
951 b43_phy_write(dev, 0x0406, 0xFF0D);
952 } else if (phy->rev == 2) {
953 b43_phy_write(dev, 0x04C0, 0xFFFF);
954 b43_phy_write(dev, 0x04C1, 0x00A9);
956 b43_phy_write(dev, 0x04C0, 0x00C1);
957 b43_phy_write(dev, 0x04C1, 0x0059);
960 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800);
961 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015);
962 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000);
963 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00);
964 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000);
965 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800);
966 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010);
967 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005);
968 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010);
969 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006);
970 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800);
971 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500);
972 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B);
975 b43_phy_mask(dev, 0x048A, 0x7FFF);
976 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8);
977 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8);
978 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D);
980 b43_phy_set(dev, 0x048A, 0x1000);
981 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000);
982 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
985 b43_phy_set(dev, 0x042B, 0x0800);
987 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200);
989 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F);
990 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300);
991 } else if (phy->rev >= 6) {
992 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
993 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
994 b43_phy_mask(dev, 0x04AD, 0x00FF);
996 b43_calc_nrssi_slope(dev);
1004 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1006 struct b43_phy *phy = &dev->phy;
1007 struct b43_phy_g *gphy = phy->g;
1008 u32 *stack = gphy->interfstack;
1011 case B43_INTERFMODE_NONWLAN:
1012 if (phy->rev != 1) {
1013 b43_phy_mask(dev, 0x042B, ~0x0800);
1014 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1017 radio_stackrestore(0x0078);
1018 b43_calc_nrssi_threshold(dev);
1019 phy_stackrestore(0x0406);
1020 b43_phy_mask(dev, 0x042B, ~0x0800);
1021 if (!dev->bad_frames_preempt) {
1022 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1024 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1025 phy_stackrestore(0x04A0);
1026 phy_stackrestore(0x04A1);
1027 phy_stackrestore(0x04A2);
1028 phy_stackrestore(0x04A8);
1029 phy_stackrestore(0x04AB);
1030 phy_stackrestore(0x04A7);
1031 phy_stackrestore(0x04A3);
1032 phy_stackrestore(0x04A9);
1033 phy_stackrestore(0x0493);
1034 phy_stackrestore(0x04AA);
1035 phy_stackrestore(0x04AC);
1037 case B43_INTERFMODE_MANUALWLAN:
1038 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1041 gphy->aci_enable = 0;
1043 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1044 phy_stackrestore(B43_PHY_G_CRS);
1045 phy_stackrestore(0x0033);
1046 phy_stackrestore(0x04A3);
1047 phy_stackrestore(0x04A9);
1048 phy_stackrestore(0x0493);
1049 phy_stackrestore(0x04AA);
1050 phy_stackrestore(0x04AC);
1051 phy_stackrestore(0x04A0);
1052 phy_stackrestore(0x04A7);
1053 if (phy->rev >= 2) {
1054 phy_stackrestore(0x04C0);
1055 phy_stackrestore(0x04C1);
1057 phy_stackrestore(0x0406);
1058 phy_stackrestore(0x04A1);
1059 phy_stackrestore(0x04AB);
1060 phy_stackrestore(0x04A8);
1061 if (phy->rev == 2) {
1062 phy_stackrestore(0x04AD);
1063 phy_stackrestore(0x04AE);
1064 } else if (phy->rev >= 3) {
1065 phy_stackrestore(0x04AD);
1066 phy_stackrestore(0x0415);
1067 phy_stackrestore(0x0416);
1068 phy_stackrestore(0x0417);
1069 ofdmtab_stackrestore(0x1A00, 0x2);
1070 ofdmtab_stackrestore(0x1A00, 0x3);
1072 phy_stackrestore(0x04A2);
1073 phy_stackrestore(0x048A);
1074 phy_stackrestore(0x042B);
1075 phy_stackrestore(0x048C);
1076 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1077 b43_calc_nrssi_slope(dev);
1084 #undef phy_stacksave
1085 #undef phy_stackrestore
1086 #undef radio_stacksave
1087 #undef radio_stackrestore
1088 #undef ofdmtab_stacksave
1089 #undef ofdmtab_stackrestore
1091 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1093 u16 reg, index, ret;
1095 static const u8 rcc_table[] = {
1096 0x02, 0x03, 0x01, 0x0F,
1097 0x06, 0x07, 0x05, 0x0F,
1098 0x0A, 0x0B, 0x09, 0x0F,
1099 0x0E, 0x0F, 0x0D, 0x0F,
1102 reg = b43_radio_read16(dev, 0x60);
1103 index = (reg & 0x001E) >> 1;
1104 ret = rcc_table[index] << 1;
1105 ret |= (reg & 0x0001);
1111 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1112 static u16 radio2050_rfover_val(struct b43_wldev *dev,
1113 u16 phy_register, unsigned int lpd)
1115 struct b43_phy *phy = &dev->phy;
1116 struct b43_phy_g *gphy = phy->g;
1117 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1122 if (has_loopback_gain(phy)) {
1123 int max_lb_gain = gphy->max_lb_gain;
1127 if (phy->radio_rev == 8)
1128 max_lb_gain += 0x3E;
1130 max_lb_gain += 0x26;
1131 if (max_lb_gain >= 0x46) {
1133 max_lb_gain -= 0x46;
1134 } else if (max_lb_gain >= 0x3A) {
1136 max_lb_gain -= 0x3A;
1137 } else if (max_lb_gain >= 0x2E) {
1139 max_lb_gain -= 0x2E;
1142 max_lb_gain -= 0x10;
1145 for (i = 0; i < 16; i++) {
1146 max_lb_gain -= (i * 6);
1147 if (max_lb_gain < 6)
1151 if ((phy->rev < 7) ||
1152 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1153 if (phy_register == B43_PHY_RFOVER) {
1155 } else if (phy_register == B43_PHY_RFOVERVAL) {
1162 return (0x0092 | extlna);
1164 return (0x0093 | extlna);
1170 if (phy_register == B43_PHY_RFOVER) {
1172 } else if (phy_register == B43_PHY_RFOVERVAL) {
1180 return (0x8092 | extlna);
1182 return (0x2092 | extlna);
1184 return (0x2093 | extlna);
1191 if ((phy->rev < 7) ||
1192 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1193 if (phy_register == B43_PHY_RFOVER) {
1195 } else if (phy_register == B43_PHY_RFOVERVAL) {
1210 if (phy_register == B43_PHY_RFOVER) {
1212 } else if (phy_register == B43_PHY_RFOVERVAL) {
1231 struct init2050_saved_values {
1232 /* Core registers */
1236 /* Radio registers */
1249 u16 phy_analogoverval;
1257 static u16 b43_radio_init2050(struct b43_wldev *dev)
1259 struct b43_phy *phy = &dev->phy;
1260 struct init2050_saved_values sav;
1265 u32 tmp1 = 0, tmp2 = 0;
1267 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
1269 sav.radio_43 = b43_radio_read16(dev, 0x43);
1270 sav.radio_51 = b43_radio_read16(dev, 0x51);
1271 sav.radio_52 = b43_radio_read16(dev, 0x52);
1272 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1273 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1274 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1275 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1277 if (phy->type == B43_PHYTYPE_B) {
1278 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1279 sav.reg_3EC = b43_read16(dev, 0x3EC);
1281 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1282 b43_write16(dev, 0x3EC, 0x3F3F);
1283 } else if (phy->gmode || phy->rev >= 2) {
1284 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1285 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1286 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1287 sav.phy_analogoverval =
1288 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1289 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1290 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1292 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1293 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1294 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1295 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1296 if (has_loopback_gain(phy)) {
1297 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1298 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1301 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1303 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1304 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1307 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1308 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1310 b43_phy_write(dev, B43_PHY_RFOVER,
1311 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1313 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1315 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1316 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1317 sav.reg_3E6 = b43_read16(dev, 0x3E6);
1318 sav.reg_3F4 = b43_read16(dev, 0x3F4);
1320 if (phy->analog == 0) {
1321 b43_write16(dev, 0x03E6, 0x0122);
1323 if (phy->analog >= 2) {
1324 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40);
1326 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1327 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1330 rcc = b43_radio_core_calibration_value(dev);
1332 if (phy->type == B43_PHYTYPE_B)
1333 b43_radio_write16(dev, 0x78, 0x26);
1334 if (phy->gmode || phy->rev >= 2) {
1335 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1336 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1339 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1340 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1341 if (phy->gmode || phy->rev >= 2) {
1342 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1343 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1346 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1347 b43_radio_set(dev, 0x51, 0x0004);
1348 if (phy->radio_rev == 8) {
1349 b43_radio_write16(dev, 0x43, 0x1F);
1351 b43_radio_write16(dev, 0x52, 0);
1352 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009);
1354 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1356 for (i = 0; i < 16; i++) {
1357 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1358 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1359 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1360 if (phy->gmode || phy->rev >= 2) {
1361 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1362 radio2050_rfover_val(dev,
1366 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1368 if (phy->gmode || phy->rev >= 2) {
1369 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1370 radio2050_rfover_val(dev,
1374 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1376 if (phy->gmode || phy->rev >= 2) {
1377 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1378 radio2050_rfover_val(dev,
1382 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1384 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1385 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1386 if (phy->gmode || phy->rev >= 2) {
1387 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1388 radio2050_rfover_val(dev,
1392 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1396 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1400 for (i = 0; i < 16; i++) {
1401 radio78 = (bitrev4(i) << 1) | 0x0020;
1402 b43_radio_write16(dev, 0x78, radio78);
1404 for (j = 0; j < 16; j++) {
1405 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1406 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1407 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1408 if (phy->gmode || phy->rev >= 2) {
1409 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1410 radio2050_rfover_val(dev,
1415 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1417 if (phy->gmode || phy->rev >= 2) {
1418 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1419 radio2050_rfover_val(dev,
1424 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1426 if (phy->gmode || phy->rev >= 2) {
1427 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1428 radio2050_rfover_val(dev,
1433 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1435 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1436 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1437 if (phy->gmode || phy->rev >= 2) {
1438 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1439 radio2050_rfover_val(dev,
1444 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1452 /* Restore the registers */
1453 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1454 b43_radio_write16(dev, 0x51, sav.radio_51);
1455 b43_radio_write16(dev, 0x52, sav.radio_52);
1456 b43_radio_write16(dev, 0x43, sav.radio_43);
1457 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1458 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1459 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1460 b43_write16(dev, 0x3E6, sav.reg_3E6);
1461 if (phy->analog != 0)
1462 b43_write16(dev, 0x3F4, sav.reg_3F4);
1463 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1464 b43_synth_pu_workaround(dev, phy->channel);
1465 if (phy->type == B43_PHYTYPE_B) {
1466 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1467 b43_write16(dev, 0x3EC, sav.reg_3EC);
1468 } else if (phy->gmode) {
1469 b43_write16(dev, B43_MMIO_PHY_RADIO,
1470 b43_read16(dev, B43_MMIO_PHY_RADIO)
1472 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1473 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1474 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1475 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1476 sav.phy_analogoverval);
1477 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1478 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1479 if (has_loopback_gain(phy)) {
1480 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1481 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1492 static void b43_phy_initb5(struct b43_wldev *dev)
1494 struct ssb_bus *bus = dev->sdev->bus;
1495 struct b43_phy *phy = &dev->phy;
1496 struct b43_phy_g *gphy = phy->g;
1500 if (phy->analog == 1) {
1501 b43_radio_set(dev, 0x007A, 0x0050);
1503 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1504 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1506 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1507 b43_phy_write(dev, offset, value);
1511 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700);
1512 if (phy->radio_ver == 0x2050)
1513 b43_phy_write(dev, 0x0038, 0x0667);
1515 if (phy->gmode || phy->rev >= 2) {
1516 if (phy->radio_ver == 0x2050) {
1517 b43_radio_set(dev, 0x007A, 0x0020);
1518 b43_radio_set(dev, 0x0051, 0x0004);
1520 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1522 b43_phy_set(dev, 0x0802, 0x0100);
1523 b43_phy_set(dev, 0x042B, 0x2000);
1525 b43_phy_write(dev, 0x001C, 0x186A);
1527 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900);
1528 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064);
1529 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A);
1532 if (dev->bad_frames_preempt) {
1533 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11));
1536 if (phy->analog == 1) {
1537 b43_phy_write(dev, 0x0026, 0xCE00);
1538 b43_phy_write(dev, 0x0021, 0x3763);
1539 b43_phy_write(dev, 0x0022, 0x1BC3);
1540 b43_phy_write(dev, 0x0023, 0x06F9);
1541 b43_phy_write(dev, 0x0024, 0x037E);
1543 b43_phy_write(dev, 0x0026, 0xCC00);
1544 b43_phy_write(dev, 0x0030, 0x00C6);
1545 b43_write16(dev, 0x03EC, 0x3F22);
1547 if (phy->analog == 1)
1548 b43_phy_write(dev, 0x0020, 0x3E1C);
1550 b43_phy_write(dev, 0x0020, 0x301C);
1552 if (phy->analog == 0)
1553 b43_write16(dev, 0x03E4, 0x3000);
1555 old_channel = phy->channel;
1556 /* Force to channel 7, even if not supported. */
1557 b43_gphy_channel_switch(dev, 7, 0);
1559 if (phy->radio_ver != 0x2050) {
1560 b43_radio_write16(dev, 0x0075, 0x0080);
1561 b43_radio_write16(dev, 0x0079, 0x0081);
1564 b43_radio_write16(dev, 0x0050, 0x0020);
1565 b43_radio_write16(dev, 0x0050, 0x0023);
1567 if (phy->radio_ver == 0x2050) {
1568 b43_radio_write16(dev, 0x0050, 0x0020);
1569 b43_radio_write16(dev, 0x005A, 0x0070);
1572 b43_radio_write16(dev, 0x005B, 0x007B);
1573 b43_radio_write16(dev, 0x005C, 0x00B0);
1575 b43_radio_set(dev, 0x007A, 0x0007);
1577 b43_gphy_channel_switch(dev, old_channel, 0);
1579 b43_phy_write(dev, 0x0014, 0x0080);
1580 b43_phy_write(dev, 0x0032, 0x00CA);
1581 b43_phy_write(dev, 0x002A, 0x88A3);
1583 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1585 if (phy->radio_ver == 0x2050)
1586 b43_radio_write16(dev, 0x005D, 0x000D);
1588 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1591 static void b43_phy_initb6(struct b43_wldev *dev)
1593 struct b43_phy *phy = &dev->phy;
1594 struct b43_phy_g *gphy = phy->g;
1598 b43_phy_write(dev, 0x003E, 0x817A);
1599 b43_radio_write16(dev, 0x007A,
1600 (b43_radio_read16(dev, 0x007A) | 0x0058));
1601 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1602 b43_radio_write16(dev, 0x51, 0x37);
1603 b43_radio_write16(dev, 0x52, 0x70);
1604 b43_radio_write16(dev, 0x53, 0xB3);
1605 b43_radio_write16(dev, 0x54, 0x9B);
1606 b43_radio_write16(dev, 0x5A, 0x88);
1607 b43_radio_write16(dev, 0x5B, 0x88);
1608 b43_radio_write16(dev, 0x5D, 0x88);
1609 b43_radio_write16(dev, 0x5E, 0x88);
1610 b43_radio_write16(dev, 0x7D, 0x88);
1611 b43_hf_write(dev, b43_hf_read(dev)
1612 | B43_HF_TSSIRPSMW);
1614 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1615 if (phy->radio_rev == 8) {
1616 b43_radio_write16(dev, 0x51, 0);
1617 b43_radio_write16(dev, 0x52, 0x40);
1618 b43_radio_write16(dev, 0x53, 0xB7);
1619 b43_radio_write16(dev, 0x54, 0x98);
1620 b43_radio_write16(dev, 0x5A, 0x88);
1621 b43_radio_write16(dev, 0x5B, 0x6B);
1622 b43_radio_write16(dev, 0x5C, 0x0F);
1623 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) {
1624 b43_radio_write16(dev, 0x5D, 0xFA);
1625 b43_radio_write16(dev, 0x5E, 0xD8);
1627 b43_radio_write16(dev, 0x5D, 0xF5);
1628 b43_radio_write16(dev, 0x5E, 0xB8);
1630 b43_radio_write16(dev, 0x0073, 0x0003);
1631 b43_radio_write16(dev, 0x007D, 0x00A8);
1632 b43_radio_write16(dev, 0x007C, 0x0001);
1633 b43_radio_write16(dev, 0x007E, 0x0008);
1636 for (offset = 0x0088; offset < 0x0098; offset++) {
1637 b43_phy_write(dev, offset, val);
1641 for (offset = 0x0098; offset < 0x00A8; offset++) {
1642 b43_phy_write(dev, offset, val);
1646 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1647 b43_phy_write(dev, offset, (val & 0x3F3F));
1650 if (phy->type == B43_PHYTYPE_G) {
1651 b43_radio_set(dev, 0x007A, 0x0020);
1652 b43_radio_set(dev, 0x0051, 0x0004);
1653 b43_phy_set(dev, 0x0802, 0x0100);
1654 b43_phy_set(dev, 0x042B, 0x2000);
1655 b43_phy_write(dev, 0x5B, 0);
1656 b43_phy_write(dev, 0x5C, 0);
1659 old_channel = phy->channel;
1660 if (old_channel >= 8)
1661 b43_gphy_channel_switch(dev, 1, 0);
1663 b43_gphy_channel_switch(dev, 13, 0);
1665 b43_radio_write16(dev, 0x0050, 0x0020);
1666 b43_radio_write16(dev, 0x0050, 0x0023);
1668 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1669 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1671 b43_radio_write16(dev, 0x50, 0x20);
1673 if (phy->radio_rev <= 2) {
1674 b43_radio_write16(dev, 0x7C, 0x20);
1675 b43_radio_write16(dev, 0x5A, 0x70);
1676 b43_radio_write16(dev, 0x5B, 0x7B);
1677 b43_radio_write16(dev, 0x5C, 0xB0);
1679 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007);
1681 b43_gphy_channel_switch(dev, old_channel, 0);
1683 b43_phy_write(dev, 0x0014, 0x0200);
1684 if (phy->radio_rev >= 6)
1685 b43_phy_write(dev, 0x2A, 0x88C2);
1687 b43_phy_write(dev, 0x2A, 0x8AC0);
1688 b43_phy_write(dev, 0x0038, 0x0668);
1689 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1690 if (phy->radio_rev <= 5) {
1691 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003);
1693 if (phy->radio_rev <= 2)
1694 b43_radio_write16(dev, 0x005D, 0x000D);
1696 if (phy->analog == 4) {
1697 b43_write16(dev, 0x3E4, 9);
1698 b43_phy_mask(dev, 0x61, 0x0FFF);
1700 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004);
1702 if (phy->type == B43_PHYTYPE_B)
1704 else if (phy->type == B43_PHYTYPE_G)
1705 b43_write16(dev, 0x03E6, 0x0);
1708 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1710 struct b43_phy *phy = &dev->phy;
1711 struct b43_phy_g *gphy = phy->g;
1712 u16 backup_phy[16] = { 0 };
1713 u16 backup_radio[3];
1715 u16 i, j, loop_i_max;
1717 u16 loop1_outer_done, loop1_inner_done;
1719 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1720 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1721 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1722 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1723 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1724 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1725 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1727 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1728 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1729 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1730 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1731 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1732 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1733 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1734 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1735 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1736 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1737 backup_bband = gphy->bbatt.att;
1738 backup_radio[0] = b43_radio_read16(dev, 0x52);
1739 backup_radio[1] = b43_radio_read16(dev, 0x43);
1740 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1742 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1743 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1744 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1745 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1746 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1747 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1748 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1749 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1750 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1751 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1752 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1754 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1755 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1756 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1757 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10);
1759 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1760 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1761 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1763 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1764 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1765 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1766 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1768 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40);
1770 if (phy->radio_rev == 8) {
1771 b43_radio_write16(dev, 0x43, 0x000F);
1773 b43_radio_write16(dev, 0x52, 0);
1774 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9);
1776 b43_gphy_set_baseband_attenuation(dev, 11);
1779 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1781 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1782 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1784 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01);
1785 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800);
1787 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1788 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1790 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) {
1791 if (phy->rev >= 7) {
1792 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1793 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
1796 b43_radio_mask(dev, 0x7A, 0x00F7);
1799 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1800 for (i = 0; i < loop_i_max; i++) {
1801 for (j = 0; j < 16; j++) {
1802 b43_radio_write16(dev, 0x43, i);
1803 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1804 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1805 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1807 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1812 loop1_outer_done = i;
1813 loop1_inner_done = j;
1815 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1817 for (j = j - 8; j < 16; j++) {
1818 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1819 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1820 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1823 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1830 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1831 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1832 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1834 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1835 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1836 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1837 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1838 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1839 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1840 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1841 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1842 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1844 b43_gphy_set_baseband_attenuation(dev, backup_bband);
1846 b43_radio_write16(dev, 0x52, backup_radio[0]);
1847 b43_radio_write16(dev, 0x43, backup_radio[1]);
1848 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1850 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1852 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1853 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1854 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1855 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1858 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1859 gphy->trsw_rx_gain = trsw_rx * 2;
1862 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1864 struct b43_phy *phy = &dev->phy;
1866 if (!b43_has_hardware_pctl(dev)) {
1867 b43_phy_write(dev, 0x047A, 0xC111);
1871 b43_phy_mask(dev, 0x0036, 0xFEFF);
1872 b43_phy_write(dev, 0x002F, 0x0202);
1873 b43_phy_set(dev, 0x047C, 0x0002);
1874 b43_phy_set(dev, 0x047A, 0xF000);
1875 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
1876 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1877 b43_phy_set(dev, 0x005D, 0x8000);
1878 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1879 b43_phy_write(dev, 0x002E, 0xC07F);
1880 b43_phy_set(dev, 0x0036, 0x0400);
1882 b43_phy_set(dev, 0x0036, 0x0200);
1883 b43_phy_set(dev, 0x0036, 0x0400);
1884 b43_phy_mask(dev, 0x005D, 0x7FFF);
1885 b43_phy_mask(dev, 0x004F, 0xFFFE);
1886 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1887 b43_phy_write(dev, 0x002E, 0xC07F);
1888 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1892 /* Hardware power control for G-PHY */
1893 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1895 struct b43_phy *phy = &dev->phy;
1896 struct b43_phy_g *gphy = phy->g;
1898 if (!b43_has_hardware_pctl(dev)) {
1899 /* No hardware power control */
1900 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
1904 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1905 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1906 b43_gphy_tssi_power_lt_init(dev);
1907 b43_gphy_gain_lt_init(dev);
1908 b43_phy_mask(dev, 0x0060, 0xFFBF);
1909 b43_phy_write(dev, 0x0014, 0x0000);
1911 B43_WARN_ON(phy->rev < 6);
1912 b43_phy_set(dev, 0x0478, 0x0800);
1913 b43_phy_mask(dev, 0x0478, 0xFEFF);
1914 b43_phy_mask(dev, 0x0801, 0xFFBF);
1916 b43_gphy_dc_lt_init(dev, 1);
1918 /* Enable hardware pctl in firmware. */
1919 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
1922 /* Initialize B/G PHY power control */
1923 static void b43_phy_init_pctl(struct b43_wldev *dev)
1925 struct ssb_bus *bus = dev->sdev->bus;
1926 struct b43_phy *phy = &dev->phy;
1927 struct b43_phy_g *gphy = phy->g;
1928 struct b43_rfatt old_rfatt;
1929 struct b43_bbatt old_bbatt;
1930 u8 old_tx_control = 0;
1932 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
1934 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1935 (bus->boardinfo.type == SSB_BOARD_BU4306))
1938 b43_phy_write(dev, 0x0028, 0x8018);
1940 /* This does something with the Analog... */
1941 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
1946 b43_hardware_pctl_early_init(dev);
1947 if (gphy->cur_idle_tssi == 0) {
1948 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1949 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084);
1951 struct b43_rfatt rfatt;
1952 struct b43_bbatt bbatt;
1954 memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
1955 memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
1956 old_tx_control = gphy->tx_control;
1959 if (phy->radio_rev == 8) {
1961 rfatt.with_padmix = 1;
1964 rfatt.with_padmix = 0;
1966 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
1968 b43_dummy_transmission(dev, false, true);
1969 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
1971 /* Current-Idle-TSSI sanity check. */
1972 if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
1974 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
1975 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
1976 "adjustment.\n", gphy->cur_idle_tssi,
1977 gphy->tgt_idle_tssi);
1978 gphy->cur_idle_tssi = 0;
1981 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1982 b43_radio_mask(dev, 0x0076, 0xFF7B);
1984 b43_set_txpower_g(dev, &old_bbatt,
1985 &old_rfatt, old_tx_control);
1988 b43_hardware_pctl_init_gphy(dev);
1989 b43_shm_clear_tssi(dev);
1992 static void b43_phy_initg(struct b43_wldev *dev)
1994 struct b43_phy *phy = &dev->phy;
1995 struct b43_phy_g *gphy = phy->g;
1999 b43_phy_initb5(dev);
2001 b43_phy_initb6(dev);
2003 if (phy->rev >= 2 || phy->gmode)
2006 if (phy->rev >= 2) {
2007 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2008 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2010 if (phy->rev == 2) {
2011 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2012 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2015 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2016 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2018 if (phy->gmode || phy->rev >= 2) {
2019 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2020 tmp &= B43_PHYVER_VERSION;
2021 if (tmp == 3 || tmp == 5) {
2022 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2023 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2026 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00);
2029 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2030 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2031 if (phy->radio_rev == 8) {
2032 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80);
2033 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4);
2035 if (has_loopback_gain(phy))
2036 b43_calc_loopback_gain(dev);
2038 if (phy->radio_rev != 8) {
2039 if (gphy->initval == 0xFFFF)
2040 gphy->initval = b43_radio_init2050(dev);
2042 b43_radio_write16(dev, 0x0078, gphy->initval);
2045 if (has_tx_magnification(phy)) {
2046 b43_radio_write16(dev, 0x52,
2047 (b43_radio_read16(dev, 0x52) & 0xFF00)
2048 | gphy->lo_control->tx_bias | gphy->
2049 lo_control->tx_magn);
2051 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias);
2053 if (phy->rev >= 6) {
2054 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2056 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
2057 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2059 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2061 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2063 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2064 if (phy->gmode || phy->rev >= 2) {
2065 b43_lo_g_adjust(dev);
2066 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2069 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) {
2070 /* The specs state to update the NRSSI LT with
2071 * the value 0x7FFFFFFF here. I think that is some weird
2072 * compiler optimization in the original driver.
2073 * Essentially, what we do here is resetting all NRSSI LT
2074 * entries to -32 (see the clamp_val() in nrssi_hw_update())
2076 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
2077 b43_calc_nrssi_threshold(dev);
2078 } else if (phy->gmode || phy->rev >= 2) {
2079 if (gphy->nrssi[0] == -1000) {
2080 B43_WARN_ON(gphy->nrssi[1] != -1000);
2081 b43_calc_nrssi_slope(dev);
2083 b43_calc_nrssi_threshold(dev);
2085 if (phy->radio_rev == 8)
2086 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2087 b43_phy_init_pctl(dev);
2088 /* FIXME: The spec says in the following if, the 0 should be replaced
2089 'if OFDM may not be used in the current locale'
2090 but OFDM is legal everywhere */
2091 if ((dev->dev->chip_id == 0x4306
2092 && dev->dev->chip_pkg == 2) || 0) {
2093 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2094 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2098 void b43_gphy_channel_switch(struct b43_wldev *dev,
2099 unsigned int channel,
2100 bool synthetic_pu_workaround)
2102 if (synthetic_pu_workaround)
2103 b43_synth_pu_workaround(dev, channel);
2105 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2107 if (channel == 14) {
2108 if (dev->dev->bus_sprom->country_code ==
2109 SSB_SPROM1CCODE_JAPAN)
2111 b43_hf_read(dev) & ~B43_HF_ACPR);
2114 b43_hf_read(dev) | B43_HF_ACPR);
2115 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2116 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2119 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2120 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2125 static void default_baseband_attenuation(struct b43_wldev *dev,
2126 struct b43_bbatt *bb)
2128 struct b43_phy *phy = &dev->phy;
2130 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2136 static void default_radio_attenuation(struct b43_wldev *dev,
2137 struct b43_rfatt *rf)
2139 struct ssb_bus *bus = dev->sdev->bus;
2140 struct b43_phy *phy = &dev->phy;
2142 rf->with_padmix = 0;
2144 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2145 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2146 if (bus->boardinfo.rev < 0x43) {
2149 } else if (bus->boardinfo.rev < 0x51) {
2155 if (phy->type == B43_PHYTYPE_A) {
2160 switch (phy->radio_ver) {
2162 switch (phy->radio_rev) {
2169 switch (phy->radio_rev) {
2174 if (phy->type == B43_PHYTYPE_G) {
2175 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2176 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2177 && bus->boardinfo.rev >= 30)
2179 else if (bus->boardinfo.vendor ==
2181 && bus->boardinfo.type ==
2187 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2188 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2189 && bus->boardinfo.rev >= 30)
2196 if (phy->type == B43_PHYTYPE_G) {
2197 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2198 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2199 && bus->boardinfo.rev >= 30)
2201 else if (bus->boardinfo.vendor ==
2203 && bus->boardinfo.type ==
2206 else if (dev->dev->chip_id == 0x4320)
2226 rf->with_padmix = 1;
2237 static u16 default_tx_control(struct b43_wldev *dev)
2239 struct b43_phy *phy = &dev->phy;
2241 if (phy->radio_ver != 0x2050)
2243 if (phy->radio_rev == 1)
2244 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2245 if (phy->radio_rev < 6)
2246 return B43_TXCTL_PA2DB;
2247 if (phy->radio_rev == 8)
2248 return B43_TXCTL_TXMIX;
2252 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2254 struct b43_phy *phy = &dev->phy;
2255 struct b43_phy_g *gphy = phy->g;
2257 u16 saved, rssi, temp;
2260 saved = b43_phy_read(dev, 0x0403);
2261 b43_switch_channel(dev, channel);
2262 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2263 if (gphy->aci_hw_rssi)
2264 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2266 rssi = saved & 0x3F;
2267 /* clamp temp to signed 5bit */
2270 for (i = 0; i < 100; i++) {
2271 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2279 b43_phy_write(dev, 0x0403, saved);
2284 static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2286 struct b43_phy *phy = &dev->phy;
2288 unsigned int channel = phy->channel;
2289 unsigned int i, j, start, end;
2291 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2295 b43_radio_lock(dev);
2296 b43_phy_mask(dev, 0x0802, 0xFFFC);
2297 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2298 b43_set_all_gains(dev, 3, 8, 1);
2300 start = (channel - 5 > 0) ? channel - 5 : 1;
2301 end = (channel + 5 < 14) ? channel + 5 : 13;
2303 for (i = start; i <= end; i++) {
2304 if (abs(channel - i) > 2)
2305 ret[i - 1] = b43_gphy_aci_detect(dev, i);
2307 b43_switch_channel(dev, channel);
2308 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003);
2309 b43_phy_mask(dev, 0x0403, 0xFFF8);
2310 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2311 b43_set_original_gains(dev);
2312 for (i = 0; i < 13; i++) {
2315 end = (i + 5 < 13) ? i + 5 : 13;
2316 for (j = i; j < end; j++)
2319 b43_radio_unlock(dev);
2320 b43_phy_unlock(dev);
2322 return ret[channel - 1];
2325 static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2330 return (num + den / 2) / den;
2333 static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2334 s16 pab0, s16 pab1, s16 pab2)
2336 s32 m1, m2, f = 256, q, delta;
2339 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2340 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2344 q = b43_tssi2dbm_ad(f * 4096 -
2345 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2349 } while (delta >= 2);
2350 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2354 u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2355 s16 pab0, s16 pab1, s16 pab2)
2361 tab = kmalloc(64, GFP_KERNEL);
2363 b43err(dev->wl, "Could not allocate memory "
2364 "for tssi2dbm table\n");
2367 for (i = 0; i < 64; i++) {
2368 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2370 b43err(dev->wl, "Could not generate "
2371 "tssi2dBm table\n");
2380 /* Initialise the TSSI->dBm lookup table */
2381 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2383 struct b43_phy *phy = &dev->phy;
2384 struct b43_phy_g *gphy = phy->g;
2385 s16 pab0, pab1, pab2;
2387 pab0 = (s16) (dev->dev->bus_sprom->pa0b0);
2388 pab1 = (s16) (dev->dev->bus_sprom->pa0b1);
2389 pab2 = (s16) (dev->dev->bus_sprom->pa0b2);
2391 B43_WARN_ON((dev->dev->chip_id == 0x4301) &&
2392 (phy->radio_ver != 0x2050)); /* Not supported anymore */
2394 gphy->dyn_tssi_tbl = 0;
2396 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2397 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2398 /* The pabX values are set in SPROM. Use them. */
2399 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 &&
2400 (s8) dev->dev->bus_sprom->itssi_bg != -1) {
2401 gphy->tgt_idle_tssi =
2402 (s8) (dev->dev->bus_sprom->itssi_bg);
2404 gphy->tgt_idle_tssi = 62;
2405 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2407 if (!gphy->tssi2dbm)
2409 gphy->dyn_tssi_tbl = 1;
2411 /* pabX values not set in SPROM. */
2412 gphy->tgt_idle_tssi = 52;
2413 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2419 static int b43_gphy_op_allocate(struct b43_wldev *dev)
2421 struct b43_phy_g *gphy;
2422 struct b43_txpower_lo_control *lo;
2425 gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2432 lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2437 gphy->lo_control = lo;
2439 err = b43_gphy_init_tssi2dbm_table(dev);
2453 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev)
2455 struct b43_phy *phy = &dev->phy;
2456 struct b43_phy_g *gphy = phy->g;
2457 const void *tssi2dbm;
2459 struct b43_txpower_lo_control *lo;
2462 /* tssi2dbm table is constant, so it is initialized at alloc time.
2463 * Save a copy of the pointer. */
2464 tssi2dbm = gphy->tssi2dbm;
2465 tgt_idle_tssi = gphy->tgt_idle_tssi;
2466 /* Save the LO pointer. */
2467 lo = gphy->lo_control;
2469 /* Zero out the whole PHY structure. */
2470 memset(gphy, 0, sizeof(*gphy));
2472 /* Restore pointers. */
2473 gphy->tssi2dbm = tssi2dbm;
2474 gphy->tgt_idle_tssi = tgt_idle_tssi;
2475 gphy->lo_control = lo;
2477 memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2480 for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2481 gphy->nrssi[i] = -1000;
2482 for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2483 gphy->nrssi_lt[i] = i;
2485 gphy->lofcal = 0xFFFF;
2486 gphy->initval = 0xFFFF;
2488 gphy->interfmode = B43_INTERFMODE_NONE;
2490 /* OFDM-table address caching. */
2491 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2493 gphy->average_tssi = 0xFF;
2495 /* Local Osciallator structure */
2497 INIT_LIST_HEAD(&lo->calib_list);
2500 static void b43_gphy_op_free(struct b43_wldev *dev)
2502 struct b43_phy *phy = &dev->phy;
2503 struct b43_phy_g *gphy = phy->g;
2505 kfree(gphy->lo_control);
2507 if (gphy->dyn_tssi_tbl)
2508 kfree(gphy->tssi2dbm);
2509 gphy->dyn_tssi_tbl = 0;
2510 gphy->tssi2dbm = NULL;
2516 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2518 struct b43_phy *phy = &dev->phy;
2519 struct b43_phy_g *gphy = phy->g;
2520 struct b43_txpower_lo_control *lo = gphy->lo_control;
2522 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2524 default_baseband_attenuation(dev, &gphy->bbatt);
2525 default_radio_attenuation(dev, &gphy->rfatt);
2526 gphy->tx_control = (default_tx_control(dev) << 4);
2527 generate_rfatt_list(dev, &lo->rfatt_list);
2528 generate_bbatt_list(dev, &lo->bbatt_list);
2530 /* Commit previous writes */
2531 b43_read32(dev, B43_MMIO_MACCTL);
2533 if (phy->rev == 1) {
2534 /* Workaround: Temporarly disable gmode through the early init
2535 * phase, as the gmode stuff is not needed for phy rev 1 */
2537 b43_wireless_core_reset(dev, 0);
2540 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2546 static int b43_gphy_op_init(struct b43_wldev *dev)
2553 static void b43_gphy_op_exit(struct b43_wldev *dev)
2555 b43_lo_g_cleanup(dev);
2558 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2560 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2561 return b43_read16(dev, B43_MMIO_PHY_DATA);
2564 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2566 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2567 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2570 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2572 /* Register 1 is a 32-bit register. */
2573 B43_WARN_ON(reg == 1);
2574 /* G-PHY needs 0x80 for read access. */
2577 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2578 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2581 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2583 /* Register 1 is a 32-bit register. */
2584 B43_WARN_ON(reg == 1);
2586 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2587 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2590 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2592 return (dev->phy.rev >= 6);
2595 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2598 struct b43_phy *phy = &dev->phy;
2599 struct b43_phy_g *gphy = phy->g;
2600 unsigned int channel;
2609 b43_phy_write(dev, 0x0015, 0x8000);
2610 b43_phy_write(dev, 0x0015, 0xCC00);
2611 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2612 if (gphy->radio_off_context.valid) {
2613 /* Restore the RFover values. */
2614 b43_phy_write(dev, B43_PHY_RFOVER,
2615 gphy->radio_off_context.rfover);
2616 b43_phy_write(dev, B43_PHY_RFOVERVAL,
2617 gphy->radio_off_context.rfoverval);
2618 gphy->radio_off_context.valid = 0;
2620 channel = phy->channel;
2621 b43_gphy_channel_switch(dev, 6, 1);
2622 b43_gphy_channel_switch(dev, channel, 0);
2624 /* Turn radio OFF */
2625 u16 rfover, rfoverval;
2627 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2628 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2629 gphy->radio_off_context.rfover = rfover;
2630 gphy->radio_off_context.rfoverval = rfoverval;
2631 gphy->radio_off_context.valid = 1;
2632 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2633 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2637 static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2638 unsigned int new_channel)
2640 if ((new_channel < 1) || (new_channel > 14))
2642 b43_gphy_channel_switch(dev, new_channel, 0);
2647 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2649 return 1; /* Default to channel 1 */
2652 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2654 struct b43_phy *phy = &dev->phy;
2658 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2661 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
2663 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT,
2664 (autodiv ? B43_ANTENNA_AUTO1 : antenna) <<
2665 B43_PHY_BBANDCFG_RXANT_SHIFT);
2668 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2669 if (antenna == B43_ANTENNA_AUTO1)
2670 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2672 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2673 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2676 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2678 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2680 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2681 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2684 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV);
2686 b43_phy_mask(dev, B43_PHY_ANTWRSETT,
2687 B43_PHY_ANTWRSETT_ARXDIV);
2690 if (phy->rev >= 2) {
2691 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10);
2692 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15);
2695 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8);
2697 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8);
2700 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2702 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
2705 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2706 enum b43_interference_mitigation mode)
2708 struct b43_phy *phy = &dev->phy;
2709 struct b43_phy_g *gphy = phy->g;
2712 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2713 if ((phy->rev == 0) || (!phy->gmode))
2716 gphy->aci_wlan_automatic = 0;
2718 case B43_INTERFMODE_AUTOWLAN:
2719 gphy->aci_wlan_automatic = 1;
2720 if (gphy->aci_enable)
2721 mode = B43_INTERFMODE_MANUALWLAN;
2723 mode = B43_INTERFMODE_NONE;
2725 case B43_INTERFMODE_NONE:
2726 case B43_INTERFMODE_NONWLAN:
2727 case B43_INTERFMODE_MANUALWLAN:
2733 currentmode = gphy->interfmode;
2734 if (currentmode == mode)
2736 if (currentmode != B43_INTERFMODE_NONE)
2737 b43_radio_interference_mitigation_disable(dev, currentmode);
2739 if (mode == B43_INTERFMODE_NONE) {
2740 gphy->aci_enable = 0;
2741 gphy->aci_hw_rssi = 0;
2743 b43_radio_interference_mitigation_enable(dev, mode);
2744 gphy->interfmode = mode;
2749 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2750 * This function converts a TSSI value to dBm in Q5.2
2752 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2754 struct b43_phy_g *gphy = dev->phy.g;
2758 tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2759 tmp = clamp_val(tmp, 0x00, 0x3F);
2760 dbm = gphy->tssi2dbm[tmp];
2765 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2766 int *_bbatt, int *_rfatt)
2768 int rfatt = *_rfatt;
2769 int bbatt = *_bbatt;
2770 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2772 /* Get baseband and radio attenuation values into their permitted ranges.
2773 * Radio attenuation affects power level 4 times as much as baseband. */
2775 /* Range constants */
2776 const int rf_min = lo->rfatt_list.min_val;
2777 const int rf_max = lo->rfatt_list.max_val;
2778 const int bb_min = lo->bbatt_list.min_val;
2779 const int bb_max = lo->bbatt_list.max_val;
2782 if (rfatt > rf_max && bbatt > bb_max - 4)
2783 break; /* Can not get it into ranges */
2784 if (rfatt < rf_min && bbatt < bb_min + 4)
2785 break; /* Can not get it into ranges */
2786 if (bbatt > bb_max && rfatt > rf_max - 1)
2787 break; /* Can not get it into ranges */
2788 if (bbatt < bb_min && rfatt < rf_min + 1)
2789 break; /* Can not get it into ranges */
2791 if (bbatt > bb_max) {
2796 if (bbatt < bb_min) {
2801 if (rfatt > rf_max) {
2806 if (rfatt < rf_min) {
2814 *_rfatt = clamp_val(rfatt, rf_min, rf_max);
2815 *_bbatt = clamp_val(bbatt, bb_min, bb_max);
2818 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2820 struct b43_phy *phy = &dev->phy;
2821 struct b43_phy_g *gphy = phy->g;
2825 b43_mac_suspend(dev);
2827 /* Calculate the new attenuation values. */
2828 bbatt = gphy->bbatt.att;
2829 bbatt += gphy->bbatt_delta;
2830 rfatt = gphy->rfatt.att;
2831 rfatt += gphy->rfatt_delta;
2833 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2834 tx_control = gphy->tx_control;
2835 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2837 if (tx_control == 0) {
2843 } else if (dev->dev->bus_sprom->
2846 bbatt += 4 * (rfatt - 2);
2849 } else if (rfatt > 4 && tx_control) {
2860 /* Save the control values */
2861 gphy->tx_control = tx_control;
2862 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2863 gphy->rfatt.att = rfatt;
2864 gphy->bbatt.att = bbatt;
2866 if (b43_debug(dev, B43_DBG_XMITPOWER))
2867 b43dbg(dev->wl, "Adjusting TX power\n");
2869 /* Adjust the hardware */
2871 b43_radio_lock(dev);
2872 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
2874 b43_radio_unlock(dev);
2875 b43_phy_unlock(dev);
2877 b43_mac_enable(dev);
2880 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
2883 struct b43_phy *phy = &dev->phy;
2884 struct b43_phy_g *gphy = phy->g;
2885 unsigned int average_tssi;
2886 int cck_result, ofdm_result;
2887 int estimated_pwr, desired_pwr, pwr_adjust;
2888 int rfatt_delta, bbatt_delta;
2889 unsigned int max_pwr;
2891 /* First get the average TSSI */
2892 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK);
2893 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G);
2894 if ((cck_result < 0) && (ofdm_result < 0)) {
2895 /* No TSSI information available */
2897 goto no_adjustment_needed;
2902 average_tssi = ofdm_result;
2903 else if (ofdm_result < 0)
2904 average_tssi = cck_result;
2906 average_tssi = (cck_result + ofdm_result) / 2;
2907 /* Merge the average with the stored value. */
2908 if (likely(gphy->average_tssi != 0xFF))
2909 average_tssi = (average_tssi + gphy->average_tssi) / 2;
2910 gphy->average_tssi = average_tssi;
2911 B43_WARN_ON(average_tssi >= B43_TSSI_MAX);
2913 /* Estimate the TX power emission based on the TSSI */
2914 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
2916 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2917 max_pwr = dev->dev->bus_sprom->maxpwr_bg;
2918 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
2919 max_pwr -= 3; /* minus 0.75 */
2920 if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) {
2922 "Invalid max-TX-power value in SPROM.\n");
2923 max_pwr = INT_TO_Q52(20); /* fake it */
2924 dev->dev->bus_sprom->maxpwr_bg = max_pwr;
2927 /* Get desired power (in Q5.2) */
2928 if (phy->desired_txpower < 0)
2929 desired_pwr = INT_TO_Q52(0);
2931 desired_pwr = INT_TO_Q52(phy->desired_txpower);
2932 /* And limit it. max_pwr already is Q5.2 */
2933 desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
2934 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2936 "[TX power] current = " Q52_FMT
2937 " dBm, desired = " Q52_FMT
2938 " dBm, max = " Q52_FMT "\n",
2939 Q52_ARG(estimated_pwr),
2940 Q52_ARG(desired_pwr),
2944 /* Calculate the adjustment delta. */
2945 pwr_adjust = desired_pwr - estimated_pwr;
2946 if (pwr_adjust == 0)
2947 goto no_adjustment_needed;
2949 /* RF attenuation delta. */
2950 rfatt_delta = ((pwr_adjust + 7) / 8);
2951 /* Lower attenuation => Bigger power output. Negate it. */
2952 rfatt_delta = -rfatt_delta;
2954 /* Baseband attenuation delta. */
2955 bbatt_delta = pwr_adjust / 2;
2956 /* Lower attenuation => Bigger power output. Negate it. */
2957 bbatt_delta = -bbatt_delta;
2958 /* RF att affects power level 4 times as much as
2959 * Baseband attennuation. Subtract it. */
2960 bbatt_delta -= 4 * rfatt_delta;
2963 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2964 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust;
2966 "[TX power deltas] %s" Q52_FMT " dBm => "
2967 "bbatt-delta = %d, rfatt-delta = %d\n",
2968 (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm),
2969 bbatt_delta, rfatt_delta);
2973 /* So do we finally need to adjust something in hardware? */
2974 if ((rfatt_delta == 0) && (bbatt_delta == 0))
2975 goto no_adjustment_needed;
2977 /* Save the deltas for later when we adjust the power. */
2978 gphy->bbatt_delta = bbatt_delta;
2979 gphy->rfatt_delta = rfatt_delta;
2981 /* We need to adjust the TX power on the device. */
2982 return B43_TXPWR_RES_NEED_ADJUST;
2984 no_adjustment_needed:
2985 return B43_TXPWR_RES_DONE;
2988 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
2990 struct b43_phy *phy = &dev->phy;
2991 struct b43_phy_g *gphy = phy->g;
2993 b43_mac_suspend(dev);
2994 //TODO: update_aci_moving_average
2995 if (gphy->aci_enable && gphy->aci_wlan_automatic) {
2996 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) {
2997 if (0 /*TODO: bunch of conditions */ ) {
2998 phy->ops->interf_mitigation(dev,
2999 B43_INTERFMODE_MANUALWLAN);
3001 } else if (0 /*TODO*/) {
3002 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3003 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3005 } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3007 //TODO: implement rev1 workaround
3009 b43_lo_g_maintanance_work(dev);
3010 b43_mac_enable(dev);
3013 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3015 struct b43_phy *phy = &dev->phy;
3017 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI))
3020 b43_mac_suspend(dev);
3021 b43_calc_nrssi_slope(dev);
3022 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3023 u8 old_chan = phy->channel;
3025 /* VCO Calibration */
3027 b43_switch_channel(dev, 1);
3029 b43_switch_channel(dev, 13);
3030 b43_switch_channel(dev, old_chan);
3032 b43_mac_enable(dev);
3035 const struct b43_phy_operations b43_phyops_g = {
3036 .allocate = b43_gphy_op_allocate,
3037 .free = b43_gphy_op_free,
3038 .prepare_structs = b43_gphy_op_prepare_structs,
3039 .prepare_hardware = b43_gphy_op_prepare_hardware,
3040 .init = b43_gphy_op_init,
3041 .exit = b43_gphy_op_exit,
3042 .phy_read = b43_gphy_op_read,
3043 .phy_write = b43_gphy_op_write,
3044 .radio_read = b43_gphy_op_radio_read,
3045 .radio_write = b43_gphy_op_radio_write,
3046 .supports_hwpctl = b43_gphy_op_supports_hwpctl,
3047 .software_rfkill = b43_gphy_op_software_rfkill,
3048 .switch_analog = b43_phyop_switch_analog_generic,
3049 .switch_channel = b43_gphy_op_switch_channel,
3050 .get_default_chan = b43_gphy_op_get_default_chan,
3051 .set_rx_antenna = b43_gphy_op_set_rx_antenna,
3052 .interf_mitigation = b43_gphy_op_interf_mitigation,
3053 .recalc_txpower = b43_gphy_op_recalc_txpower,
3054 .adjust_txpower = b43_gphy_op_adjust_txpower,
3055 .pwork_15sec = b43_gphy_op_pwork_15sec,
3056 .pwork_60sec = b43_gphy_op_pwork_60sec,