3 Broadcom B43 wireless driver
4 IEEE 802.11a/g LP-PHY driver
6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7 Copyright (c) 2009 Gábor Stefanik <netrolller.3d@gmail.com>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
29 #include "phy_common.h"
30 #include "tables_lpphy.h"
33 static inline u16 channel2freq_lp(u8 channel)
36 return (2407 + 5 * channel);
37 else if (channel == 14)
39 else if (channel < 184)
40 return (5000 + 5 * channel);
42 return (4000 + 5 * channel);
45 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
47 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
52 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
54 struct b43_phy_lp *lpphy;
56 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
64 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
66 struct b43_phy *phy = &dev->phy;
67 struct b43_phy_lp *lpphy = phy->lp;
69 memset(lpphy, 0, sizeof(*lpphy));
70 lpphy->antenna = B43_ANTENNA_DEFAULT;
75 static void b43_lpphy_op_free(struct b43_wldev *dev)
77 struct b43_phy_lp *lpphy = dev->phy.lp;
83 /* http://bcm-v4.sipsolutions.net/802.11/PHY/LP/ReadBandSrom */
84 static void lpphy_read_band_sprom(struct b43_wldev *dev)
86 struct b43_phy_lp *lpphy = dev->phy.lp;
87 struct ssb_bus *bus = dev->dev->bus;
92 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
93 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
94 lpphy->bx_arch = bus->sprom.bxa2g;
95 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
96 lpphy->rssi_vf = bus->sprom.rssismf2g;
97 lpphy->rssi_vc = bus->sprom.rssismc2g;
98 lpphy->rssi_gs = bus->sprom.rssisav2g;
99 lpphy->txpa[0] = bus->sprom.pa0b0;
100 lpphy->txpa[1] = bus->sprom.pa0b1;
101 lpphy->txpa[2] = bus->sprom.pa0b2;
102 maxpwr = bus->sprom.maxpwr_bg;
103 lpphy->max_tx_pwr_med_band = maxpwr;
104 cckpo = bus->sprom.cck2gpo;
106 * We don't read SPROM's opo as specs say. On rev8 SPROMs
107 * opo == ofdm2gpo and we don't know any SSB with LP-PHY
108 * and SPROM rev below 8.
110 B43_WARN_ON(bus->sprom.revision < 8);
111 ofdmpo = bus->sprom.ofdm2gpo;
113 for (i = 0; i < 4; i++) {
114 lpphy->tx_max_rate[i] =
115 maxpwr - (ofdmpo & 0xF) * 2;
118 ofdmpo = bus->sprom.ofdm2gpo;
119 for (i = 4; i < 15; i++) {
120 lpphy->tx_max_rate[i] =
121 maxpwr - (ofdmpo & 0xF) * 2;
126 for (i = 0; i < 4; i++)
127 lpphy->tx_max_rate[i] = maxpwr;
128 for (i = 4; i < 15; i++)
129 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
132 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
133 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
134 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
135 lpphy->bx_arch = bus->sprom.bxa5g;
136 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
137 lpphy->rssi_vf = bus->sprom.rssismf5g;
138 lpphy->rssi_vc = bus->sprom.rssismc5g;
139 lpphy->rssi_gs = bus->sprom.rssisav5g;
140 lpphy->txpa[0] = bus->sprom.pa1b0;
141 lpphy->txpa[1] = bus->sprom.pa1b1;
142 lpphy->txpa[2] = bus->sprom.pa1b2;
143 lpphy->txpal[0] = bus->sprom.pa1lob0;
144 lpphy->txpal[1] = bus->sprom.pa1lob1;
145 lpphy->txpal[2] = bus->sprom.pa1lob2;
146 lpphy->txpah[0] = bus->sprom.pa1hib0;
147 lpphy->txpah[1] = bus->sprom.pa1hib1;
148 lpphy->txpah[2] = bus->sprom.pa1hib2;
149 maxpwr = bus->sprom.maxpwr_al;
150 ofdmpo = bus->sprom.ofdm5glpo;
151 lpphy->max_tx_pwr_low_band = maxpwr;
152 for (i = 4; i < 12; i++) {
153 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
156 maxpwr = bus->sprom.maxpwr_a;
157 ofdmpo = bus->sprom.ofdm5gpo;
158 lpphy->max_tx_pwr_med_band = maxpwr;
159 for (i = 4; i < 12; i++) {
160 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
163 maxpwr = bus->sprom.maxpwr_ah;
164 ofdmpo = bus->sprom.ofdm5ghpo;
165 lpphy->max_tx_pwr_hi_band = maxpwr;
166 for (i = 4; i < 12; i++) {
167 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
173 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
175 struct b43_phy_lp *lpphy = dev->phy.lp;
179 B43_WARN_ON(dev->phy.rev >= 2);
181 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
182 isolation = lpphy->tx_isolation_med_band;
183 else if (freq <= 5320)
184 isolation = lpphy->tx_isolation_low_band;
185 else if (freq <= 5700)
186 isolation = lpphy->tx_isolation_med_band;
188 isolation = lpphy->tx_isolation_hi_band;
190 temp[0] = ((isolation - 26) / 12) << 12;
191 temp[1] = temp[0] + 0x1000;
192 temp[2] = temp[0] + 0x2000;
194 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
195 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
198 static void lpphy_table_init(struct b43_wldev *dev)
200 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
202 if (dev->phy.rev < 2)
203 lpphy_rev0_1_table_init(dev);
205 lpphy_rev2plus_table_init(dev);
207 lpphy_init_tx_gain_table(dev);
209 if (dev->phy.rev < 2)
210 lpphy_adjust_gain_table(dev, freq);
213 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
215 struct ssb_bus *bus = dev->dev->bus;
216 struct b43_phy_lp *lpphy = dev->phy.lp;
219 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
220 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
221 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
222 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
223 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
224 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
225 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
227 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
228 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
229 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
230 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
231 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
232 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
233 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
234 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
235 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
236 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
237 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
238 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
239 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
240 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
241 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
242 0xFF00, lpphy->rx_pwr_offset);
243 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
244 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
245 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
246 ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
247 ssb_pmu_set_ldo_paref(&bus->chipco, true);
248 if (dev->phy.rev == 0) {
249 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
252 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
254 ssb_pmu_set_ldo_paref(&bus->chipco, false);
255 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
257 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
259 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
260 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
261 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
262 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
264 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
265 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
266 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
267 0xFFF9, (lpphy->bx_arch << 1));
268 if (dev->phy.rev == 1 &&
269 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
278 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
279 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
283 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
286 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
287 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
288 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
289 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
297 } else if (dev->phy.rev == 1 ||
298 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
308 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
309 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
310 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
311 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
312 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
313 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
314 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
315 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
317 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
318 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
319 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
320 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
321 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
323 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
324 (bus->chip_id == 0x5354) &&
325 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
326 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
327 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
328 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
329 //FIXME the Broadcom driver caches & delays this HF write!
330 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
332 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
333 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
334 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
335 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
336 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
337 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
338 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
339 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
340 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
342 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
343 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
345 if (dev->phy.rev == 1) {
346 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
347 tmp2 = (tmp & 0x03E0) >> 5;
349 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
350 tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
351 tmp2 = (tmp & 0x1F00) >> 8;
353 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
354 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
357 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
361 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
363 static const u16 addr[] = {
375 static const u16 coefs[] = {
376 0xDE5E, 0xE832, 0xE331, 0x4D26,
377 0x0026, 0x1420, 0x0020, 0xFE08,
381 struct b43_phy_lp *lpphy = dev->phy.lp;
384 for (i = 0; i < ARRAY_SIZE(addr); i++) {
385 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
386 b43_phy_write(dev, addr[i], coefs[i]);
390 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
392 static const u16 addr[] = {
404 struct b43_phy_lp *lpphy = dev->phy.lp;
407 for (i = 0; i < ARRAY_SIZE(addr); i++)
408 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
411 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
413 struct ssb_bus *bus = dev->dev->bus;
414 struct b43_phy_lp *lpphy = dev->phy.lp;
416 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
417 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
418 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
419 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
420 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
421 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
422 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
423 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
424 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
425 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
426 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
427 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
428 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
429 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
430 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
431 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
432 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
433 if (bus->boardinfo.rev >= 0x18) {
434 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
435 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
437 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
439 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
440 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
441 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
442 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
443 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
444 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
445 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
446 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
447 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
448 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
449 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
450 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
451 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
452 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
454 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
455 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
457 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
458 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
459 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
460 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
461 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
462 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
463 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
464 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
465 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
466 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
468 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
469 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
470 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
473 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
474 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
475 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
476 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
477 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
478 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
479 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
481 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
483 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
484 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
485 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
486 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
487 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
488 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
489 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
490 0x2000 | ((u16)lpphy->rssi_gs << 10) |
491 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
493 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
494 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
495 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
496 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
499 lpphy_save_dig_flt_state(dev);
502 static void lpphy_baseband_init(struct b43_wldev *dev)
504 lpphy_table_init(dev);
505 if (dev->phy.rev >= 2)
506 lpphy_baseband_rev2plus_init(dev);
508 lpphy_baseband_rev0_1_init(dev);
511 struct b2062_freqdata {
516 /* Initialize the 2062 radio. */
517 static void lpphy_2062_init(struct b43_wldev *dev)
519 struct b43_phy_lp *lpphy = dev->phy.lp;
520 struct ssb_bus *bus = dev->dev->bus;
521 u32 crystalfreq, tmp, ref;
523 const struct b2062_freqdata *fd = NULL;
525 static const struct b2062_freqdata freqdata_tab[] = {
526 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
527 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
528 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
529 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
530 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
531 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
532 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
533 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
534 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
535 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
536 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
537 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
540 b2062_upload_init_table(dev);
542 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
543 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
544 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
545 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
546 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
547 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
548 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
549 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
550 if (dev->phy.rev > 0) {
551 b43_radio_write(dev, B2062_S_BG_CTL1,
552 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
554 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
555 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
557 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
559 /* Get the crystal freq, in Hz. */
560 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
562 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
563 B43_WARN_ON(crystalfreq == 0);
565 if (crystalfreq <= 30000000) {
567 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
570 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
573 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
574 (2 * crystalfreq)) - 8) & 0xFF;
575 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
577 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
578 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
579 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
581 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
582 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
583 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
585 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
587 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
588 if (ref < freqdata_tab[i].freq) {
589 fd = &freqdata_tab[i];
594 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
595 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
596 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
598 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
599 ((u16)(fd->data[1]) << 4) | fd->data[0]);
600 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
601 ((u16)(fd->data[3]) << 4) | fd->data[2]);
602 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
603 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
606 /* Initialize the 2063 radio. */
607 static void lpphy_2063_init(struct b43_wldev *dev)
609 b2063_upload_init_table(dev);
610 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
611 b43_radio_set(dev, B2063_COMM8, 0x38);
612 b43_radio_write(dev, B2063_REG_SP1, 0x56);
613 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
614 b43_radio_write(dev, B2063_PA_SP7, 0);
615 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
616 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
617 if (dev->phy.rev == 2) {
618 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
619 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
620 b43_radio_write(dev, B2063_PA_SP2, 0x18);
622 b43_radio_write(dev, B2063_PA_SP3, 0x20);
623 b43_radio_write(dev, B2063_PA_SP2, 0x20);
627 struct lpphy_stx_table_entry {
635 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
636 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
637 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
638 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
639 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
640 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
641 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
642 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
643 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
644 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
645 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
646 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
647 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
648 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
649 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
650 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
651 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
652 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
653 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
654 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
655 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
656 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
657 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
658 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
659 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
660 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
661 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
662 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
663 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
664 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
667 static void lpphy_sync_stx(struct b43_wldev *dev)
669 const struct lpphy_stx_table_entry *e;
673 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
674 e = &lpphy_stx_table[i];
675 tmp = b43_radio_read(dev, e->rf_addr);
677 tmp <<= e->phy_shift;
678 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
679 ~(e->mask << e->phy_shift), tmp);
683 static void lpphy_radio_init(struct b43_wldev *dev)
685 /* The radio is attached through the 4wire bus. */
686 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
688 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
691 if (dev->phy.radio_ver == 0x2062) {
692 lpphy_2062_init(dev);
694 lpphy_2063_init(dev);
696 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
697 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
698 if (dev->dev->bus->chip_id == 0x4325) {
699 // TODO SSB PMU recalibration
704 struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
706 static void lpphy_set_rc_cap(struct b43_wldev *dev)
708 struct b43_phy_lp *lpphy = dev->phy.lp;
710 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
712 if (dev->phy.rev == 1) //FIXME check channel 14!
713 rc_cap = min_t(u8, rc_cap + 5, 15);
715 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
716 max_t(u8, lpphy->rc_cap - 4, 0x80));
717 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
718 b43_radio_write(dev, B2062_S_RXG_CNT16,
719 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
722 static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
724 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
727 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
729 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
732 static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
734 struct b43_phy_lp *lpphy = dev->phy.lp;
737 lpphy->crs_usr_disable = 1;
739 lpphy->crs_sys_disable = 1;
740 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
743 static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
745 struct b43_phy_lp *lpphy = dev->phy.lp;
748 lpphy->crs_usr_disable = 0;
750 lpphy->crs_sys_disable = 0;
752 if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
753 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
754 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
757 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
762 static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx)
764 u16 trsw = (tx << 1) | rx;
765 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw);
766 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
769 static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
771 lpphy_set_deaf(dev, user);
772 lpphy_set_trsw_over(dev, false, true);
773 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
774 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
775 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
776 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
777 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
778 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
779 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
780 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
781 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
782 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
783 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
784 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
785 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
786 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
787 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
788 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
789 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
790 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
791 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
792 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
793 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
794 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
795 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
798 static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
800 lpphy_clear_deaf(dev, user);
801 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
802 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
805 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
807 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
809 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
810 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
811 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
812 if (dev->phy.rev >= 2) {
813 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
814 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
815 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
816 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
819 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
823 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
825 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
826 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
827 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
828 if (dev->phy.rev >= 2) {
829 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
830 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
831 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
832 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
835 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
839 static void lpphy_disable_tx_gain_override(struct b43_wldev *dev)
841 if (dev->phy.rev < 2)
842 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
844 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
845 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
847 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
850 static void lpphy_enable_tx_gain_override(struct b43_wldev *dev)
852 if (dev->phy.rev < 2)
853 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
855 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80);
856 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000);
858 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40);
861 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
863 struct lpphy_tx_gains gains;
866 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
867 if (dev->phy.rev < 2) {
868 tmp = b43_phy_read(dev,
869 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
870 gains.gm = tmp & 0x0007;
871 gains.pga = (tmp & 0x0078) >> 3;
872 gains.pad = (tmp & 0x780) >> 7;
874 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
875 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
876 gains.gm = tmp & 0xFF;
877 gains.pga = (tmp >> 8) & 0xFF;
883 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
885 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
887 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
890 static u16 lpphy_get_pa_gain(struct b43_wldev *dev)
892 return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F;
895 static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain)
897 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6);
898 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8);
901 static void lpphy_set_tx_gains(struct b43_wldev *dev,
902 struct lpphy_tx_gains gains)
904 u16 rf_gain, pa_gain;
906 if (dev->phy.rev < 2) {
907 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
908 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
911 pa_gain = lpphy_get_pa_gain(dev);
912 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
913 (gains.pga << 8) | gains.gm);
915 * SPEC FIXME The spec calls for (pa_gain << 8) here, but that
916 * conflicts with the spec for set_pa_gain! Vendor driver bug?
918 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
919 0x8000, gains.pad | (pa_gain << 6));
920 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
921 (gains.pga << 8) | gains.gm);
922 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
923 0x8000, gains.pad | (pa_gain << 8));
925 lpphy_set_dac_gain(dev, gains.dac);
926 lpphy_enable_tx_gain_override(dev);
929 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
931 u16 trsw = gain & 0x1;
932 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
933 u16 ext_lna = (gain & 2) >> 1;
935 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
936 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
937 0xFBFF, ext_lna << 10);
938 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
939 0xF7FF, ext_lna << 11);
940 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
943 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
945 u16 low_gain = gain & 0xFFFF;
946 u16 high_gain = (gain >> 16) & 0xF;
947 u16 ext_lna = (gain >> 21) & 0x1;
948 u16 trsw = ~(gain >> 20) & 0x1;
951 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
952 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
953 0xFDFF, ext_lna << 9);
954 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
955 0xFBFF, ext_lna << 10);
956 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
957 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
958 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
959 tmp = (gain >> 2) & 0x3;
960 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
962 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
966 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
968 if (dev->phy.rev < 2)
969 lpphy_rev0_1_set_rx_gain(dev, gain);
971 lpphy_rev2plus_set_rx_gain(dev, gain);
972 lpphy_enable_rx_gain_override(dev);
975 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
977 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
978 lpphy_set_rx_gain(dev, gain);
981 static void lpphy_stop_ddfs(struct b43_wldev *dev)
983 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
984 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
987 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
988 int incr1, int incr2, int scale_idx)
990 lpphy_stop_ddfs(dev);
991 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
992 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
993 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
994 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
995 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
996 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
997 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
998 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
999 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
1000 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
1003 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
1004 struct lpphy_iq_est *iq_est)
1008 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
1009 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
1010 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
1011 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
1012 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
1014 for (i = 0; i < 500; i++) {
1015 if (!(b43_phy_read(dev,
1016 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
1021 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
1022 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
1026 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
1027 iq_est->iq_prod <<= 16;
1028 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
1030 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
1031 iq_est->i_pwr <<= 16;
1032 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
1034 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
1035 iq_est->q_pwr <<= 16;
1036 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
1038 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
1042 static int lpphy_loopback(struct b43_wldev *dev)
1044 struct lpphy_iq_est iq_est;
1048 memset(&iq_est, 0, sizeof(iq_est));
1050 lpphy_set_trsw_over(dev, true, true);
1051 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
1052 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1053 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1054 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1055 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1056 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
1057 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
1058 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
1059 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
1060 for (i = 0; i < 32; i++) {
1061 lpphy_set_rx_gain_by_index(dev, i);
1062 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
1063 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1065 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
1066 if ((tmp > 4000) && (tmp < 10000)) {
1071 lpphy_stop_ddfs(dev);
1075 /* Fixed-point division algorithm using only integer math. */
1076 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1078 u32 quotient, remainder;
1083 quotient = dividend / divisor;
1084 remainder = dividend % divisor;
1086 while (precision > 0) {
1088 if (remainder << 1 >= divisor) {
1090 remainder = (remainder << 1) - divisor;
1095 if (remainder << 1 >= divisor)
1101 /* Read the TX power control mode from hardware. */
1102 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1104 struct b43_phy_lp *lpphy = dev->phy.lp;
1107 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1108 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1109 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1110 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1112 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1113 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1115 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1116 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1119 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1125 /* Set the TX power control mode in hardware. */
1126 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1128 struct b43_phy_lp *lpphy = dev->phy.lp;
1131 switch (lpphy->txpctl_mode) {
1132 case B43_LPPHY_TXPCTL_OFF:
1133 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1135 case B43_LPPHY_TXPCTL_HW:
1136 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1138 case B43_LPPHY_TXPCTL_SW:
1139 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1145 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1146 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1149 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1150 enum b43_lpphy_txpctl_mode mode)
1152 struct b43_phy_lp *lpphy = dev->phy.lp;
1153 enum b43_lpphy_txpctl_mode oldmode;
1155 lpphy_read_tx_pctl_mode_from_hardware(dev);
1156 oldmode = lpphy->txpctl_mode;
1157 if (oldmode == mode)
1159 lpphy->txpctl_mode = mode;
1161 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1162 //TODO Update TX Power NPT
1163 //TODO Clear all TX Power offsets
1165 if (mode == B43_LPPHY_TXPCTL_HW) {
1166 //TODO Recalculate target TX power
1167 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1168 0xFF80, lpphy->tssi_idx);
1169 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1170 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1171 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1172 lpphy_disable_tx_gain_override(dev);
1173 lpphy->tx_pwr_idx_over = -1;
1176 if (dev->phy.rev >= 2) {
1177 if (mode == B43_LPPHY_TXPCTL_HW)
1178 b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
1180 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
1182 lpphy_write_tx_pctl_mode_to_hardware(dev);
1185 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1186 unsigned int new_channel);
1188 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1190 struct b43_phy_lp *lpphy = dev->phy.lp;
1191 struct lpphy_iq_est iq_est;
1192 struct lpphy_tx_gains tx_gains;
1193 static const u32 ideal_pwr_table[21] = {
1194 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1195 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1196 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1197 0x0004c, 0x0002c, 0x0001a,
1201 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1202 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1203 enum b43_lpphy_txpctl_mode old_txpctl;
1204 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1205 int loopback, i, j, inner_sum, err;
1207 memset(&iq_est, 0, sizeof(iq_est));
1209 err = b43_lpphy_op_switch_channel(dev, 7);
1212 "RC calib: Failed to switch to channel 7, error = %d\n",
1215 old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
1216 old_bbmult = lpphy_get_bb_mult(dev);
1218 tx_gains = lpphy_get_tx_gains(dev);
1219 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1220 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1221 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1222 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1223 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1224 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1225 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1226 lpphy_read_tx_pctl_mode_from_hardware(dev);
1227 old_txpctl = lpphy->txpctl_mode;
1229 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1230 lpphy_disable_crs(dev, true);
1231 loopback = lpphy_loopback(dev);
1234 lpphy_set_rx_gain_by_index(dev, loopback);
1235 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1236 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1237 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1238 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1239 for (i = 128; i <= 159; i++) {
1240 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1242 for (j = 5; j <= 25; j++) {
1243 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1244 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1246 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1249 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1250 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1251 mean_sq_pwr = ideal_pwr - normal_pwr;
1252 mean_sq_pwr *= mean_sq_pwr;
1253 inner_sum += mean_sq_pwr;
1254 if ((i == 128) || (inner_sum < mean_sq_pwr_min)) {
1256 mean_sq_pwr_min = inner_sum;
1260 lpphy_stop_ddfs(dev);
1263 lpphy_restore_crs(dev, true);
1264 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1265 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1266 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1267 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1268 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1269 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1270 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1272 lpphy_set_bb_mult(dev, old_bbmult);
1275 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1276 * illogical. According to lwfinger, vendor driver v4.150.10.5
1277 * has a Set here, while v4.174.64.19 has a Get - regression in
1278 * the vendor driver? This should be tested this once the code
1281 lpphy_set_tx_gains(dev, tx_gains);
1283 lpphy_set_tx_power_control(dev, old_txpctl);
1285 lpphy_set_rc_cap(dev);
1288 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1290 struct ssb_bus *bus = dev->dev->bus;
1291 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1292 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1295 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1296 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1297 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1298 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1299 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1300 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1301 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1302 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1303 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1305 for (i = 0; i < 10000; i++) {
1306 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1311 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1312 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1314 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1316 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1317 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1318 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1319 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1320 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1322 if (crystal_freq == 24000000) {
1323 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1324 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1326 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1327 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1330 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1332 for (i = 0; i < 10000; i++) {
1333 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1338 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1339 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1341 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1344 static void lpphy_calibrate_rc(struct b43_wldev *dev)
1346 struct b43_phy_lp *lpphy = dev->phy.lp;
1348 if (dev->phy.rev >= 2) {
1349 lpphy_rev2plus_rc_calib(dev);
1350 } else if (!lpphy->rc_cap) {
1351 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1352 lpphy_rev0_1_rc_calib(dev);
1354 lpphy_set_rc_cap(dev);
1358 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
1360 if (dev->phy.rev >= 2)
1361 return; // rev2+ doesn't support antenna diversity
1363 if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
1366 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
1368 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
1369 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
1371 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
1373 dev->phy.lp->antenna = antenna;
1376 static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b)
1382 b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp);
1385 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1387 struct b43_phy_lp *lpphy = dev->phy.lp;
1388 struct lpphy_tx_gains gains;
1389 u32 iq_comp, tx_gain, coeff, rf_power;
1391 lpphy->tx_pwr_idx_over = index;
1392 lpphy_read_tx_pctl_mode_from_hardware(dev);
1393 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1394 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1395 if (dev->phy.rev >= 2) {
1396 iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320));
1397 tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192));
1398 gains.pad = (tx_gain >> 16) & 0xFF;
1399 gains.gm = tx_gain & 0xFF;
1400 gains.pga = (tx_gain >> 8) & 0xFF;
1401 gains.dac = (iq_comp >> 28) & 0xFF;
1402 lpphy_set_tx_gains(dev, gains);
1404 iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320));
1405 tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192));
1406 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
1407 0xF800, (tx_gain >> 4) & 0x7FFF);
1408 lpphy_set_dac_gain(dev, tx_gain & 0x7);
1409 lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F);
1411 lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF);
1412 lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF);
1413 if (dev->phy.rev >= 2) {
1414 coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448));
1416 coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448));
1418 b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF);
1419 if (dev->phy.rev >= 2) {
1420 rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576));
1421 b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00,
1422 rf_power & 0xFFFF);//SPEC FIXME mask & set != 0
1424 lpphy_enable_tx_gain_override(dev);
1427 static void lpphy_btcoex_override(struct b43_wldev *dev)
1429 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1430 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1433 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1436 //TODO check MAC control register
1438 if (dev->phy.rev >= 2) {
1439 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
1440 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
1441 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
1442 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
1443 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808);
1445 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
1446 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
1447 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
1448 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018);
1451 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
1452 if (dev->phy.rev >= 2)
1453 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
1455 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
1459 /* This was previously called lpphy_japan_filter */
1460 static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
1462 struct b43_phy_lp *lpphy = dev->phy.lp;
1463 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
1465 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
1466 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
1467 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
1468 lpphy_set_rc_cap(dev);
1470 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
1474 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1476 if (mode != TSSI_MUX_EXT) {
1477 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1478 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1479 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1480 if (mode == TSSI_MUX_POSTPA) {
1481 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1482 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1484 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1485 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1493 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1498 //SPEC TODO Call LP PHY Clear TX Power offsets
1499 for (i = 0; i < 64; i++) {
1500 if (dev->phy.rev >= 2)
1501 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1503 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1506 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1507 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1508 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1509 if (dev->phy.rev < 2) {
1510 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1511 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1513 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1514 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1515 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1516 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1517 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1519 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1520 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1521 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1522 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1523 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1524 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1525 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1526 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1527 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1528 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1530 if (dev->phy.rev < 2) {
1531 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1532 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1534 lpphy_set_tx_power_by_index(dev, 0x7F);
1537 b43_dummy_transmission(dev, true, true);
1539 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1541 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1542 0xFFC0, (tmp & 0xFF) - 32);
1545 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1547 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1548 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1551 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1553 struct lpphy_tx_gains gains;
1555 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1566 lpphy_set_tx_gains(dev, gains);
1567 lpphy_set_bb_mult(dev, 150);
1570 /* Initialize TX power control */
1571 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1573 if (0/*FIXME HWPCTL capable */) {
1574 lpphy_tx_pctl_init_hw(dev);
1575 } else { /* This device is only software TX power control capable. */
1576 lpphy_tx_pctl_init_sw(dev);
1580 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1582 struct b43_phy_lp *lpphy = dev->phy.lp;
1584 const unsigned int saved_tab_size = 256;
1585 enum b43_lpphy_txpctl_mode txpctl_mode;
1587 u16 tssi_npt, tssi_idx;
1589 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1591 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1595 lpphy_read_tx_pctl_mode_from_hardware(dev);
1596 txpctl_mode = lpphy->txpctl_mode;
1597 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1598 tssi_npt = lpphy->tssi_npt;
1599 tssi_idx = lpphy->tssi_idx;
1601 if (dev->phy.rev < 2) {
1602 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1603 saved_tab_size, saved_tab);
1605 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1606 saved_tab_size, saved_tab);
1609 lpphy_table_init(dev); //FIXME is table init needed?
1610 lpphy_baseband_init(dev);
1611 lpphy_tx_pctl_init(dev);
1612 b43_lpphy_op_software_rfkill(dev, false);
1613 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1614 if (dev->phy.rev < 2) {
1615 b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140),
1616 saved_tab_size, saved_tab);
1618 b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140),
1619 saved_tab_size, saved_tab);
1621 b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel);
1622 lpphy->tssi_npt = tssi_npt;
1623 lpphy->tssi_idx = tssi_idx;
1624 lpphy_set_analog_filter(dev, lpphy->channel);
1625 if (tx_pwr_idx_over != -1)
1626 lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over);
1628 lpphy_set_rc_cap(dev);
1629 b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna);
1630 lpphy_set_tx_power_control(dev, txpctl_mode);
1634 struct lpphy_rx_iq_comp { u8 chan; s8 c1, c0; };
1636 static const struct lpphy_rx_iq_comp lpphy_5354_iq_table[] = {
1637 { .chan = 1, .c1 = -66, .c0 = 15, },
1638 { .chan = 2, .c1 = -66, .c0 = 15, },
1639 { .chan = 3, .c1 = -66, .c0 = 15, },
1640 { .chan = 4, .c1 = -66, .c0 = 15, },
1641 { .chan = 5, .c1 = -66, .c0 = 15, },
1642 { .chan = 6, .c1 = -66, .c0 = 15, },
1643 { .chan = 7, .c1 = -66, .c0 = 14, },
1644 { .chan = 8, .c1 = -66, .c0 = 14, },
1645 { .chan = 9, .c1 = -66, .c0 = 14, },
1646 { .chan = 10, .c1 = -66, .c0 = 14, },
1647 { .chan = 11, .c1 = -66, .c0 = 14, },
1648 { .chan = 12, .c1 = -66, .c0 = 13, },
1649 { .chan = 13, .c1 = -66, .c0 = 13, },
1650 { .chan = 14, .c1 = -66, .c0 = 13, },
1653 static const struct lpphy_rx_iq_comp lpphy_rev0_1_iq_table[] = {
1654 { .chan = 1, .c1 = -64, .c0 = 13, },
1655 { .chan = 2, .c1 = -64, .c0 = 13, },
1656 { .chan = 3, .c1 = -64, .c0 = 13, },
1657 { .chan = 4, .c1 = -64, .c0 = 13, },
1658 { .chan = 5, .c1 = -64, .c0 = 12, },
1659 { .chan = 6, .c1 = -64, .c0 = 12, },
1660 { .chan = 7, .c1 = -64, .c0 = 12, },
1661 { .chan = 8, .c1 = -64, .c0 = 12, },
1662 { .chan = 9, .c1 = -64, .c0 = 12, },
1663 { .chan = 10, .c1 = -64, .c0 = 11, },
1664 { .chan = 11, .c1 = -64, .c0 = 11, },
1665 { .chan = 12, .c1 = -64, .c0 = 11, },
1666 { .chan = 13, .c1 = -64, .c0 = 11, },
1667 { .chan = 14, .c1 = -64, .c0 = 10, },
1668 { .chan = 34, .c1 = -62, .c0 = 24, },
1669 { .chan = 38, .c1 = -62, .c0 = 24, },
1670 { .chan = 42, .c1 = -62, .c0 = 24, },
1671 { .chan = 46, .c1 = -62, .c0 = 23, },
1672 { .chan = 36, .c1 = -62, .c0 = 24, },
1673 { .chan = 40, .c1 = -62, .c0 = 24, },
1674 { .chan = 44, .c1 = -62, .c0 = 23, },
1675 { .chan = 48, .c1 = -62, .c0 = 23, },
1676 { .chan = 52, .c1 = -62, .c0 = 23, },
1677 { .chan = 56, .c1 = -62, .c0 = 22, },
1678 { .chan = 60, .c1 = -62, .c0 = 22, },
1679 { .chan = 64, .c1 = -62, .c0 = 22, },
1680 { .chan = 100, .c1 = -62, .c0 = 16, },
1681 { .chan = 104, .c1 = -62, .c0 = 16, },
1682 { .chan = 108, .c1 = -62, .c0 = 15, },
1683 { .chan = 112, .c1 = -62, .c0 = 14, },
1684 { .chan = 116, .c1 = -62, .c0 = 14, },
1685 { .chan = 120, .c1 = -62, .c0 = 13, },
1686 { .chan = 124, .c1 = -62, .c0 = 12, },
1687 { .chan = 128, .c1 = -62, .c0 = 12, },
1688 { .chan = 132, .c1 = -62, .c0 = 12, },
1689 { .chan = 136, .c1 = -62, .c0 = 11, },
1690 { .chan = 140, .c1 = -62, .c0 = 10, },
1691 { .chan = 149, .c1 = -61, .c0 = 9, },
1692 { .chan = 153, .c1 = -61, .c0 = 9, },
1693 { .chan = 157, .c1 = -61, .c0 = 9, },
1694 { .chan = 161, .c1 = -61, .c0 = 8, },
1695 { .chan = 165, .c1 = -61, .c0 = 8, },
1696 { .chan = 184, .c1 = -62, .c0 = 25, },
1697 { .chan = 188, .c1 = -62, .c0 = 25, },
1698 { .chan = 192, .c1 = -62, .c0 = 25, },
1699 { .chan = 196, .c1 = -62, .c0 = 25, },
1700 { .chan = 200, .c1 = -62, .c0 = 25, },
1701 { .chan = 204, .c1 = -62, .c0 = 25, },
1702 { .chan = 208, .c1 = -62, .c0 = 25, },
1703 { .chan = 212, .c1 = -62, .c0 = 25, },
1704 { .chan = 216, .c1 = -62, .c0 = 26, },
1707 static const struct lpphy_rx_iq_comp lpphy_rev2plus_iq_comp = {
1713 static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples)
1715 struct lpphy_iq_est iq_est;
1717 int prod, ipwr, qpwr, prod_msb, q_msb, tmp1, tmp2, tmp3, tmp4, ret;
1719 c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S);
1723 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0);
1724 b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF);
1726 ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est);
1730 prod = iq_est.iq_prod;
1731 ipwr = iq_est.i_pwr;
1732 qpwr = iq_est.q_pwr;
1734 if (ipwr + qpwr < 2) {
1739 prod_msb = fls(abs(prod));
1740 q_msb = fls(abs(qpwr));
1741 tmp1 = prod_msb - 20;
1744 tmp3 = ((prod << (30 - prod_msb)) + (ipwr >> (1 + tmp1))) /
1747 tmp3 = ((prod << (30 - prod_msb)) + (ipwr << (-1 - tmp1))) /
1754 tmp4 = (qpwr << (31 - q_msb)) / (ipwr >> tmp2);
1756 tmp4 = (qpwr << (31 - q_msb)) / (ipwr << -tmp2);
1758 tmp4 -= tmp3 * tmp3;
1759 tmp4 = -int_sqrt(tmp4);
1765 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1);
1766 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8);
1770 static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops,
1773 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL,
1774 0xFFC0, samples - 1);
1775 if (loops != 0xFFFF)
1777 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops);
1778 b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6);
1779 b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1);
1782 //SPEC FIXME what does a negative freq mean?
1783 static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max)
1785 struct b43_phy_lp *lpphy = dev->phy.lp;
1787 int i, samples = 0, angle = 0;
1788 int rotation = (((36 * freq) / 20) << 16) / 100;
1789 struct b43_c32 sample;
1791 lpphy->tx_tone_freq = freq;
1794 /* Find i for which abs(freq) integrally divides 20000 * i */
1795 for (i = 1; samples * abs(freq) != 20000 * i; i++) {
1796 samples = (20000 * i) / abs(freq);
1797 if(B43_WARN_ON(samples > 63))
1804 for (i = 0; i < samples; i++) {
1805 sample = b43_cordic(angle);
1807 buf[i] = CORDIC_CONVERT((sample.i * max) & 0xFF) << 8;
1808 buf[i] |= CORDIC_CONVERT((sample.q * max) & 0xFF);
1811 b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf);
1813 lpphy_run_samples(dev, samples, 0xFFFF, 0);
1816 static void lpphy_stop_tx_tone(struct b43_wldev *dev)
1818 struct b43_phy_lp *lpphy = dev->phy.lp;
1821 lpphy->tx_tone_freq = 0;
1823 b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000);
1824 for (i = 0; i < 31; i++) {
1825 if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1))
1832 static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains,
1833 int mode, bool useindex, u8 index)
1838 static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
1840 struct b43_phy_lp *lpphy = dev->phy.lp;
1841 struct ssb_bus *bus = dev->dev->bus;
1842 struct lpphy_tx_gains gains, oldgains;
1843 int old_txpctl, old_afe_ovr, old_rf, old_bbmult;
1845 lpphy_read_tx_pctl_mode_from_hardware(dev);
1846 old_txpctl = lpphy->txpctl_mode;
1847 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
1849 oldgains = lpphy_get_tx_gains(dev);
1850 old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF;
1851 old_bbmult = lpphy_get_bb_mult(dev);
1853 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1855 if (bus->chip_id == 0x4325 && bus->chip_rev == 0)
1856 lpphy_papd_cal(dev, gains, 0, 1, 30);
1858 lpphy_papd_cal(dev, gains, 0, 1, 65);
1861 lpphy_set_tx_gains(dev, oldgains);
1862 lpphy_set_bb_mult(dev, old_bbmult);
1863 lpphy_set_tx_power_control(dev, old_txpctl);
1864 b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf);
1867 static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
1868 bool rx, bool pa, struct lpphy_tx_gains *gains)
1870 struct b43_phy_lp *lpphy = dev->phy.lp;
1871 struct ssb_bus *bus = dev->dev->bus;
1872 const struct lpphy_rx_iq_comp *iqcomp = NULL;
1873 struct lpphy_tx_gains nogains, oldgains;
1877 memset(&nogains, 0, sizeof(nogains));
1878 memset(&oldgains, 0, sizeof(oldgains));
1880 if (bus->chip_id == 0x5354) {
1881 for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) {
1882 if (lpphy_5354_iq_table[i].chan == lpphy->channel) {
1883 iqcomp = &lpphy_5354_iq_table[i];
1886 } else if (dev->phy.rev >= 2) {
1887 iqcomp = &lpphy_rev2plus_iq_comp;
1889 for (i = 0; i < ARRAY_SIZE(lpphy_rev0_1_iq_table); i++) {
1890 if (lpphy_rev0_1_iq_table[i].chan == lpphy->channel) {
1891 iqcomp = &lpphy_rev0_1_iq_table[i];
1896 if (B43_WARN_ON(!iqcomp))
1899 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1);
1900 b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S,
1901 0x00FF, iqcomp->c0 << 8);
1909 lpphy_set_trsw_over(dev, tx, rx);
1911 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1912 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1913 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
1916 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
1917 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
1921 tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
1924 lpphy_set_rx_gain(dev, 0x2D5D);
1927 oldgains = lpphy_get_tx_gains(dev);
1930 lpphy_set_tx_gains(dev, *gains);
1933 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
1934 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1935 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1936 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1937 lpphy_set_deaf(dev, false);
1939 ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0);
1941 lpphy_start_tx_tone(dev, 4000, 100);
1942 ret = lpphy_calc_rx_iq_comp(dev, 0x4000);
1943 lpphy_stop_tx_tone(dev);
1945 lpphy_clear_deaf(dev, false);
1946 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC);
1947 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
1948 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF);
1951 lpphy_set_tx_gains(dev, oldgains);
1953 lpphy_disable_tx_gain_override(dev);
1955 lpphy_disable_rx_gain_override(dev);
1956 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
1957 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF);
1961 static void lpphy_calibration(struct b43_wldev *dev)
1963 struct b43_phy_lp *lpphy = dev->phy.lp;
1964 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1965 bool full_cal = false;
1967 if (lpphy->full_calib_chan != lpphy->channel) {
1969 lpphy->full_calib_chan = lpphy->channel;
1972 b43_mac_suspend(dev);
1974 lpphy_btcoex_override(dev);
1975 if (dev->phy.rev >= 2)
1976 lpphy_save_dig_flt_state(dev);
1977 lpphy_read_tx_pctl_mode_from_hardware(dev);
1978 saved_pctl_mode = lpphy->txpctl_mode;
1979 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1980 //TODO Perform transmit power table I/Q LO calibration
1981 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1982 lpphy_pr41573_workaround(dev);
1983 if ((dev->phy.rev >= 2) && full_cal) {
1984 lpphy_papd_cal_txpwr(dev);
1986 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1987 if (dev->phy.rev >= 2)
1988 lpphy_restore_dig_flt_state(dev);
1989 lpphy_rx_iq_cal(dev, true, true, false, false, NULL);
1991 b43_mac_enable(dev);
1994 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1996 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1997 return b43_read16(dev, B43_MMIO_PHY_DATA);
2000 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2002 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2003 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2006 static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
2009 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2010 b43_write16(dev, B43_MMIO_PHY_DATA,
2011 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
2014 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2016 /* Register 1 is a 32-bit register. */
2017 B43_WARN_ON(reg == 1);
2018 /* LP-PHY needs a special bit set for read access */
2019 if (dev->phy.rev < 2) {
2025 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2026 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2029 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2031 /* Register 1 is a 32-bit register. */
2032 B43_WARN_ON(reg == 1);
2034 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2035 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2038 struct b206x_channel {
2044 static const struct b206x_channel b2062_chantbl[] = {
2045 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
2046 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2047 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2048 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
2049 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2050 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2051 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
2052 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2053 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2054 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
2055 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2056 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2057 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
2058 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2059 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2060 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
2061 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2062 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2063 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
2064 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2065 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2066 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
2067 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2068 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2069 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
2070 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2071 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2072 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
2073 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2074 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2075 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
2076 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2077 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2078 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
2079 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2080 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2081 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
2082 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2083 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2084 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
2085 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
2086 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
2087 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
2088 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
2089 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2090 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
2091 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2092 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2093 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
2094 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2095 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2096 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
2097 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2098 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2099 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
2100 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2101 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2102 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
2103 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
2104 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2105 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
2106 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2107 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2108 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
2109 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2110 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2111 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
2112 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2113 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2114 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
2115 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
2116 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2117 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
2118 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
2119 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2120 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
2121 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
2122 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2123 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
2124 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
2125 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2126 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
2127 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
2128 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2129 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
2130 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
2131 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2132 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
2133 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
2134 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2135 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
2136 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
2137 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2138 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
2139 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2140 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2141 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
2142 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2143 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2144 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
2145 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2146 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2147 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
2148 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2149 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2150 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
2151 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2152 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2153 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
2154 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2155 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2156 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
2157 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2158 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2159 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
2160 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2161 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2162 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
2163 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2164 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2165 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
2166 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2167 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2168 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
2169 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
2170 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
2171 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
2172 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
2173 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2174 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
2175 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
2176 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2177 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
2178 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
2179 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2180 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
2181 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
2182 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2183 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
2184 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
2185 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2186 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
2187 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
2188 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2189 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
2190 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
2191 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
2192 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
2193 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
2194 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2195 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
2196 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
2197 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
2200 static const struct b206x_channel b2063_chantbl[] = {
2201 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
2202 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2203 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2204 .data[10] = 0x80, .data[11] = 0x70, },
2205 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
2206 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2207 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2208 .data[10] = 0x80, .data[11] = 0x70, },
2209 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
2210 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2211 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2212 .data[10] = 0x80, .data[11] = 0x70, },
2213 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
2214 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2215 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2216 .data[10] = 0x80, .data[11] = 0x70, },
2217 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
2218 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2219 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2220 .data[10] = 0x80, .data[11] = 0x70, },
2221 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
2222 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2223 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2224 .data[10] = 0x80, .data[11] = 0x70, },
2225 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
2226 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2227 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2228 .data[10] = 0x80, .data[11] = 0x70, },
2229 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
2230 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2231 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2232 .data[10] = 0x80, .data[11] = 0x70, },
2233 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
2234 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2235 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2236 .data[10] = 0x80, .data[11] = 0x70, },
2237 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
2238 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2239 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2240 .data[10] = 0x80, .data[11] = 0x70, },
2241 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
2242 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2243 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2244 .data[10] = 0x80, .data[11] = 0x70, },
2245 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
2246 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2247 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2248 .data[10] = 0x80, .data[11] = 0x70, },
2249 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
2250 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2251 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2252 .data[10] = 0x80, .data[11] = 0x70, },
2253 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
2254 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
2255 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
2256 .data[10] = 0x80, .data[11] = 0x70, },
2257 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
2258 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
2259 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
2260 .data[10] = 0x20, .data[11] = 0x00, },
2261 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
2262 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
2263 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
2264 .data[10] = 0x20, .data[11] = 0x00, },
2265 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
2266 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
2267 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
2268 .data[10] = 0x20, .data[11] = 0x00, },
2269 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
2270 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
2271 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
2272 .data[10] = 0x20, .data[11] = 0x00, },
2273 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
2274 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
2275 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
2276 .data[10] = 0x20, .data[11] = 0x00, },
2277 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
2278 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
2279 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
2280 .data[10] = 0x20, .data[11] = 0x00, },
2281 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
2282 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
2283 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
2284 .data[10] = 0x20, .data[11] = 0x00, },
2285 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
2286 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
2287 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
2288 .data[10] = 0x20, .data[11] = 0x00, },
2289 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
2290 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
2291 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
2292 .data[10] = 0x20, .data[11] = 0x00, },
2293 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
2294 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
2295 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
2296 .data[10] = 0x10, .data[11] = 0x00, },
2297 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
2298 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
2299 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
2300 .data[10] = 0x10, .data[11] = 0x00, },
2301 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
2302 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2303 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
2304 .data[10] = 0x10, .data[11] = 0x00, },
2305 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
2306 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2307 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
2308 .data[10] = 0x00, .data[11] = 0x00, },
2309 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
2310 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2311 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
2312 .data[10] = 0x00, .data[11] = 0x00, },
2313 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
2314 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2315 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
2316 .data[10] = 0x00, .data[11] = 0x00, },
2317 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
2318 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2319 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
2320 .data[10] = 0x00, .data[11] = 0x00, },
2321 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
2322 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2323 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
2324 .data[10] = 0x00, .data[11] = 0x00, },
2325 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
2326 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2327 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2328 .data[10] = 0x00, .data[11] = 0x00, },
2329 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
2330 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2331 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2332 .data[10] = 0x00, .data[11] = 0x00, },
2333 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
2334 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2335 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2336 .data[10] = 0x00, .data[11] = 0x00, },
2337 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
2338 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2339 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2340 .data[10] = 0x00, .data[11] = 0x00, },
2341 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
2342 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2343 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2344 .data[10] = 0x00, .data[11] = 0x00, },
2345 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
2346 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2347 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2348 .data[10] = 0x00, .data[11] = 0x00, },
2349 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
2350 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2351 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2352 .data[10] = 0x00, .data[11] = 0x00, },
2353 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
2354 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2355 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2356 .data[10] = 0x00, .data[11] = 0x00, },
2357 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
2358 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2359 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2360 .data[10] = 0x00, .data[11] = 0x00, },
2361 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
2362 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2363 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2364 .data[10] = 0x00, .data[11] = 0x00, },
2365 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
2366 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
2367 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
2368 .data[10] = 0x00, .data[11] = 0x00, },
2369 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
2370 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
2371 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
2372 .data[10] = 0x50, .data[11] = 0x00, },
2373 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
2374 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
2375 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
2376 .data[10] = 0x50, .data[11] = 0x00, },
2377 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
2378 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
2379 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
2380 .data[10] = 0x50, .data[11] = 0x00, },
2381 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
2382 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
2383 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
2384 .data[10] = 0x40, .data[11] = 0x00, },
2385 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
2386 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
2387 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
2388 .data[10] = 0x40, .data[11] = 0x00, },
2389 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
2390 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
2391 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
2392 .data[10] = 0x40, .data[11] = 0x00, },
2393 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
2394 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
2395 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
2396 .data[10] = 0x40, .data[11] = 0x00, },
2397 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
2398 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
2399 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
2400 .data[10] = 0x40, .data[11] = 0x00, },
2401 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
2402 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
2403 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
2404 .data[10] = 0x40, .data[11] = 0x00, },
2407 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
2409 struct ssb_bus *bus = dev->dev->bus;
2411 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
2413 if (bus->chip_id == 0x5354) {
2414 b43_radio_write(dev, B2062_N_COMM1, 4);
2415 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
2417 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
2422 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
2424 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42);
2425 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62);
2429 static int lpphy_b2062_tune(struct b43_wldev *dev,
2430 unsigned int channel)
2432 struct b43_phy_lp *lpphy = dev->phy.lp;
2433 struct ssb_bus *bus = dev->dev->bus;
2434 const struct b206x_channel *chandata = NULL;
2435 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2436 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
2439 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
2440 if (b2062_chantbl[i].channel == channel) {
2441 chandata = &b2062_chantbl[i];
2446 if (B43_WARN_ON(!chandata))
2449 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
2450 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
2451 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
2452 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
2453 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
2454 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
2455 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
2456 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
2457 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
2458 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
2460 tmp1 = crystal_freq / 1000;
2461 tmp2 = lpphy->pdiv * 1000;
2462 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
2463 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
2464 lpphy_b2062_reset_pll_bias(dev);
2465 tmp3 = tmp2 * channel2freq_lp(channel);
2466 if (channel2freq_lp(channel) < 4000)
2471 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
2472 tmp5 = tmp7 * 0x100;
2475 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
2476 tmp5 = tmp7 * 0x100;
2479 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
2480 tmp5 = tmp7 * 0x100;
2483 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
2484 tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19);
2485 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
2486 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
2487 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
2489 lpphy_b2062_vco_calib(dev);
2490 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
2491 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
2492 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
2493 lpphy_b2062_reset_pll_bias(dev);
2494 lpphy_b2062_vco_calib(dev);
2495 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
2499 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
2503 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2507 b43_radio_mask(dev, B2063_PLL_SP1, ~0x40);
2508 tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
2509 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
2511 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
2513 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2515 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2517 b43_radio_set(dev, B2063_PLL_SP1, 0x40);
2520 static int lpphy_b2063_tune(struct b43_wldev *dev,
2521 unsigned int channel)
2523 struct ssb_bus *bus = dev->dev->bus;
2525 static const struct b206x_channel *chandata = NULL;
2526 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2527 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2528 u16 old_comm15, scale;
2529 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2530 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2532 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2533 if (b2063_chantbl[i].channel == channel) {
2534 chandata = &b2063_chantbl[i];
2539 if (B43_WARN_ON(!chandata))
2542 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2543 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2544 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2545 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2546 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2547 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2548 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2549 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2550 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2551 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2552 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2553 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2555 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2556 b43_radio_set(dev, B2063_COMM15, 0x1E);
2558 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2559 vco_freq = chandata->freq << 1;
2561 vco_freq = chandata->freq << 2;
2563 freqref = crystal_freq * 3;
2564 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2565 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2566 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2567 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2568 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2569 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2570 0xFFF8, timeout >> 2);
2571 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2572 0xFF9F,timeout << 5);
2574 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2575 999999) / 1000000) + 1;
2576 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2578 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2579 count *= (timeout + 1) * (timeoutref + 1);
2581 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2583 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2585 tmp1 = ((val3 * 62500) / freqref) << 4;
2586 tmp2 = ((val3 * 62500) % freqref) << 4;
2587 while (tmp2 >= freqref) {
2591 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2592 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2593 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2594 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2595 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2597 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2598 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2599 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2600 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2602 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2603 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2605 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2607 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2610 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2612 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2613 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2615 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2616 tmp6 *= (tmp5 * 8) * (scale + 1);
2620 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2621 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2623 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2624 if (crystal_freq > 26000000)
2625 b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2627 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2630 b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2632 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2634 b43_radio_set(dev, B2063_PLL_SP2, 0x3);
2636 b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC);
2637 lpphy_b2063_vco_calib(dev);
2638 b43_radio_write(dev, B2063_COMM15, old_comm15);
2643 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2644 unsigned int new_channel)
2646 struct b43_phy_lp *lpphy = dev->phy.lp;
2649 if (dev->phy.radio_ver == 0x2063) {
2650 err = lpphy_b2063_tune(dev, new_channel);
2654 err = lpphy_b2062_tune(dev, new_channel);
2657 lpphy_set_analog_filter(dev, new_channel);
2658 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
2661 lpphy->channel = new_channel;
2662 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2667 static int b43_lpphy_op_init(struct b43_wldev *dev)
2671 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2672 lpphy_baseband_init(dev);
2673 lpphy_radio_init(dev);
2674 lpphy_calibrate_rc(dev);
2675 err = b43_lpphy_op_switch_channel(dev, 7);
2677 b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n",
2680 lpphy_tx_pctl_init(dev);
2681 lpphy_calibration(dev);
2687 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2692 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2696 return B43_TXPWR_RES_DONE;
2699 void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
2702 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8);
2704 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0x0007);
2705 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x0007);
2709 static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev)
2714 const struct b43_phy_operations b43_phyops_lp = {
2715 .allocate = b43_lpphy_op_allocate,
2716 .free = b43_lpphy_op_free,
2717 .prepare_structs = b43_lpphy_op_prepare_structs,
2718 .init = b43_lpphy_op_init,
2719 .phy_read = b43_lpphy_op_read,
2720 .phy_write = b43_lpphy_op_write,
2721 .phy_maskset = b43_lpphy_op_maskset,
2722 .radio_read = b43_lpphy_op_radio_read,
2723 .radio_write = b43_lpphy_op_radio_write,
2724 .software_rfkill = b43_lpphy_op_software_rfkill,
2725 .switch_analog = b43_lpphy_op_switch_analog,
2726 .switch_channel = b43_lpphy_op_switch_channel,
2727 .get_default_chan = b43_lpphy_op_get_default_chan,
2728 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2729 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2730 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2731 .pwork_15sec = b43_lpphy_op_pwork_15sec,
2732 .pwork_60sec = lpphy_calibration,