drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "radio_2057.h"
  36 #include "main.h"
  37
  38 struct nphy_txgains {
  39         u16 txgm[2];
  40         u16 pga[2];
  41         u16 pad[2];
  42         u16 ipa[2];
  43 };
  44
  45 struct nphy_iqcal_params {
  46         u16 txgm;
  47         u16 pga;
  48         u16 pad;
  49         u16 ipa;
  50         u16 cal_gain;
  51         u16 ncorr[5];
  52 };
  53
  54 struct nphy_iq_est {
  55         s32 iq0_prod;
  56         u32 i0_pwr;
  57         u32 q0_pwr;
  58         s32 iq1_prod;
  59         u32 i1_pwr;
  60         u32 q1_pwr;
  61 };
  62
  63 enum b43_nphy_rf_sequence {
  64         B43_RFSEQ_RX2TX,
  65         B43_RFSEQ_TX2RX,
  66         B43_RFSEQ_RESET2RX,
  67         B43_RFSEQ_UPDATE_GAINH,
  68         B43_RFSEQ_UPDATE_GAINL,
  69         B43_RFSEQ_UPDATE_GAINU,
  70 };
  71
  72 enum n_intc_override {
  73         N_INTC_OVERRIDE_OFF = 0,
  74         N_INTC_OVERRIDE_TRSW = 1,
  75         N_INTC_OVERRIDE_PA = 2,
  76         N_INTC_OVERRIDE_EXT_LNA_PU = 3,
  77         N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
  78 };
  79
  80 enum n_rssi_type {
  81         N_RSSI_W1 = 0,
  82         N_RSSI_W2,
  83         N_RSSI_NB,
  84         N_RSSI_IQ,
  85         N_RSSI_TSSI_2G,
  86         N_RSSI_TSSI_5G,
  87         N_RSSI_TBD,
  88 };
  89
  90 enum n_rail_type {
  91         N_RAIL_I = 0,
  92         N_RAIL_Q = 1,
  93 };
  94
  95 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  96 {
  97         enum ieee80211_band band = b43_current_band(dev->wl);
  98         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  99                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
 100 }
 101
 102 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
 103 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
 104 {
 105         return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
 106                 B43_NPHY_RFSEQCA_RXEN_SHIFT;
 107 }
 108
 109 /**************************************************
 110  * RF (just without b43_nphy_rf_ctl_intc_override)
 111  **************************************************/
 112
 113 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
 114 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 115                                        enum b43_nphy_rf_sequence seq)
 116 {
 117         static const u16 trigger[] = {
 118                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 119                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 120                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 121                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 122                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 123                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 124         };
 125         int i;
 126         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
 127
 128         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 129
 130         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 131                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 132         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 133         for (i = 0; i < 200; i++) {
 134                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 135                         goto ok;
 136                 msleep(1);
 137         }
 138         b43err(dev->wl, "RF sequence status timeout\n");
 139 ok:
 140         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
 141 }
 142
 143 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
 144 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
 145                                           u16 value, u8 core, bool off,
 146                                           u8 override)
 147 {
 148         const struct nphy_rf_control_override_rev7 *e;
 149         u16 en_addrs[3][2] = {
 150                 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
 151         };
 152         u16 en_addr;
 153         u16 en_mask = field;
 154         u16 val_addr;
 155         u8 i;
 156
 157         /* Remember: we can get NULL! */
 158         e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
 159
 160         for (i = 0; i < 2; i++) {
 161                 if (override >= ARRAY_SIZE(en_addrs)) {
 162                         b43err(dev->wl, "Invalid override value %d\n", override);
 163                         return;
 164                 }
 165                 en_addr = en_addrs[override][i];
 166
 167                 if (e)
 168                         val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
 169
 170                 if (off) {
 171                         b43_phy_mask(dev, en_addr, ~en_mask);
 172                         if (e) /* Do it safer, better than wl */
 173                                 b43_phy_mask(dev, val_addr, ~e->val_mask);
 174                 } else {
 175                         if (!core || (core & (1 << i))) {
 176                                 b43_phy_set(dev, en_addr, en_mask);
 177                                 if (e)
 178                                         b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
 179                         }
 180                 }
 181         }
 182 }
 183
 184 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
 185 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
 186                                      u16 value, u8 core, bool off)
 187 {
 188         int i;
 189         u8 index = fls(field);
 190         u8 addr, en_addr, val_addr;
 191         /* we expect only one bit set */
 192         B43_WARN_ON(field & (~(1 << (index - 1))));
 193
 194         if (dev->phy.rev >= 3) {
 195                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
 196                 for (i = 0; i < 2; i++) {
 197                         if (index == 0 || index == 16) {
 198                                 b43err(dev->wl,
 199                                         "Unsupported RF Ctrl Override call\n");
 200                                 return;
 201                         }
 202
 203                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
 204                         en_addr = B43_PHY_N((i == 0) ?
 205                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
 206                         val_addr = B43_PHY_N((i == 0) ?
 207                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
 208
 209                         if (off) {
 210                                 b43_phy_mask(dev, en_addr, ~(field));
 211                                 b43_phy_mask(dev, val_addr,
 212                                                 ~(rf_ctrl->val_mask));
 213                         } else {
 214                                 if (core == 0 || ((1 << i) & core)) {
 215                                         b43_phy_set(dev, en_addr, field);
 216                                         b43_phy_maskset(dev, val_addr,
 217                                                 ~(rf_ctrl->val_mask),
 218                                                 (value << rf_ctrl->val_shift));
 219                                 }
 220                         }
 221                 }
 222         } else {
 223                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
 224                 if (off) {
 225                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
 226                         value = 0;
 227                 } else {
 228                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
 229                 }
 230
 231                 for (i = 0; i < 2; i++) {
 232                         if (index <= 1 || index == 16) {
 233                                 b43err(dev->wl,
 234                                         "Unsupported RF Ctrl Override call\n");
 235                                 return;
 236                         }
 237
 238                         if (index == 2 || index == 10 ||
 239                             (index >= 13 && index <= 15)) {
 240                                 core = 1;
 241                         }
 242
 243                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
 244                         addr = B43_PHY_N((i == 0) ?
 245                                 rf_ctrl->addr0 : rf_ctrl->addr1);
 246
 247                         if ((1 << i) & core)
 248                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
 249                                                 (value << rf_ctrl->shift));
 250
 251                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
 252                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 253                                         B43_NPHY_RFCTL_CMD_START);
 254                         udelay(1);
 255                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
 256                 }
 257         }
 258 }
 259
 260 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
 261                                                enum n_intc_override intc_override,
 262                                                u16 value, u8 core_sel)
 263 {
 264         u16 reg, tmp, tmp2, val;
 265         int core;
 266
 267         for (core = 0; core < 2; core++) {
 268                 if ((core_sel == 1 && core != 0) ||
 269                     (core_sel == 2 && core != 1))
 270                         continue;
 271
 272                 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 273
 274                 switch (intc_override) {
 275                 case N_INTC_OVERRIDE_OFF:
 276                         b43_phy_write(dev, reg, 0);
 277                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 278                         break;
 279                 case N_INTC_OVERRIDE_TRSW:
 280                         b43_phy_maskset(dev, reg, ~0xC0, value << 6);
 281                         b43_phy_set(dev, reg, 0x400);
 282
 283                         b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
 284                         b43_phy_set(dev, 0x2ff, 0x2000);
 285                         b43_phy_set(dev, 0x2ff, 0x0001);
 286                         break;
 287                 case N_INTC_OVERRIDE_PA:
 288                         tmp = 0x0030;
 289                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 290                                 val = value << 5;
 291                         else
 292                                 val = value << 4;
 293                         b43_phy_maskset(dev, reg, ~tmp, val);
 294                         b43_phy_set(dev, reg, 0x1000);
 295                         break;
 296                 case N_INTC_OVERRIDE_EXT_LNA_PU:
 297                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 298                                 tmp = 0x0001;
 299                                 tmp2 = 0x0004;
 300                                 val = value;
 301                         } else {
 302                                 tmp = 0x0004;
 303                                 tmp2 = 0x0001;
 304                                 val = value << 2;
 305                         }
 306                         b43_phy_maskset(dev, reg, ~tmp, val);
 307                         b43_phy_mask(dev, reg, ~tmp2);
 308                         break;
 309                 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
 310                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 311                                 tmp = 0x0002;
 312                                 tmp2 = 0x0008;
 313                                 val = value << 1;
 314                         } else {
 315                                 tmp = 0x0008;
 316                                 tmp2 = 0x0002;
 317                                 val = value << 3;
 318                         }
 319                         b43_phy_maskset(dev, reg, ~tmp, val);
 320                         b43_phy_mask(dev, reg, ~tmp2);
 321                         break;
 322                 }
 323         }
 324 }
 325
 326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
 327 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
 328                                           enum n_intc_override intc_override,
 329                                           u16 value, u8 core)
 330 {
 331         u8 i, j;
 332         u16 reg, tmp, val;
 333
 334         if (dev->phy.rev >= 7) {
 335                 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
 336                                                    core);
 337                 return;
 338         }
 339
 340         B43_WARN_ON(dev->phy.rev < 3);
 341
 342         for (i = 0; i < 2; i++) {
 343                 if ((core == 1 && i == 1) || (core == 2 && !i))
 344                         continue;
 345
 346                 reg = (i == 0) ?
 347                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
 348                 b43_phy_set(dev, reg, 0x400);
 349
 350                 switch (intc_override) {
 351                 case N_INTC_OVERRIDE_OFF:
 352                         b43_phy_write(dev, reg, 0);
 353                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 354                         break;
 355                 case N_INTC_OVERRIDE_TRSW:
 356                         if (!i) {
 357                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
 358                                                 0xFC3F, (value << 6));
 359                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
 360                                                 0xFFFE, 1);
 361                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 362                                                 B43_NPHY_RFCTL_CMD_START);
 363                                 for (j = 0; j < 100; j++) {
 364                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
 365                                                 j = 0;
 366                                                 break;
 367                                         }
 368                                         udelay(10);
 369                                 }
 370                                 if (j)
 371                                         b43err(dev->wl,
 372                                                 "intc override timeout\n");
 373                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
 374                                                 0xFFFE);
 375                         } else {
 376                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
 377                                                 0xFC3F, (value << 6));
 378                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 379                                                 0xFFFE, 1);
 380                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 381                                                 B43_NPHY_RFCTL_CMD_RXTX);
 382                                 for (j = 0; j < 100; j++) {
 383                                         if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
 384                                                 j = 0;
 385                                                 break;
 386                                         }
 387                                         udelay(10);
 388                                 }
 389                                 if (j)
 390                                         b43err(dev->wl,
 391                                                 "intc override timeout\n");
 392                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
 393                                                 0xFFFE);
 394                         }
 395                         break;
 396                 case N_INTC_OVERRIDE_PA:
 397                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 398                                 tmp = 0x0020;
 399                                 val = value << 5;
 400                         } else {
 401                                 tmp = 0x0010;
 402                                 val = value << 4;
 403                         }
 404                         b43_phy_maskset(dev, reg, ~tmp, val);
 405                         break;
 406                 case N_INTC_OVERRIDE_EXT_LNA_PU:
 407                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 408                                 tmp = 0x0001;
 409                                 val = value;
 410                         } else {
 411                                 tmp = 0x0004;
 412                                 val = value << 2;
 413                         }
 414                         b43_phy_maskset(dev, reg, ~tmp, val);
 415                         break;
 416                 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
 417                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 418                                 tmp = 0x0002;
 419                                 val = value << 1;
 420                         } else {
 421                                 tmp = 0x0008;
 422                                 val = value << 3;
 423                         }
 424                         b43_phy_maskset(dev, reg, ~tmp, val);
 425                         break;
 426                 }
 427         }
 428 }
 429
 430 /**************************************************
 431  * Various PHY ops
 432  **************************************************/
 433
 434 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 435 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 436                                           const u16 *clip_st)
 437 {
 438         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 439         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 440 }
 441
 442 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 443 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 444 {
 445         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 446         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 447 }
 448
 449 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 450 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 451 {
 452         u16 tmp;
 453
 454         if (dev->dev->core_rev == 16)
 455                 b43_mac_suspend(dev);
 456
 457         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 458         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 459                 B43_NPHY_CLASSCTL_WAITEDEN);
 460         tmp &= ~mask;
 461         tmp |= (val & mask);
 462         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 463
 464         if (dev->dev->core_rev == 16)
 465                 b43_mac_enable(dev);
 466
 467         return tmp;
 468 }
 469
 470 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 471 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 472 {
 473         u16 bbcfg;
 474
 475         b43_phy_force_clock(dev, 1);
 476         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 477         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 478         udelay(1);
 479         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 480         b43_phy_force_clock(dev, 0);
 481         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 482 }
 483
 484 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 485 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 486 {
 487         struct b43_phy *phy = &dev->phy;
 488         struct b43_phy_n *nphy = phy->n;
 489
 490         if (enable) {
 491                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 492                 if (nphy->deaf_count++ == 0) {
 493                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 494                         b43_nphy_classifier(dev, 0x7,
 495                                             B43_NPHY_CLASSCTL_WAITEDEN);
 496                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 497                         b43_nphy_write_clip_detection(dev, clip);
 498                 }
 499                 b43_nphy_reset_cca(dev);
 500         } else {
 501                 if (--nphy->deaf_count == 0) {
 502                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 503                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 504                 }
 505         }
 506 }
 507
 508 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 509 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 510 {
 511         struct b43_phy_n *nphy = dev->phy.n;
 512
 513         u8 i;
 514         s16 tmp;
 515         u16 data[4];
 516         s16 gain[2];
 517         u16 minmax[2];
 518         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 519
 520         if (nphy->hang_avoid)
 521                 b43_nphy_stay_in_carrier_search(dev, 1);
 522
 523         if (nphy->gain_boost) {
 524                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 525                         gain[0] = 6;
 526                         gain[1] = 6;
 527                 } else {
 528                         tmp = 40370 - 315 * dev->phy.channel;
 529                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 530                         tmp = 23242 - 224 * dev->phy.channel;
 531                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 532                 }
 533         } else {
 534                 gain[0] = 0;
 535                 gain[1] = 0;
 536         }
 537
 538         for (i = 0; i < 2; i++) {
 539                 if (nphy->elna_gain_config) {
 540                         data[0] = 19 + gain[i];
 541                         data[1] = 25 + gain[i];
 542                         data[2] = 25 + gain[i];
 543                         data[3] = 25 + gain[i];
 544                 } else {
 545                         data[0] = lna_gain[0] + gain[i];
 546                         data[1] = lna_gain[1] + gain[i];
 547                         data[2] = lna_gain[2] + gain[i];
 548                         data[3] = lna_gain[3] + gain[i];
 549                 }
 550                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 551
 552                 minmax[i] = 23 + gain[i];
 553         }
 554
 555         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 556                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 557         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 558                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 559
 560         if (nphy->hang_avoid)
 561                 b43_nphy_stay_in_carrier_search(dev, 0);
 562 }
 563
 564 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
 565 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
 566                                         u8 *events, u8 *delays, u8 length)
 567 {
 568         struct b43_phy_n *nphy = dev->phy.n;
 569         u8 i;
 570         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
 571         u16 offset1 = cmd << 4;
 572         u16 offset2 = offset1 + 0x80;
 573
 574         if (nphy->hang_avoid)
 575                 b43_nphy_stay_in_carrier_search(dev, true);
 576
 577         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
 578         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
 579
 580         for (i = length; i < 16; i++) {
 581                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
 582                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
 583         }
 584
 585         if (nphy->hang_avoid)
 586                 b43_nphy_stay_in_carrier_search(dev, false);
 587 }
 588
 589 /**************************************************
 590  * Radio 0x2057
 591  **************************************************/
 592
 593 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
 594 static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
 595 {
 596         struct b43_phy *phy = &dev->phy;
 597         u16 tmp;
 598
 599         if (phy->radio_rev == 5) {
 600                 b43_phy_mask(dev, 0x342, ~0x2);
 601                 udelay(10);
 602                 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
 603                 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
 604         }
 605
 606         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
 607         udelay(10);
 608         b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
 609         if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
 610                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 611                 return 0;
 612         }
 613         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
 614         tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
 615         b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
 616
 617         if (phy->radio_rev == 5) {
 618                 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
 619                 b43_radio_mask(dev, 0x1ca, ~0x2);
 620         }
 621         if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
 622                 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
 623                 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
 624                                   tmp << 2);
 625         }
 626
 627         return tmp & 0x3e;
 628 }
 629
 630 /* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
 631 static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
 632 {
 633         struct b43_phy *phy = &dev->phy;
 634         bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
 635                         phy->radio_rev == 6);
 636         u16 tmp;
 637
 638         if (special) {
 639                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
 640                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
 641         } else {
 642                 b43_radio_write(dev, 0x1AE, 0x61);
 643                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
 644         }
 645         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 646         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 647         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 648                                   5000000))
 649                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 650         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 651         if (special) {
 652                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
 653                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 654         } else {
 655                 b43_radio_write(dev, 0x1AE, 0x69);
 656                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
 657         }
 658         b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 659         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 660         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 661                                   5000000))
 662                 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
 663         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 664         if (special) {
 665                 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
 666                 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
 667                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
 668         } else {
 669                 b43_radio_write(dev, 0x1AE, 0x73);
 670                 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
 671                 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
 672         }
 673         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
 674         if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
 675                                   5000000)) {
 676                 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
 677                 return 0;
 678         }
 679         tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
 680         b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
 681         return tmp;
 682 }
 683
 684 static void b43_radio_2057_init_pre(struct b43_wldev *dev)
 685 {
 686         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 687         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 688         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
 689         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 690         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
 691 }
 692
 693 static void b43_radio_2057_init_post(struct b43_wldev *dev)
 694 {
 695         b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
 696
 697         b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
 698         b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
 699         mdelay(2);
 700         b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
 701         b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
 702
 703         if (dev->phy.do_full_init) {
 704                 b43_radio_2057_rcal(dev);
 705                 b43_radio_2057_rccal(dev);
 706         }
 707         b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
 708 }
 709
 710 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
 711 static void b43_radio_2057_init(struct b43_wldev *dev)
 712 {
 713         b43_radio_2057_init_pre(dev);
 714         r2057_upload_inittabs(dev);
 715         b43_radio_2057_init_post(dev);
 716 }
 717
 718 /**************************************************
 719  * Radio 0x2056
 720  **************************************************/
 721
 722 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 723                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 724 {
 725         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 726         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 727         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 728         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 729         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 730         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 731                                         e->radio_syn_pll_loopfilter1);
 732         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 733                                         e->radio_syn_pll_loopfilter2);
 734         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 735                                         e->radio_syn_pll_loopfilter3);
 736         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 737                                         e->radio_syn_pll_loopfilter4);
 738         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 739                                         e->radio_syn_pll_loopfilter5);
 740         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 741                                         e->radio_syn_reserved_addr27);
 742         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 743                                         e->radio_syn_reserved_addr28);
 744         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 745                                         e->radio_syn_reserved_addr29);
 746         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 747                                         e->radio_syn_logen_vcobuf1);
 748         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 749         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 750         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 751
 752         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 753                                         e->radio_rx0_lnaa_tune);
 754         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 755                                         e->radio_rx0_lnag_tune);
 756
 757         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 758                                         e->radio_tx0_intpaa_boost_tune);
 759         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 760                                         e->radio_tx0_intpag_boost_tune);
 761         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 762                                         e->radio_tx0_pada_boost_tune);
 763         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 764                                         e->radio_tx0_padg_boost_tune);
 765         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 766                                         e->radio_tx0_pgaa_boost_tune);
 767         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 768                                         e->radio_tx0_pgag_boost_tune);
 769         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 770                                         e->radio_tx0_mixa_boost_tune);
 771         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 772                                         e->radio_tx0_mixg_boost_tune);
 773
 774         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 775                                         e->radio_rx1_lnaa_tune);
 776         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 777                                         e->radio_rx1_lnag_tune);
 778
 779         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 780                                         e->radio_tx1_intpaa_boost_tune);
 781         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 782                                         e->radio_tx1_intpag_boost_tune);
 783         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 784                                         e->radio_tx1_pada_boost_tune);
 785         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 786                                         e->radio_tx1_padg_boost_tune);
 787         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 788                                         e->radio_tx1_pgaa_boost_tune);
 789         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 790                                         e->radio_tx1_pgag_boost_tune);
 791         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 792                                         e->radio_tx1_mixa_boost_tune);
 793         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 794                                         e->radio_tx1_mixg_boost_tune);
 795 }
 796
 797 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 798 static void b43_radio_2056_setup(struct b43_wldev *dev,
 799                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 800 {
 801         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 802         enum ieee80211_band band = b43_current_band(dev->wl);
 803         u16 offset;
 804         u8 i;
 805         u16 bias, cbias;
 806         u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
 807         u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
 808         bool is_pkg_fab_smic;
 809
 810         B43_WARN_ON(dev->phy.rev < 3);
 811
 812         is_pkg_fab_smic =
 813                 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
 814                   dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
 815                   dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
 816                  dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
 817
 818         b43_chantab_radio_2056_upload(dev, e);
 819         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 820
 821         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 822             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 823                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 824                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 825                 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
 826                     dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
 827                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 828                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 829                 } else {
 830                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 831                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 832                 }
 833         }
 834         if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
 835             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 836                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
 837                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
 838                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
 839                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
 840         }
 841         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 842             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 843                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 844                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 845                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 846                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 847         }
 848
 849         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 850                 for (i = 0; i < 2; i++) {
 851                         offset = i ? B2056_TX1 : B2056_TX0;
 852                         if (dev->phy.rev >= 5) {
 853                                 b43_radio_write(dev,
 854                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 855
 856                                 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
 857                                     dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
 858                                         bias = 0x40;
 859                                         cbias = 0x45;
 860                                         pag_boost = 0x5;
 861                                         pgag_boost = 0x33;
 862                                         mixg_boost = 0x55;
 863                                 } else {
 864                                         bias = 0x25;
 865                                         cbias = 0x20;
 866                                         if (is_pkg_fab_smic) {
 867                                                 bias = 0x2a;
 868                                                 cbias = 0x38;
 869                                         }
 870                                         pag_boost = 0x4;
 871                                         pgag_boost = 0x03;
 872                                         mixg_boost = 0x65;
 873                                 }
 874                                 padg_boost = 0x77;
 875
 876                                 b43_radio_write(dev,
 877                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 878                                         bias);
 879                                 b43_radio_write(dev,
 880                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 881                                         bias);
 882                                 b43_radio_write(dev,
 883                                         offset | B2056_TX_INTPAG_CASCBIAS,
 884                                         cbias);
 885                                 b43_radio_write(dev,
 886                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 887                                         pag_boost);
 888                                 b43_radio_write(dev,
 889                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 890                                         pgag_boost);
 891                                 b43_radio_write(dev,
 892                                         offset | B2056_TX_PADG_BOOST_TUNE,
 893                                         padg_boost);
 894                                 b43_radio_write(dev,
 895                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 896                                         mixg_boost);
 897                         } else {
 898                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 899                                 b43_radio_write(dev,
 900                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 901                                         bias);
 902                                 b43_radio_write(dev,
 903                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 904                                         bias);
 905                                 b43_radio_write(dev,
 906                                         offset | B2056_TX_INTPAG_CASCBIAS,
 907                                         0x30);
 908                         }
 909                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 910                 }
 911         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 912                 u16 freq = dev->phy.channel_freq;
 913                 if (freq < 5100) {
 914                         paa_boost = 0xA;
 915                         pada_boost = 0x77;
 916                         pgaa_boost = 0xF;
 917                         mixa_boost = 0xF;
 918                 } else if (freq < 5340) {
 919                         paa_boost = 0x8;
 920                         pada_boost = 0x77;
 921                         pgaa_boost = 0xFB;
 922                         mixa_boost = 0xF;
 923                 } else if (freq < 5650) {
 924                         paa_boost = 0x0;
 925                         pada_boost = 0x77;
 926                         pgaa_boost = 0xB;
 927                         mixa_boost = 0xF;
 928                 } else {
 929                         paa_boost = 0x0;
 930                         pada_boost = 0x77;
 931                         if (freq != 5825)
 932                                 pgaa_boost = -(freq - 18) / 36 + 168;
 933                         else
 934                                 pgaa_boost = 6;
 935                         mixa_boost = 0xF;
 936                 }
 937
 938                 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
 939
 940                 for (i = 0; i < 2; i++) {
 941                         offset = i ? B2056_TX1 : B2056_TX0;
 942
 943                         b43_radio_write(dev,
 944                                 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
 945                         b43_radio_write(dev,
 946                                 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
 947                         b43_radio_write(dev,
 948                                 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
 949                         b43_radio_write(dev,
 950                                 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
 951                         b43_radio_write(dev,
 952                                 offset | B2056_TX_TXSPARE1, 0x30);
 953                         b43_radio_write(dev,
 954                                 offset | B2056_TX_PA_SPARE2, 0xee);
 955                         b43_radio_write(dev,
 956                                 offset | B2056_TX_PADA_CASCBIAS, 0x03);
 957                         b43_radio_write(dev,
 958                                 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
 959                         b43_radio_write(dev,
 960                                 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
 961                         b43_radio_write(dev,
 962                                 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
 963                 }
 964         }
 965
 966         udelay(50);
 967         /* VCO calibration */
 968         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 969         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 970         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 971         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 972         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 973         udelay(300);
 974 }
 975
 976 static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
 977 {
 978         struct b43_phy *phy = &dev->phy;
 979         u16 mast2, tmp;
 980
 981         if (phy->rev != 3)
 982                 return 0;
 983
 984         mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
 985         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
 986
 987         udelay(10);
 988         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 989         udelay(10);
 990         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
 991
 992         if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
 993                                   1000000)) {
 994                 b43err(dev->wl, "Radio recalibration timeout\n");
 995                 return 0;
 996         }
 997
 998         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
 999         tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1000         b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1001
1002         b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1003
1004         return tmp & 0x1f;
1005 }
1006
1007 static void b43_radio_init2056_pre(struct b43_wldev *dev)
1008 {
1009         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1010                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1011         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1012         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1013                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
1014         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1015                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1016         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1017                     B43_NPHY_RFCTL_CMD_CHIP0PU);
1018 }
1019
1020 static void b43_radio_init2056_post(struct b43_wldev *dev)
1021 {
1022         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1023         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1024         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1025         msleep(1);
1026         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1027         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1028         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
1029         if (dev->phy.do_full_init)
1030                 b43_radio_2056_rcal(dev);
1031 }
1032
1033 /*
1034  * Initialize a Broadcom 2056 N-radio
1035  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1036  */
1037 static void b43_radio_init2056(struct b43_wldev *dev)
1038 {
1039         b43_radio_init2056_pre(dev);
1040         b2056_upload_inittabs(dev, 0, 0);
1041         b43_radio_init2056_post(dev);
1042 }
1043
1044 /**************************************************
1045  * Radio 0x2055
1046  **************************************************/
1047
1048 static void b43_chantab_radio_upload(struct b43_wldev *dev,
1049                                 const struct b43_nphy_channeltab_entry_rev2 *e)
1050 {
1051         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1052         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1053         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1054         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1055         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1056
1057         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1058         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1059         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1060         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1061         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1062
1063         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1064         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1065         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1066         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1067         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1068
1069         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1070         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1071         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1072         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1073         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1074
1075         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1076         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1077         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1078         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1079         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1080
1081         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1082         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
1083 }
1084
1085 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1086 static void b43_radio_2055_setup(struct b43_wldev *dev,
1087                                 const struct b43_nphy_channeltab_entry_rev2 *e)
1088 {
1089         B43_WARN_ON(dev->phy.rev >= 3);
1090
1091         b43_chantab_radio_upload(dev, e);
1092         udelay(50);
1093         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1094         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1095         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1096         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1097         udelay(300);
1098 }
1099
1100 static void b43_radio_init2055_pre(struct b43_wldev *dev)
1101 {
1102         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1103                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
1104         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1105                     B43_NPHY_RFCTL_CMD_CHIP0PU |
1106                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
1107         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1108                     B43_NPHY_RFCTL_CMD_PORFORCE);
1109 }
1110
1111 static void b43_radio_init2055_post(struct b43_wldev *dev)
1112 {
1113         struct b43_phy_n *nphy = dev->phy.n;
1114         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1115         bool workaround = false;
1116
1117         if (sprom->revision < 4)
1118                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1119                               && dev->dev->board_type == SSB_BOARD_CB2_4321
1120                               && dev->dev->board_rev >= 0x41);
1121         else
1122                 workaround =
1123                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
1124
1125         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1126         if (workaround) {
1127                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1128                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1129         }
1130         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1131         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1132         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1133         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1134         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1135         msleep(1);
1136         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
1137         if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
1138                 b43err(dev->wl, "radio post init timeout\n");
1139         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1140         b43_switch_channel(dev, dev->phy.channel);
1141         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1142         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1143         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1144         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1145         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1146         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1147         if (!nphy->gain_boost) {
1148                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1149                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1150         } else {
1151                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1152                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1153         }
1154         udelay(2);
1155 }
1156
1157 /*
1158  * Initialize a Broadcom 2055 N-radio
1159  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1160  */
1161 static void b43_radio_init2055(struct b43_wldev *dev)
1162 {
1163         b43_radio_init2055_pre(dev);
1164         if (b43_status(dev) < B43_STAT_INITIALIZED) {
1165                 /* Follow wl, not specs. Do not force uploading all regs */
1166                 b2055_upload_inittab(dev, 0, 0);
1167         } else {
1168                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1169                 b2055_upload_inittab(dev, ghz5, 0);
1170         }
1171         b43_radio_init2055_post(dev);
1172 }
1173
1174 /**************************************************
1175  * Samples
1176  **************************************************/
1177
1178 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1179 static int b43_nphy_load_samples(struct b43_wldev *dev,
1180                                         struct b43_c32 *samples, u16 len) {
1181         struct b43_phy_n *nphy = dev->phy.n;
1182         u16 i;
1183         u32 *data;
1184
1185         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1186         if (!data) {
1187                 b43err(dev->wl, "allocation for samples loading failed\n");
1188                 return -ENOMEM;
1189         }
1190         if (nphy->hang_avoid)
1191                 b43_nphy_stay_in_carrier_search(dev, 1);
1192
1193         for (i = 0; i < len; i++) {
1194                 data[i] = (samples[i].i & 0x3FF << 10);
1195                 data[i] |= samples[i].q & 0x3FF;
1196         }
1197         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1198
1199         kfree(data);
1200         if (nphy->hang_avoid)
1201                 b43_nphy_stay_in_carrier_search(dev, 0);
1202         return 0;
1203 }
1204
1205 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1206 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1207                                         bool test)
1208 {
1209         int i;
1210         u16 bw, len, rot, angle;
1211         struct b43_c32 *samples;
1212
1213
1214         bw = (dev->phy.is_40mhz) ? 40 : 20;
1215         len = bw << 3;
1216
1217         if (test) {
1218                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1219                         bw = 82;
1220                 else
1221                         bw = 80;
1222
1223                 if (dev->phy.is_40mhz)
1224                         bw <<= 1;
1225
1226                 len = bw << 1;
1227         }
1228
1229         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1230         if (!samples) {
1231                 b43err(dev->wl, "allocation for samples generation failed\n");
1232                 return 0;
1233         }
1234         rot = (((freq * 36) / bw) << 16) / 100;
1235         angle = 0;
1236
1237         for (i = 0; i < len; i++) {
1238                 samples[i] = b43_cordic(angle);
1239                 angle += rot;
1240                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1241                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1242         }
1243
1244         i = b43_nphy_load_samples(dev, samples, len);
1245         kfree(samples);
1246         return (i < 0) ? 0 : len;
1247 }
1248
1249 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1250 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1251                                         u16 wait, bool iqmode, bool dac_test)
1252 {
1253         struct b43_phy_n *nphy = dev->phy.n;
1254         int i;
1255         u16 seq_mode;
1256         u32 tmp;
1257
1258         b43_nphy_stay_in_carrier_search(dev, true);
1259
1260         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1261                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1262                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1263         }
1264
1265         /* TODO: add modify_bbmult argument */
1266         if (!dev->phy.is_40mhz)
1267                 tmp = 0x6464;
1268         else
1269                 tmp = 0x4747;
1270         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1271
1272         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1273
1274         if (loops != 0xFFFF)
1275                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1276         else
1277                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1278
1279         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1280
1281         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1282
1283         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1284         if (iqmode) {
1285                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1286                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1287         } else {
1288                 if (dac_test)
1289                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1290                 else
1291                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1292         }
1293         for (i = 0; i < 100; i++) {
1294                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
1295                         i = 0;
1296                         break;
1297                 }
1298                 udelay(10);
1299         }
1300         if (i)
1301                 b43err(dev->wl, "run samples timeout\n");
1302
1303         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1304
1305         b43_nphy_stay_in_carrier_search(dev, false);
1306 }
1307
1308 /**************************************************
1309  * RSSI
1310  **************************************************/
1311
1312 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1313 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1314                                         s8 offset, u8 core,
1315                                         enum n_rail_type rail,
1316                                         enum n_rssi_type rssi_type)
1317 {
1318         u16 tmp;
1319         bool core1or5 = (core == 1) || (core == 5);
1320         bool core2or5 = (core == 2) || (core == 5);
1321
1322         offset = clamp_val(offset, -32, 31);
1323         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1324
1325         switch (rssi_type) {
1326         case N_RSSI_NB:
1327                 if (core1or5 && rail == N_RAIL_I)
1328                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1329                 if (core1or5 && rail == N_RAIL_Q)
1330                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1331                 if (core2or5 && rail == N_RAIL_I)
1332                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1333                 if (core2or5 && rail == N_RAIL_Q)
1334                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1335                 break;
1336         case N_RSSI_W1:
1337                 if (core1or5 && rail == N_RAIL_I)
1338                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1339                 if (core1or5 && rail == N_RAIL_Q)
1340                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1341                 if (core2or5 && rail == N_RAIL_I)
1342                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1343                 if (core2or5 && rail == N_RAIL_Q)
1344                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1345                 break;
1346         case N_RSSI_W2:
1347                 if (core1or5 && rail == N_RAIL_I)
1348                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1349                 if (core1or5 && rail == N_RAIL_Q)
1350                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1351                 if (core2or5 && rail == N_RAIL_I)
1352                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1353                 if (core2or5 && rail == N_RAIL_Q)
1354                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1355                 break;
1356         case N_RSSI_TBD:
1357                 if (core1or5 && rail == N_RAIL_I)
1358                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1359                 if (core1or5 && rail == N_RAIL_Q)
1360                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1361                 if (core2or5 && rail == N_RAIL_I)
1362                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1363                 if (core2or5 && rail == N_RAIL_Q)
1364                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1365                 break;
1366         case N_RSSI_IQ:
1367                 if (core1or5 && rail == N_RAIL_I)
1368                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1369                 if (core1or5 && rail == N_RAIL_Q)
1370                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1371                 if (core2or5 && rail == N_RAIL_I)
1372                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1373                 if (core2or5 && rail == N_RAIL_Q)
1374                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1375                 break;
1376         case N_RSSI_TSSI_2G:
1377                 if (core1or5)
1378                         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1379                 if (core2or5)
1380                         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1381                 break;
1382         case N_RSSI_TSSI_5G:
1383                 if (core1or5)
1384                         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1385                 if (core2or5)
1386                         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1387                 break;
1388         }
1389 }
1390
1391 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1392                                       enum n_rssi_type rssi_type)
1393 {
1394         u8 i;
1395         u16 reg, val;
1396
1397         if (code == 0) {
1398                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1399                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1400                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1401                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1402                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1403                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1404                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1405                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1406         } else {
1407                 for (i = 0; i < 2; i++) {
1408                         if ((code == 1 && i == 1) || (code == 2 && !i))
1409                                 continue;
1410
1411                         reg = (i == 0) ?
1412                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1413                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1414
1415                         if (rssi_type == N_RSSI_W1 ||
1416                             rssi_type == N_RSSI_W2 ||
1417                             rssi_type == N_RSSI_NB) {
1418                                 reg = (i == 0) ?
1419                                         B43_NPHY_AFECTL_C1 :
1420                                         B43_NPHY_AFECTL_C2;
1421                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1422
1423                                 reg = (i == 0) ?
1424                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1425                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1426                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1427
1428                                 if (rssi_type == N_RSSI_W1)
1429                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1430                                 else if (rssi_type == N_RSSI_W2)
1431                                         val = 16;
1432                                 else
1433                                         val = 32;
1434                                 b43_phy_set(dev, reg, val);
1435
1436                                 reg = (i == 0) ?
1437                                         B43_NPHY_TXF_40CO_B1S0 :
1438                                         B43_NPHY_TXF_40CO_B32S1;
1439                                 b43_phy_set(dev, reg, 0x0020);
1440                         } else {
1441                                 if (rssi_type == N_RSSI_TBD)
1442                                         val = 0x0100;
1443                                 else if (rssi_type == N_RSSI_IQ)
1444                                         val = 0x0200;
1445                                 else
1446                                         val = 0x0300;
1447
1448                                 reg = (i == 0) ?
1449                                         B43_NPHY_AFECTL_C1 :
1450                                         B43_NPHY_AFECTL_C2;
1451
1452                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1453                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1454
1455                                 if (rssi_type != N_RSSI_IQ &&
1456                                     rssi_type != N_RSSI_TBD) {
1457                                         enum ieee80211_band band =
1458                                                 b43_current_band(dev->wl);
1459
1460                                         if (b43_nphy_ipa(dev))
1461                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1462                                         else
1463                                                 val = 0x11;
1464                                         reg = (i == 0) ? 0x2000 : 0x3000;
1465                                         reg |= B2055_PADDRV;
1466                                         b43_radio_write(dev, reg, val);
1467
1468                                         reg = (i == 0) ?
1469                                                 B43_NPHY_AFECTL_OVER1 :
1470                                                 B43_NPHY_AFECTL_OVER;
1471                                         b43_phy_set(dev, reg, 0x0200);
1472                                 }
1473                         }
1474                 }
1475         }
1476 }
1477
1478 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1479                                       enum n_rssi_type rssi_type)
1480 {
1481         u16 val;
1482         bool rssi_w1_w2_nb = false;
1483
1484         switch (rssi_type) {
1485         case N_RSSI_W1:
1486         case N_RSSI_W2:
1487         case N_RSSI_NB:
1488                 val = 0;
1489                 rssi_w1_w2_nb = true;
1490                 break;
1491         case N_RSSI_TBD:
1492                 val = 1;
1493                 break;
1494         case N_RSSI_IQ:
1495                 val = 2;
1496                 break;
1497         default:
1498                 val = 3;
1499         }
1500
1501         val = (val << 12) | (val << 14);
1502         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1503         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1504
1505         if (rssi_w1_w2_nb) {
1506                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1507                                 (rssi_type + 1) << 4);
1508                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1509                                 (rssi_type + 1) << 4);
1510         }
1511
1512         if (code == 0) {
1513                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1514                 if (rssi_w1_w2_nb) {
1515                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1516                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1517                                   B43_NPHY_RFCTL_CMD_CORESEL));
1518                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1519                                 ~(0x1 << 12 |
1520                                   0x1 << 5 |
1521                                   0x1 << 1 |
1522                                   0x1));
1523                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1524                                 ~B43_NPHY_RFCTL_CMD_START);
1525                         udelay(20);
1526                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1527                 }
1528         } else {
1529                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1530                 if (rssi_w1_w2_nb) {
1531                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1532                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1533                                   B43_NPHY_RFCTL_CMD_CORESEL),
1534                                 (B43_NPHY_RFCTL_CMD_RXEN |
1535                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1536                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1537                                 (0x1 << 12 |
1538                                   0x1 << 5 |
1539                                   0x1 << 1 |
1540                                   0x1));
1541                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1542                                 B43_NPHY_RFCTL_CMD_START);
1543                         udelay(20);
1544                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1545                 }
1546         }
1547 }
1548
1549 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1550 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1551                                  enum n_rssi_type type)
1552 {
1553         if (dev->phy.rev >= 3)
1554                 b43_nphy_rev3_rssi_select(dev, code, type);
1555         else
1556                 b43_nphy_rev2_rssi_select(dev, code, type);
1557 }
1558
1559 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1560 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1561                                        enum n_rssi_type rssi_type, u8 *buf)
1562 {
1563         int i;
1564         for (i = 0; i < 2; i++) {
1565                 if (rssi_type == N_RSSI_NB) {
1566                         if (i == 0) {
1567                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1568                                                   0xFC, buf[0]);
1569                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1570                                                   0xFC, buf[1]);
1571                         } else {
1572                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1573                                                   0xFC, buf[2 * i]);
1574                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1575                                                   0xFC, buf[2 * i + 1]);
1576                         }
1577                 } else {
1578                         if (i == 0)
1579                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1580                                                   0xF3, buf[0] << 2);
1581                         else
1582                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1583                                                   0xF3, buf[2 * i + 1] << 2);
1584                 }
1585         }
1586 }
1587
1588 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1589 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1590                               s32 *buf, u8 nsamp)
1591 {
1592         int i;
1593         int out;
1594         u16 save_regs_phy[9];
1595         u16 s[2];
1596
1597         if (dev->phy.rev >= 3) {
1598                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1599                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1600                 save_regs_phy[2] = b43_phy_read(dev,
1601                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1602                 save_regs_phy[3] = b43_phy_read(dev,
1603                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1604                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1605                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1606                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1607                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1608                 save_regs_phy[8] = 0;
1609         } else {
1610                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1611                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1612                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1613                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1614                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1615                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1616                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1617                 save_regs_phy[7] = 0;
1618                 save_regs_phy[8] = 0;
1619         }
1620
1621         b43_nphy_rssi_select(dev, 5, rssi_type);
1622
1623         if (dev->phy.rev < 2) {
1624                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1625                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1626         }
1627
1628         for (i = 0; i < 4; i++)
1629                 buf[i] = 0;
1630
1631         for (i = 0; i < nsamp; i++) {
1632                 if (dev->phy.rev < 2) {
1633                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1634                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1635                 } else {
1636                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1637                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1638                 }
1639
1640                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1641                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1642                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1643                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1644         }
1645         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1646                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1647
1648         if (dev->phy.rev < 2)
1649                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1650
1651         if (dev->phy.rev >= 3) {
1652                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1653                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1654                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1655                                 save_regs_phy[2]);
1656                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1657                                 save_regs_phy[3]);
1658                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1659                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1660                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1661                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1662         } else {
1663                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1664                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1665                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1666                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1667                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1668                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1669                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1670         }
1671
1672         return out;
1673 }
1674
1675 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1676 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1677 {
1678         struct b43_phy_n *nphy = dev->phy.n;
1679
1680         u16 saved_regs_phy_rfctl[2];
1681         u16 saved_regs_phy[22];
1682         u16 regs_to_store_rev3[] = {
1683                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1684                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1685                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1686                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1687                 B43_NPHY_RFCTL_CMD,
1688                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1689                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1690         };
1691         u16 regs_to_store_rev7[] = {
1692                 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1693                 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1694                 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1695                 0x342, 0x343, 0x346, 0x347,
1696                 0x2ff,
1697                 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1698                 B43_NPHY_RFCTL_CMD,
1699                 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1700                 0x340, 0x341, 0x344, 0x345,
1701                 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1702         };
1703         u16 *regs_to_store;
1704         int regs_amount;
1705
1706         u16 class;
1707
1708         u16 clip_state[2];
1709         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1710
1711         u8 vcm_final = 0;
1712         s32 offset[4];
1713         s32 results[8][4] = { };
1714         s32 results_min[4] = { };
1715         s32 poll_results[4] = { };
1716
1717         u16 *rssical_radio_regs = NULL;
1718         u16 *rssical_phy_regs = NULL;
1719
1720         u16 r; /* routing */
1721         u8 rx_core_state;
1722         int core, i, j, vcm;
1723
1724         if (dev->phy.rev >= 7) {
1725                 regs_to_store = regs_to_store_rev7;
1726                 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1727         } else {
1728                 regs_to_store = regs_to_store_rev3;
1729                 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1730         }
1731         BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1732
1733         class = b43_nphy_classifier(dev, 0, 0);
1734         b43_nphy_classifier(dev, 7, 4);
1735         b43_nphy_read_clip_detection(dev, clip_state);
1736         b43_nphy_write_clip_detection(dev, clip_off);
1737
1738         saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1739         saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1740         for (i = 0; i < regs_amount; i++)
1741                 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1742
1743         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1744         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
1745
1746         if (dev->phy.rev >= 7) {
1747                 /* TODO */
1748                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1749                 } else {
1750                 }
1751         } else {
1752                 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1753                 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1754                 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1755                 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1756                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1757                         b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1758                         b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1759                 } else {
1760                         b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1761                         b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1762                 }
1763         }
1764
1765         rx_core_state = b43_nphy_get_rx_core_state(dev);
1766         for (core = 0; core < 2; core++) {
1767                 if (!(rx_core_state & (1 << core)))
1768                         continue;
1769                 r = core ? B2056_RX1 : B2056_RX0;
1770                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1771                                            N_RSSI_NB);
1772                 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1773                                            N_RSSI_NB);
1774
1775                 /* Grab RSSI results for every possible VCM */
1776                 for (vcm = 0; vcm < 8; vcm++) {
1777                         if (dev->phy.rev >= 7)
1778                                 ;
1779                         else
1780                                 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1781                                                   0xE3, vcm << 2);
1782                         b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
1783                 }
1784
1785                 /* Find out which VCM got the best results */
1786                 for (i = 0; i < 4; i += 2) {
1787                         s32 currd;
1788                         s32 mind = 0x100000;
1789                         s32 minpoll = 249;
1790                         u8 minvcm = 0;
1791                         if (2 * core != i)
1792                                 continue;
1793                         for (vcm = 0; vcm < 8; vcm++) {
1794                                 currd = results[vcm][i] * results[vcm][i] +
1795                                         results[vcm][i + 1] * results[vcm][i];
1796                                 if (currd < mind) {
1797                                         mind = currd;
1798                                         minvcm = vcm;
1799                                 }
1800                                 if (results[vcm][i] < minpoll)
1801                                         minpoll = results[vcm][i];
1802                         }
1803                         vcm_final = minvcm;
1804                         results_min[i] = minpoll;
1805                 }
1806
1807                 /* Select the best VCM */
1808                 if (dev->phy.rev >= 7)
1809                         ;
1810                 else
1811                         b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1812                                           0xE3, vcm_final << 2);
1813
1814                 for (i = 0; i < 4; i++) {
1815                         if (core != i / 2)
1816                                 continue;
1817                         offset[i] = -results[vcm_final][i];
1818                         if (offset[i] < 0)
1819                                 offset[i] = -((abs(offset[i]) + 4) / 8);
1820                         else
1821                                 offset[i] = (offset[i] + 4) / 8;
1822                         if (results_min[i] == 248)
1823                                 offset[i] = -32;
1824                         b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1825                                                    (i / 2 == 0) ? 1 : 2,
1826                                                    (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1827                                                    N_RSSI_NB);
1828                 }
1829         }
1830
1831         for (core = 0; core < 2; core++) {
1832                 if (!(rx_core_state & (1 << core)))
1833                         continue;
1834                 for (i = 0; i < 2; i++) {
1835                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1836                                                    N_RAIL_I, i);
1837                         b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1838                                                    N_RAIL_Q, i);
1839                         b43_nphy_poll_rssi(dev, i, poll_results, 8);
1840                         for (j = 0; j < 4; j++) {
1841                                 if (j / 2 == core) {
1842                                         offset[j] = 232 - poll_results[j];
1843                                         if (offset[j] < 0)
1844                                                 offset[j] = -(abs(offset[j] + 4) / 8);
1845                                         else
1846                                                 offset[j] = (offset[j] + 4) / 8;
1847                                         b43_nphy_scale_offset_rssi(dev, 0,
1848                                                 offset[2 * core], core + 1, j % 2, i);
1849                                 }
1850                         }
1851                 }
1852         }
1853
1854         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1855         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1856
1857         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1858
1859         b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1860         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1861         b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1862
1863         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1864         b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1865         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1866
1867         for (i = 0; i < regs_amount; i++)
1868                 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1869
1870         /* Store for future configuration */
1871         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1872                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1873                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1874         } else {
1875                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1876                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1877         }
1878         if (dev->phy.rev >= 7) {
1879         } else {
1880                 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1881                                                        B2056_RX_RSSI_MISC);
1882                 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1883                                                        B2056_RX_RSSI_MISC);
1884         }
1885         rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1886         rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1887         rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1888         rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1889         rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1890         rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1891         rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1892         rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1893         rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1894         rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1895         rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1896         rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1897
1898         /* Remember for which channel we store configuration */
1899         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1900                 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1901         else
1902                 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1903
1904         /* End of calibration, restore configuration */
1905         b43_nphy_classifier(dev, 7, class);
1906         b43_nphy_write_clip_detection(dev, clip_state);
1907 }
1908
1909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1910 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1911 {
1912         int i, j, vcm;
1913         u8 state[4];
1914         u8 code, val;
1915         u16 class, override;
1916         u8 regs_save_radio[2];
1917         u16 regs_save_phy[2];
1918
1919         s32 offset[4];
1920         u8 core;
1921         u8 rail;
1922
1923         u16 clip_state[2];
1924         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1925         s32 results_min[4] = { };
1926         u8 vcm_final[4] = { };
1927         s32 results[4][4] = { };
1928         s32 miniq[4][2] = { };
1929
1930         if (type == N_RSSI_NB) {
1931                 code = 0;
1932                 val = 6;
1933         } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
1934                 code = 25;
1935                 val = 4;
1936         } else {
1937                 B43_WARN_ON(1);
1938                 return;
1939         }
1940
1941         class = b43_nphy_classifier(dev, 0, 0);
1942         b43_nphy_classifier(dev, 7, 4);
1943         b43_nphy_read_clip_detection(dev, clip_state);
1944         b43_nphy_write_clip_detection(dev, clip_off);
1945
1946         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1947                 override = 0x140;
1948         else
1949                 override = 0x110;
1950
1951         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1952         regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
1953         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1954         b43_radio_write(dev, B2055_C1_PD_RXTX, val);
1955
1956         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1957         regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
1958         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1959         b43_radio_write(dev, B2055_C2_PD_RXTX, val);
1960
1961         state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1962         state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1963         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1964         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1965         state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1966         state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
1967
1968         b43_nphy_rssi_select(dev, 5, type);
1969         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1970         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1971
1972         for (vcm = 0; vcm < 4; vcm++) {
1973                 u8 tmp[4];
1974                 for (j = 0; j < 4; j++)
1975                         tmp[j] = vcm;
1976                 if (type != N_RSSI_W2)
1977                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1978                 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
1979                 if (type == N_RSSI_W1 || type == N_RSSI_W2)
1980                         for (j = 0; j < 2; j++)
1981                                 miniq[vcm][j] = min(results[vcm][2 * j],
1982                                                     results[vcm][2 * j + 1]);
1983         }
1984
1985         for (i = 0; i < 4; i++) {
1986                 s32 mind = 0x100000;
1987                 u8 minvcm = 0;
1988                 s32 minpoll = 249;
1989                 s32 currd;
1990                 for (vcm = 0; vcm < 4; vcm++) {
1991                         if (type == N_RSSI_NB)
1992                                 currd = abs(results[vcm][i] - code * 8);
1993                         else
1994                                 currd = abs(miniq[vcm][i / 2] - code * 8);
1995
1996                         if (currd < mind) {
1997                                 mind = currd;
1998                                 minvcm = vcm;
1999                         }
2000
2001                         if (results[vcm][i] < minpoll)
2002                                 minpoll = results[vcm][i];
2003                 }
2004                 results_min[i] = minpoll;
2005                 vcm_final[i] = minvcm;
2006         }
2007
2008         if (type != N_RSSI_W2)
2009                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2010
2011         for (i = 0; i < 4; i++) {
2012                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2013
2014                 if (offset[i] < 0)
2015                         offset[i] = -((abs(offset[i]) + 4) / 8);
2016                 else
2017                         offset[i] = (offset[i] + 4) / 8;
2018
2019                 if (results_min[i] == 248)
2020                         offset[i] = code - 32;
2021
2022                 core = (i / 2) ? 2 : 1;
2023                 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
2024
2025                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2026                                                 type);
2027         }
2028
2029         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2030         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2031
2032         switch (state[2]) {
2033         case 1:
2034                 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
2035                 break;
2036         case 4:
2037                 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
2038                 break;
2039         case 2:
2040                 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2041                 break;
2042         default:
2043                 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
2044                 break;
2045         }
2046
2047         switch (state[3]) {
2048         case 1:
2049                 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
2050                 break;
2051         case 4:
2052                 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
2053                 break;
2054         default:
2055                 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
2056                 break;
2057         }
2058
2059         b43_nphy_rssi_select(dev, 0, type);
2060
2061         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2062         b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2063         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2064         b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2065
2066         b43_nphy_classifier(dev, 7, class);
2067         b43_nphy_write_clip_detection(dev, clip_state);
2068         /* Specs don't say about reset here, but it makes wl and b43 dumps
2069            identical, it really seems wl performs this */
2070         b43_nphy_reset_cca(dev);
2071 }
2072
2073 /*
2074  * RSSI Calibration
2075  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2076  */
2077 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2078 {
2079         if (dev->phy.rev >= 3) {
2080                 b43_nphy_rev3_rssi_cal(dev);
2081         } else {
2082                 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2083                 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2084                 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
2085         }
2086 }
2087
2088 /**************************************************
2089  * Workarounds
2090  **************************************************/
2091
2092 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2093 {
2094         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2095
2096         bool ghz5;
2097         bool ext_lna;
2098         u16 rssi_gain;
2099         struct nphy_gain_ctl_workaround_entry *e;
2100         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2101         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2102
2103         /* Prepare values */
2104         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2105                 & B43_NPHY_BANDCTL_5GHZ;
2106         ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2107                 sprom->boardflags_lo & B43_BFL_EXTLNA;
2108         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2109         if (ghz5 && dev->phy.rev >= 5)
2110                 rssi_gain = 0x90;
2111         else
2112                 rssi_gain = 0x50;
2113
2114         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2115
2116         /* Set Clip 2 detect */
2117         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2118         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2119
2120         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2121                         0x17);
2122         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2123                         0x17);
2124         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2125         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2126         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2127         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2128         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2129                         rssi_gain);
2130         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2131                         rssi_gain);
2132         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2133                         0x17);
2134         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2135                         0x17);
2136         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2137         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2138
2139         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2140         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2141         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2142         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2143         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2144         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2145         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2146         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2147         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2148         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2149         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2150         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2151
2152         b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2153         b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2154
2155         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2156                                 e->rfseq_init);
2157
2158         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2159         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2160         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2161         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2162         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2163         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2164
2165         b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2166         b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2167         b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2168         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2169         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2170         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2171                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2172         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2173                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2174         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2175 }
2176
2177 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2178 {
2179         struct b43_phy_n *nphy = dev->phy.n;
2180
2181         u8 i, j;
2182         u8 code;
2183         u16 tmp;
2184         u8 rfseq_events[3] = { 6, 8, 7 };
2185         u8 rfseq_delays[3] = { 10, 30, 1 };
2186
2187         /* Set Clip 2 detect */
2188         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2189         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2190
2191         /* Set narrowband clip threshold */
2192         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2193         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2194
2195         if (!dev->phy.is_40mhz) {
2196                 /* Set dwell lengths */
2197                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2198                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2199                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2200                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2201         }
2202
2203         /* Set wideband clip 2 threshold */
2204         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2205                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2206         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2207                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2208
2209         if (!dev->phy.is_40mhz) {
2210                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2211                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2212                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2213                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2214                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2215                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2216                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2217                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2218         }
2219
2220         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2221
2222         if (nphy->gain_boost) {
2223                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2224                         dev->phy.is_40mhz)
2225                         code = 4;
2226                 else
2227                         code = 5;
2228         } else {
2229                 code = dev->phy.is_40mhz ? 6 : 7;
2230         }
2231
2232         /* Set HPVGA2 index */
2233         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2234                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2235         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2236                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2237
2238         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2239         /* specs say about 2 loops, but wl does 4 */
2240         for (i = 0; i < 4; i++)
2241                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2242
2243         b43_nphy_adjust_lna_gain_table(dev);
2244
2245         if (nphy->elna_gain_config) {
2246                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2247                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2248                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2249                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2250                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2251
2252                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2253                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2254                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2255                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2256                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2257
2258                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2259                 /* specs say about 2 loops, but wl does 4 */
2260                 for (i = 0; i < 4; i++)
2261                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2262                                                 (code << 8 | 0x74));
2263         }
2264
2265         if (dev->phy.rev == 2) {
2266                 for (i = 0; i < 4; i++) {
2267                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2268                                         (0x0400 * i) + 0x0020);
2269                         for (j = 0; j < 21; j++) {
2270                                 tmp = j * (i < 2 ? 3 : 1);
2271                                 b43_phy_write(dev,
2272                                         B43_NPHY_TABLE_DATALO, tmp);
2273                         }
2274                 }
2275         }
2276
2277         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2278         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2279                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2280                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2281
2282         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2283                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2284 }
2285
2286 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2287 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2288 {
2289         if (dev->phy.rev >= 7)
2290                 ; /* TODO */
2291         else if (dev->phy.rev >= 3)
2292                 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2293         else
2294                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
2295 }
2296
2297 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2298 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2299 {
2300         if (!offset)
2301                 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2302         return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2303 }
2304
2305 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2306 {
2307         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2308         struct b43_phy *phy = &dev->phy;
2309
2310         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2311                                         0x1F };
2312         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2313
2314         u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2315         u8 ntab7_138_146[] = { 0x11, 0x11 };
2316         u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2317
2318         u16 lpf_20, lpf_40, lpf_11b;
2319         u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2320         u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2321         bool rccal_ovrd = false;
2322
2323         u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2324         u16 bias, conv, filt;
2325
2326         u32 tmp32;
2327         u8 core;
2328
2329         if (phy->rev == 7) {
2330                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2331                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2332                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2333                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2334                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2335                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2336                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2337                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2338                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2339                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2340                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2341                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2342                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2343                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2344                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2345                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2346                 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2347         }
2348         if (phy->rev <= 8) {
2349                 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2350                 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2351         }
2352         if (phy->rev >= 8)
2353                 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2354
2355         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2356         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2357         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2358         tmp32 &= 0xffffff;
2359         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2360         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2361         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2362
2363         if (b43_nphy_ipa(dev))
2364                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2365                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2366
2367         b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2368         b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2369
2370         lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2371         lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2372         lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2373         if (b43_nphy_ipa(dev)) {
2374                 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2375                     phy->radio_rev == 7 || phy->radio_rev == 8) {
2376                         bcap_val = b43_radio_read(dev, 0x16b);
2377                         scap_val = b43_radio_read(dev, 0x16a);
2378                         scap_val_11b = scap_val;
2379                         bcap_val_11b = bcap_val;
2380                         if (phy->radio_rev == 5 && phy->is_40mhz) {
2381                                 scap_val_11n_20 = scap_val;
2382                                 bcap_val_11n_20 = bcap_val;
2383                                 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2384                                 rccal_ovrd = true;
2385                         } else { /* Rev 7/8 */
2386                                 lpf_20 = 4;
2387                                 lpf_11b = 1;
2388                                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2389                                         scap_val_11n_20 = 0xc;
2390                                         bcap_val_11n_20 = 0xc;
2391                                         scap_val_11n_40 = 0xa;
2392                                         bcap_val_11n_40 = 0xa;
2393                                 } else {
2394                                         scap_val_11n_20 = 0x14;
2395                                         bcap_val_11n_20 = 0x14;
2396                                         scap_val_11n_40 = 0xf;
2397                                         bcap_val_11n_40 = 0xf;
2398                                 }
2399                                 rccal_ovrd = true;
2400                         }
2401                 }
2402         } else {
2403                 if (phy->radio_rev == 5) {
2404                         lpf_20 = 1;
2405                         lpf_40 = 3;
2406                         bcap_val = b43_radio_read(dev, 0x16b);
2407                         scap_val = b43_radio_read(dev, 0x16a);
2408                         scap_val_11b = scap_val;
2409                         bcap_val_11b = bcap_val;
2410                         scap_val_11n_20 = 0x11;
2411                         scap_val_11n_40 = 0x11;
2412                         bcap_val_11n_20 = 0x13;
2413                         bcap_val_11n_40 = 0x13;
2414                         rccal_ovrd = true;
2415                 }
2416         }
2417         if (rccal_ovrd) {
2418                 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2419                                    (scap_val_11b << 3) |
2420                                    lpf_11b;
2421                 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2422                                    (scap_val_11n_20 << 3) |
2423                                    lpf_20;
2424                 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2425                                    (scap_val_11n_40 << 3) |
2426                                    lpf_40;
2427                 for (core = 0; core < 2; core++) {
2428                         b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2429                                        rx2tx_lut_20_11b);
2430                         b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2431                                        rx2tx_lut_20_11n);
2432                         b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2433                                        rx2tx_lut_20_11n);
2434                         b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2435                                        rx2tx_lut_40_11n);
2436                         b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2437                                        rx2tx_lut_40_11n);
2438                         b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2439                                        rx2tx_lut_40_11n);
2440                         b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2441                                        rx2tx_lut_40_11n);
2442                         b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2443                                        rx2tx_lut_40_11n);
2444                 }
2445                 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2446         }
2447         b43_phy_write(dev, 0x32F, 0x3);
2448         if (phy->radio_rev == 4 || phy->radio_rev == 6)
2449                 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2450
2451         if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2452                 if (sprom->revision &&
2453                     sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2454                         b43_radio_write(dev, 0x5, 0x05);
2455                         b43_radio_write(dev, 0x6, 0x30);
2456                         b43_radio_write(dev, 0x7, 0x00);
2457                         b43_radio_set(dev, 0x4f, 0x1);
2458                         b43_radio_set(dev, 0xd4, 0x1);
2459                         bias = 0x1f;
2460                         conv = 0x6f;
2461                         filt = 0xaa;
2462                 } else {
2463                         bias = 0x2b;
2464                         conv = 0x7f;
2465                         filt = 0xee;
2466                 }
2467                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2468                         for (core = 0; core < 2; core++) {
2469                                 if (core == 0) {
2470                                         b43_radio_write(dev, 0x5F, bias);
2471                                         b43_radio_write(dev, 0x64, conv);
2472                                         b43_radio_write(dev, 0x66, filt);
2473                                 } else {
2474                                         b43_radio_write(dev, 0xE8, bias);
2475                                         b43_radio_write(dev, 0xE9, conv);
2476                                         b43_radio_write(dev, 0xEB, filt);
2477                                 }
2478                         }
2479                 }
2480         }
2481
2482         if (b43_nphy_ipa(dev)) {
2483                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2484                         if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2485                             phy->radio_rev == 6) {
2486                                 for (core = 0; core < 2; core++) {
2487                                         if (core == 0)
2488                                                 b43_radio_write(dev, 0x51,
2489                                                                 0x7f);
2490                                         else
2491                                                 b43_radio_write(dev, 0xd6,
2492                                                                 0x7f);
2493                                 }
2494                         }
2495                         if (phy->radio_rev == 3) {
2496                                 for (core = 0; core < 2; core++) {
2497                                         if (core == 0) {
2498                                                 b43_radio_write(dev, 0x64,
2499                                                                 0x13);
2500                                                 b43_radio_write(dev, 0x5F,
2501                                                                 0x1F);
2502                                                 b43_radio_write(dev, 0x66,
2503                                                                 0xEE);
2504                                                 b43_radio_write(dev, 0x59,
2505                                                                 0x8A);
2506                                                 b43_radio_write(dev, 0x80,
2507                                                                 0x3E);
2508                                         } else {
2509                                                 b43_radio_write(dev, 0x69,
2510                                                                 0x13);
2511                                                 b43_radio_write(dev, 0xE8,
2512                                                                 0x1F);
2513                                                 b43_radio_write(dev, 0xEB,
2514                                                                 0xEE);
2515                                                 b43_radio_write(dev, 0xDE,
2516                                                                 0x8A);
2517                                                 b43_radio_write(dev, 0x105,
2518                                                                 0x3E);
2519                                         }
2520                                 }
2521                         } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2522                                 if (!phy->is_40mhz) {
2523                                         b43_radio_write(dev, 0x5F, 0x14);
2524                                         b43_radio_write(dev, 0xE8, 0x12);
2525                                 } else {
2526                                         b43_radio_write(dev, 0x5F, 0x16);
2527                                         b43_radio_write(dev, 0xE8, 0x16);
2528                                 }
2529                         }
2530                 } else {
2531                         u16 freq = phy->channel_freq;
2532                         if ((freq >= 5180 && freq <= 5230) ||
2533                             (freq >= 5745 && freq <= 5805)) {
2534                                 b43_radio_write(dev, 0x7D, 0xFF);
2535                                 b43_radio_write(dev, 0xFE, 0xFF);
2536                         }
2537                 }
2538         } else {
2539                 if (phy->radio_rev != 5) {
2540                         for (core = 0; core < 2; core++) {
2541                                 if (core == 0) {
2542                                         b43_radio_write(dev, 0x5c, 0x61);
2543                                         b43_radio_write(dev, 0x51, 0x70);
2544                                 } else {
2545                                         b43_radio_write(dev, 0xe1, 0x61);
2546                                         b43_radio_write(dev, 0xd6, 0x70);
2547                                 }
2548                         }
2549                 }
2550         }
2551
2552         if (phy->radio_rev == 4) {
2553                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2554                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2555                 for (core = 0; core < 2; core++) {
2556                         if (core == 0) {
2557                                 b43_radio_write(dev, 0x1a1, 0x00);
2558                                 b43_radio_write(dev, 0x1a2, 0x3f);
2559                                 b43_radio_write(dev, 0x1a6, 0x3f);
2560                         } else {
2561                                 b43_radio_write(dev, 0x1a7, 0x00);
2562                                 b43_radio_write(dev, 0x1ab, 0x3f);
2563                                 b43_radio_write(dev, 0x1ac, 0x3f);
2564                         }
2565                 }
2566         } else {
2567                 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2568                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2569                 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2570                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2571
2572                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2573                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2574                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2575                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2576                 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2577                 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2578
2579                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2580                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2581                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2582                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2583         }
2584
2585         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2586
2587         b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2588         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2589         b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2590         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2591         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2592         b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2593         b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2594
2595         if (!phy->is_40mhz) {
2596                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2597                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2598         } else {
2599                 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2600                 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2601         }
2602
2603         b43_nphy_gain_ctl_workarounds(dev);
2604
2605         /* TODO
2606         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2607                             aux_adc_vmid_rev7_core0);
2608         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2609                             aux_adc_vmid_rev7_core1);
2610         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2611                             aux_adc_gain_rev7);
2612         b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2613                             aux_adc_gain_rev7);
2614         */
2615 }
2616
2617 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2618 {
2619         struct b43_phy_n *nphy = dev->phy.n;
2620         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2621
2622         /* TX to RX */
2623         u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2624         u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
2625         /* RX to TX */
2626         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2627                                         0x1F };
2628         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2629         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2630         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2631
2632         u16 vmids[5][4] = {
2633                 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2634                 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2635                 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2636                 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2637                 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2638         };
2639         u16 gains[5][4] = {
2640                 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2641                 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2642                 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2643                 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2644                 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2645         };
2646         u16 *vmid, *gain;
2647
2648         u8 pdet_range;
2649         u16 tmp16;
2650         u32 tmp32;
2651
2652         b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2653         b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
2654
2655         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2656         tmp32 &= 0xffffff;
2657         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2658
2659         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2660         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2661         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2662         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2663         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2664         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2665
2666         b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2667         b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
2668
2669         /* TX to RX */
2670         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2671                                  ARRAY_SIZE(tx2rx_events));
2672
2673         /* RX to TX */
2674         if (b43_nphy_ipa(dev))
2675                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2676                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2677         if (nphy->hw_phyrxchain != 3 &&
2678             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2679                 if (b43_nphy_ipa(dev)) {
2680                         rx2tx_delays[5] = 59;
2681                         rx2tx_delays[6] = 1;
2682                         rx2tx_events[7] = 0x1F;
2683                 }
2684                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
2685                                          ARRAY_SIZE(rx2tx_events));
2686         }
2687
2688         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2689                 0x2 : 0x9C40;
2690         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2691
2692         b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2693
2694         if (!dev->phy.is_40mhz) {
2695                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2696                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2697         } else {
2698                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2699                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2700         }
2701
2702         b43_nphy_gain_ctl_workarounds(dev);
2703
2704         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2705         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
2706
2707         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2708                 pdet_range = sprom->fem.ghz2.pdet_range;
2709         else
2710                 pdet_range = sprom->fem.ghz5.pdet_range;
2711         vmid = vmids[min_t(u16, pdet_range, 4)];
2712         gain = gains[min_t(u16, pdet_range, 4)];
2713         switch (pdet_range) {
2714         case 3:
2715                 if (!(dev->phy.rev >= 4 &&
2716                       b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2717                         break;
2718                 /* FALL THROUGH */
2719         case 0:
2720         case 1:
2721                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2722                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2723                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2724                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2725                 break;
2726         case 2:
2727                 if (dev->phy.rev >= 6) {
2728                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2729                                 vmid[3] = 0x94;
2730                         else
2731                                 vmid[3] = 0x8e;
2732                         gain[3] = 3;
2733                 } else if (dev->phy.rev == 5) {
2734                         vmid[3] = 0x84;
2735                         gain[3] = 2;
2736                 }
2737                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2738                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2739                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2740                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2741                 break;
2742         case 4:
2743         case 5:
2744                 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2745                         if (pdet_range == 4) {
2746                                 vmid[3] = 0x8e;
2747                                 tmp16 = 0x96;
2748                                 gain[3] = 0x2;
2749                         } else {
2750                                 vmid[3] = 0x89;
2751                                 tmp16 = 0x89;
2752                                 gain[3] = 0;
2753                         }
2754                 } else {
2755                         if (pdet_range == 4) {
2756                                 vmid[3] = 0x89;
2757                                 tmp16 = 0x8b;
2758                                 gain[3] = 0x2;
2759                         } else {
2760                                 vmid[3] = 0x74;
2761                                 tmp16 = 0x70;
2762                                 gain[3] = 0;
2763                         }
2764                 }
2765                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2766                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2767                 vmid[3] = tmp16;
2768                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2769                 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2770                 break;
2771         }
2772
2773         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2774         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2775         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2776         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2777         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2778         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2779         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2780         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2781         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2782         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2783         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2784         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2785
2786         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2787
2788         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2789              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2790             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2791              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2792                 tmp32 = 0x00088888;
2793         else
2794                 tmp32 = 0x88888888;
2795         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2796         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2797         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2798
2799         if (dev->phy.rev == 4 &&
2800             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2801                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2802                                 0x70);
2803                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2804                                 0x70);
2805         }
2806
2807         /* Dropped probably-always-true condition */
2808         b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2809         b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2810         b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
2811         b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2812         b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2813         b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2814         b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2815         b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2816         b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2817         b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2818         b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2819         b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
2820
2821         if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2822                 ; /* TODO: 0x0080000000000000 HF */
2823 }
2824
2825 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2826 {
2827         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2828         struct b43_phy *phy = &dev->phy;
2829         struct b43_phy_n *nphy = phy->n;
2830
2831         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2832         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
2833
2834         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2835         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2836
2837         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2838             dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
2839                 delays1[0] = 0x1;
2840                 delays1[5] = 0x14;
2841         }
2842
2843         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2844             nphy->band5g_pwrgain) {
2845                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2846                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2847         } else {
2848                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2849                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2850         }
2851
2852         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2853         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2854         if (dev->phy.rev < 3) {
2855                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2856                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2857         }
2858
2859         if (dev->phy.rev < 2) {
2860                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2861                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2862                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2863                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2864                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2865                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2866         }
2867
2868         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2869         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2870         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2871         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2872
2873         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2874         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2875
2876         b43_nphy_gain_ctl_workarounds(dev);
2877
2878         if (dev->phy.rev < 2) {
2879                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2880                         b43_hf_write(dev, b43_hf_read(dev) |
2881                                         B43_HF_MLADVW);
2882         } else if (dev->phy.rev == 2) {
2883                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2884                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2885         }
2886
2887         if (dev->phy.rev < 2)
2888                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2889                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2890
2891         /* Set phase track alpha and beta */
2892         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2893         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2894         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2895         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2896         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2897         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2898
2899         if (dev->phy.rev < 3) {
2900                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2901                              ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2902                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2903                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2904                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2905         }
2906
2907         if (dev->phy.rev == 2)
2908                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2909                                 B43_NPHY_FINERX2_CGC_DECGC);
2910 }
2911
2912 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2913 static void b43_nphy_workarounds(struct b43_wldev *dev)
2914 {
2915         struct b43_phy *phy = &dev->phy;
2916         struct b43_phy_n *nphy = phy->n;
2917
2918         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2919                 b43_nphy_classifier(dev, 1, 0);
2920         else
2921                 b43_nphy_classifier(dev, 1, 1);
2922
2923         if (nphy->hang_avoid)
2924                 b43_nphy_stay_in_carrier_search(dev, 1);
2925
2926         b43_phy_set(dev, B43_NPHY_IQFLIP,
2927                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2928
2929         if (dev->phy.rev >= 7)
2930                 b43_nphy_workarounds_rev7plus(dev);
2931         else if (dev->phy.rev >= 3)
2932                 b43_nphy_workarounds_rev3plus(dev);
2933         else
2934                 b43_nphy_workarounds_rev1_2(dev);
2935
2936         if (nphy->hang_avoid)
2937                 b43_nphy_stay_in_carrier_search(dev, 0);
2938 }
2939
2940 /**************************************************
2941  * Tx/Rx common
2942  **************************************************/
2943
2944 /*
2945  * Transmits a known value for LO calibration
2946  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2947  */
2948 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2949                                 bool iqmode, bool dac_test)
2950 {
2951         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2952         if (samp == 0)
2953                 return -1;
2954         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2955         return 0;
2956 }
2957
2958 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2959 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2960 {
2961         struct b43_phy_n *nphy = dev->phy.n;
2962
2963         bool override = false;
2964         u16 chain = 0x33;
2965
2966         if (nphy->txrx_chain == 0) {
2967                 chain = 0x11;
2968                 override = true;
2969         } else if (nphy->txrx_chain == 1) {
2970                 chain = 0x22;
2971                 override = true;
2972         }
2973
2974         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2975                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2976                         chain);
2977
2978         if (override)
2979                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2980                                 B43_NPHY_RFSEQMODE_CAOVER);
2981         else
2982                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2983                                 ~B43_NPHY_RFSEQMODE_CAOVER);
2984 }
2985
2986 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2987 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2988 {
2989         struct b43_phy_n *nphy = dev->phy.n;
2990         u16 tmp;
2991
2992         if (nphy->hang_avoid)
2993                 b43_nphy_stay_in_carrier_search(dev, 1);
2994
2995         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2996         if (tmp & 0x1)
2997                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2998         else if (tmp & 0x2)
2999                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3000
3001         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3002
3003         if (nphy->bb_mult_save & 0x80000000) {
3004                 tmp = nphy->bb_mult_save & 0xFFFF;
3005                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3006                 nphy->bb_mult_save = 0;
3007         }
3008
3009         if (nphy->hang_avoid)
3010                 b43_nphy_stay_in_carrier_search(dev, 0);
3011 }
3012
3013 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3014 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3015                                         struct nphy_txgains target,
3016                                         struct nphy_iqcal_params *params)
3017 {
3018         int i, j, indx;
3019         u16 gain;
3020
3021         if (dev->phy.rev >= 3) {
3022                 params->txgm = target.txgm[core];
3023                 params->pga = target.pga[core];
3024                 params->pad = target.pad[core];
3025                 params->ipa = target.ipa[core];
3026                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3027                                         (params->pad << 4) | (params->ipa);
3028                 for (j = 0; j < 5; j++)
3029                         params->ncorr[j] = 0x79;
3030         } else {
3031                 gain = (target.pad[core]) | (target.pga[core] << 4) |
3032                         (target.txgm[core] << 8);
3033
3034                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3035                         1 : 0;
3036                 for (i = 0; i < 9; i++)
3037                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
3038                                 break;
3039                 i = min(i, 8);
3040
3041                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3042                 params->pga = tbl_iqcal_gainparams[indx][i][2];
3043                 params->pad = tbl_iqcal_gainparams[indx][i][3];
3044                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3045                                         (params->pad << 2);
3046                 for (j = 0; j < 4; j++)
3047                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3048         }
3049 }
3050
3051 /**************************************************
3052  * Tx and Rx
3053  **************************************************/
3054
3055 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3056 {//TODO
3057 }
3058
3059 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3060                                                         bool ignore_tssi)
3061 {//TODO
3062         return B43_TXPWR_RES_DONE;
3063 }
3064
3065 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3066 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3067 {
3068         struct b43_phy_n *nphy = dev->phy.n;
3069         u8 i;
3070         u16 bmask, val, tmp;
3071         enum ieee80211_band band = b43_current_band(dev->wl);
3072
3073         if (nphy->hang_avoid)
3074                 b43_nphy_stay_in_carrier_search(dev, 1);
3075
3076         nphy->txpwrctrl = enable;
3077         if (!enable) {
3078                 if (dev->phy.rev >= 3 &&
3079                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3080                      (B43_NPHY_TXPCTL_CMD_COEFF |
3081                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3082                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3083                         /* We disable enabled TX pwr ctl, save it's state */
3084                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3085                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3086                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3087                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3088                 }
3089
3090                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3091                 for (i = 0; i < 84; i++)
3092                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3093
3094                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3095                 for (i = 0; i < 84; i++)
3096                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
3097
3098                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3099                 if (dev->phy.rev >= 3)
3100                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3101                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
3102
3103                 if (dev->phy.rev >= 3) {
3104                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3105                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3106                 } else {
3107                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3108                 }
3109
3110                 if (dev->phy.rev == 2)
3111                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3112                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3113                 else if (dev->phy.rev < 2)
3114                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3115                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
3116
3117                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3118                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
3119         } else {
3120                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3121                                     nphy->adj_pwr_tbl);
3122                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3123                                     nphy->adj_pwr_tbl);
3124
3125                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3126                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3127                 /* wl does useless check for "enable" param here */
3128                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3129                 if (dev->phy.rev >= 3) {
3130                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3131                         if (val)
3132                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3133                 }
3134                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
3135
3136                 if (band == IEEE80211_BAND_5GHZ) {
3137                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3138                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3139                         if (dev->phy.rev > 1)
3140                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3141                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3142                                                 0x64);
3143                 }
3144
3145                 if (dev->phy.rev >= 3) {
3146                         if (nphy->tx_pwr_idx[0] != 128 &&
3147                             nphy->tx_pwr_idx[1] != 128) {
3148                                 /* Recover TX pwr ctl state */
3149                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3150                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
3151                                                 nphy->tx_pwr_idx[0]);
3152                                 if (dev->phy.rev > 1)
3153                                         b43_phy_maskset(dev,
3154                                                 B43_NPHY_TXPCTL_INIT,
3155                                                 ~0xff, nphy->tx_pwr_idx[1]);
3156                         }
3157                 }
3158
3159                 if (dev->phy.rev >= 3) {
3160                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3161                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3162                 } else {
3163                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3164                 }
3165
3166                 if (dev->phy.rev == 2)
3167                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3168                 else if (dev->phy.rev < 2)
3169                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3170
3171                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3172                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
3173
3174                 if (b43_nphy_ipa(dev)) {
3175                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3176                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
3177                 }
3178         }
3179
3180         if (nphy->hang_avoid)
3181                 b43_nphy_stay_in_carrier_search(dev, 0);
3182 }
3183
3184 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
3185 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
3186 {
3187         struct b43_phy_n *nphy = dev->phy.n;
3188         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3189
3190         u8 txpi[2], bbmult, i;
3191         u16 tmp, radio_gain, dac_gain;
3192         u16 freq = dev->phy.channel_freq;
3193         u32 txgain;
3194         /* u32 gaintbl; rev3+ */
3195
3196         if (nphy->hang_avoid)
3197                 b43_nphy_stay_in_carrier_search(dev, 1);
3198
3199         if (dev->phy.rev >= 7) {
3200                 txpi[0] = txpi[1] = 30;
3201         } else if (dev->phy.rev >= 3) {
3202                 txpi[0] = 40;
3203                 txpi[1] = 40;
3204         } else if (sprom->revision < 4) {
3205                 txpi[0] = 72;
3206                 txpi[1] = 72;
3207         } else {
3208                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3209                         txpi[0] = sprom->txpid2g[0];
3210                         txpi[1] = sprom->txpid2g[1];
3211                 } else if (freq >= 4900 && freq < 5100) {
3212                         txpi[0] = sprom->txpid5gl[0];
3213                         txpi[1] = sprom->txpid5gl[1];
3214                 } else if (freq >= 5100 && freq < 5500) {
3215                         txpi[0] = sprom->txpid5g[0];
3216                         txpi[1] = sprom->txpid5g[1];
3217                 } else if (freq >= 5500) {
3218                         txpi[0] = sprom->txpid5gh[0];
3219                         txpi[1] = sprom->txpid5gh[1];
3220                 } else {
3221                         txpi[0] = 91;
3222                         txpi[1] = 91;
3223                 }
3224         }
3225         if (dev->phy.rev < 7 &&
3226             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
3227                 txpi[0] = txpi[1] = 91;
3228
3229         /*
3230         for (i = 0; i < 2; i++) {
3231                 nphy->txpwrindex[i].index_internal = txpi[i];
3232                 nphy->txpwrindex[i].index_internal_save = txpi[i];
3233         }
3234         */
3235
3236         for (i = 0; i < 2; i++) {
3237                 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3238
3239                 if (dev->phy.rev >= 3)
3240                         radio_gain = (txgain >> 16) & 0x1FFFF;
3241                 else
3242                         radio_gain = (txgain >> 16) & 0x1FFF;
3243
3244                 if (dev->phy.rev >= 7)
3245                         dac_gain = (txgain >> 8) & 0x7;
3246                 else
3247                         dac_gain = (txgain >> 8) & 0x3F;
3248                 bbmult = txgain & 0xFF;
3249
3250                 if (dev->phy.rev >= 3) {
3251                         if (i == 0)
3252                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3253                         else
3254                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3255                 } else {
3256                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3257                 }
3258
3259                 if (i == 0)
3260                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3261                 else
3262                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
3263
3264                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
3265
3266                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
3267                 if (i == 0)
3268                         tmp = (tmp & 0x00FF) | (bbmult << 8);
3269                 else
3270                         tmp = (tmp & 0xFF00) | bbmult;
3271                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
3272
3273                 if (b43_nphy_ipa(dev)) {
3274                         u32 tmp32;
3275                         u16 reg = (i == 0) ?
3276                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
3277                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3278                                                               576 + txpi[i]));
3279                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3280                         b43_phy_set(dev, reg, 0x4);
3281                 }
3282         }
3283
3284         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
3285
3286         if (nphy->hang_avoid)
3287                 b43_nphy_stay_in_carrier_search(dev, 0);
3288 }
3289
3290 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3291 {
3292         struct b43_phy *phy = &dev->phy;
3293
3294         u8 core;
3295         u16 r; /* routing */
3296
3297         if (phy->rev >= 7) {
3298                 for (core = 0; core < 2; core++) {
3299                         r = core ? 0x190 : 0x170;
3300                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3301                                 b43_radio_write(dev, r + 0x5, 0x5);
3302                                 b43_radio_write(dev, r + 0x9, 0xE);
3303                                 if (phy->rev != 5)
3304                                         b43_radio_write(dev, r + 0xA, 0);
3305                                 if (phy->rev != 7)
3306                                         b43_radio_write(dev, r + 0xB, 1);
3307                                 else
3308                                         b43_radio_write(dev, r + 0xB, 0x31);
3309                         } else {
3310                                 b43_radio_write(dev, r + 0x5, 0x9);
3311                                 b43_radio_write(dev, r + 0x9, 0xC);
3312                                 b43_radio_write(dev, r + 0xB, 0x0);
3313                                 if (phy->rev != 5)
3314                                         b43_radio_write(dev, r + 0xA, 1);
3315                                 else
3316                                         b43_radio_write(dev, r + 0xA, 0x31);
3317                         }
3318                         b43_radio_write(dev, r + 0x6, 0);
3319                         b43_radio_write(dev, r + 0x7, 0);
3320                         b43_radio_write(dev, r + 0x8, 3);
3321                         b43_radio_write(dev, r + 0xC, 0);
3322                 }
3323         } else {
3324                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3325                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3326                 else
3327                         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3328                 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3329                 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3330
3331                 for (core = 0; core < 2; core++) {
3332                         r = core ? B2056_TX1 : B2056_TX0;
3333
3334                         b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3335                         b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3336                         b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3337                         b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3338                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3339                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3340                         b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3341                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3342                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3343                                                 0x5);
3344                                 if (phy->rev != 5)
3345                                         b43_radio_write(dev, r | B2056_TX_TSSIA,
3346                                                         0x00);
3347                                 if (phy->rev >= 5)
3348                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3349                                                         0x31);
3350                                 else
3351                                         b43_radio_write(dev, r | B2056_TX_TSSIG,
3352                                                         0x11);
3353                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3354                                                 0xE);
3355                         } else {
3356                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3357                                                 0x9);
3358                                 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3359                                 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3360                                 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3361                                                 0xC);
3362                         }
3363                 }
3364         }
3365 }
3366
3367 /*
3368  * Stop radio and transmit known signal. Then check received signal strength to
3369  * get TSSI (Transmit Signal Strength Indicator).
3370  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3371  */
3372 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3373 {
3374         struct b43_phy *phy = &dev->phy;
3375         struct b43_phy_n *nphy = dev->phy.n;
3376
3377         u32 tmp;
3378         s32 rssi[4] = { };
3379
3380         /* TODO: check if we can transmit */
3381
3382         if (b43_nphy_ipa(dev))
3383                 b43_nphy_ipa_internal_tssi_setup(dev);
3384
3385         if (phy->rev >= 7)
3386                 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3387         else if (phy->rev >= 3)
3388                 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3389
3390         b43_nphy_stop_playback(dev);
3391         b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3392         udelay(20);
3393         tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3394         b43_nphy_stop_playback(dev);
3395         b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3396
3397         if (phy->rev >= 7)
3398                 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3399         else if (phy->rev >= 3)
3400                 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3401
3402         if (phy->rev >= 3) {
3403                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3404                 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3405         } else {
3406                 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3407                 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3408         }
3409         nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3410         nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3411 }
3412
3413 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3414 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3415 {
3416         struct b43_phy_n *nphy = dev->phy.n;
3417
3418         u8 idx, delta;
3419         u8 i, stf_mode;
3420
3421         /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3422          * 21 groups, each containing 4 entries.
3423          *
3424          * First group has entries for CCK modulation.
3425          * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3426          *
3427          * Group 0 is for CCK
3428          * Groups 1..4 use BPSK (group per coding rate)
3429          * Groups 5..8 use QPSK (group per coding rate)
3430          * Groups 9..12 use 16-QAM (group per coding rate)
3431          * Groups 13..16 use 64-QAM (group per coding rate)
3432          * Groups 17..20 are unknown
3433          */
3434
3435         for (i = 0; i < 4; i++)
3436                 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3437
3438         for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3439                 delta = 0;
3440                 switch (stf_mode) {
3441                 case 0:
3442                         if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3443                                 idx = 68;
3444                         } else {
3445                                 delta = 1;
3446                                 idx = dev->phy.is_40mhz ? 52 : 4;
3447                         }
3448                         break;
3449                 case 1:
3450                         idx = dev->phy.is_40mhz ? 76 : 28;
3451                         break;
3452                 case 2:
3453                         idx = dev->phy.is_40mhz ? 84 : 36;
3454                         break;
3455                 case 3:
3456                         idx = dev->phy.is_40mhz ? 92 : 44;
3457                         break;
3458                 }
3459
3460                 for (i = 0; i < 20; i++) {
3461                         nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3462                                 nphy->tx_power_offset[idx];
3463                         if (i == 0)
3464                                 idx += delta;
3465                         if (i == 14)
3466                                 idx += 1 - delta;
3467                         if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3468                             i == 13)
3469                                 idx += 1;
3470                 }
3471         }
3472 }
3473
3474 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3475 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3476 {
3477         struct b43_phy_n *nphy = dev->phy.n;
3478         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3479
3480         s16 a1[2], b0[2], b1[2];
3481         u8 idle[2];
3482         s8 target[2];
3483         s32 num, den, pwr;
3484         u32 regval[64];
3485
3486         u16 freq = dev->phy.channel_freq;
3487         u16 tmp;
3488         u16 r; /* routing */
3489         u8 i, c;
3490
3491         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3492                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3493                 b43_read32(dev, B43_MMIO_MACCTL);
3494                 udelay(1);
3495         }
3496
3497         if (nphy->hang_avoid)
3498                 b43_nphy_stay_in_carrier_search(dev, true);
3499
3500         b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3501         if (dev->phy.rev >= 3)
3502                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3503                              ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3504         else
3505                 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3506                             B43_NPHY_TXPCTL_CMD_PCTLEN);
3507
3508         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3509                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3510
3511         if (sprom->revision < 4) {
3512                 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3513                 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3514                 target[0] = target[1] = 52;
3515                 a1[0] = a1[1] = -424;
3516                 b0[0] = b0[1] = 5612;
3517                 b1[0] = b1[1] = -1393;
3518         } else {
3519                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3520                         for (c = 0; c < 2; c++) {
3521                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3522                                 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3523                                 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3524                                 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3525                                 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3526                         }
3527                 } else if (freq >= 4900 && freq < 5100) {
3528                         for (c = 0; c < 2; c++) {
3529                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3530                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3531                                 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3532                                 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3533                                 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3534                         }
3535                 } else if (freq >= 5100 && freq < 5500) {
3536                         for (c = 0; c < 2; c++) {
3537                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3538                                 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3539                                 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3540                                 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3541                                 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3542                         }
3543                 } else if (freq >= 5500) {
3544                         for (c = 0; c < 2; c++) {
3545                                 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3546                                 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3547                                 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3548                                 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3549                                 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3550                         }
3551                 } else {
3552                         idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3553                         idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3554                         target[0] = target[1] = 52;
3555                         a1[0] = a1[1] = -424;
3556                         b0[0] = b0[1] = 5612;
3557                         b1[0] = b1[1] = -1393;
3558                 }
3559         }
3560         /* target[0] = target[1] = nphy->tx_power_max; */
3561
3562         if (dev->phy.rev >= 3) {
3563                 if (sprom->fem.ghz2.tssipos)
3564                         b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3565                 if (dev->phy.rev >= 7) {
3566                         for (c = 0; c < 2; c++) {
3567                                 r = c ? 0x190 : 0x170;
3568                                 if (b43_nphy_ipa(dev))
3569                                         b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3570                         }
3571                 } else {
3572                         if (b43_nphy_ipa(dev)) {
3573                                 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3574                                 b43_radio_write(dev,
3575                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3576                                 b43_radio_write(dev,
3577                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3578                         } else {
3579                                 b43_radio_write(dev,
3580                                         B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3581                                 b43_radio_write(dev,
3582                                         B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3583                         }
3584                 }
3585         }
3586
3587         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3588                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3589                 b43_read32(dev, B43_MMIO_MACCTL);
3590                 udelay(1);
3591         }
3592
3593         if (dev->phy.rev >= 7) {
3594                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3595                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3596                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3597                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3598         } else {
3599                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3600                                 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3601                 if (dev->phy.rev > 1)
3602                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3603                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3604         }
3605
3606         if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3607                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3608
3609         b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3610                       0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3611                       3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3612         b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3613                       idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3614                       idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3615                       B43_NPHY_TXPCTL_ITSSI_BINF);
3616         b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3617                       target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3618                       target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3619
3620         for (c = 0; c < 2; c++) {
3621                 for (i = 0; i < 64; i++) {
3622                         num = 8 * (16 * b0[c] + b1[c] * i);
3623                         den = 32768 + a1[c] * i;
3624                         pwr = max((4 * num + den / 2) / den, -8);
3625                         if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3626                                 pwr = max(pwr, target[c] + 1);
3627                         regval[i] = pwr;
3628                 }
3629                 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3630         }
3631
3632         b43_nphy_tx_prepare_adjusted_power_table(dev);
3633         b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3634         b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3635
3636         if (nphy->hang_avoid)
3637                 b43_nphy_stay_in_carrier_search(dev, false);
3638 }
3639
3640 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3641 {
3642         struct b43_phy *phy = &dev->phy;
3643
3644         const u32 *table = NULL;
3645         u32 rfpwr_offset;
3646         u8 pga_gain;
3647         int i;
3648
3649         table = b43_nphy_get_tx_gain_table(dev);
3650         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3651         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3652
3653         if (phy->rev >= 3) {
3654 #if 0
3655                 nphy->gmval = (table[0] >> 16) & 0x7000;
3656 #endif
3657
3658                 for (i = 0; i < 128; i++) {
3659                         pga_gain = (table[i] >> 24) & 0xF;
3660                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3661                                 rfpwr_offset =
3662                                  b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
3663                         else
3664                                 rfpwr_offset =
3665                                  0; /* FIXME */
3666                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3667                                        rfpwr_offset);
3668                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3669                                        rfpwr_offset);
3670                 }
3671         }
3672 }
3673
3674 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3675 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
3676 {
3677         struct b43_phy_n *nphy = dev->phy.n;
3678         enum ieee80211_band band;
3679         u16 tmp;
3680
3681         if (!enable) {
3682                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3683                                                        B43_NPHY_RFCTL_INTC1);
3684                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3685                                                        B43_NPHY_RFCTL_INTC2);
3686                 band = b43_current_band(dev->wl);
3687                 if (dev->phy.rev >= 3) {
3688                         if (band == IEEE80211_BAND_5GHZ)
3689                                 tmp = 0x600;
3690                         else
3691                                 tmp = 0x480;
3692                 } else {
3693                         if (band == IEEE80211_BAND_5GHZ)
3694                                 tmp = 0x180;
3695                         else
3696                                 tmp = 0x120;
3697                 }
3698                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3699                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3700         } else {
3701                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3702                                 nphy->rfctrl_intc1_save);
3703                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3704                                 nphy->rfctrl_intc2_save);
3705         }
3706 }
3707
3708 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3709 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3710 {
3711         u16 tmp;
3712
3713         if (dev->phy.rev >= 3) {
3714                 if (b43_nphy_ipa(dev)) {
3715                         tmp = 4;
3716                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3717                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3718                 }
3719
3720                 tmp = 1;
3721                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3722                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3723         }
3724 }
3725
3726 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3727 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3728                                 u16 samps, u8 time, bool wait)
3729 {
3730         int i;
3731         u16 tmp;
3732
3733         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3734         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3735         if (wait)
3736                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
3737         else
3738                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
3739
3740         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3741
3742         for (i = 1000; i; i--) {
3743                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3744                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3745                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3746                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3747                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3748                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3749                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3750                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3751
3752                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3753                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3754                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3755                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3756                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3757                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3758                         return;
3759                 }
3760                 udelay(10);
3761         }
3762         memset(est, 0, sizeof(*est));
3763 }
3764
3765 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3766 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3767                                         struct b43_phy_n_iq_comp *pcomp)
3768 {
3769         if (write) {
3770                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3771                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3772                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3773                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
3774         } else {
3775                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3776                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3777                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3778                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3779         }
3780 }
3781
3782 #if 0
3783 /* Ready but not used anywhere */
3784 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3785 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3786 {
3787         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3788
3789         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3790         if (core == 0) {
3791                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3792                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3793         } else {
3794                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3795                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3796         }
3797         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3798         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3799         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3800         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3801         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3802         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3803         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3804         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3805 }
3806
3807 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3808 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3809 {
3810         u8 rxval, txval;
3811         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3812
3813         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3814         if (core == 0) {
3815                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3816                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3817         } else {
3818                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3819                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3820         }
3821         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3822         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3823         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3824         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3825         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3826         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3827         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3828         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3829
3830         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3831         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3832
3833         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3834                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3835                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3836         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3837                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3838         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3839                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3840         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3841                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
3842
3843         if (core == 0) {
3844                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3845                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3846         } else {
3847                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3848                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3849         }
3850
3851         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
3852         b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
3853         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3854
3855         if (core == 0) {
3856                 rxval = 1;
3857                 txval = 8;
3858         } else {
3859                 rxval = 4;
3860                 txval = 2;
3861         }
3862         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3863                                       core + 1);
3864         b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3865                                       2 - core);
3866 }
3867 #endif
3868
3869 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3870 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3871 {
3872         int i;
3873         s32 iq;
3874         u32 ii;
3875         u32 qq;
3876         int iq_nbits, qq_nbits;
3877         int arsh, brsh;
3878         u16 tmp, a, b;
3879
3880         struct nphy_iq_est est;
3881         struct b43_phy_n_iq_comp old;
3882         struct b43_phy_n_iq_comp new = { };
3883         bool error = false;
3884
3885         if (mask == 0)
3886                 return;
3887
3888         b43_nphy_rx_iq_coeffs(dev, false, &old);
3889         b43_nphy_rx_iq_coeffs(dev, true, &new);
3890         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3891         new = old;
3892
3893         for (i = 0; i < 2; i++) {
3894                 if (i == 0 && (mask & 1)) {
3895                         iq = est.iq0_prod;
3896                         ii = est.i0_pwr;
3897                         qq = est.q0_pwr;
3898                 } else if (i == 1 && (mask & 2)) {
3899                         iq = est.iq1_prod;
3900                         ii = est.i1_pwr;
3901                         qq = est.q1_pwr;
3902                 } else {
3903                         continue;
3904                 }
3905
3906                 if (ii + qq < 2) {
3907                         error = true;
3908                         break;
3909                 }
3910
3911                 iq_nbits = fls(abs(iq));
3912                 qq_nbits = fls(qq);
3913
3914                 arsh = iq_nbits - 20;
3915                 if (arsh >= 0) {
3916                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3917                         tmp = ii >> arsh;
3918                 } else {
3919                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3920                         tmp = ii << -arsh;
3921                 }
3922                 if (tmp == 0) {
3923                         error = true;
3924                         break;
3925                 }
3926                 a /= tmp;
3927
3928                 brsh = qq_nbits - 11;
3929                 if (brsh >= 0) {
3930                         b = (qq << (31 - qq_nbits));
3931                         tmp = ii >> brsh;
3932                 } else {
3933                         b = (qq << (31 - qq_nbits));
3934                         tmp = ii << -brsh;
3935                 }
3936                 if (tmp == 0) {
3937                         error = true;
3938                         break;
3939                 }
3940                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3941
3942                 if (i == 0 && (mask & 0x1)) {
3943                         if (dev->phy.rev >= 3) {
3944                                 new.a0 = a & 0x3FF;
3945                                 new.b0 = b & 0x3FF;
3946                         } else {
3947                                 new.a0 = b & 0x3FF;
3948                                 new.b0 = a & 0x3FF;
3949                         }
3950                 } else if (i == 1 && (mask & 0x2)) {
3951                         if (dev->phy.rev >= 3) {
3952                                 new.a1 = a & 0x3FF;
3953                                 new.b1 = b & 0x3FF;
3954                         } else {
3955                                 new.a1 = b & 0x3FF;
3956                                 new.b1 = a & 0x3FF;
3957                         }
3958                 }
3959         }
3960
3961         if (error)
3962                 new = old;
3963
3964         b43_nphy_rx_iq_coeffs(dev, true, &new);
3965 }
3966
3967 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3968 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3969 {
3970         u16 array[4];
3971         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3972
3973         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3974         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3975         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3976         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3977 }
3978
3979 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3980 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3981 {
3982         struct b43_phy_n *nphy = dev->phy.n;
3983
3984         u8 channel = dev->phy.channel;
3985         int tone[2] = { 57, 58 };
3986         u32 noise[2] = { 0x3FF, 0x3FF };
3987
3988         B43_WARN_ON(dev->phy.rev < 3);
3989
3990         if (nphy->hang_avoid)
3991                 b43_nphy_stay_in_carrier_search(dev, 1);
3992
3993         if (nphy->gband_spurwar_en) {
3994                 /* TODO: N PHY Adjust Analog Pfbw (7) */
3995                 if (channel == 11 && dev->phy.is_40mhz)
3996                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3997                 else
3998                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3999                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
4000         }
4001
4002         if (nphy->aband_spurwar_en) {
4003                 if (channel == 54) {
4004                         tone[0] = 0x20;
4005                         noise[0] = 0x25F;
4006                 } else if (channel == 38 || channel == 102 || channel == 118) {
4007                         if (0 /* FIXME */) {
4008                                 tone[0] = 0x20;
4009                                 noise[0] = 0x21F;
4010                         } else {
4011                                 tone[0] = 0;
4012                                 noise[0] = 0;
4013                         }
4014                 } else if (channel == 134) {
4015                         tone[0] = 0x20;
4016                         noise[0] = 0x21F;
4017                 } else if (channel == 151) {
4018                         tone[0] = 0x10;
4019                         noise[0] = 0x23F;
4020                 } else if (channel == 153 || channel == 161) {
4021                         tone[0] = 0x30;
4022                         noise[0] = 0x23F;
4023                 } else {
4024                         tone[0] = 0;
4025                         noise[0] = 0;
4026                 }
4027
4028                 if (!tone[0] && !noise[0])
4029                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
4030                 else
4031                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4032         }
4033
4034         if (nphy->hang_avoid)
4035                 b43_nphy_stay_in_carrier_search(dev, 0);
4036 }
4037
4038 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4039 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4040 {
4041         struct b43_phy_n *nphy = dev->phy.n;
4042         int i, j;
4043         u32 tmp;
4044         u32 cur_real, cur_imag, real_part, imag_part;
4045
4046         u16 buffer[7];
4047
4048         if (nphy->hang_avoid)
4049                 b43_nphy_stay_in_carrier_search(dev, true);
4050
4051         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4052
4053         for (i = 0; i < 2; i++) {
4054                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4055                         (buffer[i * 2 + 1] & 0x3FF);
4056                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4057                                 (((i + 26) << 10) | 320));
4058                 for (j = 0; j < 128; j++) {
4059                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4060                                         ((tmp >> 16) & 0xFFFF));
4061                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4062                                         (tmp & 0xFFFF));
4063                 }
4064         }
4065
4066         for (i = 0; i < 2; i++) {
4067                 tmp = buffer[5 + i];
4068                 real_part = (tmp >> 8) & 0xFF;
4069                 imag_part = (tmp & 0xFF);
4070                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4071                                 (((i + 26) << 10) | 448));
4072
4073                 if (dev->phy.rev >= 3) {
4074                         cur_real = real_part;
4075                         cur_imag = imag_part;
4076                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4077                 }
4078
4079                 for (j = 0; j < 128; j++) {
4080                         if (dev->phy.rev < 3) {
4081                                 cur_real = (real_part * loscale[j] + 128) >> 8;
4082                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4083                                 tmp = ((cur_real & 0xFF) << 8) |
4084                                         (cur_imag & 0xFF);
4085                         }
4086                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4087                                         ((tmp >> 16) & 0xFFFF));
4088                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4089                                         (tmp & 0xFFFF));
4090                 }
4091         }
4092
4093         if (dev->phy.rev >= 3) {
4094                 b43_shm_write16(dev, B43_SHM_SHARED,
4095                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4096                 b43_shm_write16(dev, B43_SHM_SHARED,
4097                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4098         }
4099
4100         if (nphy->hang_avoid)
4101                 b43_nphy_stay_in_carrier_search(dev, false);
4102 }
4103
4104 /*
4105  * Restore RSSI Calibration
4106  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4107  */
4108 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4109 {
4110         struct b43_phy_n *nphy = dev->phy.n;
4111
4112         u16 *rssical_radio_regs = NULL;
4113         u16 *rssical_phy_regs = NULL;
4114
4115         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4116                 if (!nphy->rssical_chanspec_2G.center_freq)
4117                         return;
4118                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4119                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4120         } else {
4121                 if (!nphy->rssical_chanspec_5G.center_freq)
4122                         return;
4123                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4124                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4125         }
4126
4127         if (dev->phy.rev >= 7) {
4128         } else {
4129                 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4130                                   rssical_radio_regs[0]);
4131                 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4132                                   rssical_radio_regs[1]);
4133         }
4134
4135         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4136         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4137         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4138         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4139
4140         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4141         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4142         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4143         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4144
4145         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4146         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4147         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4148         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4149 }
4150
4151 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4152 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4153 {
4154         struct b43_phy_n *nphy = dev->phy.n;
4155         u16 *save = nphy->tx_rx_cal_radio_saveregs;
4156         u16 tmp;
4157         u8 offset, i;
4158
4159         if (dev->phy.rev >= 3) {
4160             for (i = 0; i < 2; i++) {
4161                 tmp = (i == 0) ? 0x2000 : 0x3000;
4162                 offset = i * 11;
4163
4164                 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4165                 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4166                 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4167                 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4168                 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4169                 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4170                 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4171                 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4172                 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4173                 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4174                 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
4175
4176                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4177                         b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4178                         b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4179                         b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4180                         b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4181                         b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4182                         if (nphy->ipa5g_on) {
4183                                 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4184                                 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
4185                         } else {
4186                                 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4187                                 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
4188                         }
4189                         b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4190                 } else {
4191                         b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4192                         b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4193                         b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4194                         b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4195                         b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4196                         b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
4197                         if (nphy->ipa2g_on) {
4198                                 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4199                                 b43_radio_write(dev, tmp | B2055_XOCTL2,
4200                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
4201                         } else {
4202                                 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4203                                 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
4204                         }
4205                 }
4206                 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4207                 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4208                 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
4209             }
4210         } else {
4211                 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4212                 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
4213
4214                 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4215                 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
4216
4217                 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4218                 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
4219
4220                 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4221                 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4222
4223                 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4224                 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4225
4226                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4227                     B43_NPHY_BANDCTL_5GHZ)) {
4228                         b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4229                         b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4230                 } else {
4231                         b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4232                         b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4233                 }
4234
4235                 if (dev->phy.rev < 2) {
4236                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4237                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4238                 } else {
4239                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4240                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4241                 }
4242         }
4243 }
4244
4245 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4246 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4247 {
4248         struct b43_phy_n *nphy = dev->phy.n;
4249         int i;
4250         u16 scale, entry;
4251
4252         u16 tmp = nphy->txcal_bbmult;
4253         if (core == 0)
4254                 tmp >>= 8;
4255         tmp &= 0xff;
4256
4257         for (i = 0; i < 18; i++) {
4258                 scale = (ladder_lo[i].percent * tmp) / 100;
4259                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
4260                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
4261
4262                 scale = (ladder_iq[i].percent * tmp) / 100;
4263                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
4264                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
4265         }
4266 }
4267
4268 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4269 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4270 {
4271         int i;
4272         for (i = 0; i < 15; i++)
4273                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4274                                 tbl_tx_filter_coef_rev4[2][i]);
4275 }
4276
4277 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4278 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4279 {
4280         int i, j;
4281         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4282         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4283
4284         for (i = 0; i < 3; i++)
4285                 for (j = 0; j < 15; j++)
4286                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4287                                         tbl_tx_filter_coef_rev4[i][j]);
4288
4289         if (dev->phy.is_40mhz) {
4290                 for (j = 0; j < 15; j++)
4291                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4292                                         tbl_tx_filter_coef_rev4[3][j]);
4293         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4294                 for (j = 0; j < 15; j++)
4295                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4296                                         tbl_tx_filter_coef_rev4[5][j]);
4297         }
4298
4299         if (dev->phy.channel == 14)
4300                 for (j = 0; j < 15; j++)
4301                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4302                                         tbl_tx_filter_coef_rev4[6][j]);
4303 }
4304
4305 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4306 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4307 {
4308         struct b43_phy_n *nphy = dev->phy.n;
4309
4310         u16 curr_gain[2];
4311         struct nphy_txgains target;
4312         const u32 *table = NULL;
4313
4314         if (!nphy->txpwrctrl) {
4315                 int i;
4316
4317                 if (nphy->hang_avoid)
4318                         b43_nphy_stay_in_carrier_search(dev, true);
4319                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
4320                 if (nphy->hang_avoid)
4321                         b43_nphy_stay_in_carrier_search(dev, false);
4322
4323                 for (i = 0; i < 2; ++i) {
4324                         if (dev->phy.rev >= 3) {
4325                                 target.ipa[i] = curr_gain[i] & 0x000F;
4326                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4327                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4328                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4329                         } else {
4330                                 target.ipa[i] = curr_gain[i] & 0x0003;
4331                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4332                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4333                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4334                         }
4335                 }
4336         } else {
4337                 int i;
4338                 u16 index[2];
4339                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4340                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4341                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4342                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4343                         B43_NPHY_TXPCTL_STAT_BIDX) >>
4344                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4345
4346                 for (i = 0; i < 2; ++i) {
4347                         table = b43_nphy_get_tx_gain_table(dev);
4348                         if (dev->phy.rev >= 3) {
4349                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4350                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4351                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4352                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4353                         } else {
4354                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4355                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4356                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4357                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4358                         }
4359                 }
4360         }
4361
4362         return target;
4363 }
4364
4365 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4366 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4367 {
4368         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4369
4370         if (dev->phy.rev >= 3) {
4371                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4372                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4373                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4374                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4375                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
4376                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4377                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
4378                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4379                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4380                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4381                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4382                 b43_nphy_reset_cca(dev);
4383         } else {
4384                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4385                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4386                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
4387                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4388                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
4389                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4390                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4391         }
4392 }
4393
4394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4395 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4396 {
4397         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4398         u16 tmp;
4399
4400         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4401         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4402         if (dev->phy.rev >= 3) {
4403                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4404                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4405
4406                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4407                 regs[2] = tmp;
4408                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4409
4410                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4411                 regs[3] = tmp;
4412                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4413
4414                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
4415                 b43_phy_mask(dev, B43_NPHY_BBCFG,
4416                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4417
4418                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
4419                 regs[5] = tmp;
4420                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
4421
4422                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
4423                 regs[6] = tmp;
4424                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
4425                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4426                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4427
4428                 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4429                 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4430                 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
4431
4432                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4433                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4434                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4435                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4436         } else {
4437                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4438                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4439                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4440                 regs[2] = tmp;
4441                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
4442                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
4443                 regs[3] = tmp;
4444                 tmp |= 0x2000;
4445                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
4446                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
4447                 regs[4] = tmp;
4448                 tmp |= 0x2000;
4449                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
4450                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4451                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4452                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4453                         tmp = 0x0180;
4454                 else
4455                         tmp = 0x0120;
4456                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4457                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4458         }
4459 }
4460
4461 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4462 static void b43_nphy_save_cal(struct b43_wldev *dev)
4463 {
4464         struct b43_phy_n *nphy = dev->phy.n;
4465
4466         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4467         u16 *txcal_radio_regs = NULL;
4468         struct b43_chanspec *iqcal_chanspec;
4469         u16 *table = NULL;
4470
4471         if (nphy->hang_avoid)
4472                 b43_nphy_stay_in_carrier_search(dev, 1);
4473
4474         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4475                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4476                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4477                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4478                 table = nphy->cal_cache.txcal_coeffs_2G;
4479         } else {
4480                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4481                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4482                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4483                 table = nphy->cal_cache.txcal_coeffs_5G;
4484         }
4485
4486         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4487         /* TODO use some definitions */
4488         if (dev->phy.rev >= 3) {
4489                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4490                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4491                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4492                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4493                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4494                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4495                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4496                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4497         } else {
4498                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4499                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4500                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4501                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4502         }
4503         iqcal_chanspec->center_freq = dev->phy.channel_freq;
4504         iqcal_chanspec->channel_type = dev->phy.channel_type;
4505         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
4506
4507         if (nphy->hang_avoid)
4508                 b43_nphy_stay_in_carrier_search(dev, 0);
4509 }
4510
4511 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4512 static void b43_nphy_restore_cal(struct b43_wldev *dev)
4513 {
4514         struct b43_phy_n *nphy = dev->phy.n;
4515
4516         u16 coef[4];
4517         u16 *loft = NULL;
4518         u16 *table = NULL;
4519
4520         int i;
4521         u16 *txcal_radio_regs = NULL;
4522         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4523
4524         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4525                 if (!nphy->iqcal_chanspec_2G.center_freq)
4526                         return;
4527                 table = nphy->cal_cache.txcal_coeffs_2G;
4528                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4529         } else {
4530                 if (!nphy->iqcal_chanspec_5G.center_freq)
4531                         return;
4532                 table = nphy->cal_cache.txcal_coeffs_5G;
4533                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4534         }
4535
4536         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
4537
4538         for (i = 0; i < 4; i++) {
4539                 if (dev->phy.rev >= 3)
4540                         table[i] = coef[i];
4541                 else
4542                         coef[i] = 0;
4543         }
4544
4545         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4546         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4547         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
4548
4549         if (dev->phy.rev < 2)
4550                 b43_nphy_tx_iq_workaround(dev);
4551
4552         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4553                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4554                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4555         } else {
4556                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4557                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4558         }
4559
4560         /* TODO use some definitions */
4561         if (dev->phy.rev >= 3) {
4562                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4563                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4564                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4565                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4566                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4567                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4568                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4569                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4570         } else {
4571                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4572                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4573                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4574                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4575         }
4576         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4577 }
4578
4579 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4580 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4581                                 struct nphy_txgains target,
4582                                 bool full, bool mphase)
4583 {
4584         struct b43_phy_n *nphy = dev->phy.n;
4585         int i;
4586         int error = 0;
4587         int freq;
4588         bool avoid = false;
4589         u8 length;
4590         u16 tmp, core, type, count, max, numb, last = 0, cmd;
4591         const u16 *table;
4592         bool phy6or5x;
4593
4594         u16 buffer[11];
4595         u16 diq_start = 0;
4596         u16 save[2];
4597         u16 gain[2];
4598         struct nphy_iqcal_params params[2];
4599         bool updated[2] = { };
4600
4601         b43_nphy_stay_in_carrier_search(dev, true);
4602
4603         if (dev->phy.rev >= 4) {
4604                 avoid = nphy->hang_avoid;
4605                 nphy->hang_avoid = false;
4606         }
4607
4608         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4609
4610         for (i = 0; i < 2; i++) {
4611                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4612                 gain[i] = params[i].cal_gain;
4613         }
4614
4615         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
4616
4617         b43_nphy_tx_cal_radio_setup(dev);
4618         b43_nphy_tx_cal_phy_setup(dev);
4619
4620         phy6or5x = dev->phy.rev >= 6 ||
4621                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4622                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4623         if (phy6or5x) {
4624                 if (dev->phy.is_40mhz) {
4625                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4626                                         tbl_tx_iqlo_cal_loft_ladder_40);
4627                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4628                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
4629                 } else {
4630                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4631                                         tbl_tx_iqlo_cal_loft_ladder_20);
4632                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4633                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
4634                 }
4635         }
4636
4637         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4638
4639         if (!dev->phy.is_40mhz)
4640                 freq = 2500;
4641         else
4642                 freq = 5000;
4643
4644         if (nphy->mphase_cal_phase_id > 2)
4645                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4646                                         0xFFFF, 0, true, false);
4647         else
4648                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
4649
4650         if (error == 0) {
4651                 if (nphy->mphase_cal_phase_id > 2) {
4652                         table = nphy->mphase_txcal_bestcoeffs;
4653                         length = 11;
4654                         if (dev->phy.rev < 3)
4655                                 length -= 2;
4656                 } else {
4657                         if (!full && nphy->txiqlocal_coeffsvalid) {
4658                                 table = nphy->txiqlocal_bestc;
4659                                 length = 11;
4660                                 if (dev->phy.rev < 3)
4661                                         length -= 2;
4662                         } else {
4663                                 full = true;
4664                                 if (dev->phy.rev >= 3) {
4665                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4666                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4667                                 } else {
4668                                         table = tbl_tx_iqlo_cal_startcoefs;
4669                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4670                                 }
4671                         }
4672                 }
4673
4674                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
4675
4676                 if (full) {
4677                         if (dev->phy.rev >= 3)
4678                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4679                         else
4680                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4681                 } else {
4682                         if (dev->phy.rev >= 3)
4683                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4684                         else
4685                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4686                 }
4687
4688                 if (mphase) {
4689                         count = nphy->mphase_txcal_cmdidx;
4690                         numb = min(max,
4691                                 (u16)(count + nphy->mphase_txcal_numcmds));
4692                 } else {
4693                         count = 0;
4694                         numb = max;
4695                 }
4696
4697                 for (; count < numb; count++) {
4698                         if (full) {
4699                                 if (dev->phy.rev >= 3)
4700                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4701                                 else
4702                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4703                         } else {
4704                                 if (dev->phy.rev >= 3)
4705                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4706                                 else
4707                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4708                         }
4709
4710                         core = (cmd & 0x3000) >> 12;
4711                         type = (cmd & 0x0F00) >> 8;
4712
4713                         if (phy6or5x && updated[core] == 0) {
4714                                 b43_nphy_update_tx_cal_ladder(dev, core);
4715                                 updated[core] = true;
4716                         }
4717
4718                         tmp = (params[core].ncorr[type] << 8) | 0x66;
4719                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4720
4721                         if (type == 1 || type == 3 || type == 4) {
4722                                 buffer[0] = b43_ntab_read(dev,
4723                                                 B43_NTAB16(15, 69 + core));
4724                                 diq_start = buffer[0];
4725                                 buffer[0] = 0;
4726                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4727                                                 0);
4728                         }
4729
4730                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4731                         for (i = 0; i < 2000; i++) {
4732                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4733                                 if (tmp & 0xC000)
4734                                         break;
4735                                 udelay(10);
4736                         }
4737
4738                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4739                                                 buffer);
4740                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4741                                                 buffer);
4742
4743                         if (type == 1 || type == 3 || type == 4)
4744                                 buffer[0] = diq_start;
4745                 }
4746
4747                 if (mphase)
4748                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4749
4750                 last = (dev->phy.rev < 3) ? 6 : 7;
4751
4752                 if (!mphase || nphy->mphase_cal_phase_id == last) {
4753                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
4754                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
4755                         if (dev->phy.rev < 3) {
4756                                 buffer[0] = 0;
4757                                 buffer[1] = 0;
4758                                 buffer[2] = 0;
4759                                 buffer[3] = 0;
4760                         }
4761                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4762                                                 buffer);
4763                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
4764                                                 buffer);
4765                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4766                                                 buffer);
4767                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4768                                                 buffer);
4769                         length = 11;
4770                         if (dev->phy.rev < 3)
4771                                 length -= 2;
4772                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4773                                                 nphy->txiqlocal_bestc);
4774                         nphy->txiqlocal_coeffsvalid = true;
4775                         nphy->txiqlocal_chanspec.center_freq =
4776                                                         dev->phy.channel_freq;
4777                         nphy->txiqlocal_chanspec.channel_type =
4778                                                         dev->phy.channel_type;
4779                 } else {
4780                         length = 11;
4781                         if (dev->phy.rev < 3)
4782                                 length -= 2;
4783                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4784                                                 nphy->mphase_txcal_bestcoeffs);
4785                 }
4786
4787                 b43_nphy_stop_playback(dev);
4788                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4789         }
4790
4791         b43_nphy_tx_cal_phy_cleanup(dev);
4792         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
4793
4794         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4795                 b43_nphy_tx_iq_workaround(dev);
4796
4797         if (dev->phy.rev >= 4)
4798                 nphy->hang_avoid = avoid;
4799
4800         b43_nphy_stay_in_carrier_search(dev, false);
4801
4802         return error;
4803 }
4804
4805 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4806 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4807 {
4808         struct b43_phy_n *nphy = dev->phy.n;
4809         u8 i;
4810         u16 buffer[7];
4811         bool equal = true;
4812
4813         if (!nphy->txiqlocal_coeffsvalid ||
4814             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4815             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
4816                 return;
4817
4818         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4819         for (i = 0; i < 4; i++) {
4820                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4821                         equal = false;
4822                         break;
4823                 }
4824         }
4825
4826         if (!equal) {
4827                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4828                                         nphy->txiqlocal_bestc);
4829                 for (i = 0; i < 4; i++)
4830                         buffer[i] = 0;
4831                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4832                                         buffer);
4833                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4834                                         &nphy->txiqlocal_bestc[5]);
4835                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4836                                         &nphy->txiqlocal_bestc[5]);
4837         }
4838 }
4839
4840 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4841 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4842                         struct nphy_txgains target, u8 type, bool debug)
4843 {
4844         struct b43_phy_n *nphy = dev->phy.n;
4845         int i, j, index;
4846         u8 rfctl[2];
4847         u8 afectl_core;
4848         u16 tmp[6];
4849         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
4850         u32 real, imag;
4851         enum ieee80211_band band;
4852
4853         u8 use;
4854         u16 cur_hpf;
4855         u16 lna[3] = { 3, 3, 1 };
4856         u16 hpf1[3] = { 7, 2, 0 };
4857         u16 hpf2[3] = { 2, 0, 0 };
4858         u32 power[3] = { };
4859         u16 gain_save[2];
4860         u16 cal_gain[2];
4861         struct nphy_iqcal_params cal_params[2];
4862         struct nphy_iq_est est;
4863         int ret = 0;
4864         bool playtone = true;
4865         int desired = 13;
4866
4867         b43_nphy_stay_in_carrier_search(dev, 1);
4868
4869         if (dev->phy.rev < 2)
4870                 b43_nphy_reapply_tx_cal_coeffs(dev);
4871         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4872         for (i = 0; i < 2; i++) {
4873                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4874                 cal_gain[i] = cal_params[i].cal_gain;
4875         }
4876         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4877
4878         for (i = 0; i < 2; i++) {
4879                 if (i == 0) {
4880                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
4881                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
4882                         afectl_core = B43_NPHY_AFECTL_C1;
4883                 } else {
4884                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
4885                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
4886                         afectl_core = B43_NPHY_AFECTL_C2;
4887                 }
4888
4889                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4890                 tmp[2] = b43_phy_read(dev, afectl_core);
4891                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4892                 tmp[4] = b43_phy_read(dev, rfctl[0]);
4893                 tmp[5] = b43_phy_read(dev, rfctl[1]);
4894
4895                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4896                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4897                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4898                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4899                                 (1 - i));
4900                 b43_phy_set(dev, afectl_core, 0x0006);
4901                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4902
4903                 band = b43_current_band(dev->wl);
4904
4905                 if (nphy->rxcalparams & 0xFF000000) {
4906                         if (band == IEEE80211_BAND_5GHZ)
4907                                 b43_phy_write(dev, rfctl[0], 0x140);
4908                         else
4909                                 b43_phy_write(dev, rfctl[0], 0x110);
4910                 } else {
4911                         if (band == IEEE80211_BAND_5GHZ)
4912                                 b43_phy_write(dev, rfctl[0], 0x180);
4913                         else
4914                                 b43_phy_write(dev, rfctl[0], 0x120);
4915                 }
4916
4917                 if (band == IEEE80211_BAND_5GHZ)
4918                         b43_phy_write(dev, rfctl[1], 0x148);
4919                 else
4920                         b43_phy_write(dev, rfctl[1], 0x114);
4921
4922                 if (nphy->rxcalparams & 0x10000) {
4923                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4924                                         (i + 1));
4925                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4926                                         (2 - i));
4927                 }
4928
4929                 for (j = 0; j < 4; j++) {
4930                         if (j < 3) {
4931                                 cur_lna = lna[j];
4932                                 cur_hpf1 = hpf1[j];
4933                                 cur_hpf2 = hpf2[j];
4934                         } else {
4935                                 if (power[1] > 10000) {
4936                                         use = 1;
4937                                         cur_hpf = cur_hpf1;
4938                                         index = 2;
4939                                 } else {
4940                                         if (power[0] > 10000) {
4941                                                 use = 1;
4942                                                 cur_hpf = cur_hpf1;
4943                                                 index = 1;
4944                                         } else {
4945                                                 index = 0;
4946                                                 use = 2;
4947                                                 cur_hpf = cur_hpf2;
4948                                         }
4949                                 }
4950                                 cur_lna = lna[index];
4951                                 cur_hpf1 = hpf1[index];
4952                                 cur_hpf2 = hpf2[index];
4953                                 cur_hpf += desired - hweight32(power[index]);
4954                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
4955                                 if (use == 1)
4956                                         cur_hpf1 = cur_hpf;
4957                                 else
4958                                         cur_hpf2 = cur_hpf;
4959                         }
4960
4961                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4962                                         (cur_lna << 2));
4963                         b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
4964                                                                         false);
4965                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4966                         b43_nphy_stop_playback(dev);
4967
4968                         if (playtone) {
4969                                 ret = b43_nphy_tx_tone(dev, 4000,
4970                                                 (nphy->rxcalparams & 0xFFFF),
4971                                                 false, false);
4972                                 playtone = false;
4973                         } else {
4974                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4975                                                         false, false);
4976                         }
4977
4978                         if (ret == 0) {
4979                                 if (j < 3) {
4980                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4981                                                                         false);
4982                                         if (i == 0) {
4983                                                 real = est.i0_pwr;
4984                                                 imag = est.q0_pwr;
4985                                         } else {
4986                                                 real = est.i1_pwr;
4987                                                 imag = est.q1_pwr;
4988                                         }
4989                                         power[i] = ((real + imag) / 1024) + 1;
4990                                 } else {
4991                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4992                                 }
4993                                 b43_nphy_stop_playback(dev);
4994                         }
4995
4996                         if (ret != 0)
4997                                 break;
4998                 }
4999
5000                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5001                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5002                 b43_phy_write(dev, rfctl[1], tmp[5]);
5003                 b43_phy_write(dev, rfctl[0], tmp[4]);
5004                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5005                 b43_phy_write(dev, afectl_core, tmp[2]);
5006                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5007
5008                 if (ret != 0)
5009                         break;
5010         }
5011
5012         b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
5013         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5014         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
5015
5016         b43_nphy_stay_in_carrier_search(dev, 0);
5017
5018         return ret;
5019 }
5020
5021 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5022                         struct nphy_txgains target, u8 type, bool debug)
5023 {
5024         return -1;
5025 }
5026
5027 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5028 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5029                         struct nphy_txgains target, u8 type, bool debug)
5030 {
5031         if (dev->phy.rev >= 3)
5032                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5033         else
5034                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5035 }
5036
5037 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5038 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5039 {
5040         struct b43_phy *phy = &dev->phy;
5041         struct b43_phy_n *nphy = phy->n;
5042         /* u16 buf[16]; it's rev3+ */
5043
5044         nphy->phyrxchain = mask;
5045
5046         if (0 /* FIXME clk */)
5047                 return;
5048
5049         b43_mac_suspend(dev);
5050
5051         if (nphy->hang_avoid)
5052                 b43_nphy_stay_in_carrier_search(dev, true);
5053
5054         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5055                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5056
5057         if ((mask & 0x3) != 0x3) {
5058                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5059                 if (dev->phy.rev >= 3) {
5060                         /* TODO */
5061                 }
5062         } else {
5063                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5064                 if (dev->phy.rev >= 3) {
5065                         /* TODO */
5066                 }
5067         }
5068
5069         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5070
5071         if (nphy->hang_avoid)
5072                 b43_nphy_stay_in_carrier_search(dev, false);
5073
5074         b43_mac_enable(dev);
5075 }
5076
5077 /**************************************************
5078  * N-PHY init
5079  **************************************************/
5080
5081 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5082 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5083 {
5084         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5085
5086         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5087         if (preamble == 1)
5088                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5089         else
5090                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5091
5092         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5093 }
5094
5095 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5096 static void b43_nphy_bphy_init(struct b43_wldev *dev)
5097 {
5098         unsigned int i;
5099         u16 val;
5100
5101         val = 0x1E1F;
5102         for (i = 0; i < 16; i++) {
5103                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5104                 val -= 0x202;
5105         }
5106         val = 0x3E3F;
5107         for (i = 0; i < 16; i++) {
5108                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5109                 val -= 0x202;
5110         }
5111         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5112 }
5113
5114 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5115 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5116 {
5117         if (dev->phy.rev >= 3) {
5118                 if (!init)
5119                         return;
5120                 if (0 /* FIXME */) {
5121                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5122                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5123                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5124                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5125                 }
5126         } else {
5127                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5128                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5129
5130                 switch (dev->dev->bus_type) {
5131 #ifdef CONFIG_B43_BCMA
5132                 case B43_BUS_BCMA:
5133                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5134                                                  0xFC00, 0xFC00);
5135                         break;
5136 #endif
5137 #ifdef CONFIG_B43_SSB
5138                 case B43_BUS_SSB:
5139                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5140                                                 0xFC00, 0xFC00);
5141                         break;
5142 #endif
5143                 }
5144
5145                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5146                 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5147                 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5148                               0);
5149
5150                 if (init) {
5151                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5152                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5153                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5154                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5155                 }
5156         }
5157 }
5158
5159 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
5160 static int b43_phy_initn(struct b43_wldev *dev)
5161 {
5162         struct ssb_sprom *sprom = dev->dev->bus_sprom;
5163         struct b43_phy *phy = &dev->phy;
5164         struct b43_phy_n *nphy = phy->n;
5165         u8 tx_pwr_state;
5166         struct nphy_txgains target;
5167         u16 tmp;
5168         enum ieee80211_band tmp2;
5169         bool do_rssi_cal;
5170
5171         u16 clip[2];
5172         bool do_cal = false;
5173
5174         if ((dev->phy.rev >= 3) &&
5175            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
5176            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
5177                 switch (dev->dev->bus_type) {
5178 #ifdef CONFIG_B43_BCMA
5179                 case B43_BUS_BCMA:
5180                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5181                                       BCMA_CC_CHIPCTL, 0x40);
5182                         break;
5183 #endif
5184 #ifdef CONFIG_B43_SSB
5185                 case B43_BUS_SSB:
5186                         chipco_set32(&dev->dev->sdev->bus->chipco,
5187                                      SSB_CHIPCO_CHIPCTL, 0x40);
5188                         break;
5189 #endif
5190                 }
5191         }
5192         nphy->deaf_count = 0;
5193         b43_nphy_tables_init(dev);
5194         nphy->crsminpwr_adjusted = false;
5195         nphy->noisevars_adjusted = false;
5196
5197         /* Clear all overrides */
5198         if (dev->phy.rev >= 3) {
5199                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5200                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5201                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5202                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5203         } else {
5204                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5205         }
5206         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5207         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
5208         if (dev->phy.rev < 6) {
5209                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5210                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5211         }
5212         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5213                      ~(B43_NPHY_RFSEQMODE_CAOVER |
5214                        B43_NPHY_RFSEQMODE_TROVER));
5215         if (dev->phy.rev >= 3)
5216                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
5217         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5218
5219         if (dev->phy.rev <= 2) {
5220                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5221                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5222                                 ~B43_NPHY_BPHY_CTL3_SCALE,
5223                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5224         }
5225         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5226         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5227
5228         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
5229             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5230              dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
5231                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5232         else
5233                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5234         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5235         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5236         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
5237
5238         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
5239         b43_nphy_update_txrx_chain(dev);
5240
5241         if (phy->rev < 2) {
5242                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5243                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5244         }
5245
5246         tmp2 = b43_current_band(dev->wl);
5247         if (b43_nphy_ipa(dev)) {
5248                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5249                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5250                                 nphy->papd_epsilon_offset[0] << 7);
5251                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5252                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5253                                 nphy->papd_epsilon_offset[1] << 7);
5254                 b43_nphy_int_pa_set_tx_dig_filters(dev);
5255         } else if (phy->rev >= 5) {
5256                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
5257         }
5258
5259         b43_nphy_workarounds(dev);
5260
5261         /* Reset CCA, in init code it differs a little from standard way */
5262         b43_phy_force_clock(dev, 1);
5263         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5264         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5265         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
5266         b43_phy_force_clock(dev, 0);
5267
5268         b43_mac_phy_clock_set(dev, true);
5269
5270         b43_nphy_pa_override(dev, false);
5271         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5272         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5273         b43_nphy_pa_override(dev, true);
5274
5275         b43_nphy_classifier(dev, 0, 0);
5276         b43_nphy_read_clip_detection(dev, clip);
5277         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5278                 b43_nphy_bphy_init(dev);
5279
5280         tx_pwr_state = nphy->txpwrctrl;
5281         b43_nphy_tx_power_ctrl(dev, false);
5282         b43_nphy_tx_power_fix(dev);
5283         b43_nphy_tx_power_ctl_idle_tssi(dev);
5284         b43_nphy_tx_power_ctl_setup(dev);
5285         b43_nphy_tx_gain_table_upload(dev);
5286
5287         if (nphy->phyrxchain != 3)
5288                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
5289         if (nphy->mphase_cal_phase_id > 0)
5290                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5291
5292         do_rssi_cal = false;
5293         if (phy->rev >= 3) {
5294                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5295                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
5296                 else
5297                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
5298
5299                 if (do_rssi_cal)
5300                         b43_nphy_rssi_cal(dev);
5301                 else
5302                         b43_nphy_restore_rssi_cal(dev);
5303         } else {
5304                 b43_nphy_rssi_cal(dev);
5305         }
5306
5307         if (!((nphy->measure_hold & 0x6) != 0)) {
5308                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5309                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
5310                 else
5311                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
5312
5313                 if (nphy->mute)
5314                         do_cal = false;
5315
5316                 if (do_cal) {
5317                         target = b43_nphy_get_tx_gains(dev);
5318
5319                         if (nphy->antsel_type == 2)
5320                                 b43_nphy_superswitch_init(dev, true);
5321                         if (nphy->perical != 2) {
5322                                 b43_nphy_rssi_cal(dev);
5323                                 if (phy->rev >= 3) {
5324                                         nphy->cal_orig_pwr_idx[0] =
5325                                             nphy->txpwrindex[0].index_internal;
5326                                         nphy->cal_orig_pwr_idx[1] =
5327                                             nphy->txpwrindex[1].index_internal;
5328                                         /* TODO N PHY Pre Calibrate TX Gain */
5329                                         target = b43_nphy_get_tx_gains(dev);
5330                                 }
5331                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5332                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5333                                                 b43_nphy_save_cal(dev);
5334                         } else if (nphy->mphase_cal_phase_id == 0)
5335                                 ;/* N PHY Periodic Calibration with arg 3 */
5336                 } else {
5337                         b43_nphy_restore_cal(dev);
5338                 }
5339         }
5340
5341         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
5342         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
5343         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5344         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5345         if (phy->rev >= 3 && phy->rev <= 6)
5346                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
5347         b43_nphy_tx_lp_fbw(dev);
5348         if (phy->rev >= 3)
5349                 b43_nphy_spur_workaround(dev);
5350
5351         return 0;
5352 }
5353
5354 /**************************************************
5355  * Channel switching ops.
5356  **************************************************/
5357
5358 static void b43_chantab_phy_upload(struct b43_wldev *dev,
5359                                    const struct b43_phy_n_sfo_cfg *e)
5360 {
5361         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5362         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5363         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5364         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5365         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5366         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5367 }
5368
5369 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5370 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5371 {
5372         switch (dev->dev->bus_type) {
5373 #ifdef CONFIG_B43_BCMA
5374         case B43_BUS_BCMA:
5375                 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5376                                              avoid);
5377                 break;
5378 #endif
5379 #ifdef CONFIG_B43_SSB
5380         case B43_BUS_SSB:
5381                 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5382                                             avoid);
5383                 break;
5384 #endif
5385         }
5386 }
5387
5388 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
5389 static void b43_nphy_channel_setup(struct b43_wldev *dev,
5390                                 const struct b43_phy_n_sfo_cfg *e,
5391                                 struct ieee80211_channel *new_channel)
5392 {
5393         struct b43_phy *phy = &dev->phy;
5394         struct b43_phy_n *nphy = dev->phy.n;
5395         int ch = new_channel->hw_value;
5396
5397         u16 old_band_5ghz;
5398         u16 tmp16;
5399
5400         old_band_5ghz =
5401                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5402         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
5403                 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5404                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
5405                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
5406                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
5407                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
5408         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
5409                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
5410                 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5411                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
5412                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
5413                 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
5414         }
5415
5416         b43_chantab_phy_upload(dev, e);
5417
5418         if (new_channel->hw_value == 14) {
5419                 b43_nphy_classifier(dev, 2, 0);
5420                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5421         } else {
5422                 b43_nphy_classifier(dev, 2, 2);
5423                 if (new_channel->band == IEEE80211_BAND_2GHZ)
5424                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5425         }
5426
5427         if (!nphy->txpwrctrl)
5428                 b43_nphy_tx_power_fix(dev);
5429
5430         if (dev->phy.rev < 3)
5431                 b43_nphy_adjust_lna_gain_table(dev);
5432
5433         b43_nphy_tx_lp_fbw(dev);
5434
5435         if (dev->phy.rev >= 3 &&
5436             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5437                 bool avoid = false;
5438                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5439                         avoid = true;
5440                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5441                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5442                                 avoid = true;
5443                 } else { /* 40MHz */
5444                         if (nphy->aband_spurwar_en &&
5445                             (ch == 38 || ch == 102 || ch == 118))
5446                                 avoid = dev->dev->chip_id == 0x4716;
5447                 }
5448
5449                 b43_nphy_pmu_spur_avoid(dev, avoid);
5450
5451                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5452                     dev->dev->chip_id == 43225) {
5453                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5454                                     avoid ? 0x5341 : 0x8889);
5455                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5456                 }
5457
5458                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5459                         ; /* TODO: reset PLL */
5460
5461                 if (avoid)
5462                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5463                 else
5464                         b43_phy_mask(dev, B43_NPHY_BBCFG,
5465                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5466
5467                 b43_nphy_reset_cca(dev);
5468
5469                 /* wl sets useless phy_isspuravoid here */
5470         }
5471
5472         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5473
5474         if (phy->rev >= 3)
5475                 b43_nphy_spur_workaround(dev);
5476 }
5477
5478 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
5479 static int b43_nphy_set_channel(struct b43_wldev *dev,
5480                                 struct ieee80211_channel *channel,
5481                                 enum nl80211_channel_type channel_type)
5482 {
5483         struct b43_phy *phy = &dev->phy;
5484
5485         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5486         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
5487
5488         u8 tmp;
5489
5490         if (dev->phy.rev >= 3) {
5491                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5492                                                         channel->center_freq);
5493                 if (!tabent_r3)
5494                         return -ESRCH;
5495         } else {
5496                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5497                                                         channel->hw_value);
5498                 if (!tabent_r2)
5499                         return -ESRCH;
5500         }
5501
5502         /* Channel is set later in common code, but we need to set it on our
5503            own to let this function's subcalls work properly. */
5504         phy->channel = channel->hw_value;
5505         phy->channel_freq = channel->center_freq;
5506
5507         if (b43_channel_type_is_40mhz(phy->channel_type) !=
5508                 b43_channel_type_is_40mhz(channel_type))
5509                 ; /* TODO: BMAC BW Set (channel_type) */
5510
5511         if (channel_type == NL80211_CHAN_HT40PLUS)
5512                 b43_phy_set(dev, B43_NPHY_RXCTL,
5513                                 B43_NPHY_RXCTL_BSELU20);
5514         else if (channel_type == NL80211_CHAN_HT40MINUS)
5515                 b43_phy_mask(dev, B43_NPHY_RXCTL,
5516                                 ~B43_NPHY_RXCTL_BSELU20);
5517
5518         if (dev->phy.rev >= 3) {
5519                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
5520                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
5521                 b43_radio_2056_setup(dev, tabent_r3);
5522                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
5523         } else {
5524                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
5525                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
5526                 b43_radio_2055_setup(dev, tabent_r2);
5527                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
5528         }
5529
5530         return 0;
5531 }
5532
5533 /**************************************************
5534  * Basic PHY ops.
5535  **************************************************/
5536
5537 static int b43_nphy_op_allocate(struct b43_wldev *dev)
5538 {
5539         struct b43_phy_n *nphy;
5540
5541         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5542         if (!nphy)
5543                 return -ENOMEM;
5544         dev->phy.n = nphy;
5545
5546         return 0;
5547 }
5548
5549 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5550 {
5551         struct b43_phy *phy = &dev->phy;
5552         struct b43_phy_n *nphy = phy->n;
5553         struct ssb_sprom *sprom = dev->dev->bus_sprom;
5554
5555         memset(nphy, 0, sizeof(*nphy));
5556
5557         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
5558         nphy->spur_avoid = (phy->rev >= 3) ?
5559                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
5560         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5561         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5562         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
5563         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
5564         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5565          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5566         nphy->tx_pwr_idx[0] = 128;
5567         nphy->tx_pwr_idx[1] = 128;
5568
5569         /* Hardware TX power control and 5GHz power gain */
5570         nphy->txpwrctrl = false;
5571         nphy->pwg_gain_5ghz = false;
5572         if (dev->phy.rev >= 3 ||
5573             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5574              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5575                 nphy->txpwrctrl = true;
5576                 nphy->pwg_gain_5ghz = true;
5577         } else if (sprom->revision >= 4) {
5578                 if (dev->phy.rev >= 2 &&
5579                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5580                         nphy->txpwrctrl = true;
5581 #ifdef CONFIG_B43_SSB
5582                         if (dev->dev->bus_type == B43_BUS_SSB &&
5583                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5584                                 struct pci_dev *pdev =
5585                                         dev->dev->sdev->bus->host_pci;
5586                                 if (pdev->device == 0x4328 ||
5587                                     pdev->device == 0x432a)
5588                                         nphy->pwg_gain_5ghz = true;
5589                         }
5590 #endif
5591                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5592                         nphy->pwg_gain_5ghz = true;
5593                 }
5594         }
5595
5596         if (dev->phy.rev >= 3) {
5597                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5598                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5599         }
5600 }
5601
5602 static void b43_nphy_op_free(struct b43_wldev *dev)
5603 {
5604         struct b43_phy *phy = &dev->phy;
5605         struct b43_phy_n *nphy = phy->n;
5606
5607         kfree(nphy);
5608         phy->n = NULL;
5609 }
5610
5611 static int b43_nphy_op_init(struct b43_wldev *dev)
5612 {
5613         return b43_phy_initn(dev);
5614 }
5615
5616 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5617 {
5618 #if B43_DEBUG
5619         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5620                 /* OFDM registers are onnly available on A/G-PHYs */
5621                 b43err(dev->wl, "Invalid OFDM PHY access at "
5622                        "0x%04X on N-PHY\n", offset);
5623                 dump_stack();
5624         }
5625         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5626                 /* Ext-G registers are only available on G-PHYs */
5627                 b43err(dev->wl, "Invalid EXT-G PHY access at "
5628                        "0x%04X on N-PHY\n", offset);
5629                 dump_stack();
5630         }
5631 #endif /* B43_DEBUG */
5632 }
5633
5634 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5635 {
5636         check_phyreg(dev, reg);
5637         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5638         return b43_read16(dev, B43_MMIO_PHY_DATA);
5639 }
5640
5641 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5642 {
5643         check_phyreg(dev, reg);
5644         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5645         b43_write16(dev, B43_MMIO_PHY_DATA, value);
5646 }
5647
5648 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5649                                  u16 set)
5650 {
5651         check_phyreg(dev, reg);
5652         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5653         b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
5654 }
5655
5656 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5657 {
5658         /* Register 1 is a 32-bit register. */
5659         B43_WARN_ON(reg == 1);
5660
5661         if (dev->phy.rev >= 7)
5662                 reg |= 0x200; /* Radio 0x2057 */
5663         else
5664                 reg |= 0x100;
5665
5666         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5667         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5668 }
5669
5670 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5671 {
5672         /* Register 1 is a 32-bit register. */
5673         B43_WARN_ON(reg == 1);
5674
5675         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5676         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5677 }
5678
5679 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
5680 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5681                                         bool blocked)
5682 {
5683         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5684                 b43err(dev->wl, "MAC not suspended\n");
5685
5686         if (blocked) {
5687                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5688                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5689                 if (dev->phy.rev >= 7) {
5690                         /* TODO */
5691                 } else if (dev->phy.rev >= 3) {
5692                         b43_radio_mask(dev, 0x09, ~0x2);
5693
5694                         b43_radio_write(dev, 0x204D, 0);
5695                         b43_radio_write(dev, 0x2053, 0);
5696                         b43_radio_write(dev, 0x2058, 0);
5697                         b43_radio_write(dev, 0x205E, 0);
5698                         b43_radio_mask(dev, 0x2062, ~0xF0);
5699                         b43_radio_write(dev, 0x2064, 0);
5700
5701                         b43_radio_write(dev, 0x304D, 0);
5702                         b43_radio_write(dev, 0x3053, 0);
5703                         b43_radio_write(dev, 0x3058, 0);
5704                         b43_radio_write(dev, 0x305E, 0);
5705                         b43_radio_mask(dev, 0x3062, ~0xF0);
5706                         b43_radio_write(dev, 0x3064, 0);
5707                 }
5708         } else {
5709                 if (dev->phy.rev >= 7) {
5710                         if (!dev->phy.radio_on)
5711                                 b43_radio_2057_init(dev);
5712                         b43_switch_channel(dev, dev->phy.channel);
5713                 } else if (dev->phy.rev >= 3) {
5714                         if (!dev->phy.radio_on)
5715                                 b43_radio_init2056(dev);
5716                         b43_switch_channel(dev, dev->phy.channel);
5717                 } else {
5718                         b43_radio_init2055(dev);
5719                 }
5720         }
5721 }
5722
5723 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
5724 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5725 {
5726         u16 override = on ? 0x0 : 0x7FFF;
5727         u16 core = on ? 0xD : 0x00FD;
5728
5729         if (dev->phy.rev >= 3) {
5730                 if (on) {
5731                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5732                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5733                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5734                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5735                 } else {
5736                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5737                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5738                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5739                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5740                 }
5741         } else {
5742                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5743         }
5744 }
5745
5746 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5747                                       unsigned int new_channel)
5748 {
5749         struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5750         enum nl80211_channel_type channel_type =
5751                 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5752
5753         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5754                 if ((new_channel < 1) || (new_channel > 14))
5755                         return -EINVAL;
5756         } else {
5757                 if (new_channel > 200)
5758                         return -EINVAL;
5759         }
5760
5761         return b43_nphy_set_channel(dev, channel, channel_type);
5762 }
5763
5764 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5765 {
5766         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5767                 return 1;
5768         return 36;
5769 }
5770
5771 const struct b43_phy_operations b43_phyops_n = {
5772         .allocate               = b43_nphy_op_allocate,
5773         .free                   = b43_nphy_op_free,
5774         .prepare_structs        = b43_nphy_op_prepare_structs,
5775         .init                   = b43_nphy_op_init,
5776         .phy_read               = b43_nphy_op_read,
5777         .phy_write              = b43_nphy_op_write,
5778         .phy_maskset            = b43_nphy_op_maskset,
5779         .radio_read             = b43_nphy_op_radio_read,
5780         .radio_write            = b43_nphy_op_radio_write,
5781         .software_rfkill        = b43_nphy_op_software_rfkill,
5782         .switch_analog          = b43_nphy_op_switch_analog,
5783         .switch_channel         = b43_nphy_op_switch_channel,
5784         .get_default_chan       = b43_nphy_op_get_default_chan,
5785         .recalc_txpower         = b43_nphy_op_recalc_txpower,
5786         .adjust_txpower         = b43_nphy_op_adjust_txpower,
5787 };