drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "radio_2055.h"
  33 #include "radio_2056.h"
  34 #include "main.h"
  35
  36 struct nphy_txgains {
  37         u16 txgm[2];
  38         u16 pga[2];
  39         u16 pad[2];
  40         u16 ipa[2];
  41 };
  42
  43 struct nphy_iqcal_params {
  44         u16 txgm;
  45         u16 pga;
  46         u16 pad;
  47         u16 ipa;
  48         u16 cal_gain;
  49         u16 ncorr[5];
  50 };
  51
  52 struct nphy_iq_est {
  53         s32 iq0_prod;
  54         u32 i0_pwr;
  55         u32 q0_pwr;
  56         s32 iq1_prod;
  57         u32 i1_pwr;
  58         u32 q1_pwr;
  59 };
  60
  61 enum b43_nphy_rf_sequence {
  62         B43_RFSEQ_RX2TX,
  63         B43_RFSEQ_TX2RX,
  64         B43_RFSEQ_RESET2RX,
  65         B43_RFSEQ_UPDATE_GAINH,
  66         B43_RFSEQ_UPDATE_GAINL,
  67         B43_RFSEQ_UPDATE_GAINU,
  68 };
  69
  70 enum b43_nphy_rssi_type {
  71         B43_NPHY_RSSI_X = 0,
  72         B43_NPHY_RSSI_Y,
  73         B43_NPHY_RSSI_Z,
  74         B43_NPHY_RSSI_PWRDET,
  75         B43_NPHY_RSSI_TSSI_I,
  76         B43_NPHY_RSSI_TSSI_Q,
  77         B43_NPHY_RSSI_TBD,
  78 };
  79
  80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  81                                                 bool enable);
  82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  83                                         u8 *events, u8 *delays, u8 length);
  84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  85                                        enum b43_nphy_rf_sequence seq);
  86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  87                                                 u16 value, u8 core, bool off);
  88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  89                                                 u16 value, u8 core);
  90
  91 static inline bool b43_channel_type_is_40mhz(
  92                                         enum nl80211_channel_type channel_type)
  93 {
  94         return (channel_type == NL80211_CHAN_HT40MINUS ||
  95                 channel_type == NL80211_CHAN_HT40PLUS);
  96 }
  97
  98 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  99 {//TODO
 100 }
 101
 102 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
 103 {//TODO
 104 }
 105
 106 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 107                                                         bool ignore_tssi)
 108 {//TODO
 109         return B43_TXPWR_RES_DONE;
 110 }
 111
 112 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 113                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 114 {
 115         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 116         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 117         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 118         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 119         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 120
 121         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 122         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 123         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 124         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 125         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 126
 127         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 128         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 129         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 130         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 131         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 132
 133         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 134         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 135         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 136         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 137         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 138
 139         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 140         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 141         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 142         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 143         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 144
 145         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 146         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 147 }
 148
 149 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 150                                    const struct b43_phy_n_sfo_cfg *e)
 151 {
 152         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 153         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 154         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 155         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 156         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 157         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 158 }
 159
 160 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 161 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 162 {
 163         struct b43_phy_n *nphy = dev->phy.n;
 164         u8 i;
 165         u16 tmp;
 166
 167         if (nphy->hang_avoid)
 168                 b43_nphy_stay_in_carrier_search(dev, 1);
 169
 170         nphy->txpwrctrl = enable;
 171         if (!enable) {
 172                 if (dev->phy.rev >= 3)
 173                         ; /* TODO */
 174
 175                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 176                 for (i = 0; i < 84; i++)
 177                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 178
 179                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 180                 for (i = 0; i < 84; i++)
 181                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 182
 183                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 184                 if (dev->phy.rev >= 3)
 185                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 186                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 187
 188                 if (dev->phy.rev >= 3) {
 189                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 190                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 191                 } else {
 192                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 193                 }
 194
 195                 if (dev->phy.rev == 2)
 196                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 197                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 198                 else if (dev->phy.rev < 2)
 199                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 200                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 201
 202                 if (dev->phy.rev < 2 && 0)
 203                         ; /* TODO */
 204         } else {
 205                 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
 206         }
 207
 208         if (nphy->hang_avoid)
 209                 b43_nphy_stay_in_carrier_search(dev, 0);
 210 }
 211
 212 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 213 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 214 {
 215         struct b43_phy_n *nphy = dev->phy.n;
 216         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 217
 218         u8 txpi[2], bbmult, i;
 219         u16 tmp, radio_gain, dac_gain;
 220         u16 freq = dev->phy.channel_freq;
 221         u32 txgain;
 222         /* u32 gaintbl; rev3+ */
 223
 224         if (nphy->hang_avoid)
 225                 b43_nphy_stay_in_carrier_search(dev, 1);
 226
 227         if (dev->phy.rev >= 3) {
 228                 txpi[0] = 40;
 229                 txpi[1] = 40;
 230         } else if (sprom->revision < 4) {
 231                 txpi[0] = 72;
 232                 txpi[1] = 72;
 233         } else {
 234                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 235                         txpi[0] = sprom->txpid2g[0];
 236                         txpi[1] = sprom->txpid2g[1];
 237                 } else if (freq >= 4900 && freq < 5100) {
 238                         txpi[0] = sprom->txpid5gl[0];
 239                         txpi[1] = sprom->txpid5gl[1];
 240                 } else if (freq >= 5100 && freq < 5500) {
 241                         txpi[0] = sprom->txpid5g[0];
 242                         txpi[1] = sprom->txpid5g[1];
 243                 } else if (freq >= 5500) {
 244                         txpi[0] = sprom->txpid5gh[0];
 245                         txpi[1] = sprom->txpid5gh[1];
 246                 } else {
 247                         txpi[0] = 91;
 248                         txpi[1] = 91;
 249                 }
 250         }
 251
 252         /*
 253         for (i = 0; i < 2; i++) {
 254                 nphy->txpwrindex[i].index_internal = txpi[i];
 255                 nphy->txpwrindex[i].index_internal_save = txpi[i];
 256         }
 257         */
 258
 259         for (i = 0; i < 2; i++) {
 260                 if (dev->phy.rev >= 3) {
 261                         /* FIXME: support 5GHz */
 262                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 263                         radio_gain = (txgain >> 16) & 0x1FFFF;
 264                 } else {
 265                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 266                         radio_gain = (txgain >> 16) & 0x1FFF;
 267                 }
 268
 269                 dac_gain = (txgain >> 8) & 0x3F;
 270                 bbmult = txgain & 0xFF;
 271
 272                 if (dev->phy.rev >= 3) {
 273                         if (i == 0)
 274                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 275                         else
 276                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 277                 } else {
 278                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 279                 }
 280
 281                 if (i == 0)
 282                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 283                 else
 284                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 285
 286                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
 287                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
 288
 289                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 290                 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 291
 292                 if (i == 0)
 293                         tmp = (tmp & 0x00FF) | (bbmult << 8);
 294                 else
 295                         tmp = (tmp & 0xFF00) | bbmult;
 296
 297                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
 298                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
 299
 300                 if (0)
 301                         ; /* TODO */
 302         }
 303
 304         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 305
 306         if (nphy->hang_avoid)
 307                 b43_nphy_stay_in_carrier_search(dev, 0);
 308 }
 309
 310
 311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 312 static void b43_radio_2055_setup(struct b43_wldev *dev,
 313                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 314 {
 315         B43_WARN_ON(dev->phy.rev >= 3);
 316
 317         b43_chantab_radio_upload(dev, e);
 318         udelay(50);
 319         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 320         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 321         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 322         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 323         udelay(300);
 324 }
 325
 326 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 327 {
 328         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 329                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 330         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 331                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 332                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 333         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 334                     B43_NPHY_RFCTL_CMD_PORFORCE);
 335 }
 336
 337 static void b43_radio_init2055_post(struct b43_wldev *dev)
 338 {
 339         struct b43_phy_n *nphy = dev->phy.n;
 340         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 341         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 342         int i;
 343         u16 val;
 344         bool workaround = false;
 345
 346         if (sprom->revision < 4)
 347                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
 348                                 binfo->type != 0x46D ||
 349                                 binfo->rev < 0x41);
 350         else
 351                 workaround =
 352                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 353
 354         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 355         if (workaround) {
 356                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 357                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 358         }
 359         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 360         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 361         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 362         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 363         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 364         msleep(1);
 365         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 366         for (i = 0; i < 200; i++) {
 367                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 368                 if (val & 0x80) {
 369                         i = 0;
 370                         break;
 371                 }
 372                 udelay(10);
 373         }
 374         if (i)
 375                 b43err(dev->wl, "radio post init timeout\n");
 376         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 377         b43_switch_channel(dev, dev->phy.channel);
 378         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 379         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 380         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 381         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 382         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 383         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 384         if (!nphy->gain_boost) {
 385                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 386                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 387         } else {
 388                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 389                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 390         }
 391         udelay(2);
 392 }
 393
 394 /*
 395  * Initialize a Broadcom 2055 N-radio
 396  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 397  */
 398 static void b43_radio_init2055(struct b43_wldev *dev)
 399 {
 400         b43_radio_init2055_pre(dev);
 401         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 402                 /* Follow wl, not specs. Do not force uploading all regs */
 403                 b2055_upload_inittab(dev, 0, 0);
 404         } else {
 405                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 406                 b2055_upload_inittab(dev, ghz5, 0);
 407         }
 408         b43_radio_init2055_post(dev);
 409 }
 410
 411 /*
 412  * Initialize a Broadcom 2056 N-radio
 413  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 414  */
 415 static void b43_radio_init2056(struct b43_wldev *dev)
 416 {
 417         /* TODO */
 418 }
 419
 420
 421 /*
 422  * Upload the N-PHY tables.
 423  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 424  */
 425 static void b43_nphy_tables_init(struct b43_wldev *dev)
 426 {
 427         if (dev->phy.rev < 3)
 428                 b43_nphy_rev0_1_2_tables_init(dev);
 429         else
 430                 b43_nphy_rev3plus_tables_init(dev);
 431 }
 432
 433 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 434 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 435 {
 436         struct b43_phy_n *nphy = dev->phy.n;
 437         enum ieee80211_band band;
 438         u16 tmp;
 439
 440         if (!enable) {
 441                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 442                                                        B43_NPHY_RFCTL_INTC1);
 443                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 444                                                        B43_NPHY_RFCTL_INTC2);
 445                 band = b43_current_band(dev->wl);
 446                 if (dev->phy.rev >= 3) {
 447                         if (band == IEEE80211_BAND_5GHZ)
 448                                 tmp = 0x600;
 449                         else
 450                                 tmp = 0x480;
 451                 } else {
 452                         if (band == IEEE80211_BAND_5GHZ)
 453                                 tmp = 0x180;
 454                         else
 455                                 tmp = 0x120;
 456                 }
 457                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 458                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 459         } else {
 460                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 461                                 nphy->rfctrl_intc1_save);
 462                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 463                                 nphy->rfctrl_intc2_save);
 464         }
 465 }
 466
 467 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 468 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 469 {
 470         struct b43_phy_n *nphy = dev->phy.n;
 471         u16 tmp;
 472         enum ieee80211_band band = b43_current_band(dev->wl);
 473         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 474                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 475
 476         if (dev->phy.rev >= 3) {
 477                 if (ipa) {
 478                         tmp = 4;
 479                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 480                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 481                 }
 482
 483                 tmp = 1;
 484                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 485                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 486         }
 487 }
 488
 489 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 490 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 491 {
 492         u32 tmslow;
 493
 494         if (dev->phy.type != B43_PHYTYPE_N)
 495                 return;
 496
 497         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 498         if (force)
 499                 tmslow |= SSB_TMSLOW_FGC;
 500         else
 501                 tmslow &= ~SSB_TMSLOW_FGC;
 502         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 503 }
 504
 505 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 506 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 507 {
 508         u16 bbcfg;
 509
 510         b43_nphy_bmac_clock_fgc(dev, 1);
 511         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 512         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 513         udelay(1);
 514         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 515         b43_nphy_bmac_clock_fgc(dev, 0);
 516         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 517 }
 518
 519 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 520 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 521 {
 522         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 523
 524         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 525         if (preamble == 1)
 526                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 527         else
 528                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 529
 530         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 531 }
 532
 533 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 534 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 535 {
 536         struct b43_phy_n *nphy = dev->phy.n;
 537
 538         bool override = false;
 539         u16 chain = 0x33;
 540
 541         if (nphy->txrx_chain == 0) {
 542                 chain = 0x11;
 543                 override = true;
 544         } else if (nphy->txrx_chain == 1) {
 545                 chain = 0x22;
 546                 override = true;
 547         }
 548
 549         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 550                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 551                         chain);
 552
 553         if (override)
 554                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 555                                 B43_NPHY_RFSEQMODE_CAOVER);
 556         else
 557                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 558                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 559 }
 560
 561 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 562 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 563                                 u16 samps, u8 time, bool wait)
 564 {
 565         int i;
 566         u16 tmp;
 567
 568         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 569         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 570         if (wait)
 571                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 572         else
 573                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 574
 575         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 576
 577         for (i = 1000; i; i--) {
 578                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 579                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 580                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 581                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 582                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 583                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 584                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 585                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 586
 587                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 588                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 589                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 590                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 591                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 592                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 593                         return;
 594                 }
 595                 udelay(10);
 596         }
 597         memset(est, 0, sizeof(*est));
 598 }
 599
 600 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 601 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 602                                         struct b43_phy_n_iq_comp *pcomp)
 603 {
 604         if (write) {
 605                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 606                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 607                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 608                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 609         } else {
 610                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 611                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 612                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 613                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 614         }
 615 }
 616
 617 #if 0
 618 /* Ready but not used anywhere */
 619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 620 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 621 {
 622         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 623
 624         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 625         if (core == 0) {
 626                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 627                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 628         } else {
 629                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 630                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 631         }
 632         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 633         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 634         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 635         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 636         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 637         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 638         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 639         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 640 }
 641
 642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 643 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 644 {
 645         u8 rxval, txval;
 646         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 647
 648         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 649         if (core == 0) {
 650                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 651                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 652         } else {
 653                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 654                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 655         }
 656         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 657         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 658         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 659         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 660         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 661         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 662         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 663         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 664
 665         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 666         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 667
 668         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 669                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 670                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 671         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 672                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 673         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 674                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 675         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 676                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 677
 678         if (core == 0) {
 679                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 680                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 681         } else {
 682                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 683                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 684         }
 685
 686         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 687         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 688         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 689
 690         if (core == 0) {
 691                 rxval = 1;
 692                 txval = 8;
 693         } else {
 694                 rxval = 4;
 695                 txval = 2;
 696         }
 697         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 698         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 699 }
 700 #endif
 701
 702 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 703 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 704 {
 705         int i;
 706         s32 iq;
 707         u32 ii;
 708         u32 qq;
 709         int iq_nbits, qq_nbits;
 710         int arsh, brsh;
 711         u16 tmp, a, b;
 712
 713         struct nphy_iq_est est;
 714         struct b43_phy_n_iq_comp old;
 715         struct b43_phy_n_iq_comp new = { };
 716         bool error = false;
 717
 718         if (mask == 0)
 719                 return;
 720
 721         b43_nphy_rx_iq_coeffs(dev, false, &old);
 722         b43_nphy_rx_iq_coeffs(dev, true, &new);
 723         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 724         new = old;
 725
 726         for (i = 0; i < 2; i++) {
 727                 if (i == 0 && (mask & 1)) {
 728                         iq = est.iq0_prod;
 729                         ii = est.i0_pwr;
 730                         qq = est.q0_pwr;
 731                 } else if (i == 1 && (mask & 2)) {
 732                         iq = est.iq1_prod;
 733                         ii = est.i1_pwr;
 734                         qq = est.q1_pwr;
 735                 } else {
 736                         continue;
 737                 }
 738
 739                 if (ii + qq < 2) {
 740                         error = true;
 741                         break;
 742                 }
 743
 744                 iq_nbits = fls(abs(iq));
 745                 qq_nbits = fls(qq);
 746
 747                 arsh = iq_nbits - 20;
 748                 if (arsh >= 0) {
 749                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 750                         tmp = ii >> arsh;
 751                 } else {
 752                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 753                         tmp = ii << -arsh;
 754                 }
 755                 if (tmp == 0) {
 756                         error = true;
 757                         break;
 758                 }
 759                 a /= tmp;
 760
 761                 brsh = qq_nbits - 11;
 762                 if (brsh >= 0) {
 763                         b = (qq << (31 - qq_nbits));
 764                         tmp = ii >> brsh;
 765                 } else {
 766                         b = (qq << (31 - qq_nbits));
 767                         tmp = ii << -brsh;
 768                 }
 769                 if (tmp == 0) {
 770                         error = true;
 771                         break;
 772                 }
 773                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 774
 775                 if (i == 0 && (mask & 0x1)) {
 776                         if (dev->phy.rev >= 3) {
 777                                 new.a0 = a & 0x3FF;
 778                                 new.b0 = b & 0x3FF;
 779                         } else {
 780                                 new.a0 = b & 0x3FF;
 781                                 new.b0 = a & 0x3FF;
 782                         }
 783                 } else if (i == 1 && (mask & 0x2)) {
 784                         if (dev->phy.rev >= 3) {
 785                                 new.a1 = a & 0x3FF;
 786                                 new.b1 = b & 0x3FF;
 787                         } else {
 788                                 new.a1 = b & 0x3FF;
 789                                 new.b1 = a & 0x3FF;
 790                         }
 791                 }
 792         }
 793
 794         if (error)
 795                 new = old;
 796
 797         b43_nphy_rx_iq_coeffs(dev, true, &new);
 798 }
 799
 800 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 801 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 802 {
 803         u16 array[4];
 804         int i;
 805
 806         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 807         for (i = 0; i < 4; i++)
 808                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 809
 810         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 811         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 812         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 813         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 814 }
 815
 816 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 817 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
 818                                           const u16 *clip_st)
 819 {
 820         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 821         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 822 }
 823
 824 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 825 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 826 {
 827         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 828         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 829 }
 830
 831 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 832 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 833 {
 834         if (dev->phy.rev >= 3) {
 835                 if (!init)
 836                         return;
 837                 if (0 /* FIXME */) {
 838                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 839                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 840                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 841                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 842                 }
 843         } else {
 844                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 845                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 846
 847                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 848                                         0xFC00);
 849                 b43_write32(dev, B43_MMIO_MACCTL,
 850                         b43_read32(dev, B43_MMIO_MACCTL) &
 851                         ~B43_MACCTL_GPOUTSMSK);
 852                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 853                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 854                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 855                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 856
 857                 if (init) {
 858                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 859                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 860                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 861                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 862                 }
 863         }
 864 }
 865
 866 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 867 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 868 {
 869         u16 tmp;
 870
 871         if (dev->dev->id.revision == 16)
 872                 b43_mac_suspend(dev);
 873
 874         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 875         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 876                 B43_NPHY_CLASSCTL_WAITEDEN);
 877         tmp &= ~mask;
 878         tmp |= (val & mask);
 879         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 880
 881         if (dev->dev->id.revision == 16)
 882                 b43_mac_enable(dev);
 883
 884         return tmp;
 885 }
 886
 887 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 888 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 889 {
 890         struct b43_phy *phy = &dev->phy;
 891         struct b43_phy_n *nphy = phy->n;
 892
 893         if (enable) {
 894                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
 895                 if (nphy->deaf_count++ == 0) {
 896                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 897                         b43_nphy_classifier(dev, 0x7, 0);
 898                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 899                         b43_nphy_write_clip_detection(dev, clip);
 900                 }
 901                 b43_nphy_reset_cca(dev);
 902         } else {
 903                 if (--nphy->deaf_count == 0) {
 904                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 905                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 906                 }
 907         }
 908 }
 909
 910 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 911 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 912 {
 913         struct b43_phy_n *nphy = dev->phy.n;
 914         u16 tmp;
 915
 916         if (nphy->hang_avoid)
 917                 b43_nphy_stay_in_carrier_search(dev, 1);
 918
 919         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 920         if (tmp & 0x1)
 921                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 922         else if (tmp & 0x2)
 923                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
 924
 925         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 926
 927         if (nphy->bb_mult_save & 0x80000000) {
 928                 tmp = nphy->bb_mult_save & 0xFFFF;
 929                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 930                 nphy->bb_mult_save = 0;
 931         }
 932
 933         if (nphy->hang_avoid)
 934                 b43_nphy_stay_in_carrier_search(dev, 0);
 935 }
 936
 937 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 938 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 939 {
 940         struct b43_phy_n *nphy = dev->phy.n;
 941
 942         u8 channel = dev->phy.channel;
 943         int tone[2] = { 57, 58 };
 944         u32 noise[2] = { 0x3FF, 0x3FF };
 945
 946         B43_WARN_ON(dev->phy.rev < 3);
 947
 948         if (nphy->hang_avoid)
 949                 b43_nphy_stay_in_carrier_search(dev, 1);
 950
 951         if (nphy->gband_spurwar_en) {
 952                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 953                 if (channel == 11 && dev->phy.is_40mhz)
 954                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 955                 else
 956                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 957                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 958         }
 959
 960         if (nphy->aband_spurwar_en) {
 961                 if (channel == 54) {
 962                         tone[0] = 0x20;
 963                         noise[0] = 0x25F;
 964                 } else if (channel == 38 || channel == 102 || channel == 118) {
 965                         if (0 /* FIXME */) {
 966                                 tone[0] = 0x20;
 967                                 noise[0] = 0x21F;
 968                         } else {
 969                                 tone[0] = 0;
 970                                 noise[0] = 0;
 971                         }
 972                 } else if (channel == 134) {
 973                         tone[0] = 0x20;
 974                         noise[0] = 0x21F;
 975                 } else if (channel == 151) {
 976                         tone[0] = 0x10;
 977                         noise[0] = 0x23F;
 978                 } else if (channel == 153 || channel == 161) {
 979                         tone[0] = 0x30;
 980                         noise[0] = 0x23F;
 981                 } else {
 982                         tone[0] = 0;
 983                         noise[0] = 0;
 984                 }
 985
 986                 if (!tone[0] && !noise[0])
 987                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 988                 else
 989                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 990         }
 991
 992         if (nphy->hang_avoid)
 993                 b43_nphy_stay_in_carrier_search(dev, 0);
 994 }
 995
 996 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 997 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 998 {
 999         struct b43_phy_n *nphy = dev->phy.n;
1000
1001         u8 i;
1002         s16 tmp;
1003         u16 data[4];
1004         s16 gain[2];
1005         u16 minmax[2];
1006         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1007
1008         if (nphy->hang_avoid)
1009                 b43_nphy_stay_in_carrier_search(dev, 1);
1010
1011         if (nphy->gain_boost) {
1012                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1013                         gain[0] = 6;
1014                         gain[1] = 6;
1015                 } else {
1016                         tmp = 40370 - 315 * dev->phy.channel;
1017                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1018                         tmp = 23242 - 224 * dev->phy.channel;
1019                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1020                 }
1021         } else {
1022                 gain[0] = 0;
1023                 gain[1] = 0;
1024         }
1025
1026         for (i = 0; i < 2; i++) {
1027                 if (nphy->elna_gain_config) {
1028                         data[0] = 19 + gain[i];
1029                         data[1] = 25 + gain[i];
1030                         data[2] = 25 + gain[i];
1031                         data[3] = 25 + gain[i];
1032                 } else {
1033                         data[0] = lna_gain[0] + gain[i];
1034                         data[1] = lna_gain[1] + gain[i];
1035                         data[2] = lna_gain[2] + gain[i];
1036                         data[3] = lna_gain[3] + gain[i];
1037                 }
1038                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1039
1040                 minmax[i] = 23 + gain[i];
1041         }
1042
1043         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1044                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1045         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1046                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1047
1048         if (nphy->hang_avoid)
1049                 b43_nphy_stay_in_carrier_search(dev, 0);
1050 }
1051
1052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1053 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1054 {
1055         struct b43_phy_n *nphy = dev->phy.n;
1056         u8 i, j;
1057         u8 code;
1058         u16 tmp;
1059
1060         /* TODO: for PHY >= 3
1061         s8 *lna1_gain, *lna2_gain;
1062         u8 *gain_db, *gain_bits;
1063         u16 *rfseq_init;
1064         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1065         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1066         */
1067
1068         u8 rfseq_events[3] = { 6, 8, 7 };
1069         u8 rfseq_delays[3] = { 10, 30, 1 };
1070
1071         if (dev->phy.rev >= 3) {
1072                 /* TODO */
1073         } else {
1074                 /* Set Clip 2 detect */
1075                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1076                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1077                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1078                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1079
1080                 /* Set narrowband clip threshold */
1081                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1082                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1083
1084                 if (!dev->phy.is_40mhz) {
1085                         /* Set dwell lengths */
1086                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1087                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1088                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1089                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1090                 }
1091
1092                 /* Set wideband clip 2 threshold */
1093                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1094                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1095                                 21);
1096                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1097                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1098                                 21);
1099
1100                 if (!dev->phy.is_40mhz) {
1101                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1102                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1103                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1104                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1105                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1106                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1107                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1108                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1109                 }
1110
1111                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1112
1113                 if (nphy->gain_boost) {
1114                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1115                             dev->phy.is_40mhz)
1116                                 code = 4;
1117                         else
1118                                 code = 5;
1119                 } else {
1120                         code = dev->phy.is_40mhz ? 6 : 7;
1121                 }
1122
1123                 /* Set HPVGA2 index */
1124                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1125                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1126                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1127                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1128                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1129                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1130
1131                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1132                 /* specs say about 2 loops, but wl does 4 */
1133                 for (i = 0; i < 4; i++)
1134                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1135                                                         (code << 8 | 0x7C));
1136
1137                 b43_nphy_adjust_lna_gain_table(dev);
1138
1139                 if (nphy->elna_gain_config) {
1140                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1141                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1142                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1143                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1144                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1145
1146                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1147                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1148                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1149                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1150                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1151
1152                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1153                         /* specs say about 2 loops, but wl does 4 */
1154                         for (i = 0; i < 4; i++)
1155                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1156                                                         (code << 8 | 0x74));
1157                 }
1158
1159                 if (dev->phy.rev == 2) {
1160                         for (i = 0; i < 4; i++) {
1161                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1162                                                 (0x0400 * i) + 0x0020);
1163                                 for (j = 0; j < 21; j++) {
1164                                         tmp = j * (i < 2 ? 3 : 1);
1165                                         b43_phy_write(dev,
1166                                                 B43_NPHY_TABLE_DATALO, tmp);
1167                                 }
1168                         }
1169
1170                         b43_nphy_set_rf_sequence(dev, 5,
1171                                         rfseq_events, rfseq_delays, 3);
1172                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1173                                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1174                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1175
1176                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1177                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1178                                                 0xFF80, 4);
1179                 }
1180         }
1181 }
1182
1183 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1184 static void b43_nphy_workarounds(struct b43_wldev *dev)
1185 {
1186         struct ssb_bus *bus = dev->dev->bus;
1187         struct b43_phy *phy = &dev->phy;
1188         struct b43_phy_n *nphy = phy->n;
1189
1190         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1191         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1192
1193         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1194         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1195
1196         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1197                 b43_nphy_classifier(dev, 1, 0);
1198         else
1199                 b43_nphy_classifier(dev, 1, 1);
1200
1201         if (nphy->hang_avoid)
1202                 b43_nphy_stay_in_carrier_search(dev, 1);
1203
1204         b43_phy_set(dev, B43_NPHY_IQFLIP,
1205                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1206
1207         if (dev->phy.rev >= 3) {
1208                 /* TODO */
1209         } else {
1210                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1211                     nphy->band5g_pwrgain) {
1212                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1213                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1214                 } else {
1215                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1216                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1217                 }
1218
1219                 /* TODO: convert to b43_ntab_write? */
1220                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1221                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1222                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1223                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1224                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1225                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1226                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1227                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1228
1229                 if (dev->phy.rev < 2) {
1230                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1231                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1232                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1233                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1234                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1235                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1236                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1237                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1238                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1239                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1240                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1241                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1242                 }
1243
1244                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1245                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1246                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1247                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1248
1249                 if (bus->sprom.boardflags2_lo & 0x100 &&
1250                     bus->boardinfo.type == 0x8B) {
1251                         delays1[0] = 0x1;
1252                         delays1[5] = 0x14;
1253                 }
1254                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1255                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1256
1257                 b43_nphy_gain_ctrl_workarounds(dev);
1258
1259                 if (dev->phy.rev < 2) {
1260                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1261                                 b43_hf_write(dev, b43_hf_read(dev) |
1262                                                 B43_HF_MLADVW);
1263                 } else if (dev->phy.rev == 2) {
1264                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1265                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1266                 }
1267
1268                 if (dev->phy.rev < 2)
1269                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1270                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1271
1272                 /* Set phase track alpha and beta */
1273                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1274                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1275                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1276                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1277                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1278                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1279
1280                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1281                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1282                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1283                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1284                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1285
1286                 if (dev->phy.rev == 2)
1287                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1288                                         B43_NPHY_FINERX2_CGC_DECGC);
1289         }
1290
1291         if (nphy->hang_avoid)
1292                 b43_nphy_stay_in_carrier_search(dev, 0);
1293 }
1294
1295 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1296 static int b43_nphy_load_samples(struct b43_wldev *dev,
1297                                         struct b43_c32 *samples, u16 len) {
1298         struct b43_phy_n *nphy = dev->phy.n;
1299         u16 i;
1300         u32 *data;
1301
1302         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1303         if (!data) {
1304                 b43err(dev->wl, "allocation for samples loading failed\n");
1305                 return -ENOMEM;
1306         }
1307         if (nphy->hang_avoid)
1308                 b43_nphy_stay_in_carrier_search(dev, 1);
1309
1310         for (i = 0; i < len; i++) {
1311                 data[i] = (samples[i].i & 0x3FF << 10);
1312                 data[i] |= samples[i].q & 0x3FF;
1313         }
1314         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1315
1316         kfree(data);
1317         if (nphy->hang_avoid)
1318                 b43_nphy_stay_in_carrier_search(dev, 0);
1319         return 0;
1320 }
1321
1322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1323 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1324                                         bool test)
1325 {
1326         int i;
1327         u16 bw, len, rot, angle;
1328         struct b43_c32 *samples;
1329
1330
1331         bw = (dev->phy.is_40mhz) ? 40 : 20;
1332         len = bw << 3;
1333
1334         if (test) {
1335                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1336                         bw = 82;
1337                 else
1338                         bw = 80;
1339
1340                 if (dev->phy.is_40mhz)
1341                         bw <<= 1;
1342
1343                 len = bw << 1;
1344         }
1345
1346         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1347         if (!samples) {
1348                 b43err(dev->wl, "allocation for samples generation failed\n");
1349                 return 0;
1350         }
1351         rot = (((freq * 36) / bw) << 16) / 100;
1352         angle = 0;
1353
1354         for (i = 0; i < len; i++) {
1355                 samples[i] = b43_cordic(angle);
1356                 angle += rot;
1357                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1358                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1359         }
1360
1361         i = b43_nphy_load_samples(dev, samples, len);
1362         kfree(samples);
1363         return (i < 0) ? 0 : len;
1364 }
1365
1366 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1367 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1368                                         u16 wait, bool iqmode, bool dac_test)
1369 {
1370         struct b43_phy_n *nphy = dev->phy.n;
1371         int i;
1372         u16 seq_mode;
1373         u32 tmp;
1374
1375         if (nphy->hang_avoid)
1376                 b43_nphy_stay_in_carrier_search(dev, true);
1377
1378         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1379                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1380                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1381         }
1382
1383         if (!dev->phy.is_40mhz)
1384                 tmp = 0x6464;
1385         else
1386                 tmp = 0x4747;
1387         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1388
1389         if (nphy->hang_avoid)
1390                 b43_nphy_stay_in_carrier_search(dev, false);
1391
1392         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1393
1394         if (loops != 0xFFFF)
1395                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1396         else
1397                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1398
1399         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1400
1401         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1402
1403         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1404         if (iqmode) {
1405                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1406                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1407         } else {
1408                 if (dac_test)
1409                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1410                 else
1411                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1412         }
1413         for (i = 0; i < 100; i++) {
1414                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1415                         i = 0;
1416                         break;
1417                 }
1418                 udelay(10);
1419         }
1420         if (i)
1421                 b43err(dev->wl, "run samples timeout\n");
1422
1423         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1424 }
1425
1426 /*
1427  * Transmits a known value for LO calibration
1428  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1429  */
1430 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1431                                 bool iqmode, bool dac_test)
1432 {
1433         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1434         if (samp == 0)
1435                 return -1;
1436         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1437         return 0;
1438 }
1439
1440 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1441 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1442 {
1443         struct b43_phy_n *nphy = dev->phy.n;
1444         int i, j;
1445         u32 tmp;
1446         u32 cur_real, cur_imag, real_part, imag_part;
1447
1448         u16 buffer[7];
1449
1450         if (nphy->hang_avoid)
1451                 b43_nphy_stay_in_carrier_search(dev, true);
1452
1453         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1454
1455         for (i = 0; i < 2; i++) {
1456                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1457                         (buffer[i * 2 + 1] & 0x3FF);
1458                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1459                                 (((i + 26) << 10) | 320));
1460                 for (j = 0; j < 128; j++) {
1461                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1462                                         ((tmp >> 16) & 0xFFFF));
1463                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1464                                         (tmp & 0xFFFF));
1465                 }
1466         }
1467
1468         for (i = 0; i < 2; i++) {
1469                 tmp = buffer[5 + i];
1470                 real_part = (tmp >> 8) & 0xFF;
1471                 imag_part = (tmp & 0xFF);
1472                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1473                                 (((i + 26) << 10) | 448));
1474
1475                 if (dev->phy.rev >= 3) {
1476                         cur_real = real_part;
1477                         cur_imag = imag_part;
1478                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1479                 }
1480
1481                 for (j = 0; j < 128; j++) {
1482                         if (dev->phy.rev < 3) {
1483                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1484                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1485                                 tmp = ((cur_real & 0xFF) << 8) |
1486                                         (cur_imag & 0xFF);
1487                         }
1488                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1489                                         ((tmp >> 16) & 0xFFFF));
1490                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1491                                         (tmp & 0xFFFF));
1492                 }
1493         }
1494
1495         if (dev->phy.rev >= 3) {
1496                 b43_shm_write16(dev, B43_SHM_SHARED,
1497                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1498                 b43_shm_write16(dev, B43_SHM_SHARED,
1499                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1500         }
1501
1502         if (nphy->hang_avoid)
1503                 b43_nphy_stay_in_carrier_search(dev, false);
1504 }
1505
1506 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1507 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1508                                         u8 *events, u8 *delays, u8 length)
1509 {
1510         struct b43_phy_n *nphy = dev->phy.n;
1511         u8 i;
1512         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1513         u16 offset1 = cmd << 4;
1514         u16 offset2 = offset1 + 0x80;
1515
1516         if (nphy->hang_avoid)
1517                 b43_nphy_stay_in_carrier_search(dev, true);
1518
1519         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1520         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1521
1522         for (i = length; i < 16; i++) {
1523                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1524                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1525         }
1526
1527         if (nphy->hang_avoid)
1528                 b43_nphy_stay_in_carrier_search(dev, false);
1529 }
1530
1531 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1532 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1533                                        enum b43_nphy_rf_sequence seq)
1534 {
1535         static const u16 trigger[] = {
1536                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1537                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1538                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1539                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1540                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1541                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1542         };
1543         int i;
1544         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1545
1546         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1547
1548         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1549                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1550         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1551         for (i = 0; i < 200; i++) {
1552                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1553                         goto ok;
1554                 msleep(1);
1555         }
1556         b43err(dev->wl, "RF sequence status timeout\n");
1557 ok:
1558         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1559 }
1560
1561 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1562 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1563                                                 u16 value, u8 core, bool off)
1564 {
1565         int i;
1566         u8 index = fls(field);
1567         u8 addr, en_addr, val_addr;
1568         /* we expect only one bit set */
1569         B43_WARN_ON(field & (~(1 << (index - 1))));
1570
1571         if (dev->phy.rev >= 3) {
1572                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1573                 for (i = 0; i < 2; i++) {
1574                         if (index == 0 || index == 16) {
1575                                 b43err(dev->wl,
1576                                         "Unsupported RF Ctrl Override call\n");
1577                                 return;
1578                         }
1579
1580                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1581                         en_addr = B43_PHY_N((i == 0) ?
1582                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1583                         val_addr = B43_PHY_N((i == 0) ?
1584                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1585
1586                         if (off) {
1587                                 b43_phy_mask(dev, en_addr, ~(field));
1588                                 b43_phy_mask(dev, val_addr,
1589                                                 ~(rf_ctrl->val_mask));
1590                         } else {
1591                                 if (core == 0 || ((1 << core) & i) != 0) {
1592                                         b43_phy_set(dev, en_addr, field);
1593                                         b43_phy_maskset(dev, val_addr,
1594                                                 ~(rf_ctrl->val_mask),
1595                                                 (value << rf_ctrl->val_shift));
1596                                 }
1597                         }
1598                 }
1599         } else {
1600                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1601                 if (off) {
1602                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1603                         value = 0;
1604                 } else {
1605                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1606                 }
1607
1608                 for (i = 0; i < 2; i++) {
1609                         if (index <= 1 || index == 16) {
1610                                 b43err(dev->wl,
1611                                         "Unsupported RF Ctrl Override call\n");
1612                                 return;
1613                         }
1614
1615                         if (index == 2 || index == 10 ||
1616                             (index >= 13 && index <= 15)) {
1617                                 core = 1;
1618                         }
1619
1620                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1621                         addr = B43_PHY_N((i == 0) ?
1622                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1623
1624                         if ((core & (1 << i)) != 0)
1625                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1626                                                 (value << rf_ctrl->shift));
1627
1628                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1629                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1630                                         B43_NPHY_RFCTL_CMD_START);
1631                         udelay(1);
1632                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1633                 }
1634         }
1635 }
1636
1637 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1638 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1639                                                 u16 value, u8 core)
1640 {
1641         u8 i, j;
1642         u16 reg, tmp, val;
1643
1644         B43_WARN_ON(dev->phy.rev < 3);
1645         B43_WARN_ON(field > 4);
1646
1647         for (i = 0; i < 2; i++) {
1648                 if ((core == 1 && i == 1) || (core == 2 && !i))
1649                         continue;
1650
1651                 reg = (i == 0) ?
1652                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1653                 b43_phy_mask(dev, reg, 0xFBFF);
1654
1655                 switch (field) {
1656                 case 0:
1657                         b43_phy_write(dev, reg, 0);
1658                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1659                         break;
1660                 case 1:
1661                         if (!i) {
1662                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1663                                                 0xFC3F, (value << 6));
1664                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1665                                                 0xFFFE, 1);
1666                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1667                                                 B43_NPHY_RFCTL_CMD_START);
1668                                 for (j = 0; j < 100; j++) {
1669                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1670                                                 j = 0;
1671                                                 break;
1672                                         }
1673                                         udelay(10);
1674                                 }
1675                                 if (j)
1676                                         b43err(dev->wl,
1677                                                 "intc override timeout\n");
1678                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1679                                                 0xFFFE);
1680                         } else {
1681                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1682                                                 0xFC3F, (value << 6));
1683                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1684                                                 0xFFFE, 1);
1685                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1686                                                 B43_NPHY_RFCTL_CMD_RXTX);
1687                                 for (j = 0; j < 100; j++) {
1688                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1689                                                 j = 0;
1690                                                 break;
1691                                         }
1692                                         udelay(10);
1693                                 }
1694                                 if (j)
1695                                         b43err(dev->wl,
1696                                                 "intc override timeout\n");
1697                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1698                                                 0xFFFE);
1699                         }
1700                         break;
1701                 case 2:
1702                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1703                                 tmp = 0x0020;
1704                                 val = value << 5;
1705                         } else {
1706                                 tmp = 0x0010;
1707                                 val = value << 4;
1708                         }
1709                         b43_phy_maskset(dev, reg, ~tmp, val);
1710                         break;
1711                 case 3:
1712                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1713                                 tmp = 0x0001;
1714                                 val = value;
1715                         } else {
1716                                 tmp = 0x0004;
1717                                 val = value << 2;
1718                         }
1719                         b43_phy_maskset(dev, reg, ~tmp, val);
1720                         break;
1721                 case 4:
1722                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1723                                 tmp = 0x0002;
1724                                 val = value << 1;
1725                         } else {
1726                                 tmp = 0x0008;
1727                                 val = value << 3;
1728                         }
1729                         b43_phy_maskset(dev, reg, ~tmp, val);
1730                         break;
1731                 }
1732         }
1733 }
1734
1735 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
1736 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1737 {
1738         unsigned int i;
1739         u16 val;
1740
1741         val = 0x1E1F;
1742         for (i = 0; i < 16; i++) {
1743                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1744                 val -= 0x202;
1745         }
1746         val = 0x3E3F;
1747         for (i = 0; i < 16; i++) {
1748                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
1749                 val -= 0x202;
1750         }
1751         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1752 }
1753
1754 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1755 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1756                                         s8 offset, u8 core, u8 rail,
1757                                         enum b43_nphy_rssi_type type)
1758 {
1759         u16 tmp;
1760         bool core1or5 = (core == 1) || (core == 5);
1761         bool core2or5 = (core == 2) || (core == 5);
1762
1763         offset = clamp_val(offset, -32, 31);
1764         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1765
1766         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1767                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1768         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1769                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1770         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
1771                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1772         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
1773                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1774
1775         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1776                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1777         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1778                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1779         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1780                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1781         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1782                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1783
1784         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1785                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1786         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1787                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1788         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1789                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1790         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1791                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1792
1793         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1794                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1795         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1796                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1797         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1798                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1799         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1800                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1801
1802         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1803                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1804         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1805                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1806         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1807                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1808         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1809                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1810
1811         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1812                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1813         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1814                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1815
1816         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1817                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1818         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1819                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1820 }
1821
1822 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1823 {
1824         u16 val;
1825
1826         if (type < 3)
1827                 val = 0;
1828         else if (type == 6)
1829                 val = 1;
1830         else if (type == 3)
1831                 val = 2;
1832         else
1833                 val = 3;
1834
1835         val = (val << 12) | (val << 14);
1836         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1837         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1838
1839         if (type < 3) {
1840                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1841                                 (type + 1) << 4);
1842                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1843                                 (type + 1) << 4);
1844         }
1845
1846         if (code == 0) {
1847                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1848                 if (type < 3) {
1849                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1850                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1851                                   B43_NPHY_RFCTL_CMD_CORESEL));
1852                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1853                                 ~(0x1 << 12 |
1854                                   0x1 << 5 |
1855                                   0x1 << 1 |
1856                                   0x1));
1857                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1858                                 ~B43_NPHY_RFCTL_CMD_START);
1859                         udelay(20);
1860                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1861                 }
1862         } else {
1863                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1864                 if (type < 3) {
1865                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1866                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1867                                   B43_NPHY_RFCTL_CMD_CORESEL),
1868                                 (B43_NPHY_RFCTL_CMD_RXEN |
1869                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1870                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1871                                 (0x1 << 12 |
1872                                   0x1 << 5 |
1873                                   0x1 << 1 |
1874                                   0x1));
1875                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1876                                 B43_NPHY_RFCTL_CMD_START);
1877                         udelay(20);
1878                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1879                 }
1880         }
1881 }
1882
1883 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1884 {
1885         struct b43_phy_n *nphy = dev->phy.n;
1886         u8 i;
1887         u16 reg, val;
1888
1889         if (code == 0) {
1890                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1891                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1892                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1893                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1894                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1895                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1896                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1897                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1898         } else {
1899                 for (i = 0; i < 2; i++) {
1900                         if ((code == 1 && i == 1) || (code == 2 && !i))
1901                                 continue;
1902
1903                         reg = (i == 0) ?
1904                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1905                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1906
1907                         if (type < 3) {
1908                                 reg = (i == 0) ?
1909                                         B43_NPHY_AFECTL_C1 :
1910                                         B43_NPHY_AFECTL_C2;
1911                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1912
1913                                 reg = (i == 0) ?
1914                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1915                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1916                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1917
1918                                 if (type == 0)
1919                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1920                                 else if (type == 1)
1921                                         val = 16;
1922                                 else
1923                                         val = 32;
1924                                 b43_phy_set(dev, reg, val);
1925
1926                                 reg = (i == 0) ?
1927                                         B43_NPHY_TXF_40CO_B1S0 :
1928                                         B43_NPHY_TXF_40CO_B32S1;
1929                                 b43_phy_set(dev, reg, 0x0020);
1930                         } else {
1931                                 if (type == 6)
1932                                         val = 0x0100;
1933                                 else if (type == 3)
1934                                         val = 0x0200;
1935                                 else
1936                                         val = 0x0300;
1937
1938                                 reg = (i == 0) ?
1939                                         B43_NPHY_AFECTL_C1 :
1940                                         B43_NPHY_AFECTL_C2;
1941
1942                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1943                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1944
1945                                 if (type != 3 && type != 6) {
1946                                         enum ieee80211_band band =
1947                                                 b43_current_band(dev->wl);
1948
1949                                         if ((nphy->ipa2g_on &&
1950                                                 band == IEEE80211_BAND_2GHZ) ||
1951                                                 (nphy->ipa5g_on &&
1952                                                 band == IEEE80211_BAND_5GHZ))
1953                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1954                                         else
1955                                                 val = 0x11;
1956                                         reg = (i == 0) ? 0x2000 : 0x3000;
1957                                         reg |= B2055_PADDRV;
1958                                         b43_radio_write16(dev, reg, val);
1959
1960                                         reg = (i == 0) ?
1961                                                 B43_NPHY_AFECTL_OVER1 :
1962                                                 B43_NPHY_AFECTL_OVER;
1963                                         b43_phy_set(dev, reg, 0x0200);
1964                                 }
1965                         }
1966                 }
1967         }
1968 }
1969
1970 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1971 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1972 {
1973         if (dev->phy.rev >= 3)
1974                 b43_nphy_rev3_rssi_select(dev, code, type);
1975         else
1976                 b43_nphy_rev2_rssi_select(dev, code, type);
1977 }
1978
1979 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1980 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1981 {
1982         int i;
1983         for (i = 0; i < 2; i++) {
1984                 if (type == 2) {
1985                         if (i == 0) {
1986                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1987                                                   0xFC, buf[0]);
1988                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1989                                                   0xFC, buf[1]);
1990                         } else {
1991                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1992                                                   0xFC, buf[2 * i]);
1993                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1994                                                   0xFC, buf[2 * i + 1]);
1995                         }
1996                 } else {
1997                         if (i == 0)
1998                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1999                                                   0xF3, buf[0] << 2);
2000                         else
2001                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2002                                                   0xF3, buf[2 * i + 1] << 2);
2003                 }
2004         }
2005 }
2006
2007 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2008 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2009                                 u8 nsamp)
2010 {
2011         int i;
2012         int out;
2013         u16 save_regs_phy[9];
2014         u16 s[2];
2015
2016         if (dev->phy.rev >= 3) {
2017                 save_regs_phy[0] = b43_phy_read(dev,
2018                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2019                 save_regs_phy[1] = b43_phy_read(dev,
2020                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2021                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2022                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2023                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2024                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2025                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2026                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2027         } else if (dev->phy.rev == 2) {
2028                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2029                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2030                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2031                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2032                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2033                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2034                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2035         }
2036
2037         b43_nphy_rssi_select(dev, 5, type);
2038
2039         if (dev->phy.rev < 2) {
2040                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2041                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2042         }
2043
2044         for (i = 0; i < 4; i++)
2045                 buf[i] = 0;
2046
2047         for (i = 0; i < nsamp; i++) {
2048                 if (dev->phy.rev < 2) {
2049                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2050                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2051                 } else {
2052                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2053                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2054                 }
2055
2056                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2057                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2058                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2059                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2060         }
2061         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2062                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2063
2064         if (dev->phy.rev < 2)
2065                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2066
2067         if (dev->phy.rev >= 3) {
2068                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2069                                 save_regs_phy[0]);
2070                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2071                                 save_regs_phy[1]);
2072                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2073                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2074                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2075                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2076                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2077                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2078         } else if (dev->phy.rev == 2) {
2079                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2080                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2081                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2082                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2083                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2084                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2085                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2086         }
2087
2088         return out;
2089 }
2090
2091 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2092 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2093 {
2094         int i, j;
2095         u8 state[4];
2096         u8 code, val;
2097         u16 class, override;
2098         u8 regs_save_radio[2];
2099         u16 regs_save_phy[2];
2100
2101         s8 offset[4];
2102         u8 core;
2103         u8 rail;
2104
2105         u16 clip_state[2];
2106         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2107         s32 results_min[4] = { };
2108         u8 vcm_final[4] = { };
2109         s32 results[4][4] = { };
2110         s32 miniq[4][2] = { };
2111
2112         if (type == 2) {
2113                 code = 0;
2114                 val = 6;
2115         } else if (type < 2) {
2116                 code = 25;
2117                 val = 4;
2118         } else {
2119                 B43_WARN_ON(1);
2120                 return;
2121         }
2122
2123         class = b43_nphy_classifier(dev, 0, 0);
2124         b43_nphy_classifier(dev, 7, 4);
2125         b43_nphy_read_clip_detection(dev, clip_state);
2126         b43_nphy_write_clip_detection(dev, clip_off);
2127
2128         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2129                 override = 0x140;
2130         else
2131                 override = 0x110;
2132
2133         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2134         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2135         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2136         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2137
2138         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2139         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2140         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2141         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2142
2143         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2144         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2145         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2146         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2147         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2148         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2149
2150         b43_nphy_rssi_select(dev, 5, type);
2151         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2152         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2153
2154         for (i = 0; i < 4; i++) {
2155                 u8 tmp[4];
2156                 for (j = 0; j < 4; j++)
2157                         tmp[j] = i;
2158                 if (type != 1)
2159                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2160                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2161                 if (type < 2)
2162                         for (j = 0; j < 2; j++)
2163                                 miniq[i][j] = min(results[i][2 * j],
2164                                                 results[i][2 * j + 1]);
2165         }
2166
2167         for (i = 0; i < 4; i++) {
2168                 s32 mind = 40;
2169                 u8 minvcm = 0;
2170                 s32 minpoll = 249;
2171                 s32 curr;
2172                 for (j = 0; j < 4; j++) {
2173                         if (type == 2)
2174                                 curr = abs(results[j][i]);
2175                         else
2176                                 curr = abs(miniq[j][i / 2] - code * 8);
2177
2178                         if (curr < mind) {
2179                                 mind = curr;
2180                                 minvcm = j;
2181                         }
2182
2183                         if (results[j][i] < minpoll)
2184                                 minpoll = results[j][i];
2185                 }
2186                 results_min[i] = minpoll;
2187                 vcm_final[i] = minvcm;
2188         }
2189
2190         if (type != 1)
2191                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2192
2193         for (i = 0; i < 4; i++) {
2194                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2195
2196                 if (offset[i] < 0)
2197                         offset[i] = -((abs(offset[i]) + 4) / 8);
2198                 else
2199                         offset[i] = (offset[i] + 4) / 8;
2200
2201                 if (results_min[i] == 248)
2202                         offset[i] = code - 32;
2203
2204                 core = (i / 2) ? 2 : 1;
2205                 rail = (i % 2) ? 1 : 0;
2206
2207                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2208                                                 type);
2209         }
2210
2211         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2212         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2213
2214         switch (state[2]) {
2215         case 1:
2216                 b43_nphy_rssi_select(dev, 1, 2);
2217                 break;
2218         case 4:
2219                 b43_nphy_rssi_select(dev, 1, 0);
2220                 break;
2221         case 2:
2222                 b43_nphy_rssi_select(dev, 1, 1);
2223                 break;
2224         default:
2225                 b43_nphy_rssi_select(dev, 1, 1);
2226                 break;
2227         }
2228
2229         switch (state[3]) {
2230         case 1:
2231                 b43_nphy_rssi_select(dev, 2, 2);
2232                 break;
2233         case 4:
2234                 b43_nphy_rssi_select(dev, 2, 0);
2235                 break;
2236         default:
2237                 b43_nphy_rssi_select(dev, 2, 1);
2238                 break;
2239         }
2240
2241         b43_nphy_rssi_select(dev, 0, type);
2242
2243         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2244         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2245         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2246         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2247
2248         b43_nphy_classifier(dev, 7, class);
2249         b43_nphy_write_clip_detection(dev, clip_state);
2250         /* Specs don't say about reset here, but it makes wl and b43 dumps
2251            identical, it really seems wl performs this */
2252         b43_nphy_reset_cca(dev);
2253 }
2254
2255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2256 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2257 {
2258         /* TODO */
2259 }
2260
2261 /*
2262  * RSSI Calibration
2263  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2264  */
2265 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2266 {
2267         if (dev->phy.rev >= 3) {
2268                 b43_nphy_rev3_rssi_cal(dev);
2269         } else {
2270                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2271                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2272                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2273         }
2274 }
2275
2276 /*
2277  * Restore RSSI Calibration
2278  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2279  */
2280 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2281 {
2282         struct b43_phy_n *nphy = dev->phy.n;
2283
2284         u16 *rssical_radio_regs = NULL;
2285         u16 *rssical_phy_regs = NULL;
2286
2287         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2288                 if (!nphy->rssical_chanspec_2G.center_freq)
2289                         return;
2290                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2291                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2292         } else {
2293                 if (!nphy->rssical_chanspec_5G.center_freq)
2294                         return;
2295                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2296                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2297         }
2298
2299         /* TODO use some definitions */
2300         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2301         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2302
2303         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2304         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2305         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2306         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2307
2308         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2309         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2310         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2311         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2312
2313         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2314         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2315         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2316         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2317 }
2318
2319 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2320 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2321 {
2322         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2323                 if (dev->phy.rev >= 6) {
2324                         /* TODO If the chip is 47162
2325                                 return txpwrctrl_tx_gain_ipa_rev5 */
2326                         return txpwrctrl_tx_gain_ipa_rev6;
2327                 } else if (dev->phy.rev >= 5) {
2328                         return txpwrctrl_tx_gain_ipa_rev5;
2329                 } else {
2330                         return txpwrctrl_tx_gain_ipa;
2331                 }
2332         } else {
2333                 return txpwrctrl_tx_gain_ipa_5g;
2334         }
2335 }
2336
2337 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2338 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2339 {
2340         struct b43_phy_n *nphy = dev->phy.n;
2341         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2342         u16 tmp;
2343         u8 offset, i;
2344
2345         if (dev->phy.rev >= 3) {
2346             for (i = 0; i < 2; i++) {
2347                 tmp = (i == 0) ? 0x2000 : 0x3000;
2348                 offset = i * 11;
2349
2350                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2351                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2352                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2353                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2354                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2355                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2356                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2357                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2358                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2359                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2360                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2361
2362                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2363                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2364                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2365                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2366                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2367                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2368                         if (nphy->ipa5g_on) {
2369                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2370                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2371                         } else {
2372                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2373                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2374                         }
2375                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2376                 } else {
2377                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2378                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2379                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2380                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2381                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2382                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2383                         if (nphy->ipa2g_on) {
2384                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2385                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2386                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2387                         } else {
2388                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2389                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2390                         }
2391                 }
2392                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2393                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2394                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2395             }
2396         } else {
2397                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2398                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2399
2400                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2401                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2402
2403                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2404                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2405
2406                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2407                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2408
2409                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2410                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2411
2412                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2413                     B43_NPHY_BANDCTL_5GHZ)) {
2414                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2415                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2416                 } else {
2417                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2418                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2419                 }
2420
2421                 if (dev->phy.rev < 2) {
2422                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2423                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2424                 } else {
2425                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2426                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2427                 }
2428         }
2429 }
2430
2431 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2432 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2433                                         struct nphy_txgains target,
2434                                         struct nphy_iqcal_params *params)
2435 {
2436         int i, j, indx;
2437         u16 gain;
2438
2439         if (dev->phy.rev >= 3) {
2440                 params->txgm = target.txgm[core];
2441                 params->pga = target.pga[core];
2442                 params->pad = target.pad[core];
2443                 params->ipa = target.ipa[core];
2444                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2445                                         (params->pad << 4) | (params->ipa);
2446                 for (j = 0; j < 5; j++)
2447                         params->ncorr[j] = 0x79;
2448         } else {
2449                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2450                         (target.txgm[core] << 8);
2451
2452                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2453                         1 : 0;
2454                 for (i = 0; i < 9; i++)
2455                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2456                                 break;
2457                 i = min(i, 8);
2458
2459                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2460                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2461                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2462                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2463                                         (params->pad << 2);
2464                 for (j = 0; j < 4; j++)
2465                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2466         }
2467 }
2468
2469 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2470 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2471 {
2472         struct b43_phy_n *nphy = dev->phy.n;
2473         int i;
2474         u16 scale, entry;
2475
2476         u16 tmp = nphy->txcal_bbmult;
2477         if (core == 0)
2478                 tmp >>= 8;
2479         tmp &= 0xff;
2480
2481         for (i = 0; i < 18; i++) {
2482                 scale = (ladder_lo[i].percent * tmp) / 100;
2483                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2484                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2485
2486                 scale = (ladder_iq[i].percent * tmp) / 100;
2487                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2488                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2489         }
2490 }
2491
2492 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2493 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2494 {
2495         int i;
2496         for (i = 0; i < 15; i++)
2497                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2498                                 tbl_tx_filter_coef_rev4[2][i]);
2499 }
2500
2501 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2502 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2503 {
2504         int i, j;
2505         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2506         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2507
2508         for (i = 0; i < 3; i++)
2509                 for (j = 0; j < 15; j++)
2510                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2511                                         tbl_tx_filter_coef_rev4[i][j]);
2512
2513         if (dev->phy.is_40mhz) {
2514                 for (j = 0; j < 15; j++)
2515                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2516                                         tbl_tx_filter_coef_rev4[3][j]);
2517         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2518                 for (j = 0; j < 15; j++)
2519                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2520                                         tbl_tx_filter_coef_rev4[5][j]);
2521         }
2522
2523         if (dev->phy.channel == 14)
2524                 for (j = 0; j < 15; j++)
2525                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2526                                         tbl_tx_filter_coef_rev4[6][j]);
2527 }
2528
2529 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2530 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2531 {
2532         struct b43_phy_n *nphy = dev->phy.n;
2533
2534         u16 curr_gain[2];
2535         struct nphy_txgains target;
2536         const u32 *table = NULL;
2537
2538         if (!nphy->txpwrctrl) {
2539                 int i;
2540
2541                 if (nphy->hang_avoid)
2542                         b43_nphy_stay_in_carrier_search(dev, true);
2543                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2544                 if (nphy->hang_avoid)
2545                         b43_nphy_stay_in_carrier_search(dev, false);
2546
2547                 for (i = 0; i < 2; ++i) {
2548                         if (dev->phy.rev >= 3) {
2549                                 target.ipa[i] = curr_gain[i] & 0x000F;
2550                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2551                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2552                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2553                         } else {
2554                                 target.ipa[i] = curr_gain[i] & 0x0003;
2555                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2556                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2557                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2558                         }
2559                 }
2560         } else {
2561                 int i;
2562                 u16 index[2];
2563                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2564                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2565                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2566                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2567                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2568                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2569
2570                 for (i = 0; i < 2; ++i) {
2571                         if (dev->phy.rev >= 3) {
2572                                 enum ieee80211_band band =
2573                                         b43_current_band(dev->wl);
2574
2575                                 if ((nphy->ipa2g_on &&
2576                                      band == IEEE80211_BAND_2GHZ) ||
2577                                     (nphy->ipa5g_on &&
2578                                      band == IEEE80211_BAND_5GHZ)) {
2579                                         table = b43_nphy_get_ipa_gain_table(dev);
2580                                 } else {
2581                                         if (band == IEEE80211_BAND_5GHZ) {
2582                                                 if (dev->phy.rev == 3)
2583                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2584                                                 else if (dev->phy.rev == 4)
2585                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2586                                                 else
2587                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2588                                         } else {
2589                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2590                                         }
2591                                 }
2592
2593                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2594                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2595                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2596                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2597                         } else {
2598                                 table = b43_ntab_tx_gain_rev0_1_2;
2599
2600                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2601                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2602                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2603                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2604                         }
2605                 }
2606         }
2607
2608         return target;
2609 }
2610
2611 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2612 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2613 {
2614         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2615
2616         if (dev->phy.rev >= 3) {
2617                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2618                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2619                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2620                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2621                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2622                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2623                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2624                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2625                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2626                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2627                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2628                 b43_nphy_reset_cca(dev);
2629         } else {
2630                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2631                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2632                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2633                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2634                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2635                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2636                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2637         }
2638 }
2639
2640 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2641 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2642 {
2643         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2644         u16 tmp;
2645
2646         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2647         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2648         if (dev->phy.rev >= 3) {
2649                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2650                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2651
2652                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2653                 regs[2] = tmp;
2654                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2655
2656                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2657                 regs[3] = tmp;
2658                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2659
2660                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2661                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2662                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2663
2664                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2665                 regs[5] = tmp;
2666                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2667
2668                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2669                 regs[6] = tmp;
2670                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2671                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2672                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2673
2674                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2675                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2676                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2677
2678                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2679                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2680                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2681                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2682         } else {
2683                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2684                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2685                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2686                 regs[2] = tmp;
2687                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2688                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2689                 regs[3] = tmp;
2690                 tmp |= 0x2000;
2691                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2692                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2693                 regs[4] = tmp;
2694                 tmp |= 0x2000;
2695                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2696                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2697                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2698                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2699                         tmp = 0x0180;
2700                 else
2701                         tmp = 0x0120;
2702                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2703                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2704         }
2705 }
2706
2707 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2708 static void b43_nphy_save_cal(struct b43_wldev *dev)
2709 {
2710         struct b43_phy_n *nphy = dev->phy.n;
2711
2712         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2713         u16 *txcal_radio_regs = NULL;
2714         struct b43_chanspec *iqcal_chanspec;
2715         u16 *table = NULL;
2716
2717         if (nphy->hang_avoid)
2718                 b43_nphy_stay_in_carrier_search(dev, 1);
2719
2720         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2721                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2722                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2723                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2724                 table = nphy->cal_cache.txcal_coeffs_2G;
2725         } else {
2726                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2727                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2728                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2729                 table = nphy->cal_cache.txcal_coeffs_5G;
2730         }
2731
2732         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2733         /* TODO use some definitions */
2734         if (dev->phy.rev >= 3) {
2735                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2736                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2737                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2738                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2739                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2740                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2741                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2742                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2743         } else {
2744                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2745                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2746                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2747                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2748         }
2749         iqcal_chanspec->center_freq = dev->phy.channel_freq;
2750         iqcal_chanspec->channel_type = dev->phy.channel_type;
2751         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
2752
2753         if (nphy->hang_avoid)
2754                 b43_nphy_stay_in_carrier_search(dev, 0);
2755 }
2756
2757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2758 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2759 {
2760         struct b43_phy_n *nphy = dev->phy.n;
2761
2762         u16 coef[4];
2763         u16 *loft = NULL;
2764         u16 *table = NULL;
2765
2766         int i;
2767         u16 *txcal_radio_regs = NULL;
2768         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2769
2770         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2771                 if (!nphy->iqcal_chanspec_2G.center_freq)
2772                         return;
2773                 table = nphy->cal_cache.txcal_coeffs_2G;
2774                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2775         } else {
2776                 if (!nphy->iqcal_chanspec_5G.center_freq)
2777                         return;
2778                 table = nphy->cal_cache.txcal_coeffs_5G;
2779                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2780         }
2781
2782         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2783
2784         for (i = 0; i < 4; i++) {
2785                 if (dev->phy.rev >= 3)
2786                         table[i] = coef[i];
2787                 else
2788                         coef[i] = 0;
2789         }
2790
2791         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2792         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2793         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2794
2795         if (dev->phy.rev < 2)
2796                 b43_nphy_tx_iq_workaround(dev);
2797
2798         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2799                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2800                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2801         } else {
2802                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2803                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2804         }
2805
2806         /* TODO use some definitions */
2807         if (dev->phy.rev >= 3) {
2808                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2809                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2810                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2811                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2812                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2813                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2814                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2815                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2816         } else {
2817                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2818                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2819                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2820                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2821         }
2822         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2823 }
2824
2825 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2826 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2827                                 struct nphy_txgains target,
2828                                 bool full, bool mphase)
2829 {
2830         struct b43_phy_n *nphy = dev->phy.n;
2831         int i;
2832         int error = 0;
2833         int freq;
2834         bool avoid = false;
2835         u8 length;
2836         u16 tmp, core, type, count, max, numb, last, cmd;
2837         const u16 *table;
2838         bool phy6or5x;
2839
2840         u16 buffer[11];
2841         u16 diq_start = 0;
2842         u16 save[2];
2843         u16 gain[2];
2844         struct nphy_iqcal_params params[2];
2845         bool updated[2] = { };
2846
2847         b43_nphy_stay_in_carrier_search(dev, true);
2848
2849         if (dev->phy.rev >= 4) {
2850                 avoid = nphy->hang_avoid;
2851                 nphy->hang_avoid = 0;
2852         }
2853
2854         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2855
2856         for (i = 0; i < 2; i++) {
2857                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2858                 gain[i] = params[i].cal_gain;
2859         }
2860
2861         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2862
2863         b43_nphy_tx_cal_radio_setup(dev);
2864         b43_nphy_tx_cal_phy_setup(dev);
2865
2866         phy6or5x = dev->phy.rev >= 6 ||
2867                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2868                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2869         if (phy6or5x) {
2870                 if (dev->phy.is_40mhz) {
2871                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2872                                         tbl_tx_iqlo_cal_loft_ladder_40);
2873                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2874                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2875                 } else {
2876                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2877                                         tbl_tx_iqlo_cal_loft_ladder_20);
2878                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2879                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2880                 }
2881         }
2882
2883         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2884
2885         if (!dev->phy.is_40mhz)
2886                 freq = 2500;
2887         else
2888                 freq = 5000;
2889
2890         if (nphy->mphase_cal_phase_id > 2)
2891                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2892                                         0xFFFF, 0, true, false);
2893         else
2894                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2895
2896         if (error == 0) {
2897                 if (nphy->mphase_cal_phase_id > 2) {
2898                         table = nphy->mphase_txcal_bestcoeffs;
2899                         length = 11;
2900                         if (dev->phy.rev < 3)
2901                                 length -= 2;
2902                 } else {
2903                         if (!full && nphy->txiqlocal_coeffsvalid) {
2904                                 table = nphy->txiqlocal_bestc;
2905                                 length = 11;
2906                                 if (dev->phy.rev < 3)
2907                                         length -= 2;
2908                         } else {
2909                                 full = true;
2910                                 if (dev->phy.rev >= 3) {
2911                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2912                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2913                                 } else {
2914                                         table = tbl_tx_iqlo_cal_startcoefs;
2915                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2916                                 }
2917                         }
2918                 }
2919
2920                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2921
2922                 if (full) {
2923                         if (dev->phy.rev >= 3)
2924                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2925                         else
2926                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2927                 } else {
2928                         if (dev->phy.rev >= 3)
2929                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2930                         else
2931                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2932                 }
2933
2934                 if (mphase) {
2935                         count = nphy->mphase_txcal_cmdidx;
2936                         numb = min(max,
2937                                 (u16)(count + nphy->mphase_txcal_numcmds));
2938                 } else {
2939                         count = 0;
2940                         numb = max;
2941                 }
2942
2943                 for (; count < numb; count++) {
2944                         if (full) {
2945                                 if (dev->phy.rev >= 3)
2946                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2947                                 else
2948                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2949                         } else {
2950                                 if (dev->phy.rev >= 3)
2951                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2952                                 else
2953                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2954                         }
2955
2956                         core = (cmd & 0x3000) >> 12;
2957                         type = (cmd & 0x0F00) >> 8;
2958
2959                         if (phy6or5x && updated[core] == 0) {
2960                                 b43_nphy_update_tx_cal_ladder(dev, core);
2961                                 updated[core] = 1;
2962                         }
2963
2964                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2965                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2966
2967                         if (type == 1 || type == 3 || type == 4) {
2968                                 buffer[0] = b43_ntab_read(dev,
2969                                                 B43_NTAB16(15, 69 + core));
2970                                 diq_start = buffer[0];
2971                                 buffer[0] = 0;
2972                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2973                                                 0);
2974                         }
2975
2976                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2977                         for (i = 0; i < 2000; i++) {
2978                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2979                                 if (tmp & 0xC000)
2980                                         break;
2981                                 udelay(10);
2982                         }
2983
2984                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2985                                                 buffer);
2986                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2987                                                 buffer);
2988
2989                         if (type == 1 || type == 3 || type == 4)
2990                                 buffer[0] = diq_start;
2991                 }
2992
2993                 if (mphase)
2994                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2995
2996                 last = (dev->phy.rev < 3) ? 6 : 7;
2997
2998                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2999                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3000                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3001                         if (dev->phy.rev < 3) {
3002                                 buffer[0] = 0;
3003                                 buffer[1] = 0;
3004                                 buffer[2] = 0;
3005                                 buffer[3] = 0;
3006                         }
3007                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3008                                                 buffer);
3009                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3010                                                 buffer);
3011                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3012                                                 buffer);
3013                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3014                                                 buffer);
3015                         length = 11;
3016                         if (dev->phy.rev < 3)
3017                                 length -= 2;
3018                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3019                                                 nphy->txiqlocal_bestc);
3020                         nphy->txiqlocal_coeffsvalid = true;
3021                         nphy->txiqlocal_chanspec.center_freq =
3022                                                         dev->phy.channel_freq;
3023                         nphy->txiqlocal_chanspec.channel_type =
3024                                                         dev->phy.channel_type;
3025                 } else {
3026                         length = 11;
3027                         if (dev->phy.rev < 3)
3028                                 length -= 2;
3029                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3030                                                 nphy->mphase_txcal_bestcoeffs);
3031                 }
3032
3033                 b43_nphy_stop_playback(dev);
3034                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3035         }
3036
3037         b43_nphy_tx_cal_phy_cleanup(dev);
3038         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3039
3040         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3041                 b43_nphy_tx_iq_workaround(dev);
3042
3043         if (dev->phy.rev >= 4)
3044                 nphy->hang_avoid = avoid;
3045
3046         b43_nphy_stay_in_carrier_search(dev, false);
3047
3048         return error;
3049 }
3050
3051 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3052 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3053 {
3054         struct b43_phy_n *nphy = dev->phy.n;
3055         u8 i;
3056         u16 buffer[7];
3057         bool equal = true;
3058
3059         if (!nphy->txiqlocal_coeffsvalid ||
3060             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3061             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3062                 return;
3063
3064         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3065         for (i = 0; i < 4; i++) {
3066                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3067                         equal = false;
3068                         break;
3069                 }
3070         }
3071
3072         if (!equal) {
3073                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3074                                         nphy->txiqlocal_bestc);
3075                 for (i = 0; i < 4; i++)
3076                         buffer[i] = 0;
3077                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3078                                         buffer);
3079                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3080                                         &nphy->txiqlocal_bestc[5]);
3081                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3082                                         &nphy->txiqlocal_bestc[5]);
3083         }
3084 }
3085
3086 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3087 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3088                         struct nphy_txgains target, u8 type, bool debug)
3089 {
3090         struct b43_phy_n *nphy = dev->phy.n;
3091         int i, j, index;
3092         u8 rfctl[2];
3093         u8 afectl_core;
3094         u16 tmp[6];
3095         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3096         u32 real, imag;
3097         enum ieee80211_band band;
3098
3099         u8 use;
3100         u16 cur_hpf;
3101         u16 lna[3] = { 3, 3, 1 };
3102         u16 hpf1[3] = { 7, 2, 0 };
3103         u16 hpf2[3] = { 2, 0, 0 };
3104         u32 power[3] = { };
3105         u16 gain_save[2];
3106         u16 cal_gain[2];
3107         struct nphy_iqcal_params cal_params[2];
3108         struct nphy_iq_est est;
3109         int ret = 0;
3110         bool playtone = true;
3111         int desired = 13;
3112
3113         b43_nphy_stay_in_carrier_search(dev, 1);
3114
3115         if (dev->phy.rev < 2)
3116                 b43_nphy_reapply_tx_cal_coeffs(dev);
3117         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3118         for (i = 0; i < 2; i++) {
3119                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3120                 cal_gain[i] = cal_params[i].cal_gain;
3121         }
3122         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3123
3124         for (i = 0; i < 2; i++) {
3125                 if (i == 0) {
3126                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3127                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3128                         afectl_core = B43_NPHY_AFECTL_C1;
3129                 } else {
3130                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3131                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3132                         afectl_core = B43_NPHY_AFECTL_C2;
3133                 }
3134
3135                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3136                 tmp[2] = b43_phy_read(dev, afectl_core);
3137                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3138                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3139                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3140
3141                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3142                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3143                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3144                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3145                                 (1 - i));
3146                 b43_phy_set(dev, afectl_core, 0x0006);
3147                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3148
3149                 band = b43_current_band(dev->wl);
3150
3151                 if (nphy->rxcalparams & 0xFF000000) {
3152                         if (band == IEEE80211_BAND_5GHZ)
3153                                 b43_phy_write(dev, rfctl[0], 0x140);
3154                         else
3155                                 b43_phy_write(dev, rfctl[0], 0x110);
3156                 } else {
3157                         if (band == IEEE80211_BAND_5GHZ)
3158                                 b43_phy_write(dev, rfctl[0], 0x180);
3159                         else
3160                                 b43_phy_write(dev, rfctl[0], 0x120);
3161                 }
3162
3163                 if (band == IEEE80211_BAND_5GHZ)
3164                         b43_phy_write(dev, rfctl[1], 0x148);
3165                 else
3166                         b43_phy_write(dev, rfctl[1], 0x114);
3167
3168                 if (nphy->rxcalparams & 0x10000) {
3169                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3170                                         (i + 1));
3171                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3172                                         (2 - i));
3173                 }
3174
3175                 for (j = 0; j < 4; j++) {
3176                         if (j < 3) {
3177                                 cur_lna = lna[j];
3178                                 cur_hpf1 = hpf1[j];
3179                                 cur_hpf2 = hpf2[j];
3180                         } else {
3181                                 if (power[1] > 10000) {
3182                                         use = 1;
3183                                         cur_hpf = cur_hpf1;
3184                                         index = 2;
3185                                 } else {
3186                                         if (power[0] > 10000) {
3187                                                 use = 1;
3188                                                 cur_hpf = cur_hpf1;
3189                                                 index = 1;
3190                                         } else {
3191                                                 index = 0;
3192                                                 use = 2;
3193                                                 cur_hpf = cur_hpf2;
3194                                         }
3195                                 }
3196                                 cur_lna = lna[index];
3197                                 cur_hpf1 = hpf1[index];
3198                                 cur_hpf2 = hpf2[index];
3199                                 cur_hpf += desired - hweight32(power[index]);
3200                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3201                                 if (use == 1)
3202                                         cur_hpf1 = cur_hpf;
3203                                 else
3204                                         cur_hpf2 = cur_hpf;
3205                         }
3206
3207                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3208                                         (cur_lna << 2));
3209                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3210                                                                         false);
3211                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3212                         b43_nphy_stop_playback(dev);
3213
3214                         if (playtone) {
3215                                 ret = b43_nphy_tx_tone(dev, 4000,
3216                                                 (nphy->rxcalparams & 0xFFFF),
3217                                                 false, false);
3218                                 playtone = false;
3219                         } else {
3220                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3221                                                         false, false);
3222                         }
3223
3224                         if (ret == 0) {
3225                                 if (j < 3) {
3226                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3227                                                                         false);
3228                                         if (i == 0) {
3229                                                 real = est.i0_pwr;
3230                                                 imag = est.q0_pwr;
3231                                         } else {
3232                                                 real = est.i1_pwr;
3233                                                 imag = est.q1_pwr;
3234                                         }
3235                                         power[i] = ((real + imag) / 1024) + 1;
3236                                 } else {
3237                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3238                                 }
3239                                 b43_nphy_stop_playback(dev);
3240                         }
3241
3242                         if (ret != 0)
3243                                 break;
3244                 }
3245
3246                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3247                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3248                 b43_phy_write(dev, rfctl[1], tmp[5]);
3249                 b43_phy_write(dev, rfctl[0], tmp[4]);
3250                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3251                 b43_phy_write(dev, afectl_core, tmp[2]);
3252                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3253
3254                 if (ret != 0)
3255                         break;
3256         }
3257
3258         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3259         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3260         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3261
3262         b43_nphy_stay_in_carrier_search(dev, 0);
3263
3264         return ret;
3265 }
3266
3267 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3268                         struct nphy_txgains target, u8 type, bool debug)
3269 {
3270         return -1;
3271 }
3272
3273 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3274 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3275                         struct nphy_txgains target, u8 type, bool debug)
3276 {
3277         if (dev->phy.rev >= 3)
3278                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3279         else
3280                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3281 }
3282
3283 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3284 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3285 {
3286         u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3287         if (on)
3288                 tmslow |= SSB_TMSLOW_PHYCLK;
3289         else
3290                 tmslow &= ~SSB_TMSLOW_PHYCLK;
3291         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3292 }
3293
3294 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3295 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3296 {
3297         struct b43_phy *phy = &dev->phy;
3298         struct b43_phy_n *nphy = phy->n;
3299         /* u16 buf[16]; it's rev3+ */
3300
3301         nphy->phyrxchain = mask;
3302
3303         if (0 /* FIXME clk */)
3304                 return;
3305
3306         b43_mac_suspend(dev);
3307
3308         if (nphy->hang_avoid)
3309                 b43_nphy_stay_in_carrier_search(dev, true);
3310
3311         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3312                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3313
3314         if ((mask & 0x3) != 0x3) {
3315                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3316                 if (dev->phy.rev >= 3) {
3317                         /* TODO */
3318                 }
3319         } else {
3320                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3321                 if (dev->phy.rev >= 3) {
3322                         /* TODO */
3323                 }
3324         }
3325
3326         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3327
3328         if (nphy->hang_avoid)
3329                 b43_nphy_stay_in_carrier_search(dev, false);
3330
3331         b43_mac_enable(dev);
3332 }
3333
3334 /*
3335  * Init N-PHY
3336  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3337  */
3338 int b43_phy_initn(struct b43_wldev *dev)
3339 {
3340         struct ssb_bus *bus = dev->dev->bus;
3341         struct b43_phy *phy = &dev->phy;
3342         struct b43_phy_n *nphy = phy->n;
3343         u8 tx_pwr_state;
3344         struct nphy_txgains target;
3345         u16 tmp;
3346         enum ieee80211_band tmp2;
3347         bool do_rssi_cal;
3348
3349         u16 clip[2];
3350         bool do_cal = false;
3351
3352         if ((dev->phy.rev >= 3) &&
3353            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3354            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3355                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3356         }
3357         nphy->deaf_count = 0;
3358         b43_nphy_tables_init(dev);
3359         nphy->crsminpwr_adjusted = false;
3360         nphy->noisevars_adjusted = false;
3361
3362         /* Clear all overrides */
3363         if (dev->phy.rev >= 3) {
3364                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3365                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3366                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3367                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3368         } else {
3369                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3370         }
3371         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3372         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3373         if (dev->phy.rev < 6) {
3374                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3375                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3376         }
3377         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3378                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3379                        B43_NPHY_RFSEQMODE_TROVER));
3380         if (dev->phy.rev >= 3)
3381                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3382         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3383
3384         if (dev->phy.rev <= 2) {
3385                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3386                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3387                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3388                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3389         }
3390         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3391         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3392
3393         if (bus->sprom.boardflags2_lo & 0x100 ||
3394             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3395              bus->boardinfo.type == 0x8B))
3396                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3397         else
3398                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3399         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3400         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3401         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3402
3403         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3404         b43_nphy_update_txrx_chain(dev);
3405
3406         if (phy->rev < 2) {
3407                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3408                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3409         }
3410
3411         tmp2 = b43_current_band(dev->wl);
3412         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3413             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3414                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3415                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3416                                 nphy->papd_epsilon_offset[0] << 7);
3417                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3418                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3419                                 nphy->papd_epsilon_offset[1] << 7);
3420                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3421         } else if (phy->rev >= 5) {
3422                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3423         }
3424
3425         b43_nphy_workarounds(dev);
3426
3427         /* Reset CCA, in init code it differs a little from standard way */
3428         b43_nphy_bmac_clock_fgc(dev, 1);
3429         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3430         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3431         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3432         b43_nphy_bmac_clock_fgc(dev, 0);
3433
3434         b43_nphy_mac_phy_clock_set(dev, true);
3435
3436         b43_nphy_pa_override(dev, false);
3437         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3438         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3439         b43_nphy_pa_override(dev, true);
3440
3441         b43_nphy_classifier(dev, 0, 0);
3442         b43_nphy_read_clip_detection(dev, clip);
3443         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3444                 b43_nphy_bphy_init(dev);
3445
3446         tx_pwr_state = nphy->txpwrctrl;
3447         b43_nphy_tx_power_ctrl(dev, false);
3448         b43_nphy_tx_power_fix(dev);
3449         /* TODO N PHY TX Power Control Idle TSSI */
3450         /* TODO N PHY TX Power Control Setup */
3451
3452         if (phy->rev >= 3) {
3453                 /* TODO */
3454         } else {
3455                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3456                                         b43_ntab_tx_gain_rev0_1_2);
3457                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3458                                         b43_ntab_tx_gain_rev0_1_2);
3459         }
3460
3461         if (nphy->phyrxchain != 3)
3462                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3463         if (nphy->mphase_cal_phase_id > 0)
3464                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3465
3466         do_rssi_cal = false;
3467         if (phy->rev >= 3) {
3468                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3469                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3470                 else
3471                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3472
3473                 if (do_rssi_cal)
3474                         b43_nphy_rssi_cal(dev);
3475                 else
3476                         b43_nphy_restore_rssi_cal(dev);
3477         } else {
3478                 b43_nphy_rssi_cal(dev);
3479         }
3480
3481         if (!((nphy->measure_hold & 0x6) != 0)) {
3482                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3483                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3484                 else
3485                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3486
3487                 if (nphy->mute)
3488                         do_cal = false;
3489
3490                 if (do_cal) {
3491                         target = b43_nphy_get_tx_gains(dev);
3492
3493                         if (nphy->antsel_type == 2)
3494                                 b43_nphy_superswitch_init(dev, true);
3495                         if (nphy->perical != 2) {
3496                                 b43_nphy_rssi_cal(dev);
3497                                 if (phy->rev >= 3) {
3498                                         nphy->cal_orig_pwr_idx[0] =
3499                                             nphy->txpwrindex[0].index_internal;
3500                                         nphy->cal_orig_pwr_idx[1] =
3501                                             nphy->txpwrindex[1].index_internal;
3502                                         /* TODO N PHY Pre Calibrate TX Gain */
3503                                         target = b43_nphy_get_tx_gains(dev);
3504                                 }
3505                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3506                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3507                                                 b43_nphy_save_cal(dev);
3508                         } else if (nphy->mphase_cal_phase_id == 0)
3509                                 ;/* N PHY Periodic Calibration with arg 3 */
3510                 } else {
3511                         b43_nphy_restore_cal(dev);
3512                 }
3513         }
3514
3515         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3516         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3517         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3518         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3519         if (phy->rev >= 3 && phy->rev <= 6)
3520                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3521         b43_nphy_tx_lp_fbw(dev);
3522         if (phy->rev >= 3)
3523                 b43_nphy_spur_workaround(dev);
3524
3525         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3526         return 0;
3527 }
3528
3529 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3530 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3531                                 const struct b43_phy_n_sfo_cfg *e,
3532                                 struct ieee80211_channel *new_channel)
3533 {
3534         struct b43_phy *phy = &dev->phy;
3535         struct b43_phy_n *nphy = dev->phy.n;
3536
3537         u16 old_band_5ghz;
3538         u32 tmp32;
3539
3540         old_band_5ghz =
3541                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3542         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3543                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3544                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3545                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3546                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3547                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3548         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3549                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3550                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3551                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3552                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3553                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3554         }
3555
3556         b43_chantab_phy_upload(dev, e);
3557
3558         if (new_channel->hw_value == 14) {
3559                 b43_nphy_classifier(dev, 2, 0);
3560                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3561         } else {
3562                 b43_nphy_classifier(dev, 2, 2);
3563                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3564                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3565         }
3566
3567         if (!nphy->txpwrctrl)
3568                 b43_nphy_tx_power_fix(dev);
3569
3570         if (dev->phy.rev < 3)
3571                 b43_nphy_adjust_lna_gain_table(dev);
3572
3573         b43_nphy_tx_lp_fbw(dev);
3574
3575         if (dev->phy.rev >= 3 && 0) {
3576                 /* TODO */
3577         }
3578
3579         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3580
3581         if (phy->rev >= 3)
3582                 b43_nphy_spur_workaround(dev);
3583 }
3584
3585 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3586 static int b43_nphy_set_channel(struct b43_wldev *dev,
3587                                 struct ieee80211_channel *channel,
3588                                 enum nl80211_channel_type channel_type)
3589 {
3590         struct b43_phy *phy = &dev->phy;
3591
3592         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3593         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3594
3595         u8 tmp;
3596
3597         if (dev->phy.rev >= 3) {
3598                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3599                                                         channel->center_freq);
3600                 tabent_r3 = NULL;
3601                 if (!tabent_r3)
3602                         return -ESRCH;
3603         } else {
3604                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3605                                                         channel->hw_value);
3606                 if (!tabent_r2)
3607                         return -ESRCH;
3608         }
3609
3610         /* Channel is set later in common code, but we need to set it on our
3611            own to let this function's subcalls work properly. */
3612         phy->channel = channel->hw_value;
3613         phy->channel_freq = channel->center_freq;
3614
3615         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3616                 b43_channel_type_is_40mhz(channel_type))
3617                 ; /* TODO: BMAC BW Set (channel_type) */
3618
3619         if (channel_type == NL80211_CHAN_HT40PLUS)
3620                 b43_phy_set(dev, B43_NPHY_RXCTL,
3621                                 B43_NPHY_RXCTL_BSELU20);
3622         else if (channel_type == NL80211_CHAN_HT40MINUS)
3623                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3624                                 ~B43_NPHY_RXCTL_BSELU20);
3625
3626         if (dev->phy.rev >= 3) {
3627                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3628                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3629                 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3630                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3631         } else {
3632                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3633                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3634                 b43_radio_2055_setup(dev, tabent_r2);
3635                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3636         }
3637
3638         return 0;
3639 }
3640
3641 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3642 {
3643         struct b43_phy_n *nphy;
3644
3645         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3646         if (!nphy)
3647                 return -ENOMEM;
3648         dev->phy.n = nphy;
3649
3650         return 0;
3651 }
3652
3653 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3654 {
3655         struct b43_phy *phy = &dev->phy;
3656         struct b43_phy_n *nphy = phy->n;
3657
3658         memset(nphy, 0, sizeof(*nphy));
3659
3660         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3661         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3662         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3663         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3664 }
3665
3666 static void b43_nphy_op_free(struct b43_wldev *dev)
3667 {
3668         struct b43_phy *phy = &dev->phy;
3669         struct b43_phy_n *nphy = phy->n;
3670
3671         kfree(nphy);
3672         phy->n = NULL;
3673 }
3674
3675 static int b43_nphy_op_init(struct b43_wldev *dev)
3676 {
3677         return b43_phy_initn(dev);
3678 }
3679
3680 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3681 {
3682 #if B43_DEBUG
3683         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3684                 /* OFDM registers are onnly available on A/G-PHYs */
3685                 b43err(dev->wl, "Invalid OFDM PHY access at "
3686                        "0x%04X on N-PHY\n", offset);
3687                 dump_stack();
3688         }
3689         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3690                 /* Ext-G registers are only available on G-PHYs */
3691                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3692                        "0x%04X on N-PHY\n", offset);
3693                 dump_stack();
3694         }
3695 #endif /* B43_DEBUG */
3696 }
3697
3698 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3699 {
3700         check_phyreg(dev, reg);
3701         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3702         return b43_read16(dev, B43_MMIO_PHY_DATA);
3703 }
3704
3705 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3706 {
3707         check_phyreg(dev, reg);
3708         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3709         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3710 }
3711
3712 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3713                                  u16 set)
3714 {
3715         check_phyreg(dev, reg);
3716         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3717         b43_write16(dev, B43_MMIO_PHY_DATA,
3718                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3719 }
3720
3721 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3722 {
3723         /* Register 1 is a 32-bit register. */
3724         B43_WARN_ON(reg == 1);
3725         /* N-PHY needs 0x100 for read access */
3726         reg |= 0x100;
3727
3728         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3729         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3730 }
3731
3732 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3733 {
3734         /* Register 1 is a 32-bit register. */
3735         B43_WARN_ON(reg == 1);
3736
3737         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3738         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3739 }
3740
3741 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3742 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3743                                         bool blocked)
3744 {
3745         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3746                 b43err(dev->wl, "MAC not suspended\n");
3747
3748         if (blocked) {
3749                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3750                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3751                 if (dev->phy.rev >= 3) {
3752                         b43_radio_mask(dev, 0x09, ~0x2);
3753
3754                         b43_radio_write(dev, 0x204D, 0);
3755                         b43_radio_write(dev, 0x2053, 0);
3756                         b43_radio_write(dev, 0x2058, 0);
3757                         b43_radio_write(dev, 0x205E, 0);
3758                         b43_radio_mask(dev, 0x2062, ~0xF0);
3759                         b43_radio_write(dev, 0x2064, 0);
3760
3761                         b43_radio_write(dev, 0x304D, 0);
3762                         b43_radio_write(dev, 0x3053, 0);
3763                         b43_radio_write(dev, 0x3058, 0);
3764                         b43_radio_write(dev, 0x305E, 0);
3765                         b43_radio_mask(dev, 0x3062, ~0xF0);
3766                         b43_radio_write(dev, 0x3064, 0);
3767                 }
3768         } else {
3769                 if (dev->phy.rev >= 3) {
3770                         b43_radio_init2056(dev);
3771                         b43_switch_channel(dev, dev->phy.channel);
3772                 } else {
3773                         b43_radio_init2055(dev);
3774                 }
3775         }
3776 }
3777
3778 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3779 {
3780         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3781                       on ? 0 : 0x7FFF);
3782 }
3783
3784 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3785                                       unsigned int new_channel)
3786 {
3787         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3788         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
3789
3790         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3791                 if ((new_channel < 1) || (new_channel > 14))
3792                         return -EINVAL;
3793         } else {
3794                 if (new_channel > 200)
3795                         return -EINVAL;
3796         }
3797
3798         return b43_nphy_set_channel(dev, channel, channel_type);
3799 }
3800
3801 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3802 {
3803         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3804                 return 1;
3805         return 36;
3806 }
3807
3808 const struct b43_phy_operations b43_phyops_n = {
3809         .allocate               = b43_nphy_op_allocate,
3810         .free                   = b43_nphy_op_free,
3811         .prepare_structs        = b43_nphy_op_prepare_structs,
3812         .init                   = b43_nphy_op_init,
3813         .phy_read               = b43_nphy_op_read,
3814         .phy_write              = b43_nphy_op_write,
3815         .phy_maskset            = b43_nphy_op_maskset,
3816         .radio_read             = b43_nphy_op_radio_read,
3817         .radio_write            = b43_nphy_op_radio_write,
3818         .software_rfkill        = b43_nphy_op_software_rfkill,
3819         .switch_analog          = b43_nphy_op_switch_analog,
3820         .switch_channel         = b43_nphy_op_switch_channel,
3821         .get_default_chan       = b43_nphy_op_get_default_chan,
3822         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3823         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3824 };