3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/types.h>
30 #include "tables_nphy.h"
40 struct nphy_iqcal_params {
58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
69 return B43_TXPWR_RES_DONE;
72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
73 const struct b43_nphy_channeltab_entry *e)
75 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
76 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
77 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
78 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
79 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
80 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
81 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
82 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
83 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
84 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
85 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
86 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
87 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
88 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
89 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
90 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
91 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
92 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
93 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
94 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
95 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
96 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
100 const struct b43_nphy_channeltab_entry *e)
102 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
103 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
104 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
105 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
106 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
107 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
115 /* Tune the hardware to a new channel. */
116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
118 const struct b43_nphy_channeltab_entry *tabent;
120 tabent = b43_nphy_get_chantabent(dev, channel);
124 //FIXME enable/disable band select upper20 in RXCTL
125 if (0 /*FIXME 5Ghz*/)
126 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
128 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
129 b43_chantab_radio_upload(dev, tabent);
131 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
132 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
133 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
135 if (0 /*FIXME 5Ghz*/)
136 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
138 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
139 b43_chantab_phy_upload(dev, tabent);
140 b43_nphy_tx_power_fix(dev);
145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
147 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
148 ~B43_NPHY_RFCTL_CMD_PORFORCE);
149 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
150 B43_NPHY_RFCTL_CMD_CHIP0PU |
151 B43_NPHY_RFCTL_CMD_OEPORFORCE);
152 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
153 B43_NPHY_RFCTL_CMD_PORFORCE);
156 static void b43_radio_init2055_post(struct b43_wldev *dev)
158 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
159 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
163 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
165 if ((sprom->revision != 4) ||
166 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
167 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
168 (binfo->type != 0x46D) ||
169 (binfo->rev < 0x41)) {
170 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
171 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
175 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
177 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
179 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
181 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
183 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
185 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
187 for (i = 0; i < 100; i++) {
188 val = b43_radio_read16(dev, B2055_CAL_COUT2);
194 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
196 nphy_channel_switch(dev, dev->phy.channel);
197 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
198 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
199 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
200 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
203 /* Initialize a Broadcom 2055 N-radio */
204 static void b43_radio_init2055(struct b43_wldev *dev)
206 b43_radio_init2055_pre(dev);
207 if (b43_status(dev) < B43_STAT_INITIALIZED)
208 b2055_upload_inittab(dev, 0, 1);
210 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
211 b43_radio_init2055_post(dev);
214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
216 b43_radio_init2055(dev);
219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
221 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
222 ~B43_NPHY_RFCTL_CMD_EN);
225 #define ntab_upload(dev, offset, data) do { \
227 for (i = 0; i < (offset##_SIZE); i++) \
228 b43_ntab_write(dev, (offset) + i, (data)[i]); \
232 * Upload the N-PHY tables.
233 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
235 static void b43_nphy_tables_init(struct b43_wldev *dev)
237 if (dev->phy.rev < 3)
238 b43_nphy_rev0_1_2_tables_init(dev);
240 b43_nphy_rev3plus_tables_init(dev);
243 static void b43_nphy_workarounds(struct b43_wldev *dev)
245 struct b43_phy *phy = &dev->phy;
248 b43_phy_set(dev, B43_NPHY_IQFLIP,
249 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
250 if (1 /* FIXME band is 2.4GHz */) {
251 b43_phy_set(dev, B43_NPHY_CLASSCTL,
252 B43_NPHY_CLASSCTL_CCKEN);
254 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
255 ~B43_NPHY_CLASSCTL_CCKEN);
257 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
258 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
260 /* Fixup some tables */
261 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
274 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
275 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
277 //TODO set RF sequence
279 /* Set narrowband clip threshold */
280 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
281 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
283 /* Set wideband clip 2 threshold */
284 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
285 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
286 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
287 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
288 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
289 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
291 /* Set Clip 2 detect */
292 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
293 B43_NPHY_C1_CGAINI_CL2DETECT);
294 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
295 B43_NPHY_C2_CGAINI_CL2DETECT);
298 /* Set dwell lengths */
299 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
300 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
301 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
302 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
304 /* Set gain backoff */
305 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
306 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
307 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
308 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
309 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
310 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
312 /* Set HPVGA2 index */
313 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
314 ~B43_NPHY_C1_INITGAIN_HPVGA2,
315 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
316 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
317 ~B43_NPHY_C2_INITGAIN_HPVGA2,
318 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
320 //FIXME verify that the specs really mean to use autoinc here.
321 for (i = 0; i < 3; i++)
322 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
325 /* Set minimum gain value */
326 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
327 ~B43_NPHY_C1_MINGAIN,
328 23 << B43_NPHY_C1_MINGAIN_SHIFT);
329 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
330 ~B43_NPHY_C2_MINGAIN,
331 23 << B43_NPHY_C2_MINGAIN_SHIFT);
334 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
335 ~B43_NPHY_SCRAM_SIGCTL_SCM);
338 /* Set phase track alpha and beta */
339 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
340 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
341 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
342 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
343 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
344 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
348 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
350 struct b43_phy_n *nphy = dev->phy.n;
351 enum ieee80211_band band;
355 nphy->rfctrl_intc1_save = b43_phy_read(dev,
356 B43_NPHY_RFCTL_INTC1);
357 nphy->rfctrl_intc2_save = b43_phy_read(dev,
358 B43_NPHY_RFCTL_INTC2);
359 band = b43_current_band(dev->wl);
360 if (dev->phy.rev >= 3) {
361 if (band == IEEE80211_BAND_5GHZ)
366 if (band == IEEE80211_BAND_5GHZ)
371 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
372 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
374 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
375 nphy->rfctrl_intc1_save);
376 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
377 nphy->rfctrl_intc2_save);
381 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
382 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
386 if (dev->phy.type != B43_PHYTYPE_N)
389 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
391 tmslow |= SSB_TMSLOW_FGC;
393 tmslow &= ~SSB_TMSLOW_FGC;
394 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
398 static void b43_nphy_reset_cca(struct b43_wldev *dev)
402 b43_nphy_bmac_clock_fgc(dev, 1);
403 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
404 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
406 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
407 b43_nphy_bmac_clock_fgc(dev, 0);
408 /* TODO: N PHY Force RF Seq with argument 2 */
411 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
412 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
413 struct b43_phy_n_iq_comp *pcomp)
416 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
417 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
418 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
419 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
421 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
422 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
423 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
424 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
428 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
429 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
434 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
435 for (i = 0; i < 4; i++)
436 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
438 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
439 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
440 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
441 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
444 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
445 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
447 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
448 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
451 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
452 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
454 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
455 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
458 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
459 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
463 if (dev->dev->id.revision == 16)
464 b43_mac_suspend(dev);
466 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
467 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
468 B43_NPHY_CLASSCTL_WAITEDEN);
471 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
473 if (dev->dev->id.revision == 16)
479 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
480 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
482 struct b43_phy *phy = &dev->phy;
483 struct b43_phy_n *nphy = phy->n;
486 u16 clip[] = { 0xFFFF, 0xFFFF };
487 if (nphy->deaf_count++ == 0) {
488 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
489 b43_nphy_classifier(dev, 0x7, 0);
490 b43_nphy_read_clip_detection(dev, nphy->clip_state);
491 b43_nphy_write_clip_detection(dev, clip);
493 b43_nphy_reset_cca(dev);
495 if (--nphy->deaf_count == 0) {
496 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
497 b43_nphy_write_clip_detection(dev, nphy->clip_state);
502 enum b43_nphy_rf_sequence {
506 B43_RFSEQ_UPDATE_GAINH,
507 B43_RFSEQ_UPDATE_GAINL,
508 B43_RFSEQ_UPDATE_GAINU,
511 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
512 enum b43_nphy_rf_sequence seq)
514 static const u16 trigger[] = {
515 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
516 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
517 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
518 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
519 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
520 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
524 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
526 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
527 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
528 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
529 for (i = 0; i < 200; i++) {
530 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
534 b43err(dev->wl, "RF sequence status timeout\n");
536 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
537 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
540 static void b43_nphy_bphy_init(struct b43_wldev *dev)
546 for (i = 0; i < 14; i++) {
547 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
551 for (i = 0; i < 16; i++) {
552 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
555 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
558 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
559 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
560 s8 offset, u8 core, u8 rail, u8 type)
563 bool core1or5 = (core == 1) || (core == 5);
564 bool core2or5 = (core == 2) || (core == 5);
566 offset = clamp_val(offset, -32, 31);
567 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
569 if (core1or5 && (rail == 0) && (type == 2))
570 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
571 if (core1or5 && (rail == 1) && (type == 2))
572 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
573 if (core2or5 && (rail == 0) && (type == 2))
574 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
575 if (core2or5 && (rail == 1) && (type == 2))
576 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
577 if (core1or5 && (rail == 0) && (type == 0))
578 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
579 if (core1or5 && (rail == 1) && (type == 0))
580 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
581 if (core2or5 && (rail == 0) && (type == 0))
582 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
583 if (core2or5 && (rail == 1) && (type == 0))
584 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
585 if (core1or5 && (rail == 0) && (type == 1))
586 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
587 if (core1or5 && (rail == 1) && (type == 1))
588 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
589 if (core2or5 && (rail == 0) && (type == 1))
590 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
591 if (core2or5 && (rail == 1) && (type == 1))
592 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
593 if (core1or5 && (rail == 0) && (type == 6))
594 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
595 if (core1or5 && (rail == 1) && (type == 6))
596 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
597 if (core2or5 && (rail == 0) && (type == 6))
598 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
599 if (core2or5 && (rail == 1) && (type == 6))
600 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
601 if (core1or5 && (rail == 0) && (type == 3))
602 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
603 if (core1or5 && (rail == 1) && (type == 3))
604 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
605 if (core2or5 && (rail == 0) && (type == 3))
606 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
607 if (core2or5 && (rail == 1) && (type == 3))
608 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
609 if (core1or5 && (type == 4))
610 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
611 if (core2or5 && (type == 4))
612 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
613 if (core1or5 && (type == 5))
614 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
615 if (core2or5 && (type == 5))
616 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
620 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
624 if (dev->phy.rev >= 3) {
636 val = (val << 12) | (val << 14);
637 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
638 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
641 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
643 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
647 /* TODO use some definitions */
649 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
651 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
653 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
655 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
658 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
662 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
665 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
667 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
668 0xEFDC, (code << 1 | 0x1021));
669 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
672 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
679 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
680 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
683 for (i = 0; i < 2; i++) {
686 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
688 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
691 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
693 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
694 0xFC, buf[2 * i + 1]);
698 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
701 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
702 0xF3, buf[2 * i + 1] << 2);
707 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
708 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
713 u16 save_regs_phy[9];
716 if (dev->phy.rev >= 3) {
717 save_regs_phy[0] = b43_phy_read(dev,
718 B43_NPHY_RFCTL_LUT_TRSW_UP1);
719 save_regs_phy[1] = b43_phy_read(dev,
720 B43_NPHY_RFCTL_LUT_TRSW_UP2);
721 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
722 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
723 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
724 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
725 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
726 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
729 b43_nphy_rssi_select(dev, 5, type);
731 if (dev->phy.rev < 2) {
732 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
733 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
736 for (i = 0; i < 4; i++)
739 for (i = 0; i < nsamp; i++) {
740 if (dev->phy.rev < 2) {
741 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
742 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
744 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
745 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
748 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
749 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
750 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
751 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
753 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
754 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
756 if (dev->phy.rev < 2)
757 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
759 if (dev->phy.rev >= 3) {
760 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
762 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
764 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
765 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
766 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
767 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
768 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
769 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
775 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
776 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
782 u8 regs_save_radio[2];
783 u16 regs_save_phy[2];
787 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
788 s32 results_min[4] = { };
789 u8 vcm_final[4] = { };
790 s32 results[4][4] = { };
791 s32 miniq[4][2] = { };
796 } else if (type < 2) {
804 class = b43_nphy_classifier(dev, 0, 0);
805 b43_nphy_classifier(dev, 7, 4);
806 b43_nphy_read_clip_detection(dev, clip_state);
807 b43_nphy_write_clip_detection(dev, clip_off);
809 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
814 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
815 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
816 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
817 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
819 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
820 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
821 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
822 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
824 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
825 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
826 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
827 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
828 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
829 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
831 b43_nphy_rssi_select(dev, 5, type);
832 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
833 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
835 for (i = 0; i < 4; i++) {
837 for (j = 0; j < 4; j++)
840 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
841 b43_nphy_poll_rssi(dev, type, results[i], 8);
843 for (j = 0; j < 2; j++)
844 miniq[i][j] = min(results[i][2 * j],
845 results[i][2 * j + 1]);
848 for (i = 0; i < 4; i++) {
853 for (j = 0; j < 4; j++) {
855 curr = abs(results[j][i]);
857 curr = abs(miniq[j][i / 2] - code * 8);
864 if (results[j][i] < minpoll)
865 minpoll = results[j][i];
867 results_min[i] = minpoll;
868 vcm_final[i] = minvcm;
872 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
874 for (i = 0; i < 4; i++) {
875 offset[i] = (code * 8) - results[vcm_final[i]][i];
878 offset[i] = -((abs(offset[i]) + 4) / 8);
880 offset[i] = (offset[i] + 4) / 8;
882 if (results_min[i] == 248)
883 offset[i] = code - 32;
886 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
889 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
893 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
894 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
898 b43_nphy_rssi_select(dev, 1, 2);
901 b43_nphy_rssi_select(dev, 1, 0);
904 b43_nphy_rssi_select(dev, 1, 1);
907 b43_nphy_rssi_select(dev, 1, 1);
913 b43_nphy_rssi_select(dev, 2, 2);
916 b43_nphy_rssi_select(dev, 2, 0);
919 b43_nphy_rssi_select(dev, 2, 1);
923 b43_nphy_rssi_select(dev, 0, type);
925 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
926 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
927 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
928 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
930 b43_nphy_classifier(dev, 7, class);
931 b43_nphy_write_clip_detection(dev, clip_state);
934 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
935 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
942 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
944 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
946 if (dev->phy.rev >= 3) {
947 b43_nphy_rev3_rssi_cal(dev);
949 b43_nphy_rev2_rssi_cal(dev, 2);
950 b43_nphy_rev2_rssi_cal(dev, 0);
951 b43_nphy_rev2_rssi_cal(dev, 1);
956 * Restore RSSI Calibration
957 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
959 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
961 struct b43_phy_n *nphy = dev->phy.n;
963 u16 *rssical_radio_regs = NULL;
964 u16 *rssical_phy_regs = NULL;
966 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
967 if (!nphy->rssical_chanspec_2G)
969 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
970 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
972 if (!nphy->rssical_chanspec_5G)
974 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
975 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
978 /* TODO use some definitions */
979 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
980 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
982 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
983 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
984 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
985 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
987 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
988 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
989 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
990 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
992 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
993 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
994 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
995 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1000 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
1002 int b43_phy_initn(struct b43_wldev *dev)
1004 struct ssb_bus *bus = dev->dev->bus;
1005 struct b43_phy *phy = &dev->phy;
1006 struct b43_phy_n *nphy = phy->n;
1008 struct nphy_txgains target;
1010 enum ieee80211_band tmp2;
1014 bool do_cal = false;
1016 if ((dev->phy.rev >= 3) &&
1017 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
1018 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
1019 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
1021 nphy->deaf_count = 0;
1022 b43_nphy_tables_init(dev);
1023 nphy->crsminpwr_adjusted = false;
1024 nphy->noisevars_adjusted = false;
1026 /* Clear all overrides */
1027 if (dev->phy.rev >= 3) {
1028 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
1029 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1030 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
1031 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
1033 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1035 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
1036 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
1037 if (dev->phy.rev < 6) {
1038 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
1039 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
1041 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1042 ~(B43_NPHY_RFSEQMODE_CAOVER |
1043 B43_NPHY_RFSEQMODE_TROVER));
1044 if (dev->phy.rev >= 3)
1045 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
1046 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
1048 if (dev->phy.rev <= 2) {
1049 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
1050 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1051 ~B43_NPHY_BPHY_CTL3_SCALE,
1052 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
1054 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
1055 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
1057 if (bus->sprom.boardflags2_lo & 0x100 ||
1058 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
1059 bus->boardinfo.type == 0x8B))
1060 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
1062 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
1063 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
1064 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
1065 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
1067 /* TODO MIMO-Config */
1068 /* TODO Update TX/RX chain */
1071 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
1072 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
1075 tmp2 = b43_current_band(dev->wl);
1076 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
1077 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
1078 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
1079 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
1080 nphy->papd_epsilon_offset[0] << 7);
1081 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
1082 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
1083 nphy->papd_epsilon_offset[1] << 7);
1084 /* TODO N PHY IPA Set TX Dig Filters */
1085 } else if (phy->rev >= 5) {
1086 /* TODO N PHY Ext PA Set TX Dig Filters */
1089 b43_nphy_workarounds(dev);
1091 /* Reset CCA, in init code it differs a little from standard way */
1092 /* b43_nphy_bmac_clock_fgc(dev, 1); */
1093 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
1094 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
1095 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
1096 /* b43_nphy_bmac_clock_fgc(dev, 0); */
1098 /* TODO N PHY MAC PHY Clock Set with argument 1 */
1100 b43_nphy_pa_override(dev, false);
1101 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1102 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1103 b43_nphy_pa_override(dev, true);
1105 b43_nphy_classifier(dev, 0, 0);
1106 b43_nphy_read_clip_detection(dev, clip);
1107 tx_pwr_state = nphy->txpwrctrl;
1108 /* TODO N PHY TX power control with argument 0
1109 (turning off power control) */
1110 /* TODO Fix the TX Power Settings */
1111 /* TODO N PHY TX Power Control Idle TSSI */
1112 /* TODO N PHY TX Power Control Setup */
1114 if (phy->rev >= 3) {
1117 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1118 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1121 if (nphy->phyrxchain != 3)
1122 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
1123 if (nphy->mphase_cal_phase_id > 0)
1124 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
1126 do_rssi_cal = false;
1127 if (phy->rev >= 3) {
1128 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1129 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
1131 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
1134 b43_nphy_rssi_cal(dev);
1136 b43_nphy_restore_rssi_cal(dev);
1138 b43_nphy_rssi_cal(dev);
1141 if (!((nphy->measure_hold & 0x6) != 0)) {
1142 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1143 do_cal = (nphy->iqcal_chanspec_2G == 0);
1145 do_cal = (nphy->iqcal_chanspec_5G == 0);
1151 /* target = b43_nphy_get_tx_gains(dev); */
1153 if (nphy->antsel_type == 2)
1154 ;/*TODO NPHY Superswitch Init with argument 1*/
1155 if (nphy->perical != 2) {
1156 b43_nphy_rssi_cal(dev);
1157 if (phy->rev >= 3) {
1158 nphy->cal_orig_pwr_idx[0] =
1159 nphy->txpwrindex[0].index_internal;
1160 nphy->cal_orig_pwr_idx[1] =
1161 nphy->txpwrindex[1].index_internal;
1162 /* TODO N PHY Pre Calibrate TX Gain */
1163 /*target = b43_nphy_get_tx_gains(dev)*/
1170 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
1171 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
1173 else if (nphy->mphase_cal_phase_id == 0)
1174 N PHY Periodic Calibration with argument 3
1176 b43_nphy_restore_cal(dev);
1180 /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
1181 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
1182 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
1183 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
1184 if (phy->rev >= 3 && phy->rev <= 6)
1185 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
1186 /* b43_nphy_tx_lp_fbw(dev); */
1187 /* TODO N PHY Spur Workaround */
1189 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
1193 static int b43_nphy_op_allocate(struct b43_wldev *dev)
1195 struct b43_phy_n *nphy;
1197 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
1205 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
1207 struct b43_phy *phy = &dev->phy;
1208 struct b43_phy_n *nphy = phy->n;
1210 memset(nphy, 0, sizeof(*nphy));
1212 //TODO init struct b43_phy_n
1215 static void b43_nphy_op_free(struct b43_wldev *dev)
1217 struct b43_phy *phy = &dev->phy;
1218 struct b43_phy_n *nphy = phy->n;
1224 static int b43_nphy_op_init(struct b43_wldev *dev)
1226 return b43_phy_initn(dev);
1229 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
1232 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
1233 /* OFDM registers are onnly available on A/G-PHYs */
1234 b43err(dev->wl, "Invalid OFDM PHY access at "
1235 "0x%04X on N-PHY\n", offset);
1238 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
1239 /* Ext-G registers are only available on G-PHYs */
1240 b43err(dev->wl, "Invalid EXT-G PHY access at "
1241 "0x%04X on N-PHY\n", offset);
1244 #endif /* B43_DEBUG */
1247 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
1249 check_phyreg(dev, reg);
1250 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1251 return b43_read16(dev, B43_MMIO_PHY_DATA);
1254 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1256 check_phyreg(dev, reg);
1257 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1258 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1261 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1263 /* Register 1 is a 32-bit register. */
1264 B43_WARN_ON(reg == 1);
1265 /* N-PHY needs 0x100 for read access */
1268 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1269 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1272 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1274 /* Register 1 is a 32-bit register. */
1275 B43_WARN_ON(reg == 1);
1277 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1278 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1281 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
1286 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
1288 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1292 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
1293 unsigned int new_channel)
1295 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1296 if ((new_channel < 1) || (new_channel > 14))
1299 if (new_channel > 200)
1303 return nphy_channel_switch(dev, new_channel);
1306 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
1308 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1313 const struct b43_phy_operations b43_phyops_n = {
1314 .allocate = b43_nphy_op_allocate,
1315 .free = b43_nphy_op_free,
1316 .prepare_structs = b43_nphy_op_prepare_structs,
1317 .init = b43_nphy_op_init,
1318 .phy_read = b43_nphy_op_read,
1319 .phy_write = b43_nphy_op_write,
1320 .radio_read = b43_nphy_op_radio_read,
1321 .radio_write = b43_nphy_op_radio_write,
1322 .software_rfkill = b43_nphy_op_software_rfkill,
1323 .switch_analog = b43_nphy_op_switch_analog,
1324 .switch_channel = b43_nphy_op_switch_channel,
1325 .get_default_chan = b43_nphy_op_get_default_chan,
1326 .recalc_txpower = b43_nphy_op_recalc_txpower,
1327 .adjust_txpower = b43_nphy_op_adjust_txpower,