drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  59 {//TODO
  60 }
  61
  62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  63 {//TODO
  64 }
  65
  66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  67                                                         bool ignore_tssi)
  68 {//TODO
  69         return B43_TXPWR_RES_DONE;
  70 }
  71
  72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  73                                      const struct b43_nphy_channeltab_entry *e)
  74 {
  75         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  77         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  78         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  79         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  80         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  81         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  82         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  83         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  84         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  86         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  88         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  89         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  90         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  91         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  93         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  94         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  95         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  96         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  97 }
  98
  99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 100                                    const struct b43_nphy_channeltab_entry *e)
 101 {
 102         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 103         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 104         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 105         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 106         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 107         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 108 }
 109
 110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 111 {
 112         //TODO
 113 }
 114
 115 /* Tune the hardware to a new channel. */
 116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 117 {
 118         const struct b43_nphy_channeltab_entry *tabent;
 119
 120         tabent = b43_nphy_get_chantabent(dev, channel);
 121         if (!tabent)
 122                 return -ESRCH;
 123
 124         //FIXME enable/disable band select upper20 in RXCTL
 125         if (0 /*FIXME 5Ghz*/)
 126                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 127         else
 128                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 129         b43_chantab_radio_upload(dev, tabent);
 130         udelay(50);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 133         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 134         udelay(300);
 135         if (0 /*FIXME 5Ghz*/)
 136                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 137         else
 138                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 139         b43_chantab_phy_upload(dev, tabent);
 140         b43_nphy_tx_power_fix(dev);
 141
 142         return 0;
 143 }
 144
 145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 146 {
 147         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 148                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 149         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 150                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 151                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 152         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 153                     B43_NPHY_RFCTL_CMD_PORFORCE);
 154 }
 155
 156 static void b43_radio_init2055_post(struct b43_wldev *dev)
 157 {
 158         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 159         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 160         int i;
 161         u16 val;
 162
 163         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 164         msleep(1);
 165         if ((sprom->revision != 4) ||
 166            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 167                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 168                     (binfo->type != 0x46D) ||
 169                     (binfo->rev < 0x41)) {
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 172                         msleep(1);
 173                 }
 174         }
 175         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 176         msleep(1);
 177         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 178         msleep(1);
 179         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 180         msleep(1);
 181         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 182         msleep(1);
 183         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 184         msleep(1);
 185         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 186         msleep(1);
 187         for (i = 0; i < 100; i++) {
 188                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 189                 if (val & 0x80)
 190                         break;
 191                 udelay(10);
 192         }
 193         msleep(1);
 194         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 195         msleep(1);
 196         nphy_channel_switch(dev, dev->phy.channel);
 197         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 199         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 200         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 201 }
 202
 203 /* Initialize a Broadcom 2055 N-radio */
 204 static void b43_radio_init2055(struct b43_wldev *dev)
 205 {
 206         b43_radio_init2055_pre(dev);
 207         if (b43_status(dev) < B43_STAT_INITIALIZED)
 208                 b2055_upload_inittab(dev, 0, 1);
 209         else
 210                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 211         b43_radio_init2055_post(dev);
 212 }
 213
 214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 215 {
 216         b43_radio_init2055(dev);
 217 }
 218
 219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 220 {
 221         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 222                      ~B43_NPHY_RFCTL_CMD_EN);
 223 }
 224
 225 #define ntab_upload(dev, offset, data) do { \
 226                 unsigned int i;                                         \
 227                 for (i = 0; i < (offset##_SIZE); i++)                   \
 228                         b43_ntab_write(dev, (offset) + i, (data)[i]);   \
 229         } while (0)
 230
 231 /*
 232  * Upload the N-PHY tables.
 233  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 234  */
 235 static void b43_nphy_tables_init(struct b43_wldev *dev)
 236 {
 237         if (dev->phy.rev < 3)
 238                 b43_nphy_rev0_1_2_tables_init(dev);
 239         else
 240                 b43_nphy_rev3plus_tables_init(dev);
 241 }
 242
 243 static void b43_nphy_workarounds(struct b43_wldev *dev)
 244 {
 245         struct b43_phy *phy = &dev->phy;
 246         unsigned int i;
 247
 248         b43_phy_set(dev, B43_NPHY_IQFLIP,
 249                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 250         if (1 /* FIXME band is 2.4GHz */) {
 251                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 252                             B43_NPHY_CLASSCTL_CCKEN);
 253         } else {
 254                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 255                              ~B43_NPHY_CLASSCTL_CCKEN);
 256         }
 257         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 258         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 259
 260         /* Fixup some tables */
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 265         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 266         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 267         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 268         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 269         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 270         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 271
 272         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 273         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 274         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 275         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 276
 277         //TODO set RF sequence
 278
 279         /* Set narrowband clip threshold */
 280         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 281         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 282
 283         /* Set wideband clip 2 threshold */
 284         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 285                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 286                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 287         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 288                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 289                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 290
 291         /* Set Clip 2 detect */
 292         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 293                     B43_NPHY_C1_CGAINI_CL2DETECT);
 294         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 295                     B43_NPHY_C2_CGAINI_CL2DETECT);
 296
 297         if (0 /*FIXME*/) {
 298                 /* Set dwell lengths */
 299                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 300                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 301                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 302                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 303
 304                 /* Set gain backoff */
 305                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 306                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 307                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 308                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 309                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 310                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 311
 312                 /* Set HPVGA2 index */
 313                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 314                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 315                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 316                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 317                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 318                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 319
 320                 //FIXME verify that the specs really mean to use autoinc here.
 321                 for (i = 0; i < 3; i++)
 322                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 323         }
 324
 325         /* Set minimum gain value */
 326         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 327                         ~B43_NPHY_C1_MINGAIN,
 328                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 329         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 330                         ~B43_NPHY_C2_MINGAIN,
 331                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 332
 333         if (phy->rev < 2) {
 334                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 335                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 336         }
 337
 338         /* Set phase track alpha and beta */
 339         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 340         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 341         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 342         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 343         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 344         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 345 }
 346
 347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 348 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 349 {
 350         struct b43_phy_n *nphy = dev->phy.n;
 351         enum ieee80211_band band;
 352         u16 tmp;
 353
 354         if (!enable) {
 355                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 356                                                        B43_NPHY_RFCTL_INTC1);
 357                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 358                                                        B43_NPHY_RFCTL_INTC2);
 359                 band = b43_current_band(dev->wl);
 360                 if (dev->phy.rev >= 3) {
 361                         if (band == IEEE80211_BAND_5GHZ)
 362                                 tmp = 0x600;
 363                         else
 364                                 tmp = 0x480;
 365                 } else {
 366                         if (band == IEEE80211_BAND_5GHZ)
 367                                 tmp = 0x180;
 368                         else
 369                                 tmp = 0x120;
 370                 }
 371                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 372                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 373         } else {
 374                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 375                                 nphy->rfctrl_intc1_save);
 376                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 377                                 nphy->rfctrl_intc2_save);
 378         }
 379 }
 380
 381 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 382 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 383 {
 384         u32 tmslow;
 385
 386         if (dev->phy.type != B43_PHYTYPE_N)
 387                 return;
 388
 389         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 390         if (force)
 391                 tmslow |= SSB_TMSLOW_FGC;
 392         else
 393                 tmslow &= ~SSB_TMSLOW_FGC;
 394         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 395 }
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 398 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 399 {
 400         u16 bbcfg;
 401
 402         b43_nphy_bmac_clock_fgc(dev, 1);
 403         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 404         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 405         udelay(1);
 406         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 407         b43_nphy_bmac_clock_fgc(dev, 0);
 408         /* TODO: N PHY Force RF Seq with argument 2 */
 409 }
 410
 411 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 412 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 413                                 u16 samps, u8 time, bool wait)
 414 {
 415         int i;
 416         u16 tmp;
 417
 418         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 419         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 420         if (wait)
 421                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 422         else
 423                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 424
 425         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 426
 427         for (i = 1000; i; i--) {
 428                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 429                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 430                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 431                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 432                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 433                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 434                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 435                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 436
 437                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 438                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 439                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 440                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 441                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 442                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 443                         return;
 444                 }
 445                 udelay(10);
 446         }
 447         memset(est, 0, sizeof(*est));
 448 }
 449
 450 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 451 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 452                                         struct b43_phy_n_iq_comp *pcomp)
 453 {
 454         if (write) {
 455                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 456                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 457                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 458                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 459         } else {
 460                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 461                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 462                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 463                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 464         }
 465 }
 466
 467 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 468 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 469 {
 470         u16 array[4];
 471         int i;
 472
 473         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 474         for (i = 0; i < 4; i++)
 475                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 476
 477         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 478         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 479         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 480         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 481 }
 482
 483 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 484 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 485 {
 486         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 487         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 488 }
 489
 490 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 491 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 492 {
 493         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 494         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 495 }
 496
 497 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 498 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 499 {
 500         u16 tmp;
 501
 502         if (dev->dev->id.revision == 16)
 503                 b43_mac_suspend(dev);
 504
 505         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 506         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 507                 B43_NPHY_CLASSCTL_WAITEDEN);
 508         tmp &= ~mask;
 509         tmp |= (val & mask);
 510         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 511
 512         if (dev->dev->id.revision == 16)
 513                 b43_mac_enable(dev);
 514
 515         return tmp;
 516 }
 517
 518 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 519 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 520 {
 521         struct b43_phy *phy = &dev->phy;
 522         struct b43_phy_n *nphy = phy->n;
 523
 524         if (enable) {
 525                 u16 clip[] = { 0xFFFF, 0xFFFF };
 526                 if (nphy->deaf_count++ == 0) {
 527                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 528                         b43_nphy_classifier(dev, 0x7, 0);
 529                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 530                         b43_nphy_write_clip_detection(dev, clip);
 531                 }
 532                 b43_nphy_reset_cca(dev);
 533         } else {
 534                 if (--nphy->deaf_count == 0) {
 535                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 536                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 537                 }
 538         }
 539 }
 540
 541 enum b43_nphy_rf_sequence {
 542         B43_RFSEQ_RX2TX,
 543         B43_RFSEQ_TX2RX,
 544         B43_RFSEQ_RESET2RX,
 545         B43_RFSEQ_UPDATE_GAINH,
 546         B43_RFSEQ_UPDATE_GAINL,
 547         B43_RFSEQ_UPDATE_GAINU,
 548 };
 549
 550 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 551                                        enum b43_nphy_rf_sequence seq)
 552 {
 553         static const u16 trigger[] = {
 554                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 555                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 556                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 557                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 558                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 559                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 560         };
 561         int i;
 562
 563         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 564
 565         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 566                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 567         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 568         for (i = 0; i < 200; i++) {
 569                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 570                         goto ok;
 571                 msleep(1);
 572         }
 573         b43err(dev->wl, "RF sequence status timeout\n");
 574 ok:
 575         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 576                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 577 }
 578
 579 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 580 {
 581         unsigned int i;
 582         u16 val;
 583
 584         val = 0x1E1F;
 585         for (i = 0; i < 14; i++) {
 586                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 587                 val -= 0x202;
 588         }
 589         val = 0x3E3F;
 590         for (i = 0; i < 16; i++) {
 591                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 592                 val -= 0x202;
 593         }
 594         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 595 }
 596
 597 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 598 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 599                                        s8 offset, u8 core, u8 rail, u8 type)
 600 {
 601         u16 tmp;
 602         bool core1or5 = (core == 1) || (core == 5);
 603         bool core2or5 = (core == 2) || (core == 5);
 604
 605         offset = clamp_val(offset, -32, 31);
 606         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 607
 608         if (core1or5 && (rail == 0) && (type == 2))
 609                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 610         if (core1or5 && (rail == 1) && (type == 2))
 611                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 612         if (core2or5 && (rail == 0) && (type == 2))
 613                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 614         if (core2or5 && (rail == 1) && (type == 2))
 615                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 616         if (core1or5 && (rail == 0) && (type == 0))
 617                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 618         if (core1or5 && (rail == 1) && (type == 0))
 619                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 620         if (core2or5 && (rail == 0) && (type == 0))
 621                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 622         if (core2or5 && (rail == 1) && (type == 0))
 623                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 624         if (core1or5 && (rail == 0) && (type == 1))
 625                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 626         if (core1or5 && (rail == 1) && (type == 1))
 627                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 628         if (core2or5 && (rail == 0) && (type == 1))
 629                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
 630         if (core2or5 && (rail == 1) && (type == 1))
 631                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
 632         if (core1or5 && (rail == 0) && (type == 6))
 633                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
 634         if (core1or5 && (rail == 1) && (type == 6))
 635                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
 636         if (core2or5 && (rail == 0) && (type == 6))
 637                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
 638         if (core2or5 && (rail == 1) && (type == 6))
 639                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
 640         if (core1or5 && (rail == 0) && (type == 3))
 641                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
 642         if (core1or5 && (rail == 1) && (type == 3))
 643                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
 644         if (core2or5 && (rail == 0) && (type == 3))
 645                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
 646         if (core2or5 && (rail == 1) && (type == 3))
 647                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
 648         if (core1or5 && (type == 4))
 649                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
 650         if (core2or5 && (type == 4))
 651                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
 652         if (core1or5 && (type == 5))
 653                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
 654         if (core2or5 && (type == 5))
 655                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 656 }
 657
 658 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
 659 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
 660 {
 661         u16 val;
 662
 663         if (dev->phy.rev >= 3) {
 664                 /* TODO */
 665         } else {
 666                 if (type < 3)
 667                         val = 0;
 668                 else if (type == 6)
 669                         val = 1;
 670                 else if (type == 3)
 671                         val = 2;
 672                 else
 673                         val = 3;
 674
 675                 val = (val << 12) | (val << 14);
 676                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
 677                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
 678
 679                 if (type < 3) {
 680                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
 681                                         (type + 1) << 4);
 682                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
 683                                         (type + 1) << 4);
 684                 }
 685
 686                 /* TODO use some definitions */
 687                 if (code == 0) {
 688                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
 689                         if (type < 3) {
 690                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 691                                                 0xFEC7, 0);
 692                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 693                                                 0xEFDC, 0);
 694                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 695                                                 0xFFFE, 0);
 696                                 udelay(20);
 697                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 698                                                 0xFFFE, 0);
 699                         }
 700                 } else {
 701                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
 702                                         0x3000);
 703                         if (type < 3) {
 704                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 705                                                 0xFEC7, 0x0180);
 706                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 707                                                 0xEFDC, (code << 1 | 0x1021));
 708                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 709                                                 0xFFFE, 0x0001);
 710                                 udelay(20);
 711                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 712                                                 0xFFFE, 0);
 713                         }
 714                 }
 715         }
 716 }
 717
 718 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
 719 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
 720 {
 721         int i;
 722         for (i = 0; i < 2; i++) {
 723                 if (type == 2) {
 724                         if (i == 0) {
 725                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
 726                                                   0xFC, buf[0]);
 727                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
 728                                                   0xFC, buf[1]);
 729                         } else {
 730                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
 731                                                   0xFC, buf[2 * i]);
 732                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
 733                                                   0xFC, buf[2 * i + 1]);
 734                         }
 735                 } else {
 736                         if (i == 0)
 737                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
 738                                                   0xF3, buf[0] << 2);
 739                         else
 740                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
 741                                                   0xF3, buf[2 * i + 1] << 2);
 742                 }
 743         }
 744 }
 745
 746 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
 747 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
 748                                 u8 nsamp)
 749 {
 750         int i;
 751         int out;
 752         u16 save_regs_phy[9];
 753         u16 s[2];
 754
 755         if (dev->phy.rev >= 3) {
 756                 save_regs_phy[0] = b43_phy_read(dev,
 757                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
 758                 save_regs_phy[1] = b43_phy_read(dev,
 759                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
 760                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 761                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 762                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 763                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 764                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
 765                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
 766         }
 767
 768         b43_nphy_rssi_select(dev, 5, type);
 769
 770         if (dev->phy.rev < 2) {
 771                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
 772                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
 773         }
 774
 775         for (i = 0; i < 4; i++)
 776                 buf[i] = 0;
 777
 778         for (i = 0; i < nsamp; i++) {
 779                 if (dev->phy.rev < 2) {
 780                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
 781                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
 782                 } else {
 783                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
 784                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
 785                 }
 786
 787                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
 788                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
 789                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
 790                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
 791         }
 792         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
 793                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
 794
 795         if (dev->phy.rev < 2)
 796                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
 797
 798         if (dev->phy.rev >= 3) {
 799                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
 800                                 save_regs_phy[0]);
 801                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
 802                                 save_regs_phy[1]);
 803                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
 804                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
 805                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
 806                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
 807                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
 808                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
 809         }
 810
 811         return out;
 812 }
 813
 814 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
 815 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
 816 {
 817         int i, j;
 818         u8 state[4];
 819         u8 code, val;
 820         u16 class, override;
 821         u8 regs_save_radio[2];
 822         u16 regs_save_phy[2];
 823         s8 offset[4];
 824
 825         u16 clip_state[2];
 826         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
 827         s32 results_min[4] = { };
 828         u8 vcm_final[4] = { };
 829         s32 results[4][4] = { };
 830         s32 miniq[4][2] = { };
 831
 832         if (type == 2) {
 833                 code = 0;
 834                 val = 6;
 835         } else if (type < 2) {
 836                 code = 25;
 837                 val = 4;
 838         } else {
 839                 B43_WARN_ON(1);
 840                 return;
 841         }
 842
 843         class = b43_nphy_classifier(dev, 0, 0);
 844         b43_nphy_classifier(dev, 7, 4);
 845         b43_nphy_read_clip_detection(dev, clip_state);
 846         b43_nphy_write_clip_detection(dev, clip_off);
 847
 848         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 849                 override = 0x140;
 850         else
 851                 override = 0x110;
 852
 853         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 854         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
 855         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
 856         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
 857
 858         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 859         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
 860         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
 861         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
 862
 863         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
 864         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
 865         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
 866         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
 867         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
 868         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
 869
 870         b43_nphy_rssi_select(dev, 5, type);
 871         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
 872         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
 873
 874         for (i = 0; i < 4; i++) {
 875                 u8 tmp[4];
 876                 for (j = 0; j < 4; j++)
 877                         tmp[j] = i;
 878                 if (type != 1)
 879                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
 880                 b43_nphy_poll_rssi(dev, type, results[i], 8);
 881                 if (type < 2)
 882                         for (j = 0; j < 2; j++)
 883                                 miniq[i][j] = min(results[i][2 * j],
 884                                                 results[i][2 * j + 1]);
 885         }
 886
 887         for (i = 0; i < 4; i++) {
 888                 s32 mind = 40;
 889                 u8 minvcm = 0;
 890                 s32 minpoll = 249;
 891                 s32 curr;
 892                 for (j = 0; j < 4; j++) {
 893                         if (type == 2)
 894                                 curr = abs(results[j][i]);
 895                         else
 896                                 curr = abs(miniq[j][i / 2] - code * 8);
 897
 898                         if (curr < mind) {
 899                                 mind = curr;
 900                                 minvcm = j;
 901                         }
 902
 903                         if (results[j][i] < minpoll)
 904                                 minpoll = results[j][i];
 905                 }
 906                 results_min[i] = minpoll;
 907                 vcm_final[i] = minvcm;
 908         }
 909
 910         if (type != 1)
 911                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
 912
 913         for (i = 0; i < 4; i++) {
 914                 offset[i] = (code * 8) - results[vcm_final[i]][i];
 915
 916                 if (offset[i] < 0)
 917                         offset[i] = -((abs(offset[i]) + 4) / 8);
 918                 else
 919                         offset[i] = (offset[i] + 4) / 8;
 920
 921                 if (results_min[i] == 248)
 922                         offset[i] = code - 32;
 923
 924                 if (i % 2 == 0)
 925                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
 926                                                         type);
 927                 else
 928                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
 929                                                         type);
 930         }
 931
 932         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
 933         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
 934
 935         switch (state[2]) {
 936         case 1:
 937                 b43_nphy_rssi_select(dev, 1, 2);
 938                 break;
 939         case 4:
 940                 b43_nphy_rssi_select(dev, 1, 0);
 941                 break;
 942         case 2:
 943                 b43_nphy_rssi_select(dev, 1, 1);
 944                 break;
 945         default:
 946                 b43_nphy_rssi_select(dev, 1, 1);
 947                 break;
 948         }
 949
 950         switch (state[3]) {
 951         case 1:
 952                 b43_nphy_rssi_select(dev, 2, 2);
 953                 break;
 954         case 4:
 955                 b43_nphy_rssi_select(dev, 2, 0);
 956                 break;
 957         default:
 958                 b43_nphy_rssi_select(dev, 2, 1);
 959                 break;
 960         }
 961
 962         b43_nphy_rssi_select(dev, 0, type);
 963
 964         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
 965         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
 966         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
 967         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
 968
 969         b43_nphy_classifier(dev, 7, class);
 970         b43_nphy_write_clip_detection(dev, clip_state);
 971 }
 972
 973 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
 974 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
 975 {
 976         /* TODO */
 977 }
 978
 979 /*
 980  * RSSI Calibration
 981  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
 982  */
 983 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
 984 {
 985         if (dev->phy.rev >= 3) {
 986                 b43_nphy_rev3_rssi_cal(dev);
 987         } else {
 988                 b43_nphy_rev2_rssi_cal(dev, 2);
 989                 b43_nphy_rev2_rssi_cal(dev, 0);
 990                 b43_nphy_rev2_rssi_cal(dev, 1);
 991         }
 992 }
 993
 994 /*
 995  * Restore RSSI Calibration
 996  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
 997  */
 998 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
 999 {
1000         struct b43_phy_n *nphy = dev->phy.n;
1001
1002         u16 *rssical_radio_regs = NULL;
1003         u16 *rssical_phy_regs = NULL;
1004
1005         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1006                 if (!nphy->rssical_chanspec_2G)
1007                         return;
1008                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1009                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1010         } else {
1011                 if (!nphy->rssical_chanspec_5G)
1012                         return;
1013                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1014                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1015         }
1016
1017         /* TODO use some definitions */
1018         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1019         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1020
1021         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1022         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1023         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1024         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1025
1026         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1027         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1028         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1029         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1030
1031         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1032         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1033         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1034         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1035 }
1036
1037 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1038 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1039 {
1040         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1041                 if (dev->phy.rev >= 6) {
1042                         /* TODO If the chip is 47162
1043                                 return txpwrctrl_tx_gain_ipa_rev5 */
1044                         return txpwrctrl_tx_gain_ipa_rev6;
1045                 } else if (dev->phy.rev >= 5) {
1046                         return txpwrctrl_tx_gain_ipa_rev5;
1047                 } else {
1048                         return txpwrctrl_tx_gain_ipa;
1049                 }
1050         } else {
1051                 return txpwrctrl_tx_gain_ipa_5g;
1052         }
1053 }
1054
1055 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1056 static void b43_nphy_restore_cal(struct b43_wldev *dev)
1057 {
1058         struct b43_phy_n *nphy = dev->phy.n;
1059
1060         u16 coef[4];
1061         u16 *loft = NULL;
1062         u16 *table = NULL;
1063
1064         int i;
1065         u16 *txcal_radio_regs = NULL;
1066         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1067
1068         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1069                 if (nphy->iqcal_chanspec_2G == 0)
1070                         return;
1071                 table = nphy->cal_cache.txcal_coeffs_2G;
1072                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1073         } else {
1074                 if (nphy->iqcal_chanspec_5G == 0)
1075                         return;
1076                 table = nphy->cal_cache.txcal_coeffs_5G;
1077                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1078         }
1079
1080         /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1081                 width 16, and data from table */
1082
1083         for (i = 0; i < 4; i++) {
1084                 if (dev->phy.rev >= 3)
1085                         table[i] = coef[i];
1086                 else
1087                         coef[i] = 0;
1088         }
1089
1090         /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1091                 width 16, and data from coef */
1092         /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1093                 width 16 and data from loft */
1094         /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1095                 width 16 and data from loft */
1096
1097         if (dev->phy.rev < 2)
1098                 b43_nphy_tx_iq_workaround(dev);
1099
1100         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1101                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1102                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1103         } else {
1104                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1105                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1106         }
1107
1108         /* TODO use some definitions */
1109         if (dev->phy.rev >= 3) {
1110                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1111                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1112                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1113                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1114                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1115                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1116                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1117                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1118         } else {
1119                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1120                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1121                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1122                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1123         }
1124         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1125 }
1126
1127 /*
1128  * Init N-PHY
1129  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
1130  */
1131 int b43_phy_initn(struct b43_wldev *dev)
1132 {
1133         struct ssb_bus *bus = dev->dev->bus;
1134         struct b43_phy *phy = &dev->phy;
1135         struct b43_phy_n *nphy = phy->n;
1136         u8 tx_pwr_state;
1137         struct nphy_txgains target;
1138         u16 tmp;
1139         enum ieee80211_band tmp2;
1140         bool do_rssi_cal;
1141
1142         u16 clip[2];
1143         bool do_cal = false;
1144
1145         if ((dev->phy.rev >= 3) &&
1146            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
1147            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
1148                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
1149         }
1150         nphy->deaf_count = 0;
1151         b43_nphy_tables_init(dev);
1152         nphy->crsminpwr_adjusted = false;
1153         nphy->noisevars_adjusted = false;
1154
1155         /* Clear all overrides */
1156         if (dev->phy.rev >= 3) {
1157                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
1158                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1159                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
1160                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
1161         } else {
1162                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1163         }
1164         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
1165         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
1166         if (dev->phy.rev < 6) {
1167                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
1168                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
1169         }
1170         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1171                      ~(B43_NPHY_RFSEQMODE_CAOVER |
1172                        B43_NPHY_RFSEQMODE_TROVER));
1173         if (dev->phy.rev >= 3)
1174                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
1175         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
1176
1177         if (dev->phy.rev <= 2) {
1178                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
1179                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1180                                 ~B43_NPHY_BPHY_CTL3_SCALE,
1181                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
1182         }
1183         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
1184         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
1185
1186         if (bus->sprom.boardflags2_lo & 0x100 ||
1187             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
1188              bus->boardinfo.type == 0x8B))
1189                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
1190         else
1191                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
1192         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
1193         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
1194         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
1195
1196         /* TODO MIMO-Config */
1197         /* TODO Update TX/RX chain */
1198
1199         if (phy->rev < 2) {
1200                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
1201                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
1202         }
1203
1204         tmp2 = b43_current_band(dev->wl);
1205         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
1206             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
1207                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
1208                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
1209                                 nphy->papd_epsilon_offset[0] << 7);
1210                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
1211                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
1212                                 nphy->papd_epsilon_offset[1] << 7);
1213                 /* TODO N PHY IPA Set TX Dig Filters */
1214         } else if (phy->rev >= 5) {
1215                 /* TODO N PHY Ext PA Set TX Dig Filters */
1216         }
1217
1218         b43_nphy_workarounds(dev);
1219
1220         /* Reset CCA, in init code it differs a little from standard way */
1221         /* b43_nphy_bmac_clock_fgc(dev, 1); */
1222         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
1223         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
1224         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
1225         /* b43_nphy_bmac_clock_fgc(dev, 0); */
1226
1227         /* TODO N PHY MAC PHY Clock Set with argument 1 */
1228
1229         b43_nphy_pa_override(dev, false);
1230         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1231         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1232         b43_nphy_pa_override(dev, true);
1233
1234         b43_nphy_classifier(dev, 0, 0);
1235         b43_nphy_read_clip_detection(dev, clip);
1236         tx_pwr_state = nphy->txpwrctrl;
1237         /* TODO N PHY TX power control with argument 0
1238                 (turning off power control) */
1239         /* TODO Fix the TX Power Settings */
1240         /* TODO N PHY TX Power Control Idle TSSI */
1241         /* TODO N PHY TX Power Control Setup */
1242
1243         if (phy->rev >= 3) {
1244                 /* TODO */
1245         } else {
1246                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1247                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1248         }
1249
1250         if (nphy->phyrxchain != 3)
1251                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
1252         if (nphy->mphase_cal_phase_id > 0)
1253                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
1254
1255         do_rssi_cal = false;
1256         if (phy->rev >= 3) {
1257                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1258                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
1259                 else
1260                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
1261
1262                 if (do_rssi_cal)
1263                         b43_nphy_rssi_cal(dev);
1264                 else
1265                         b43_nphy_restore_rssi_cal(dev);
1266         } else {
1267                 b43_nphy_rssi_cal(dev);
1268         }
1269
1270         if (!((nphy->measure_hold & 0x6) != 0)) {
1271                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1272                         do_cal = (nphy->iqcal_chanspec_2G == 0);
1273                 else
1274                         do_cal = (nphy->iqcal_chanspec_5G == 0);
1275
1276                 if (nphy->mute)
1277                         do_cal = false;
1278
1279                 if (do_cal) {
1280                         /* target = b43_nphy_get_tx_gains(dev); */
1281
1282                         if (nphy->antsel_type == 2)
1283                                 ;/*TODO NPHY Superswitch Init with argument 1*/
1284                         if (nphy->perical != 2) {
1285                                 b43_nphy_rssi_cal(dev);
1286                                 if (phy->rev >= 3) {
1287                                         nphy->cal_orig_pwr_idx[0] =
1288                                             nphy->txpwrindex[0].index_internal;
1289                                         nphy->cal_orig_pwr_idx[1] =
1290                                             nphy->txpwrindex[1].index_internal;
1291                                         /* TODO N PHY Pre Calibrate TX Gain */
1292                                         /*target = b43_nphy_get_tx_gains(dev)*/
1293                                 }
1294                         }
1295                 }
1296         }
1297
1298         /*
1299         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
1300                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
1301                         Call N PHY Save Cal
1302                 else if (nphy->mphase_cal_phase_id == 0)
1303                         N PHY Periodic Calibration with argument 3
1304         } else {
1305                 b43_nphy_restore_cal(dev);
1306         }
1307         */
1308
1309         /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
1310         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
1311         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
1312         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
1313         if (phy->rev >= 3 && phy->rev <= 6)
1314                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
1315         /* b43_nphy_tx_lp_fbw(dev); */
1316         /* TODO N PHY Spur Workaround */
1317
1318         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
1319         return 0;
1320 }
1321
1322 static int b43_nphy_op_allocate(struct b43_wldev *dev)
1323 {
1324         struct b43_phy_n *nphy;
1325
1326         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
1327         if (!nphy)
1328                 return -ENOMEM;
1329         dev->phy.n = nphy;
1330
1331         return 0;
1332 }
1333
1334 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
1335 {
1336         struct b43_phy *phy = &dev->phy;
1337         struct b43_phy_n *nphy = phy->n;
1338
1339         memset(nphy, 0, sizeof(*nphy));
1340
1341         //TODO init struct b43_phy_n
1342 }
1343
1344 static void b43_nphy_op_free(struct b43_wldev *dev)
1345 {
1346         struct b43_phy *phy = &dev->phy;
1347         struct b43_phy_n *nphy = phy->n;
1348
1349         kfree(nphy);
1350         phy->n = NULL;
1351 }
1352
1353 static int b43_nphy_op_init(struct b43_wldev *dev)
1354 {
1355         return b43_phy_initn(dev);
1356 }
1357
1358 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
1359 {
1360 #if B43_DEBUG
1361         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
1362                 /* OFDM registers are onnly available on A/G-PHYs */
1363                 b43err(dev->wl, "Invalid OFDM PHY access at "
1364                        "0x%04X on N-PHY\n", offset);
1365                 dump_stack();
1366         }
1367         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
1368                 /* Ext-G registers are only available on G-PHYs */
1369                 b43err(dev->wl, "Invalid EXT-G PHY access at "
1370                        "0x%04X on N-PHY\n", offset);
1371                 dump_stack();
1372         }
1373 #endif /* B43_DEBUG */
1374 }
1375
1376 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
1377 {
1378         check_phyreg(dev, reg);
1379         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1380         return b43_read16(dev, B43_MMIO_PHY_DATA);
1381 }
1382
1383 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1384 {
1385         check_phyreg(dev, reg);
1386         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1387         b43_write16(dev, B43_MMIO_PHY_DATA, value);
1388 }
1389
1390 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1391 {
1392         /* Register 1 is a 32-bit register. */
1393         B43_WARN_ON(reg == 1);
1394         /* N-PHY needs 0x100 for read access */
1395         reg |= 0x100;
1396
1397         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1398         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1399 }
1400
1401 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1402 {
1403         /* Register 1 is a 32-bit register. */
1404         B43_WARN_ON(reg == 1);
1405
1406         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1407         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1408 }
1409
1410 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
1411                                         bool blocked)
1412 {//TODO
1413 }
1414
1415 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
1416 {
1417         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1418                       on ? 0 : 0x7FFF);
1419 }
1420
1421 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
1422                                       unsigned int new_channel)
1423 {
1424         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1425                 if ((new_channel < 1) || (new_channel > 14))
1426                         return -EINVAL;
1427         } else {
1428                 if (new_channel > 200)
1429                         return -EINVAL;
1430         }
1431
1432         return nphy_channel_switch(dev, new_channel);
1433 }
1434
1435 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
1436 {
1437         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1438                 return 1;
1439         return 36;
1440 }
1441
1442 const struct b43_phy_operations b43_phyops_n = {
1443         .allocate               = b43_nphy_op_allocate,
1444         .free                   = b43_nphy_op_free,
1445         .prepare_structs        = b43_nphy_op_prepare_structs,
1446         .init                   = b43_nphy_op_init,
1447         .phy_read               = b43_nphy_op_read,
1448         .phy_write              = b43_nphy_op_write,
1449         .radio_read             = b43_nphy_op_radio_read,
1450         .radio_write            = b43_nphy_op_radio_write,
1451         .software_rfkill        = b43_nphy_op_software_rfkill,
1452         .switch_analog          = b43_nphy_op_switch_analog,
1453         .switch_channel         = b43_nphy_op_switch_channel,
1454         .get_default_chan       = b43_nphy_op_get_default_chan,
1455         .recalc_txpower         = b43_nphy_op_recalc_txpower,
1456         .adjust_txpower         = b43_nphy_op_adjust_txpower,
1457 };