3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/types.h>
30 #include "tables_nphy.h"
40 struct nphy_iqcal_params {
58 enum b43_nphy_rf_sequence {
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
68 u8 *events, u8 *delays, u8 length);
69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
70 enum b43_nphy_rf_sequence seq);
71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
72 u16 value, u8 core, bool off);
73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
87 return B43_TXPWR_RES_DONE;
90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
91 const struct b43_nphy_channeltab_entry *e)
93 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
94 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
95 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
96 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
97 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
98 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
99 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
100 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
101 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
102 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
103 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
104 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
105 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
106 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
107 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
108 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
109 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
110 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
111 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
112 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
113 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
114 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
117 static void b43_chantab_phy_upload(struct b43_wldev *dev,
118 const struct b43_nphy_channeltab_entry *e)
120 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
121 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
122 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
123 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
124 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
125 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
128 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
133 /* Tune the hardware to a new channel. */
134 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
136 const struct b43_nphy_channeltab_entry *tabent;
138 tabent = b43_nphy_get_chantabent(dev, channel);
142 //FIXME enable/disable band select upper20 in RXCTL
143 if (0 /*FIXME 5Ghz*/)
144 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
146 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
147 b43_chantab_radio_upload(dev, tabent);
149 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
150 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
151 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
153 if (0 /*FIXME 5Ghz*/)
154 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
156 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
157 b43_chantab_phy_upload(dev, tabent);
158 b43_nphy_tx_power_fix(dev);
163 static void b43_radio_init2055_pre(struct b43_wldev *dev)
165 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
166 ~B43_NPHY_RFCTL_CMD_PORFORCE);
167 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
168 B43_NPHY_RFCTL_CMD_CHIP0PU |
169 B43_NPHY_RFCTL_CMD_OEPORFORCE);
170 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
171 B43_NPHY_RFCTL_CMD_PORFORCE);
174 static void b43_radio_init2055_post(struct b43_wldev *dev)
176 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
177 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
181 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
183 if ((sprom->revision != 4) ||
184 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
185 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
186 (binfo->type != 0x46D) ||
187 (binfo->rev < 0x41)) {
188 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
189 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
193 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
195 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
197 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
199 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
201 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
203 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
205 for (i = 0; i < 100; i++) {
206 val = b43_radio_read16(dev, B2055_CAL_COUT2);
212 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
214 nphy_channel_switch(dev, dev->phy.channel);
215 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
216 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
217 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
218 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
221 /* Initialize a Broadcom 2055 N-radio */
222 static void b43_radio_init2055(struct b43_wldev *dev)
224 b43_radio_init2055_pre(dev);
225 if (b43_status(dev) < B43_STAT_INITIALIZED)
226 b2055_upload_inittab(dev, 0, 1);
228 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
229 b43_radio_init2055_post(dev);
232 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
234 b43_radio_init2055(dev);
237 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
239 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
240 ~B43_NPHY_RFCTL_CMD_EN);
244 * Upload the N-PHY tables.
245 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
247 static void b43_nphy_tables_init(struct b43_wldev *dev)
249 if (dev->phy.rev < 3)
250 b43_nphy_rev0_1_2_tables_init(dev);
252 b43_nphy_rev3plus_tables_init(dev);
255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
256 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
258 struct b43_phy_n *nphy = dev->phy.n;
259 enum ieee80211_band band;
263 nphy->rfctrl_intc1_save = b43_phy_read(dev,
264 B43_NPHY_RFCTL_INTC1);
265 nphy->rfctrl_intc2_save = b43_phy_read(dev,
266 B43_NPHY_RFCTL_INTC2);
267 band = b43_current_band(dev->wl);
268 if (dev->phy.rev >= 3) {
269 if (band == IEEE80211_BAND_5GHZ)
274 if (band == IEEE80211_BAND_5GHZ)
279 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
280 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
282 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
283 nphy->rfctrl_intc1_save);
284 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
285 nphy->rfctrl_intc2_save);
289 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
290 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
292 struct b43_phy_n *nphy = dev->phy.n;
294 enum ieee80211_band band = b43_current_band(dev->wl);
295 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
296 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
298 if (dev->phy.rev >= 3) {
301 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
302 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
306 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
307 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
312 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
316 if (dev->phy.type != B43_PHYTYPE_N)
319 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
321 tmslow |= SSB_TMSLOW_FGC;
323 tmslow &= ~SSB_TMSLOW_FGC;
324 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
327 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
328 static void b43_nphy_reset_cca(struct b43_wldev *dev)
332 b43_nphy_bmac_clock_fgc(dev, 1);
333 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
334 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
336 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
337 b43_nphy_bmac_clock_fgc(dev, 0);
338 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
342 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
344 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
346 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
348 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
350 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
352 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
355 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
356 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
358 struct b43_phy_n *nphy = dev->phy.n;
360 bool override = false;
363 if (nphy->txrx_chain == 0) {
366 } else if (nphy->txrx_chain == 1) {
371 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
372 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
376 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
377 B43_NPHY_RFSEQMODE_CAOVER);
379 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
380 ~B43_NPHY_RFSEQMODE_CAOVER);
383 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
384 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
385 u16 samps, u8 time, bool wait)
390 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
391 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
393 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
395 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
397 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
399 for (i = 1000; i; i--) {
400 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
401 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
402 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
403 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
404 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
405 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
406 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
407 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
409 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
410 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
411 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
412 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
413 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
414 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
419 memset(est, 0, sizeof(*est));
422 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
423 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
424 struct b43_phy_n_iq_comp *pcomp)
427 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
428 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
429 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
430 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
432 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
433 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
434 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
435 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
440 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
442 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
444 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
446 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
447 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
449 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
450 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
452 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
453 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
454 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
455 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
456 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
457 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
458 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
459 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
462 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
463 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
466 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
468 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
470 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
471 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
473 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
474 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
476 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
477 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
478 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
479 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
480 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
481 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
482 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
483 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
485 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
486 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
488 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
489 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
490 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
491 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
492 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
493 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
494 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
495 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
498 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
499 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
501 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
502 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
505 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
506 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
507 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
516 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
517 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
521 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
527 int iq_nbits, qq_nbits;
531 struct nphy_iq_est est;
532 struct b43_phy_n_iq_comp old;
533 struct b43_phy_n_iq_comp new = { };
539 b43_nphy_rx_iq_coeffs(dev, false, &old);
540 b43_nphy_rx_iq_coeffs(dev, true, &new);
541 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
544 for (i = 0; i < 2; i++) {
545 if (i == 0 && (mask & 1)) {
549 } else if (i == 1 && (mask & 2)) {
563 iq_nbits = fls(abs(iq));
566 arsh = iq_nbits - 20;
568 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
571 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
580 brsh = qq_nbits - 11;
582 b = (qq << (31 - qq_nbits));
585 b = (qq << (31 - qq_nbits));
592 b = int_sqrt(b / tmp - a * a) - (1 << 10);
594 if (i == 0 && (mask & 0x1)) {
595 if (dev->phy.rev >= 3) {
602 } else if (i == 1 && (mask & 0x2)) {
603 if (dev->phy.rev >= 3) {
616 b43_nphy_rx_iq_coeffs(dev, true, &new);
619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
620 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
625 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
626 for (i = 0; i < 4; i++)
627 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
629 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
630 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
631 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
632 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
636 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
638 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
639 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
643 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
645 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
646 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
650 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
654 if (dev->dev->id.revision == 16)
655 b43_mac_suspend(dev);
657 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
658 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
659 B43_NPHY_CLASSCTL_WAITEDEN);
662 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
664 if (dev->dev->id.revision == 16)
670 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
671 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
673 struct b43_phy *phy = &dev->phy;
674 struct b43_phy_n *nphy = phy->n;
677 u16 clip[] = { 0xFFFF, 0xFFFF };
678 if (nphy->deaf_count++ == 0) {
679 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
680 b43_nphy_classifier(dev, 0x7, 0);
681 b43_nphy_read_clip_detection(dev, nphy->clip_state);
682 b43_nphy_write_clip_detection(dev, clip);
684 b43_nphy_reset_cca(dev);
686 if (--nphy->deaf_count == 0) {
687 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
688 b43_nphy_write_clip_detection(dev, nphy->clip_state);
693 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
694 static void b43_nphy_stop_playback(struct b43_wldev *dev)
696 struct b43_phy_n *nphy = dev->phy.n;
699 if (nphy->hang_avoid)
700 b43_nphy_stay_in_carrier_search(dev, 1);
702 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
704 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
706 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
708 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
710 if (nphy->bb_mult_save & 0x80000000) {
711 tmp = nphy->bb_mult_save & 0xFFFF;
712 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
713 nphy->bb_mult_save = 0;
716 if (nphy->hang_avoid)
717 b43_nphy_stay_in_carrier_search(dev, 0);
720 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
721 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
723 struct b43_phy_n *nphy = dev->phy.n;
725 unsigned int channel;
726 int tone[2] = { 57, 58 };
727 u32 noise[2] = { 0x3FF, 0x3FF };
729 B43_WARN_ON(dev->phy.rev < 3);
731 if (nphy->hang_avoid)
732 b43_nphy_stay_in_carrier_search(dev, 1);
734 /* FIXME: channel = radio_chanspec */
736 if (nphy->gband_spurwar_en) {
737 /* TODO: N PHY Adjust Analog Pfbw (7) */
738 if (channel == 11 && dev->phy.is_40mhz)
739 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
741 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
742 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
745 if (nphy->aband_spurwar_en) {
749 } else if (channel == 38 || channel == 102 || channel == 118) {
757 } else if (channel == 134) {
760 } else if (channel == 151) {
763 } else if (channel == 153 || channel == 161) {
771 if (!tone[0] && !noise[0])
772 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
774 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
777 if (nphy->hang_avoid)
778 b43_nphy_stay_in_carrier_search(dev, 0);
781 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
782 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
784 struct b43_phy_n *nphy = dev->phy.n;
788 /* TODO: for PHY >= 3
789 s8 *lna1_gain, *lna2_gain;
790 u8 *gain_db, *gain_bits;
792 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
793 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
796 u8 rfseq_events[3] = { 6, 8, 7 };
797 u8 rfseq_delays[3] = { 10, 30, 1 };
799 if (dev->phy.rev >= 3) {
802 /* Set Clip 2 detect */
803 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
804 B43_NPHY_C1_CGAINI_CL2DETECT);
805 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
806 B43_NPHY_C2_CGAINI_CL2DETECT);
808 /* Set narrowband clip threshold */
809 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
810 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
812 if (!dev->phy.is_40mhz) {
813 /* Set dwell lengths */
814 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
815 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
816 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
817 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
820 /* Set wideband clip 2 threshold */
821 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
822 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
824 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
825 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
828 if (!dev->phy.is_40mhz) {
829 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
830 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
831 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
832 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
833 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
834 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
835 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
836 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
839 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
841 if (nphy->gain_boost) {
842 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
848 code = dev->phy.is_40mhz ? 6 : 7;
851 /* Set HPVGA2 index */
852 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
853 ~B43_NPHY_C1_INITGAIN_HPVGA2,
854 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
855 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
856 ~B43_NPHY_C2_INITGAIN_HPVGA2,
857 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
859 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
860 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
862 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
865 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
867 if (nphy->elna_gain_config) {
868 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
869 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
870 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
871 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
872 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
874 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
875 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
876 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
877 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
878 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
880 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
881 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
883 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
887 if (dev->phy.rev == 2) {
888 for (i = 0; i < 4; i++) {
889 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
890 (0x0400 * i) + 0x0020);
891 for (j = 0; j < 21; j++)
893 B43_NPHY_TABLE_DATALO, 3 * j);
896 b43_nphy_set_rf_sequence(dev, 5,
897 rfseq_events, rfseq_delays, 3);
898 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
899 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
900 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
902 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
903 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
910 static void b43_nphy_workarounds(struct b43_wldev *dev)
912 struct ssb_bus *bus = dev->dev->bus;
913 struct b43_phy *phy = &dev->phy;
914 struct b43_phy_n *nphy = phy->n;
916 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
917 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
919 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
920 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
922 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
923 b43_nphy_classifier(dev, 1, 0);
925 b43_nphy_classifier(dev, 1, 1);
927 if (nphy->hang_avoid)
928 b43_nphy_stay_in_carrier_search(dev, 1);
930 b43_phy_set(dev, B43_NPHY_IQFLIP,
931 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
933 if (dev->phy.rev >= 3) {
936 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
937 nphy->band5g_pwrgain) {
938 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
939 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
941 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
942 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
945 /* TODO: convert to b43_ntab_write? */
946 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
947 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
948 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
949 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
950 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
951 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
952 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
953 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
955 if (dev->phy.rev < 2) {
956 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
957 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
958 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
959 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
960 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
961 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
962 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
963 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
964 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
965 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
966 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
967 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
970 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
971 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
972 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
973 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
975 if (bus->sprom.boardflags2_lo & 0x100 &&
976 bus->boardinfo.type == 0x8B) {
980 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
981 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
983 b43_nphy_gain_crtl_workarounds(dev);
985 if (dev->phy.rev < 2) {
986 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
987 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
988 } else if (dev->phy.rev == 2) {
989 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
990 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
993 if (dev->phy.rev < 2)
994 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
995 ~B43_NPHY_SCRAM_SIGCTL_SCM);
997 /* Set phase track alpha and beta */
998 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
999 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1000 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1001 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1002 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1003 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1005 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1006 (u16)~B43_NPHY_PIL_DW_64QAM);
1007 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1008 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1009 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1011 if (dev->phy.rev == 2)
1012 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1013 B43_NPHY_FINERX2_CGC_DECGC);
1016 if (nphy->hang_avoid)
1017 b43_nphy_stay_in_carrier_search(dev, 0);
1020 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1021 static int b43_nphy_load_samples(struct b43_wldev *dev,
1022 struct b43_c32 *samples, u16 len) {
1023 struct b43_phy_n *nphy = dev->phy.n;
1027 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1029 b43err(dev->wl, "allocation for samples loading failed\n");
1032 if (nphy->hang_avoid)
1033 b43_nphy_stay_in_carrier_search(dev, 1);
1035 for (i = 0; i < len; i++) {
1036 data[i] = (samples[i].i & 0x3FF << 10);
1037 data[i] |= samples[i].q & 0x3FF;
1039 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1042 if (nphy->hang_avoid)
1043 b43_nphy_stay_in_carrier_search(dev, 0);
1047 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1048 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1052 u16 bw, len, rot, angle;
1053 struct b43_c32 *samples;
1056 bw = (dev->phy.is_40mhz) ? 40 : 20;
1060 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1065 if (dev->phy.is_40mhz)
1071 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1073 b43err(dev->wl, "allocation for samples generation failed\n");
1076 rot = (((freq * 36) / bw) << 16) / 100;
1079 for (i = 0; i < len; i++) {
1080 samples[i] = b43_cordic(angle);
1082 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1083 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1086 i = b43_nphy_load_samples(dev, samples, len);
1088 return (i < 0) ? 0 : len;
1091 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1092 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1093 u16 wait, bool iqmode, bool dac_test)
1095 struct b43_phy_n *nphy = dev->phy.n;
1100 if (nphy->hang_avoid)
1101 b43_nphy_stay_in_carrier_search(dev, true);
1103 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1104 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1105 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1108 if (!dev->phy.is_40mhz)
1112 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1114 if (nphy->hang_avoid)
1115 b43_nphy_stay_in_carrier_search(dev, false);
1117 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1119 if (loops != 0xFFFF)
1120 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1122 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1124 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1126 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1128 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1130 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1131 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1134 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1136 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1138 for (i = 0; i < 100; i++) {
1139 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1146 b43err(dev->wl, "run samples timeout\n");
1148 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1152 * Transmits a known value for LO calibration
1153 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1155 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1156 bool iqmode, bool dac_test)
1158 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1161 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1165 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1166 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1168 struct b43_phy_n *nphy = dev->phy.n;
1171 u32 cur_real, cur_imag, real_part, imag_part;
1175 if (nphy->hang_avoid)
1176 b43_nphy_stay_in_carrier_search(dev, true);
1178 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1180 for (i = 0; i < 2; i++) {
1181 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1182 (buffer[i * 2 + 1] & 0x3FF);
1183 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1184 (((i + 26) << 10) | 320));
1185 for (j = 0; j < 128; j++) {
1186 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1187 ((tmp >> 16) & 0xFFFF));
1188 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1193 for (i = 0; i < 2; i++) {
1194 tmp = buffer[5 + i];
1195 real_part = (tmp >> 8) & 0xFF;
1196 imag_part = (tmp & 0xFF);
1197 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1198 (((i + 26) << 10) | 448));
1200 if (dev->phy.rev >= 3) {
1201 cur_real = real_part;
1202 cur_imag = imag_part;
1203 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1206 for (j = 0; j < 128; j++) {
1207 if (dev->phy.rev < 3) {
1208 cur_real = (real_part * loscale[j] + 128) >> 8;
1209 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1210 tmp = ((cur_real & 0xFF) << 8) |
1213 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1214 ((tmp >> 16) & 0xFFFF));
1215 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1220 if (dev->phy.rev >= 3) {
1221 b43_shm_write16(dev, B43_SHM_SHARED,
1222 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1223 b43_shm_write16(dev, B43_SHM_SHARED,
1224 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1227 if (nphy->hang_avoid)
1228 b43_nphy_stay_in_carrier_search(dev, false);
1231 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1232 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1233 u8 *events, u8 *delays, u8 length)
1235 struct b43_phy_n *nphy = dev->phy.n;
1237 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1238 u16 offset1 = cmd << 4;
1239 u16 offset2 = offset1 + 0x80;
1241 if (nphy->hang_avoid)
1242 b43_nphy_stay_in_carrier_search(dev, true);
1244 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1245 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1247 for (i = length; i < 16; i++) {
1248 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1249 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1252 if (nphy->hang_avoid)
1253 b43_nphy_stay_in_carrier_search(dev, false);
1256 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1257 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1258 enum b43_nphy_rf_sequence seq)
1260 static const u16 trigger[] = {
1261 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1262 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1263 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1264 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1265 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1266 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1269 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1271 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1273 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1274 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1275 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1276 for (i = 0; i < 200; i++) {
1277 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1281 b43err(dev->wl, "RF sequence status timeout\n");
1283 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1286 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1287 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1288 u16 value, u8 core, bool off)
1291 u8 index = fls(field);
1292 u8 addr, en_addr, val_addr;
1293 /* we expect only one bit set */
1294 B43_WARN_ON(field & (~(1 << (index - 1))));
1296 if (dev->phy.rev >= 3) {
1297 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1298 for (i = 0; i < 2; i++) {
1299 if (index == 0 || index == 16) {
1301 "Unsupported RF Ctrl Override call\n");
1305 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1306 en_addr = B43_PHY_N((i == 0) ?
1307 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1308 val_addr = B43_PHY_N((i == 0) ?
1309 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1312 b43_phy_mask(dev, en_addr, ~(field));
1313 b43_phy_mask(dev, val_addr,
1314 ~(rf_ctrl->val_mask));
1316 if (core == 0 || ((1 << core) & i) != 0) {
1317 b43_phy_set(dev, en_addr, field);
1318 b43_phy_maskset(dev, val_addr,
1319 ~(rf_ctrl->val_mask),
1320 (value << rf_ctrl->val_shift));
1325 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1327 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1330 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1333 for (i = 0; i < 2; i++) {
1334 if (index <= 1 || index == 16) {
1336 "Unsupported RF Ctrl Override call\n");
1340 if (index == 2 || index == 10 ||
1341 (index >= 13 && index <= 15)) {
1345 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1346 addr = B43_PHY_N((i == 0) ?
1347 rf_ctrl->addr0 : rf_ctrl->addr1);
1349 if ((core & (1 << i)) != 0)
1350 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1351 (value << rf_ctrl->shift));
1353 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1354 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1355 B43_NPHY_RFCTL_CMD_START);
1357 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1362 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1363 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1369 B43_WARN_ON(dev->phy.rev < 3);
1370 B43_WARN_ON(field > 4);
1372 for (i = 0; i < 2; i++) {
1373 if ((core == 1 && i == 1) || (core == 2 && !i))
1377 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1378 b43_phy_mask(dev, reg, 0xFBFF);
1382 b43_phy_write(dev, reg, 0);
1383 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1387 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1388 0xFC3F, (value << 6));
1389 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1391 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1392 B43_NPHY_RFCTL_CMD_START);
1393 for (j = 0; j < 100; j++) {
1394 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1402 "intc override timeout\n");
1403 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1406 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1407 0xFC3F, (value << 6));
1408 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1410 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1411 B43_NPHY_RFCTL_CMD_RXTX);
1412 for (j = 0; j < 100; j++) {
1413 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1421 "intc override timeout\n");
1422 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1427 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1434 b43_phy_maskset(dev, reg, ~tmp, val);
1437 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1444 b43_phy_maskset(dev, reg, ~tmp, val);
1447 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1454 b43_phy_maskset(dev, reg, ~tmp, val);
1460 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1466 for (i = 0; i < 14; i++) {
1467 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1471 for (i = 0; i < 16; i++) {
1472 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1475 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1478 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1479 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1480 s8 offset, u8 core, u8 rail, u8 type)
1483 bool core1or5 = (core == 1) || (core == 5);
1484 bool core2or5 = (core == 2) || (core == 5);
1486 offset = clamp_val(offset, -32, 31);
1487 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1489 if (core1or5 && (rail == 0) && (type == 2))
1490 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1491 if (core1or5 && (rail == 1) && (type == 2))
1492 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1493 if (core2or5 && (rail == 0) && (type == 2))
1494 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1495 if (core2or5 && (rail == 1) && (type == 2))
1496 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1497 if (core1or5 && (rail == 0) && (type == 0))
1498 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1499 if (core1or5 && (rail == 1) && (type == 0))
1500 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1501 if (core2or5 && (rail == 0) && (type == 0))
1502 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1503 if (core2or5 && (rail == 1) && (type == 0))
1504 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1505 if (core1or5 && (rail == 0) && (type == 1))
1506 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1507 if (core1or5 && (rail == 1) && (type == 1))
1508 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1509 if (core2or5 && (rail == 0) && (type == 1))
1510 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1511 if (core2or5 && (rail == 1) && (type == 1))
1512 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1513 if (core1or5 && (rail == 0) && (type == 6))
1514 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1515 if (core1or5 && (rail == 1) && (type == 6))
1516 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1517 if (core2or5 && (rail == 0) && (type == 6))
1518 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1519 if (core2or5 && (rail == 1) && (type == 6))
1520 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1521 if (core1or5 && (rail == 0) && (type == 3))
1522 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1523 if (core1or5 && (rail == 1) && (type == 3))
1524 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1525 if (core2or5 && (rail == 0) && (type == 3))
1526 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1527 if (core2or5 && (rail == 1) && (type == 3))
1528 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1529 if (core1or5 && (type == 4))
1530 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1531 if (core2or5 && (type == 4))
1532 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1533 if (core1or5 && (type == 5))
1534 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1535 if (core2or5 && (type == 5))
1536 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1539 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1552 val = (val << 12) | (val << 14);
1553 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1554 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1557 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1559 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1563 /* TODO use some definitions */
1565 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1567 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1568 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1569 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1571 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1574 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1577 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1579 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1580 0xEFDC, (code << 1 | 0x1021));
1581 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1583 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1588 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1590 struct b43_phy_n *nphy = dev->phy.n;
1595 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1596 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1597 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1598 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1599 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1600 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1601 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1602 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1604 for (i = 0; i < 2; i++) {
1605 if ((code == 1 && i == 1) || (code == 2 && !i))
1609 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1610 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1614 B43_NPHY_AFECTL_C1 :
1616 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1619 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1620 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1621 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1624 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1629 b43_phy_set(dev, reg, val);
1632 B43_NPHY_TXF_40CO_B1S0 :
1633 B43_NPHY_TXF_40CO_B32S1;
1634 b43_phy_set(dev, reg, 0x0020);
1644 B43_NPHY_AFECTL_C1 :
1647 b43_phy_maskset(dev, reg, 0xFCFF, val);
1648 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1650 if (type != 3 && type != 6) {
1651 enum ieee80211_band band =
1652 b43_current_band(dev->wl);
1654 if ((nphy->ipa2g_on &&
1655 band == IEEE80211_BAND_2GHZ) ||
1657 band == IEEE80211_BAND_5GHZ))
1658 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1661 reg = (i == 0) ? 0x2000 : 0x3000;
1662 reg |= B2055_PADDRV;
1663 b43_radio_write16(dev, reg, val);
1666 B43_NPHY_AFECTL_OVER1 :
1667 B43_NPHY_AFECTL_OVER;
1668 b43_phy_set(dev, reg, 0x0200);
1675 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1676 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1678 if (dev->phy.rev >= 3)
1679 b43_nphy_rev3_rssi_select(dev, code, type);
1681 b43_nphy_rev2_rssi_select(dev, code, type);
1684 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1685 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1688 for (i = 0; i < 2; i++) {
1691 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1693 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1696 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1698 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1699 0xFC, buf[2 * i + 1]);
1703 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1706 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1707 0xF3, buf[2 * i + 1] << 2);
1712 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1713 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1718 u16 save_regs_phy[9];
1721 if (dev->phy.rev >= 3) {
1722 save_regs_phy[0] = b43_phy_read(dev,
1723 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1724 save_regs_phy[1] = b43_phy_read(dev,
1725 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1726 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1727 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1728 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1729 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1730 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1731 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1734 b43_nphy_rssi_select(dev, 5, type);
1736 if (dev->phy.rev < 2) {
1737 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1738 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1741 for (i = 0; i < 4; i++)
1744 for (i = 0; i < nsamp; i++) {
1745 if (dev->phy.rev < 2) {
1746 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1747 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1749 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1750 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1753 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1754 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1755 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1756 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1758 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1759 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1761 if (dev->phy.rev < 2)
1762 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1764 if (dev->phy.rev >= 3) {
1765 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1767 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1769 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1770 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1771 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1772 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1773 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1774 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1781 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1786 u16 class, override;
1787 u8 regs_save_radio[2];
1788 u16 regs_save_phy[2];
1792 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1793 s32 results_min[4] = { };
1794 u8 vcm_final[4] = { };
1795 s32 results[4][4] = { };
1796 s32 miniq[4][2] = { };
1801 } else if (type < 2) {
1809 class = b43_nphy_classifier(dev, 0, 0);
1810 b43_nphy_classifier(dev, 7, 4);
1811 b43_nphy_read_clip_detection(dev, clip_state);
1812 b43_nphy_write_clip_detection(dev, clip_off);
1814 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1819 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1820 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1821 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1822 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1824 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1825 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1826 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1827 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1829 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1830 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1831 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1832 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1833 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1834 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1836 b43_nphy_rssi_select(dev, 5, type);
1837 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1838 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1840 for (i = 0; i < 4; i++) {
1842 for (j = 0; j < 4; j++)
1845 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1846 b43_nphy_poll_rssi(dev, type, results[i], 8);
1848 for (j = 0; j < 2; j++)
1849 miniq[i][j] = min(results[i][2 * j],
1850 results[i][2 * j + 1]);
1853 for (i = 0; i < 4; i++) {
1858 for (j = 0; j < 4; j++) {
1860 curr = abs(results[j][i]);
1862 curr = abs(miniq[j][i / 2] - code * 8);
1869 if (results[j][i] < minpoll)
1870 minpoll = results[j][i];
1872 results_min[i] = minpoll;
1873 vcm_final[i] = minvcm;
1877 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1879 for (i = 0; i < 4; i++) {
1880 offset[i] = (code * 8) - results[vcm_final[i]][i];
1883 offset[i] = -((abs(offset[i]) + 4) / 8);
1885 offset[i] = (offset[i] + 4) / 8;
1887 if (results_min[i] == 248)
1888 offset[i] = code - 32;
1891 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1894 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1898 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1899 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1903 b43_nphy_rssi_select(dev, 1, 2);
1906 b43_nphy_rssi_select(dev, 1, 0);
1909 b43_nphy_rssi_select(dev, 1, 1);
1912 b43_nphy_rssi_select(dev, 1, 1);
1918 b43_nphy_rssi_select(dev, 2, 2);
1921 b43_nphy_rssi_select(dev, 2, 0);
1924 b43_nphy_rssi_select(dev, 2, 1);
1928 b43_nphy_rssi_select(dev, 0, type);
1930 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1931 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1932 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1933 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1935 b43_nphy_classifier(dev, 7, class);
1936 b43_nphy_write_clip_detection(dev, clip_state);
1939 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1940 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1947 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1949 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1951 if (dev->phy.rev >= 3) {
1952 b43_nphy_rev3_rssi_cal(dev);
1954 b43_nphy_rev2_rssi_cal(dev, 2);
1955 b43_nphy_rev2_rssi_cal(dev, 0);
1956 b43_nphy_rev2_rssi_cal(dev, 1);
1961 * Restore RSSI Calibration
1962 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1964 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1966 struct b43_phy_n *nphy = dev->phy.n;
1968 u16 *rssical_radio_regs = NULL;
1969 u16 *rssical_phy_regs = NULL;
1971 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1972 if (!nphy->rssical_chanspec_2G)
1974 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1975 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1977 if (!nphy->rssical_chanspec_5G)
1979 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1980 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1983 /* TODO use some definitions */
1984 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1985 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1987 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1988 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1989 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1990 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1992 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1993 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1994 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1995 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1997 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1998 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1999 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2000 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2003 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2004 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2006 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2007 if (dev->phy.rev >= 6) {
2008 /* TODO If the chip is 47162
2009 return txpwrctrl_tx_gain_ipa_rev5 */
2010 return txpwrctrl_tx_gain_ipa_rev6;
2011 } else if (dev->phy.rev >= 5) {
2012 return txpwrctrl_tx_gain_ipa_rev5;
2014 return txpwrctrl_tx_gain_ipa;
2017 return txpwrctrl_tx_gain_ipa_5g;
2021 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2022 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2024 struct b43_phy_n *nphy = dev->phy.n;
2025 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2029 if (dev->phy.rev >= 3) {
2030 for (i = 0; i < 2; i++) {
2031 tmp = (i == 0) ? 0x2000 : 0x3000;
2034 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2035 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2036 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2037 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2038 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2039 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2040 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2041 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2042 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2043 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2044 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2046 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2047 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2048 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2049 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2050 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2051 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2052 if (nphy->ipa5g_on) {
2053 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2054 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2056 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2057 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2059 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2061 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2062 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2063 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2064 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2065 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2066 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2067 if (nphy->ipa2g_on) {
2068 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2069 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2070 (dev->phy.rev < 5) ? 0x11 : 0x01);
2072 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2073 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2076 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2077 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2078 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2081 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2082 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2084 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2085 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2087 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2088 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2090 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2091 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2093 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2094 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2096 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2097 B43_NPHY_BANDCTL_5GHZ)) {
2098 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2099 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2101 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2102 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2105 if (dev->phy.rev < 2) {
2106 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2107 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2109 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2110 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2115 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2116 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2117 struct nphy_txgains target,
2118 struct nphy_iqcal_params *params)
2123 if (dev->phy.rev >= 3) {
2124 params->txgm = target.txgm[core];
2125 params->pga = target.pga[core];
2126 params->pad = target.pad[core];
2127 params->ipa = target.ipa[core];
2128 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2129 (params->pad << 4) | (params->ipa);
2130 for (j = 0; j < 5; j++)
2131 params->ncorr[j] = 0x79;
2133 gain = (target.pad[core]) | (target.pga[core] << 4) |
2134 (target.txgm[core] << 8);
2136 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2138 for (i = 0; i < 9; i++)
2139 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2143 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2144 params->pga = tbl_iqcal_gainparams[indx][i][2];
2145 params->pad = tbl_iqcal_gainparams[indx][i][3];
2146 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2148 for (j = 0; j < 4; j++)
2149 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2153 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2154 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2156 struct b43_phy_n *nphy = dev->phy.n;
2160 u16 tmp = nphy->txcal_bbmult;
2165 for (i = 0; i < 18; i++) {
2166 scale = (ladder_lo[i].percent * tmp) / 100;
2167 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2168 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2170 scale = (ladder_iq[i].percent * tmp) / 100;
2171 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2172 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2176 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2177 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2180 for (i = 0; i < 15; i++)
2181 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2182 tbl_tx_filter_coef_rev4[2][i]);
2185 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2186 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2189 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2190 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2192 for (i = 0; i < 3; i++)
2193 for (j = 0; j < 15; j++)
2194 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2195 tbl_tx_filter_coef_rev4[i][j]);
2197 if (dev->phy.is_40mhz) {
2198 for (j = 0; j < 15; j++)
2199 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2200 tbl_tx_filter_coef_rev4[3][j]);
2201 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2202 for (j = 0; j < 15; j++)
2203 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2204 tbl_tx_filter_coef_rev4[5][j]);
2207 if (dev->phy.channel == 14)
2208 for (j = 0; j < 15; j++)
2209 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2210 tbl_tx_filter_coef_rev4[6][j]);
2213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2214 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2216 struct b43_phy_n *nphy = dev->phy.n;
2219 struct nphy_txgains target;
2220 const u32 *table = NULL;
2222 if (nphy->txpwrctrl == 0) {
2225 if (nphy->hang_avoid)
2226 b43_nphy_stay_in_carrier_search(dev, true);
2227 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2228 if (nphy->hang_avoid)
2229 b43_nphy_stay_in_carrier_search(dev, false);
2231 for (i = 0; i < 2; ++i) {
2232 if (dev->phy.rev >= 3) {
2233 target.ipa[i] = curr_gain[i] & 0x000F;
2234 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2235 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2236 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2238 target.ipa[i] = curr_gain[i] & 0x0003;
2239 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2240 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2241 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2247 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2248 B43_NPHY_TXPCTL_STAT_BIDX) >>
2249 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2250 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2251 B43_NPHY_TXPCTL_STAT_BIDX) >>
2252 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2254 for (i = 0; i < 2; ++i) {
2255 if (dev->phy.rev >= 3) {
2256 enum ieee80211_band band =
2257 b43_current_band(dev->wl);
2259 if ((nphy->ipa2g_on &&
2260 band == IEEE80211_BAND_2GHZ) ||
2262 band == IEEE80211_BAND_5GHZ)) {
2263 table = b43_nphy_get_ipa_gain_table(dev);
2265 if (band == IEEE80211_BAND_5GHZ) {
2266 if (dev->phy.rev == 3)
2267 table = b43_ntab_tx_gain_rev3_5ghz;
2268 else if (dev->phy.rev == 4)
2269 table = b43_ntab_tx_gain_rev4_5ghz;
2271 table = b43_ntab_tx_gain_rev5plus_5ghz;
2273 table = b43_ntab_tx_gain_rev3plus_2ghz;
2277 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2278 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2279 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2280 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2282 table = b43_ntab_tx_gain_rev0_1_2;
2284 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2285 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2286 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2287 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2295 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2296 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2298 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2300 if (dev->phy.rev >= 3) {
2301 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2302 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2303 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2304 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2305 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2306 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2307 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2308 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2309 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2310 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2311 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2312 b43_nphy_reset_cca(dev);
2314 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2315 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2316 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2317 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2318 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2319 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2320 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2324 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2325 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2327 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2330 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2331 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2332 if (dev->phy.rev >= 3) {
2333 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2334 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2336 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2338 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2340 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2342 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2344 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2345 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2347 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2349 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2351 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2353 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2354 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2355 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2357 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2358 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2359 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2361 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2362 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2363 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2364 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2366 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2367 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2368 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2370 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2371 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2374 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2375 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2378 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2379 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2380 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2381 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2385 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2386 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2390 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2391 static void b43_nphy_save_cal(struct b43_wldev *dev)
2393 struct b43_phy_n *nphy = dev->phy.n;
2395 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2396 u16 *txcal_radio_regs = NULL;
2400 if (nphy->hang_avoid)
2401 b43_nphy_stay_in_carrier_search(dev, 1);
2403 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2404 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2405 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2406 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2407 table = nphy->cal_cache.txcal_coeffs_2G;
2409 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2410 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2411 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2412 table = nphy->cal_cache.txcal_coeffs_5G;
2415 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2416 /* TODO use some definitions */
2417 if (dev->phy.rev >= 3) {
2418 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2419 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2420 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2421 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2422 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2423 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2424 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2425 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2427 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2428 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2429 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2430 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2432 *iqcal_chanspec = nphy->radio_chanspec;
2433 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2435 if (nphy->hang_avoid)
2436 b43_nphy_stay_in_carrier_search(dev, 0);
2439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2440 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2442 struct b43_phy_n *nphy = dev->phy.n;
2449 u16 *txcal_radio_regs = NULL;
2450 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2452 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2453 if (nphy->iqcal_chanspec_2G == 0)
2455 table = nphy->cal_cache.txcal_coeffs_2G;
2456 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2458 if (nphy->iqcal_chanspec_5G == 0)
2460 table = nphy->cal_cache.txcal_coeffs_5G;
2461 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2464 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2466 for (i = 0; i < 4; i++) {
2467 if (dev->phy.rev >= 3)
2473 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2474 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2475 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2477 if (dev->phy.rev < 2)
2478 b43_nphy_tx_iq_workaround(dev);
2480 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2481 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2482 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2484 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2485 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2488 /* TODO use some definitions */
2489 if (dev->phy.rev >= 3) {
2490 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2491 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2492 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2493 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2494 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2495 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2496 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2497 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2499 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2500 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2501 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2502 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2504 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2507 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2508 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2509 struct nphy_txgains target,
2510 bool full, bool mphase)
2512 struct b43_phy_n *nphy = dev->phy.n;
2518 u16 tmp, core, type, count, max, numb, last, cmd;
2526 struct nphy_iqcal_params params[2];
2527 bool updated[2] = { };
2529 b43_nphy_stay_in_carrier_search(dev, true);
2531 if (dev->phy.rev >= 4) {
2532 avoid = nphy->hang_avoid;
2533 nphy->hang_avoid = 0;
2536 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2538 for (i = 0; i < 2; i++) {
2539 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
2540 gain[i] = params[i].cal_gain;
2543 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2545 b43_nphy_tx_cal_radio_setup(dev);
2546 b43_nphy_tx_cal_phy_setup(dev);
2548 phy6or5x = dev->phy.rev >= 6 ||
2549 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2550 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2552 if (dev->phy.is_40mhz) {
2553 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2554 tbl_tx_iqlo_cal_loft_ladder_40);
2555 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2556 tbl_tx_iqlo_cal_iqimb_ladder_40);
2558 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2559 tbl_tx_iqlo_cal_loft_ladder_20);
2560 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2561 tbl_tx_iqlo_cal_iqimb_ladder_20);
2565 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2567 if (!dev->phy.is_40mhz)
2572 if (nphy->mphase_cal_phase_id > 2)
2573 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2574 0xFFFF, 0, true, false);
2576 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2579 if (nphy->mphase_cal_phase_id > 2) {
2580 table = nphy->mphase_txcal_bestcoeffs;
2582 if (dev->phy.rev < 3)
2585 if (!full && nphy->txiqlocal_coeffsvalid) {
2586 table = nphy->txiqlocal_bestc;
2588 if (dev->phy.rev < 3)
2592 if (dev->phy.rev >= 3) {
2593 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2594 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2596 table = tbl_tx_iqlo_cal_startcoefs;
2597 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2602 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2605 if (dev->phy.rev >= 3)
2606 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2608 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2610 if (dev->phy.rev >= 3)
2611 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2613 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2617 count = nphy->mphase_txcal_cmdidx;
2619 (u16)(count + nphy->mphase_txcal_numcmds));
2625 for (; count < numb; count++) {
2627 if (dev->phy.rev >= 3)
2628 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2630 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2632 if (dev->phy.rev >= 3)
2633 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2635 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2638 core = (cmd & 0x3000) >> 12;
2639 type = (cmd & 0x0F00) >> 8;
2641 if (phy6or5x && updated[core] == 0) {
2642 b43_nphy_update_tx_cal_ladder(dev, core);
2646 tmp = (params[core].ncorr[type] << 8) | 0x66;
2647 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2649 if (type == 1 || type == 3 || type == 4) {
2650 buffer[0] = b43_ntab_read(dev,
2651 B43_NTAB16(15, 69 + core));
2652 diq_start = buffer[0];
2654 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2658 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2659 for (i = 0; i < 2000; i++) {
2660 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2666 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2668 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2671 if (type == 1 || type == 3 || type == 4)
2672 buffer[0] = diq_start;
2676 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2678 last = (dev->phy.rev < 3) ? 6 : 7;
2680 if (!mphase || nphy->mphase_cal_phase_id == last) {
2681 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2682 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2683 if (dev->phy.rev < 3) {
2689 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2691 b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2693 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2695 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2698 if (dev->phy.rev < 3)
2700 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2701 nphy->txiqlocal_bestc);
2702 nphy->txiqlocal_coeffsvalid = true;
2703 /* TODO: Set nphy->txiqlocal_chanspec to
2704 the current channel */
2707 if (dev->phy.rev < 3)
2709 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2710 nphy->mphase_txcal_bestcoeffs);
2713 b43_nphy_stop_playback(dev);
2714 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2717 b43_nphy_tx_cal_phy_cleanup(dev);
2718 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2720 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2721 b43_nphy_tx_iq_workaround(dev);
2723 if (dev->phy.rev >= 4)
2724 nphy->hang_avoid = avoid;
2726 b43_nphy_stay_in_carrier_search(dev, false);
2731 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2732 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2734 struct b43_phy_n *nphy = dev->phy.n;
2739 if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2742 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2743 for (i = 0; i < 4; i++) {
2744 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2751 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2752 nphy->txiqlocal_bestc);
2753 for (i = 0; i < 4; i++)
2755 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2757 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2758 &nphy->txiqlocal_bestc[5]);
2759 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2760 &nphy->txiqlocal_bestc[5]);
2764 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2765 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2766 struct nphy_txgains target, u8 type, bool debug)
2768 struct b43_phy_n *nphy = dev->phy.n;
2773 u16 cur_hpf1, cur_hpf2, cur_lna;
2775 enum ieee80211_band band;
2779 u16 lna[3] = { 3, 3, 1 };
2780 u16 hpf1[3] = { 7, 2, 0 };
2781 u16 hpf2[3] = { 2, 0, 0 };
2785 struct nphy_iqcal_params cal_params[2];
2786 struct nphy_iq_est est;
2788 bool playtone = true;
2791 b43_nphy_stay_in_carrier_search(dev, 1);
2793 if (dev->phy.rev < 2)
2794 b43_nphy_reapply_tx_cal_coeffs(dev);
2795 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2796 for (i = 0; i < 2; i++) {
2797 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2798 cal_gain[i] = cal_params[i].cal_gain;
2800 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2802 for (i = 0; i < 2; i++) {
2804 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2805 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2806 afectl_core = B43_NPHY_AFECTL_C1;
2808 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2809 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2810 afectl_core = B43_NPHY_AFECTL_C2;
2813 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2814 tmp[2] = b43_phy_read(dev, afectl_core);
2815 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2816 tmp[4] = b43_phy_read(dev, rfctl[0]);
2817 tmp[5] = b43_phy_read(dev, rfctl[1]);
2819 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2820 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2821 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2822 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2824 b43_phy_set(dev, afectl_core, 0x0006);
2825 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2827 band = b43_current_band(dev->wl);
2829 if (nphy->rxcalparams & 0xFF000000) {
2830 if (band == IEEE80211_BAND_5GHZ)
2831 b43_phy_write(dev, rfctl[0], 0x140);
2833 b43_phy_write(dev, rfctl[0], 0x110);
2835 if (band == IEEE80211_BAND_5GHZ)
2836 b43_phy_write(dev, rfctl[0], 0x180);
2838 b43_phy_write(dev, rfctl[0], 0x120);
2841 if (band == IEEE80211_BAND_5GHZ)
2842 b43_phy_write(dev, rfctl[1], 0x148);
2844 b43_phy_write(dev, rfctl[1], 0x114);
2846 if (nphy->rxcalparams & 0x10000) {
2847 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2849 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2853 for (j = 0; i < 4; j++) {
2859 if (power[1] > 10000) {
2864 if (power[0] > 10000) {
2874 cur_lna = lna[index];
2875 cur_hpf1 = hpf1[index];
2876 cur_hpf2 = hpf2[index];
2877 cur_hpf += desired - hweight32(power[index]);
2878 cur_hpf = clamp_val(cur_hpf, 0, 10);
2885 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2887 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2889 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2890 b43_nphy_stop_playback(dev);
2893 ret = b43_nphy_tx_tone(dev, 4000,
2894 (nphy->rxcalparams & 0xFFFF),
2898 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2904 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2913 power[i] = ((real + imag) / 1024) + 1;
2915 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2917 b43_nphy_stop_playback(dev);
2924 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2925 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2926 b43_phy_write(dev, rfctl[1], tmp[5]);
2927 b43_phy_write(dev, rfctl[0], tmp[4]);
2928 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2929 b43_phy_write(dev, afectl_core, tmp[2]);
2930 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2936 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2937 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2938 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2940 b43_nphy_stay_in_carrier_search(dev, 0);
2945 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2946 struct nphy_txgains target, u8 type, bool debug)
2951 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2952 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2953 struct nphy_txgains target, u8 type, bool debug)
2955 if (dev->phy.rev >= 3)
2956 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2958 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2963 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2965 int b43_phy_initn(struct b43_wldev *dev)
2967 struct ssb_bus *bus = dev->dev->bus;
2968 struct b43_phy *phy = &dev->phy;
2969 struct b43_phy_n *nphy = phy->n;
2971 struct nphy_txgains target;
2973 enum ieee80211_band tmp2;
2977 bool do_cal = false;
2979 if ((dev->phy.rev >= 3) &&
2980 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2981 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2982 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2984 nphy->deaf_count = 0;
2985 b43_nphy_tables_init(dev);
2986 nphy->crsminpwr_adjusted = false;
2987 nphy->noisevars_adjusted = false;
2989 /* Clear all overrides */
2990 if (dev->phy.rev >= 3) {
2991 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2992 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2993 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2994 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2996 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2998 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2999 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3000 if (dev->phy.rev < 6) {
3001 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3002 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3004 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3005 ~(B43_NPHY_RFSEQMODE_CAOVER |
3006 B43_NPHY_RFSEQMODE_TROVER));
3007 if (dev->phy.rev >= 3)
3008 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3009 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3011 if (dev->phy.rev <= 2) {
3012 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3013 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3014 ~B43_NPHY_BPHY_CTL3_SCALE,
3015 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3017 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3018 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3020 if (bus->sprom.boardflags2_lo & 0x100 ||
3021 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3022 bus->boardinfo.type == 0x8B))
3023 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3025 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3026 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3027 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3028 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3030 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3031 b43_nphy_update_txrx_chain(dev);
3034 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3035 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3038 tmp2 = b43_current_band(dev->wl);
3039 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3040 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3041 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3042 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3043 nphy->papd_epsilon_offset[0] << 7);
3044 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3045 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3046 nphy->papd_epsilon_offset[1] << 7);
3047 b43_nphy_int_pa_set_tx_dig_filters(dev);
3048 } else if (phy->rev >= 5) {
3049 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3052 b43_nphy_workarounds(dev);
3054 /* Reset CCA, in init code it differs a little from standard way */
3055 b43_nphy_bmac_clock_fgc(dev, 1);
3056 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3057 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3058 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3059 b43_nphy_bmac_clock_fgc(dev, 0);
3061 /* TODO N PHY MAC PHY Clock Set with argument 1 */
3063 b43_nphy_pa_override(dev, false);
3064 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3065 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3066 b43_nphy_pa_override(dev, true);
3068 b43_nphy_classifier(dev, 0, 0);
3069 b43_nphy_read_clip_detection(dev, clip);
3070 tx_pwr_state = nphy->txpwrctrl;
3071 /* TODO N PHY TX power control with argument 0
3072 (turning off power control) */
3073 /* TODO Fix the TX Power Settings */
3074 /* TODO N PHY TX Power Control Idle TSSI */
3075 /* TODO N PHY TX Power Control Setup */
3077 if (phy->rev >= 3) {
3080 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3081 b43_ntab_tx_gain_rev0_1_2);
3082 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3083 b43_ntab_tx_gain_rev0_1_2);
3086 if (nphy->phyrxchain != 3)
3087 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3088 if (nphy->mphase_cal_phase_id > 0)
3089 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3091 do_rssi_cal = false;
3092 if (phy->rev >= 3) {
3093 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3094 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3096 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3099 b43_nphy_rssi_cal(dev);
3101 b43_nphy_restore_rssi_cal(dev);
3103 b43_nphy_rssi_cal(dev);
3106 if (!((nphy->measure_hold & 0x6) != 0)) {
3107 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3108 do_cal = (nphy->iqcal_chanspec_2G == 0);
3110 do_cal = (nphy->iqcal_chanspec_5G == 0);
3116 target = b43_nphy_get_tx_gains(dev);
3118 if (nphy->antsel_type == 2)
3119 ;/*TODO NPHY Superswitch Init with argument 1*/
3120 if (nphy->perical != 2) {
3121 b43_nphy_rssi_cal(dev);
3122 if (phy->rev >= 3) {
3123 nphy->cal_orig_pwr_idx[0] =
3124 nphy->txpwrindex[0].index_internal;
3125 nphy->cal_orig_pwr_idx[1] =
3126 nphy->txpwrindex[1].index_internal;
3127 /* TODO N PHY Pre Calibrate TX Gain */
3128 target = b43_nphy_get_tx_gains(dev);
3134 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3135 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3136 b43_nphy_save_cal(dev);
3137 else if (nphy->mphase_cal_phase_id == 0)
3138 ;/* N PHY Periodic Calibration with argument 3 */
3140 b43_nphy_restore_cal(dev);
3143 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3144 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3145 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3146 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3147 if (phy->rev >= 3 && phy->rev <= 6)
3148 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3149 b43_nphy_tx_lp_fbw(dev);
3151 b43_nphy_spur_workaround(dev);
3153 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3157 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3159 struct b43_phy_n *nphy;
3161 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3169 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3171 struct b43_phy *phy = &dev->phy;
3172 struct b43_phy_n *nphy = phy->n;
3174 memset(nphy, 0, sizeof(*nphy));
3176 //TODO init struct b43_phy_n
3179 static void b43_nphy_op_free(struct b43_wldev *dev)
3181 struct b43_phy *phy = &dev->phy;
3182 struct b43_phy_n *nphy = phy->n;
3188 static int b43_nphy_op_init(struct b43_wldev *dev)
3190 return b43_phy_initn(dev);
3193 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3196 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3197 /* OFDM registers are onnly available on A/G-PHYs */
3198 b43err(dev->wl, "Invalid OFDM PHY access at "
3199 "0x%04X on N-PHY\n", offset);
3202 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3203 /* Ext-G registers are only available on G-PHYs */
3204 b43err(dev->wl, "Invalid EXT-G PHY access at "
3205 "0x%04X on N-PHY\n", offset);
3208 #endif /* B43_DEBUG */
3211 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3213 check_phyreg(dev, reg);
3214 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3215 return b43_read16(dev, B43_MMIO_PHY_DATA);
3218 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3220 check_phyreg(dev, reg);
3221 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3222 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3225 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3227 /* Register 1 is a 32-bit register. */
3228 B43_WARN_ON(reg == 1);
3229 /* N-PHY needs 0x100 for read access */
3232 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3233 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3236 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3238 /* Register 1 is a 32-bit register. */
3239 B43_WARN_ON(reg == 1);
3241 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3242 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3245 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3250 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3252 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3256 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3257 unsigned int new_channel)
3259 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3260 if ((new_channel < 1) || (new_channel > 14))
3263 if (new_channel > 200)
3267 return nphy_channel_switch(dev, new_channel);
3270 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3272 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3277 const struct b43_phy_operations b43_phyops_n = {
3278 .allocate = b43_nphy_op_allocate,
3279 .free = b43_nphy_op_free,
3280 .prepare_structs = b43_nphy_op_prepare_structs,
3281 .init = b43_nphy_op_init,
3282 .phy_read = b43_nphy_op_read,
3283 .phy_write = b43_nphy_op_write,
3284 .radio_read = b43_nphy_op_radio_read,
3285 .radio_write = b43_nphy_op_radio_write,
3286 .software_rfkill = b43_nphy_op_software_rfkill,
3287 .switch_analog = b43_nphy_op_switch_analog,
3288 .switch_channel = b43_nphy_op_switch_channel,
3289 .get_default_chan = b43_nphy_op_get_default_chan,
3290 .recalc_txpower = b43_nphy_op_recalc_txpower,
3291 .adjust_txpower = b43_nphy_op_adjust_txpower,