3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
32 #include "tables_nphy.h"
33 #include "radio_2055.h"
34 #include "radio_2056.h"
44 struct nphy_iqcal_params {
62 enum b43_nphy_rf_sequence {
66 B43_RFSEQ_UPDATE_GAINH,
67 B43_RFSEQ_UPDATE_GAINL,
68 B43_RFSEQ_UPDATE_GAINU,
71 enum b43_nphy_rssi_type {
81 /* TODO: reorder functions */
82 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
84 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
85 u8 *events, u8 *delays, u8 length);
86 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
87 enum b43_nphy_rf_sequence seq);
88 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
89 u16 value, u8 core, bool off);
90 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
92 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev);
94 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96 enum ieee80211_band band = b43_current_band(dev->wl);
97 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
98 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
101 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
105 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
109 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
112 return B43_TXPWR_RES_DONE;
115 static void b43_chantab_radio_upload(struct b43_wldev *dev,
116 const struct b43_nphy_channeltab_entry_rev2 *e)
118 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
119 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
120 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
121 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
122 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
124 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
125 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
126 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
127 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
128 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
130 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
131 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
132 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
133 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
134 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
136 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
137 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
138 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
139 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
140 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
142 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
143 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
144 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
145 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
146 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
148 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
149 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
152 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
153 const struct b43_nphy_channeltab_entry_rev3 *e)
155 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
156 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
157 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
158 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
159 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
161 e->radio_syn_pll_loopfilter1);
162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
163 e->radio_syn_pll_loopfilter2);
164 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
165 e->radio_syn_pll_loopfilter3);
166 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
167 e->radio_syn_pll_loopfilter4);
168 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
169 e->radio_syn_pll_loopfilter5);
170 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
171 e->radio_syn_reserved_addr27);
172 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
173 e->radio_syn_reserved_addr28);
174 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
175 e->radio_syn_reserved_addr29);
176 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
177 e->radio_syn_logen_vcobuf1);
178 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
179 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
180 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
182 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
183 e->radio_rx0_lnaa_tune);
184 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
185 e->radio_rx0_lnag_tune);
187 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
188 e->radio_tx0_intpaa_boost_tune);
189 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
190 e->radio_tx0_intpag_boost_tune);
191 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
192 e->radio_tx0_pada_boost_tune);
193 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
194 e->radio_tx0_padg_boost_tune);
195 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
196 e->radio_tx0_pgaa_boost_tune);
197 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
198 e->radio_tx0_pgag_boost_tune);
199 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
200 e->radio_tx0_mixa_boost_tune);
201 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
202 e->radio_tx0_mixg_boost_tune);
204 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
205 e->radio_rx1_lnaa_tune);
206 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
207 e->radio_rx1_lnag_tune);
209 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
210 e->radio_tx1_intpaa_boost_tune);
211 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
212 e->radio_tx1_intpag_boost_tune);
213 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
214 e->radio_tx1_pada_boost_tune);
215 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
216 e->radio_tx1_padg_boost_tune);
217 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
218 e->radio_tx1_pgaa_boost_tune);
219 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
220 e->radio_tx1_pgag_boost_tune);
221 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
222 e->radio_tx1_mixa_boost_tune);
223 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
224 e->radio_tx1_mixg_boost_tune);
227 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
228 static void b43_radio_2056_setup(struct b43_wldev *dev,
229 const struct b43_nphy_channeltab_entry_rev3 *e)
231 struct ssb_sprom *sprom = dev->dev->bus_sprom;
232 enum ieee80211_band band = b43_current_band(dev->wl);
235 u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
237 B43_WARN_ON(dev->phy.rev < 3);
239 b43_chantab_radio_2056_upload(dev, e);
240 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
242 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
243 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
244 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
245 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
246 if (dev->dev->chip_id == 0x4716) {
247 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
248 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
250 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
251 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
254 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
255 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
256 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
257 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
258 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
259 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
262 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
263 for (i = 0; i < 2; i++) {
264 offset = i ? B2056_TX1 : B2056_TX0;
265 if (dev->phy.rev >= 5) {
267 offset | B2056_TX_PADG_IDAC, 0xcc);
269 if (dev->dev->chip_id == 0x4716) {
285 offset | B2056_TX_INTPAG_IMAIN_STAT,
288 offset | B2056_TX_INTPAG_IAUX_STAT,
291 offset | B2056_TX_INTPAG_CASCBIAS,
294 offset | B2056_TX_INTPAG_BOOST_TUNE,
297 offset | B2056_TX_PGAG_BOOST_TUNE,
300 offset | B2056_TX_PADG_BOOST_TUNE,
303 offset | B2056_TX_MIXG_BOOST_TUNE,
306 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
308 offset | B2056_TX_INTPAG_IMAIN_STAT,
311 offset | B2056_TX_INTPAG_IAUX_STAT,
314 offset | B2056_TX_INTPAG_CASCBIAS,
317 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
319 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
324 /* VCO calibration */
325 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
326 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
327 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
328 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
329 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
333 static void b43_chantab_phy_upload(struct b43_wldev *dev,
334 const struct b43_phy_n_sfo_cfg *e)
336 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
337 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
338 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
339 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
340 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
341 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
344 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
345 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
347 struct b43_phy_n *nphy = dev->phy.n;
350 enum ieee80211_band band = b43_current_band(dev->wl);
352 if (nphy->hang_avoid)
353 b43_nphy_stay_in_carrier_search(dev, 1);
355 nphy->txpwrctrl = enable;
357 if (dev->phy.rev >= 3 &&
358 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
359 (B43_NPHY_TXPCTL_CMD_COEFF |
360 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
361 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
362 /* We disable enabled TX pwr ctl, save it's state */
363 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
364 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
365 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
366 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
369 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
370 for (i = 0; i < 84; i++)
371 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
373 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
374 for (i = 0; i < 84; i++)
375 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
377 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
378 if (dev->phy.rev >= 3)
379 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
380 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
382 if (dev->phy.rev >= 3) {
383 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
384 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
386 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
389 if (dev->phy.rev == 2)
390 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
391 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
392 else if (dev->phy.rev < 2)
393 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
394 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
396 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
397 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
399 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
401 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
404 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
405 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
406 /* wl does useless check for "enable" param here */
407 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
408 if (dev->phy.rev >= 3) {
409 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
411 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
413 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
415 if (band == IEEE80211_BAND_5GHZ) {
416 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
417 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
418 if (dev->phy.rev > 1)
419 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
420 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
424 if (dev->phy.rev >= 3) {
425 if (nphy->tx_pwr_idx[0] != 128 &&
426 nphy->tx_pwr_idx[1] != 128) {
427 /* Recover TX pwr ctl state */
428 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
429 ~B43_NPHY_TXPCTL_CMD_INIT,
430 nphy->tx_pwr_idx[0]);
431 if (dev->phy.rev > 1)
433 B43_NPHY_TXPCTL_INIT,
434 ~0xff, nphy->tx_pwr_idx[1]);
438 if (dev->phy.rev >= 3) {
439 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
440 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
442 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
445 if (dev->phy.rev == 2)
446 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
447 else if (dev->phy.rev < 2)
448 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
450 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
451 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
453 if (b43_nphy_ipa(dev)) {
454 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
455 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
459 if (nphy->hang_avoid)
460 b43_nphy_stay_in_carrier_search(dev, 0);
463 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
464 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
466 struct b43_phy_n *nphy = dev->phy.n;
467 struct ssb_sprom *sprom = dev->dev->bus_sprom;
469 u8 txpi[2], bbmult, i;
470 u16 tmp, radio_gain, dac_gain;
471 u16 freq = dev->phy.channel_freq;
473 /* u32 gaintbl; rev3+ */
475 if (nphy->hang_avoid)
476 b43_nphy_stay_in_carrier_search(dev, 1);
478 if (dev->phy.rev >= 3) {
481 } else if (sprom->revision < 4) {
485 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
486 txpi[0] = sprom->txpid2g[0];
487 txpi[1] = sprom->txpid2g[1];
488 } else if (freq >= 4900 && freq < 5100) {
489 txpi[0] = sprom->txpid5gl[0];
490 txpi[1] = sprom->txpid5gl[1];
491 } else if (freq >= 5100 && freq < 5500) {
492 txpi[0] = sprom->txpid5g[0];
493 txpi[1] = sprom->txpid5g[1];
494 } else if (freq >= 5500) {
495 txpi[0] = sprom->txpid5gh[0];
496 txpi[1] = sprom->txpid5gh[1];
504 for (i = 0; i < 2; i++) {
505 nphy->txpwrindex[i].index_internal = txpi[i];
506 nphy->txpwrindex[i].index_internal_save = txpi[i];
510 for (i = 0; i < 2; i++) {
511 if (dev->phy.rev >= 3) {
512 /* FIXME: support 5GHz */
513 txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
514 radio_gain = (txgain >> 16) & 0x1FFFF;
516 txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
517 radio_gain = (txgain >> 16) & 0x1FFF;
520 dac_gain = (txgain >> 8) & 0x3F;
521 bbmult = txgain & 0xFF;
523 if (dev->phy.rev >= 3) {
525 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
527 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
529 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
533 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
535 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
537 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
539 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
541 tmp = (tmp & 0x00FF) | (bbmult << 8);
543 tmp = (tmp & 0xFF00) | bbmult;
544 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
546 if (b43_nphy_ipa(dev)) {
549 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
550 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, txpi[i]));
551 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
552 b43_phy_set(dev, reg, 0x4);
556 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
558 if (nphy->hang_avoid)
559 b43_nphy_stay_in_carrier_search(dev, 0);
562 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
564 struct b43_phy *phy = &dev->phy;
566 const u32 *table = NULL;
568 TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
575 if (b43_nphy_ipa(dev)) {
576 table = b43_nphy_get_ipa_gain_table(dev);
578 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
580 table = b43_ntab_tx_gain_rev3_5ghz;
582 table = b43_ntab_tx_gain_rev4_5ghz;
584 table = b43_ntab_tx_gain_rev5plus_5ghz;
586 table = b43_ntab_tx_gain_rev3plus_2ghz;
590 table = b43_ntab_tx_gain_rev0_1_2;
592 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
593 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
597 nphy->gmval = (table[0] >> 16) & 0x7000;
599 for (i = 0; i < 128; i++) {
600 pga_gain = (table[i] >> 24) & 0xF;
601 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
602 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
604 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
605 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
607 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
614 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
615 static void b43_radio_2055_setup(struct b43_wldev *dev,
616 const struct b43_nphy_channeltab_entry_rev2 *e)
618 B43_WARN_ON(dev->phy.rev >= 3);
620 b43_chantab_radio_upload(dev, e);
622 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
623 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
624 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
625 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
629 static void b43_radio_init2055_pre(struct b43_wldev *dev)
631 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
632 ~B43_NPHY_RFCTL_CMD_PORFORCE);
633 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
634 B43_NPHY_RFCTL_CMD_CHIP0PU |
635 B43_NPHY_RFCTL_CMD_OEPORFORCE);
636 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
637 B43_NPHY_RFCTL_CMD_PORFORCE);
640 static void b43_radio_init2055_post(struct b43_wldev *dev)
642 struct b43_phy_n *nphy = dev->phy.n;
643 struct ssb_sprom *sprom = dev->dev->bus_sprom;
646 bool workaround = false;
648 if (sprom->revision < 4)
649 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
650 && dev->dev->board_type == 0x46D
651 && dev->dev->board_rev >= 0x41);
654 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
656 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
658 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
659 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
661 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
662 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
663 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
664 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
665 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
667 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
668 for (i = 0; i < 200; i++) {
669 val = b43_radio_read(dev, B2055_CAL_COUT2);
677 b43err(dev->wl, "radio post init timeout\n");
678 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
679 b43_switch_channel(dev, dev->phy.channel);
680 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
681 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
682 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
683 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
684 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
685 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
686 if (!nphy->gain_boost) {
687 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
688 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
690 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
691 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
697 * Initialize a Broadcom 2055 N-radio
698 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
700 static void b43_radio_init2055(struct b43_wldev *dev)
702 b43_radio_init2055_pre(dev);
703 if (b43_status(dev) < B43_STAT_INITIALIZED) {
704 /* Follow wl, not specs. Do not force uploading all regs */
705 b2055_upload_inittab(dev, 0, 0);
707 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
708 b2055_upload_inittab(dev, ghz5, 0);
710 b43_radio_init2055_post(dev);
713 static void b43_radio_init2056_pre(struct b43_wldev *dev)
715 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
716 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
717 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
718 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
719 B43_NPHY_RFCTL_CMD_OEPORFORCE);
720 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
721 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
722 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
723 B43_NPHY_RFCTL_CMD_CHIP0PU);
726 static void b43_radio_init2056_post(struct b43_wldev *dev)
728 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
729 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
730 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
732 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
733 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
734 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
737 Call Radio 2056 Recalibrate
742 * Initialize a Broadcom 2056 N-radio
743 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
745 static void b43_radio_init2056(struct b43_wldev *dev)
747 b43_radio_init2056_pre(dev);
748 b2056_upload_inittabs(dev, 0, 0);
749 b43_radio_init2056_post(dev);
753 * Upload the N-PHY tables.
754 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
756 static void b43_nphy_tables_init(struct b43_wldev *dev)
758 if (dev->phy.rev < 3)
759 b43_nphy_rev0_1_2_tables_init(dev);
761 b43_nphy_rev3plus_tables_init(dev);
764 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
765 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
767 struct b43_phy_n *nphy = dev->phy.n;
768 enum ieee80211_band band;
772 nphy->rfctrl_intc1_save = b43_phy_read(dev,
773 B43_NPHY_RFCTL_INTC1);
774 nphy->rfctrl_intc2_save = b43_phy_read(dev,
775 B43_NPHY_RFCTL_INTC2);
776 band = b43_current_band(dev->wl);
777 if (dev->phy.rev >= 3) {
778 if (band == IEEE80211_BAND_5GHZ)
783 if (band == IEEE80211_BAND_5GHZ)
788 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
789 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
791 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
792 nphy->rfctrl_intc1_save);
793 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
794 nphy->rfctrl_intc2_save);
798 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
799 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
803 if (dev->phy.rev >= 3) {
804 if (b43_nphy_ipa(dev)) {
806 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
807 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
811 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
812 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
816 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
817 static void b43_nphy_reset_cca(struct b43_wldev *dev)
821 b43_phy_force_clock(dev, 1);
822 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
823 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
825 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
826 b43_phy_force_clock(dev, 0);
827 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
830 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
831 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
833 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
835 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
837 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
839 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
841 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
844 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
845 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
847 struct b43_phy_n *nphy = dev->phy.n;
849 bool override = false;
852 if (nphy->txrx_chain == 0) {
855 } else if (nphy->txrx_chain == 1) {
860 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
861 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
865 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
866 B43_NPHY_RFSEQMODE_CAOVER);
868 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
869 ~B43_NPHY_RFSEQMODE_CAOVER);
872 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
873 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
874 u16 samps, u8 time, bool wait)
879 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
880 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
882 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
884 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
886 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
888 for (i = 1000; i; i--) {
889 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
890 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
891 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
892 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
893 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
894 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
895 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
896 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
898 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
899 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
900 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
901 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
902 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
903 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
908 memset(est, 0, sizeof(*est));
911 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
912 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
913 struct b43_phy_n_iq_comp *pcomp)
916 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
917 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
918 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
919 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
921 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
922 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
923 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
924 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
929 /* Ready but not used anywhere */
930 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
931 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
933 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
935 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
937 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
938 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
940 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
941 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
943 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
944 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
945 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
946 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
947 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
948 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
949 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
950 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
953 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
954 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
957 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
959 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
961 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
962 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
964 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
965 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
967 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
968 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
969 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
970 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
971 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
972 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
973 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
974 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
976 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
977 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
979 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
980 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
981 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
982 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
983 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
984 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
985 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
986 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
987 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
990 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
991 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
993 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
994 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
997 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
998 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
999 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1008 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
1009 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
1013 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
1014 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
1020 int iq_nbits, qq_nbits;
1024 struct nphy_iq_est est;
1025 struct b43_phy_n_iq_comp old;
1026 struct b43_phy_n_iq_comp new = { };
1032 b43_nphy_rx_iq_coeffs(dev, false, &old);
1033 b43_nphy_rx_iq_coeffs(dev, true, &new);
1034 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
1037 for (i = 0; i < 2; i++) {
1038 if (i == 0 && (mask & 1)) {
1042 } else if (i == 1 && (mask & 2)) {
1055 iq_nbits = fls(abs(iq));
1058 arsh = iq_nbits - 20;
1060 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
1063 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
1072 brsh = qq_nbits - 11;
1074 b = (qq << (31 - qq_nbits));
1077 b = (qq << (31 - qq_nbits));
1084 b = int_sqrt(b / tmp - a * a) - (1 << 10);
1086 if (i == 0 && (mask & 0x1)) {
1087 if (dev->phy.rev >= 3) {
1094 } else if (i == 1 && (mask & 0x2)) {
1095 if (dev->phy.rev >= 3) {
1108 b43_nphy_rx_iq_coeffs(dev, true, &new);
1111 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
1112 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
1115 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
1117 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
1118 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
1119 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
1120 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
1123 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1124 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
1127 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
1128 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
1131 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1132 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
1134 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
1135 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
1138 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
1139 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1141 if (dev->phy.rev >= 3) {
1144 if (0 /* FIXME */) {
1145 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1146 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1147 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1148 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1151 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1152 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1154 switch (dev->dev->bus_type) {
1155 #ifdef CONFIG_B43_BCMA
1157 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1161 #ifdef CONFIG_B43_SSB
1163 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1169 b43_write32(dev, B43_MMIO_MACCTL,
1170 b43_read32(dev, B43_MMIO_MACCTL) &
1171 ~B43_MACCTL_GPOUTSMSK);
1172 b43_write16(dev, B43_MMIO_GPIO_MASK,
1173 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1174 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1175 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1178 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1179 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1180 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1181 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1186 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1187 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1191 if (dev->dev->core_rev == 16)
1192 b43_mac_suspend(dev);
1194 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1195 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1196 B43_NPHY_CLASSCTL_WAITEDEN);
1198 tmp |= (val & mask);
1199 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1201 if (dev->dev->core_rev == 16)
1202 b43_mac_enable(dev);
1207 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1208 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1210 struct b43_phy *phy = &dev->phy;
1211 struct b43_phy_n *nphy = phy->n;
1214 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1215 if (nphy->deaf_count++ == 0) {
1216 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1217 b43_nphy_classifier(dev, 0x7, 0);
1218 b43_nphy_read_clip_detection(dev, nphy->clip_state);
1219 b43_nphy_write_clip_detection(dev, clip);
1221 b43_nphy_reset_cca(dev);
1223 if (--nphy->deaf_count == 0) {
1224 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1225 b43_nphy_write_clip_detection(dev, nphy->clip_state);
1230 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1231 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1233 struct b43_phy_n *nphy = dev->phy.n;
1236 if (nphy->hang_avoid)
1237 b43_nphy_stay_in_carrier_search(dev, 1);
1239 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1241 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1243 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1245 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1247 if (nphy->bb_mult_save & 0x80000000) {
1248 tmp = nphy->bb_mult_save & 0xFFFF;
1249 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1250 nphy->bb_mult_save = 0;
1253 if (nphy->hang_avoid)
1254 b43_nphy_stay_in_carrier_search(dev, 0);
1257 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1258 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1260 struct b43_phy_n *nphy = dev->phy.n;
1262 u8 channel = dev->phy.channel;
1263 int tone[2] = { 57, 58 };
1264 u32 noise[2] = { 0x3FF, 0x3FF };
1266 B43_WARN_ON(dev->phy.rev < 3);
1268 if (nphy->hang_avoid)
1269 b43_nphy_stay_in_carrier_search(dev, 1);
1271 if (nphy->gband_spurwar_en) {
1272 /* TODO: N PHY Adjust Analog Pfbw (7) */
1273 if (channel == 11 && dev->phy.is_40mhz)
1274 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1276 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1277 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1280 if (nphy->aband_spurwar_en) {
1281 if (channel == 54) {
1284 } else if (channel == 38 || channel == 102 || channel == 118) {
1285 if (0 /* FIXME */) {
1292 } else if (channel == 134) {
1295 } else if (channel == 151) {
1298 } else if (channel == 153 || channel == 161) {
1306 if (!tone[0] && !noise[0])
1307 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1309 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1312 if (nphy->hang_avoid)
1313 b43_nphy_stay_in_carrier_search(dev, 0);
1316 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1317 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1319 struct b43_phy_n *nphy = dev->phy.n;
1326 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1328 if (nphy->hang_avoid)
1329 b43_nphy_stay_in_carrier_search(dev, 1);
1331 if (nphy->gain_boost) {
1332 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1336 tmp = 40370 - 315 * dev->phy.channel;
1337 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1338 tmp = 23242 - 224 * dev->phy.channel;
1339 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1346 for (i = 0; i < 2; i++) {
1347 if (nphy->elna_gain_config) {
1348 data[0] = 19 + gain[i];
1349 data[1] = 25 + gain[i];
1350 data[2] = 25 + gain[i];
1351 data[3] = 25 + gain[i];
1353 data[0] = lna_gain[0] + gain[i];
1354 data[1] = lna_gain[1] + gain[i];
1355 data[2] = lna_gain[2] + gain[i];
1356 data[3] = lna_gain[3] + gain[i];
1358 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1360 minmax[i] = 23 + gain[i];
1363 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1364 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1365 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1366 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1368 if (nphy->hang_avoid)
1369 b43_nphy_stay_in_carrier_search(dev, 0);
1372 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1373 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1375 struct b43_phy_n *nphy = dev->phy.n;
1376 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1378 /* PHY rev 0, 1, 2 */
1382 u8 rfseq_events[3] = { 6, 8, 7 };
1383 u8 rfseq_delays[3] = { 10, 30, 1 };
1389 struct nphy_gain_ctl_workaround_entry *e;
1390 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1391 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1393 if (dev->phy.rev >= 3) {
1394 /* Prepare values */
1395 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1396 & B43_NPHY_BANDCTL_5GHZ;
1397 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1398 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1399 if (ghz5 && dev->phy.rev >= 5)
1404 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1406 /* Set Clip 2 detect */
1407 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1408 B43_NPHY_C1_CGAINI_CL2DETECT);
1409 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1410 B43_NPHY_C2_CGAINI_CL2DETECT);
1412 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1414 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1416 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1417 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1418 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1419 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1420 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1422 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1424 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1426 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1428 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1429 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1431 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1432 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1433 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1434 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1435 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1436 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1437 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1438 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1439 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1440 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1441 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1442 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1444 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1445 b43_phy_write(dev, 0x2A7, e->init_gain);
1446 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1448 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1450 /* TODO: check defines. Do not match variables names */
1451 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1452 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1453 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1454 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1455 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1456 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1458 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1459 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1460 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1461 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1462 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1463 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1464 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1465 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1466 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1467 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1469 /* Set Clip 2 detect */
1470 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1471 B43_NPHY_C1_CGAINI_CL2DETECT);
1472 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1473 B43_NPHY_C2_CGAINI_CL2DETECT);
1475 /* Set narrowband clip threshold */
1476 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1477 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1479 if (!dev->phy.is_40mhz) {
1480 /* Set dwell lengths */
1481 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1482 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1483 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1484 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1487 /* Set wideband clip 2 threshold */
1488 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1489 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1491 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1492 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1495 if (!dev->phy.is_40mhz) {
1496 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1497 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1498 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1499 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1500 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1501 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1502 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1503 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1506 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1508 if (nphy->gain_boost) {
1509 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1515 code = dev->phy.is_40mhz ? 6 : 7;
1518 /* Set HPVGA2 index */
1519 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1520 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1521 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1522 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1523 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1524 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1526 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1527 /* specs say about 2 loops, but wl does 4 */
1528 for (i = 0; i < 4; i++)
1529 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1530 (code << 8 | 0x7C));
1532 b43_nphy_adjust_lna_gain_table(dev);
1534 if (nphy->elna_gain_config) {
1535 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1536 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1537 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1538 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1539 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1541 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1542 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1543 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1544 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1545 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1547 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1548 /* specs say about 2 loops, but wl does 4 */
1549 for (i = 0; i < 4; i++)
1550 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1551 (code << 8 | 0x74));
1554 if (dev->phy.rev == 2) {
1555 for (i = 0; i < 4; i++) {
1556 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1557 (0x0400 * i) + 0x0020);
1558 for (j = 0; j < 21; j++) {
1559 tmp = j * (i < 2 ? 3 : 1);
1561 B43_NPHY_TABLE_DATALO, tmp);
1566 b43_nphy_set_rf_sequence(dev, 5,
1567 rfseq_events, rfseq_delays, 3);
1568 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1569 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1570 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1572 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1573 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1578 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1580 struct b43_phy_n *nphy = dev->phy.n;
1581 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1584 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1585 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1587 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1589 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1590 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1591 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1596 b43_phy_write(dev, 0x23f, 0x1f8);
1597 b43_phy_write(dev, 0x240, 0x1f8);
1599 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1601 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1603 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1604 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1605 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1606 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1607 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1608 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1610 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1611 b43_phy_write(dev, 0x2AE, 0x000C);
1614 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1615 ARRAY_SIZE(tx2rx_events));
1618 if (b43_nphy_ipa(dev))
1619 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1620 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1621 if (nphy->hw_phyrxchain != 3 &&
1622 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1623 if (b43_nphy_ipa(dev)) {
1624 rx2tx_delays[5] = 59;
1625 rx2tx_delays[6] = 1;
1626 rx2tx_events[7] = 0x1F;
1628 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
1629 ARRAY_SIZE(rx2tx_events));
1632 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1634 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1636 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1638 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1639 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1641 b43_nphy_gain_ctrl_workarounds(dev);
1643 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1644 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1648 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1649 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1650 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1651 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1652 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1653 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1654 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1655 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1656 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1657 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1658 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1659 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1661 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1663 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1664 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1665 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1666 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1670 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1671 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1672 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1674 if (dev->phy.rev == 4 &&
1675 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1676 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1678 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1682 b43_phy_write(dev, 0x224, 0x03eb);
1683 b43_phy_write(dev, 0x225, 0x03eb);
1684 b43_phy_write(dev, 0x226, 0x0341);
1685 b43_phy_write(dev, 0x227, 0x0341);
1686 b43_phy_write(dev, 0x228, 0x042b);
1687 b43_phy_write(dev, 0x229, 0x042b);
1688 b43_phy_write(dev, 0x22a, 0x0381);
1689 b43_phy_write(dev, 0x22b, 0x0381);
1690 b43_phy_write(dev, 0x22c, 0x042b);
1691 b43_phy_write(dev, 0x22d, 0x042b);
1692 b43_phy_write(dev, 0x22e, 0x0381);
1693 b43_phy_write(dev, 0x22f, 0x0381);
1696 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1698 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1699 struct b43_phy *phy = &dev->phy;
1700 struct b43_phy_n *nphy = phy->n;
1702 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1703 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1705 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1706 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1708 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1709 nphy->band5g_pwrgain) {
1710 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1711 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1713 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1714 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1717 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1718 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1719 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1720 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1722 if (dev->phy.rev < 2) {
1723 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1724 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1725 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1726 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1727 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1728 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1731 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1732 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1733 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1734 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1736 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
1737 dev->dev->board_type == 0x8B) {
1741 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1742 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1744 b43_nphy_gain_ctrl_workarounds(dev);
1746 if (dev->phy.rev < 2) {
1747 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1748 b43_hf_write(dev, b43_hf_read(dev) |
1750 } else if (dev->phy.rev == 2) {
1751 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1752 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1755 if (dev->phy.rev < 2)
1756 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1757 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1759 /* Set phase track alpha and beta */
1760 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1761 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1762 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1763 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1764 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1765 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1767 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1768 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1769 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1770 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1771 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1773 if (dev->phy.rev == 2)
1774 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1775 B43_NPHY_FINERX2_CGC_DECGC);
1778 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1779 static void b43_nphy_workarounds(struct b43_wldev *dev)
1781 struct b43_phy *phy = &dev->phy;
1782 struct b43_phy_n *nphy = phy->n;
1784 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1785 b43_nphy_classifier(dev, 1, 0);
1787 b43_nphy_classifier(dev, 1, 1);
1789 if (nphy->hang_avoid)
1790 b43_nphy_stay_in_carrier_search(dev, 1);
1792 b43_phy_set(dev, B43_NPHY_IQFLIP,
1793 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1795 if (dev->phy.rev >= 3)
1796 b43_nphy_workarounds_rev3plus(dev);
1798 b43_nphy_workarounds_rev1_2(dev);
1800 if (nphy->hang_avoid)
1801 b43_nphy_stay_in_carrier_search(dev, 0);
1804 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1805 static int b43_nphy_load_samples(struct b43_wldev *dev,
1806 struct b43_c32 *samples, u16 len) {
1807 struct b43_phy_n *nphy = dev->phy.n;
1811 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1813 b43err(dev->wl, "allocation for samples loading failed\n");
1816 if (nphy->hang_avoid)
1817 b43_nphy_stay_in_carrier_search(dev, 1);
1819 for (i = 0; i < len; i++) {
1820 data[i] = (samples[i].i & 0x3FF << 10);
1821 data[i] |= samples[i].q & 0x3FF;
1823 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1826 if (nphy->hang_avoid)
1827 b43_nphy_stay_in_carrier_search(dev, 0);
1831 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1832 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1836 u16 bw, len, rot, angle;
1837 struct b43_c32 *samples;
1840 bw = (dev->phy.is_40mhz) ? 40 : 20;
1844 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1849 if (dev->phy.is_40mhz)
1855 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1857 b43err(dev->wl, "allocation for samples generation failed\n");
1860 rot = (((freq * 36) / bw) << 16) / 100;
1863 for (i = 0; i < len; i++) {
1864 samples[i] = b43_cordic(angle);
1866 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1867 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1870 i = b43_nphy_load_samples(dev, samples, len);
1872 return (i < 0) ? 0 : len;
1875 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1876 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1877 u16 wait, bool iqmode, bool dac_test)
1879 struct b43_phy_n *nphy = dev->phy.n;
1884 if (nphy->hang_avoid)
1885 b43_nphy_stay_in_carrier_search(dev, true);
1887 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1888 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1889 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1892 if (!dev->phy.is_40mhz)
1896 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1898 if (nphy->hang_avoid)
1899 b43_nphy_stay_in_carrier_search(dev, false);
1901 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1903 if (loops != 0xFFFF)
1904 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1906 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1908 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1910 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1912 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1914 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1915 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1918 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1920 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1922 for (i = 0; i < 100; i++) {
1923 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1930 b43err(dev->wl, "run samples timeout\n");
1932 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1936 * Transmits a known value for LO calibration
1937 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1939 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1940 bool iqmode, bool dac_test)
1942 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1945 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1949 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1950 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1952 struct b43_phy_n *nphy = dev->phy.n;
1955 u32 cur_real, cur_imag, real_part, imag_part;
1959 if (nphy->hang_avoid)
1960 b43_nphy_stay_in_carrier_search(dev, true);
1962 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1964 for (i = 0; i < 2; i++) {
1965 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1966 (buffer[i * 2 + 1] & 0x3FF);
1967 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1968 (((i + 26) << 10) | 320));
1969 for (j = 0; j < 128; j++) {
1970 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1971 ((tmp >> 16) & 0xFFFF));
1972 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1977 for (i = 0; i < 2; i++) {
1978 tmp = buffer[5 + i];
1979 real_part = (tmp >> 8) & 0xFF;
1980 imag_part = (tmp & 0xFF);
1981 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1982 (((i + 26) << 10) | 448));
1984 if (dev->phy.rev >= 3) {
1985 cur_real = real_part;
1986 cur_imag = imag_part;
1987 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1990 for (j = 0; j < 128; j++) {
1991 if (dev->phy.rev < 3) {
1992 cur_real = (real_part * loscale[j] + 128) >> 8;
1993 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1994 tmp = ((cur_real & 0xFF) << 8) |
1997 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1998 ((tmp >> 16) & 0xFFFF));
1999 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2004 if (dev->phy.rev >= 3) {
2005 b43_shm_write16(dev, B43_SHM_SHARED,
2006 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
2007 b43_shm_write16(dev, B43_SHM_SHARED,
2008 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
2011 if (nphy->hang_avoid)
2012 b43_nphy_stay_in_carrier_search(dev, false);
2015 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
2016 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
2017 u8 *events, u8 *delays, u8 length)
2019 struct b43_phy_n *nphy = dev->phy.n;
2021 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
2022 u16 offset1 = cmd << 4;
2023 u16 offset2 = offset1 + 0x80;
2025 if (nphy->hang_avoid)
2026 b43_nphy_stay_in_carrier_search(dev, true);
2028 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
2029 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
2031 for (i = length; i < 16; i++) {
2032 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
2033 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
2036 if (nphy->hang_avoid)
2037 b43_nphy_stay_in_carrier_search(dev, false);
2040 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
2041 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
2042 enum b43_nphy_rf_sequence seq)
2044 static const u16 trigger[] = {
2045 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
2046 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
2047 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
2048 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
2049 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
2050 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
2053 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
2055 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
2057 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2058 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
2059 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
2060 for (i = 0; i < 200; i++) {
2061 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
2065 b43err(dev->wl, "RF sequence status timeout\n");
2067 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
2070 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
2071 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
2072 u16 value, u8 core, bool off)
2075 u8 index = fls(field);
2076 u8 addr, en_addr, val_addr;
2077 /* we expect only one bit set */
2078 B43_WARN_ON(field & (~(1 << (index - 1))));
2080 if (dev->phy.rev >= 3) {
2081 const struct nphy_rf_control_override_rev3 *rf_ctrl;
2082 for (i = 0; i < 2; i++) {
2083 if (index == 0 || index == 16) {
2085 "Unsupported RF Ctrl Override call\n");
2089 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
2090 en_addr = B43_PHY_N((i == 0) ?
2091 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
2092 val_addr = B43_PHY_N((i == 0) ?
2093 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
2096 b43_phy_mask(dev, en_addr, ~(field));
2097 b43_phy_mask(dev, val_addr,
2098 ~(rf_ctrl->val_mask));
2100 if (core == 0 || ((1 << core) & i) != 0) {
2101 b43_phy_set(dev, en_addr, field);
2102 b43_phy_maskset(dev, val_addr,
2103 ~(rf_ctrl->val_mask),
2104 (value << rf_ctrl->val_shift));
2109 const struct nphy_rf_control_override_rev2 *rf_ctrl;
2111 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
2114 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
2117 for (i = 0; i < 2; i++) {
2118 if (index <= 1 || index == 16) {
2120 "Unsupported RF Ctrl Override call\n");
2124 if (index == 2 || index == 10 ||
2125 (index >= 13 && index <= 15)) {
2129 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
2130 addr = B43_PHY_N((i == 0) ?
2131 rf_ctrl->addr0 : rf_ctrl->addr1);
2133 if ((core & (1 << i)) != 0)
2134 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
2135 (value << rf_ctrl->shift));
2137 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2138 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2139 B43_NPHY_RFCTL_CMD_START);
2141 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
2146 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
2147 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
2153 B43_WARN_ON(dev->phy.rev < 3);
2154 B43_WARN_ON(field > 4);
2156 for (i = 0; i < 2; i++) {
2157 if ((core == 1 && i == 1) || (core == 2 && !i))
2161 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
2162 b43_phy_mask(dev, reg, 0xFBFF);
2166 b43_phy_write(dev, reg, 0);
2167 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2171 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
2172 0xFC3F, (value << 6));
2173 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
2175 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2176 B43_NPHY_RFCTL_CMD_START);
2177 for (j = 0; j < 100; j++) {
2178 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
2186 "intc override timeout\n");
2187 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
2190 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
2191 0xFC3F, (value << 6));
2192 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
2194 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2195 B43_NPHY_RFCTL_CMD_RXTX);
2196 for (j = 0; j < 100; j++) {
2197 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2205 "intc override timeout\n");
2206 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2211 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2218 b43_phy_maskset(dev, reg, ~tmp, val);
2221 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2228 b43_phy_maskset(dev, reg, ~tmp, val);
2231 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2238 b43_phy_maskset(dev, reg, ~tmp, val);
2244 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2245 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2251 for (i = 0; i < 16; i++) {
2252 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2256 for (i = 0; i < 16; i++) {
2257 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2260 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2263 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2264 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2265 s8 offset, u8 core, u8 rail,
2266 enum b43_nphy_rssi_type type)
2269 bool core1or5 = (core == 1) || (core == 5);
2270 bool core2or5 = (core == 2) || (core == 5);
2272 offset = clamp_val(offset, -32, 31);
2273 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2275 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2276 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2277 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2278 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2279 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2280 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2281 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2282 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2284 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2285 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2286 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2287 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2288 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2289 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2290 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2291 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2293 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2294 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2295 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2296 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2297 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2298 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2299 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2300 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2302 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2303 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2304 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2305 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2306 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2307 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2308 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2309 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2311 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2312 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2313 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2314 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2315 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2316 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2317 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2318 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2320 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2321 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2322 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2323 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2325 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2326 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2327 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2328 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2331 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2344 val = (val << 12) | (val << 14);
2345 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2346 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2349 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2351 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2356 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2358 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2359 ~(B43_NPHY_RFCTL_CMD_RXEN |
2360 B43_NPHY_RFCTL_CMD_CORESEL));
2361 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2366 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2367 ~B43_NPHY_RFCTL_CMD_START);
2369 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2372 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2374 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2375 ~(B43_NPHY_RFCTL_CMD_RXEN |
2376 B43_NPHY_RFCTL_CMD_CORESEL),
2377 (B43_NPHY_RFCTL_CMD_RXEN |
2378 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2379 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2384 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2385 B43_NPHY_RFCTL_CMD_START);
2387 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2392 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2398 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2399 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2400 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2401 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2402 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2403 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2404 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2405 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2407 for (i = 0; i < 2; i++) {
2408 if ((code == 1 && i == 1) || (code == 2 && !i))
2412 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2413 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2417 B43_NPHY_AFECTL_C1 :
2419 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2422 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2423 B43_NPHY_RFCTL_LUT_TRSW_UP2;
2424 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2427 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2432 b43_phy_set(dev, reg, val);
2435 B43_NPHY_TXF_40CO_B1S0 :
2436 B43_NPHY_TXF_40CO_B32S1;
2437 b43_phy_set(dev, reg, 0x0020);
2447 B43_NPHY_AFECTL_C1 :
2450 b43_phy_maskset(dev, reg, 0xFCFF, val);
2451 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2453 if (type != 3 && type != 6) {
2454 enum ieee80211_band band =
2455 b43_current_band(dev->wl);
2457 if (b43_nphy_ipa(dev))
2458 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2461 reg = (i == 0) ? 0x2000 : 0x3000;
2462 reg |= B2055_PADDRV;
2463 b43_radio_write16(dev, reg, val);
2466 B43_NPHY_AFECTL_OVER1 :
2467 B43_NPHY_AFECTL_OVER;
2468 b43_phy_set(dev, reg, 0x0200);
2475 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2476 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2478 if (dev->phy.rev >= 3)
2479 b43_nphy_rev3_rssi_select(dev, code, type);
2481 b43_nphy_rev2_rssi_select(dev, code, type);
2484 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2485 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2488 for (i = 0; i < 2; i++) {
2491 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2493 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2496 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2498 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2499 0xFC, buf[2 * i + 1]);
2503 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2506 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2507 0xF3, buf[2 * i + 1] << 2);
2512 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2513 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2518 u16 save_regs_phy[9];
2521 if (dev->phy.rev >= 3) {
2522 save_regs_phy[0] = b43_phy_read(dev,
2523 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2524 save_regs_phy[1] = b43_phy_read(dev,
2525 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2526 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2527 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2528 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2529 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2530 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2531 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2532 save_regs_phy[8] = 0;
2534 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2535 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2536 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2537 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2538 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2539 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2540 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2541 save_regs_phy[7] = 0;
2542 save_regs_phy[8] = 0;
2545 b43_nphy_rssi_select(dev, 5, type);
2547 if (dev->phy.rev < 2) {
2548 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2549 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2552 for (i = 0; i < 4; i++)
2555 for (i = 0; i < nsamp; i++) {
2556 if (dev->phy.rev < 2) {
2557 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2558 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2560 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2561 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2564 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2565 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2566 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2567 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2569 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2570 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2572 if (dev->phy.rev < 2)
2573 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2575 if (dev->phy.rev >= 3) {
2576 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2578 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2580 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2581 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2582 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2583 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2584 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2585 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2587 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2588 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2589 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2590 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2591 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2592 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2593 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2599 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2600 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2605 u16 class, override;
2606 u8 regs_save_radio[2];
2607 u16 regs_save_phy[2];
2614 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2615 s32 results_min[4] = { };
2616 u8 vcm_final[4] = { };
2617 s32 results[4][4] = { };
2618 s32 miniq[4][2] = { };
2623 } else if (type < 2) {
2631 class = b43_nphy_classifier(dev, 0, 0);
2632 b43_nphy_classifier(dev, 7, 4);
2633 b43_nphy_read_clip_detection(dev, clip_state);
2634 b43_nphy_write_clip_detection(dev, clip_off);
2636 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2641 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2642 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2643 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2644 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2646 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2647 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2648 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2649 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2651 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2652 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2653 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2654 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2655 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2656 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2658 b43_nphy_rssi_select(dev, 5, type);
2659 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2660 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2662 for (i = 0; i < 4; i++) {
2664 for (j = 0; j < 4; j++)
2667 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2668 b43_nphy_poll_rssi(dev, type, results[i], 8);
2670 for (j = 0; j < 2; j++)
2671 miniq[i][j] = min(results[i][2 * j],
2672 results[i][2 * j + 1]);
2675 for (i = 0; i < 4; i++) {
2680 for (j = 0; j < 4; j++) {
2682 curr = abs(results[j][i]);
2684 curr = abs(miniq[j][i / 2] - code * 8);
2691 if (results[j][i] < minpoll)
2692 minpoll = results[j][i];
2694 results_min[i] = minpoll;
2695 vcm_final[i] = minvcm;
2699 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2701 for (i = 0; i < 4; i++) {
2702 offset[i] = (code * 8) - results[vcm_final[i]][i];
2705 offset[i] = -((abs(offset[i]) + 4) / 8);
2707 offset[i] = (offset[i] + 4) / 8;
2709 if (results_min[i] == 248)
2710 offset[i] = code - 32;
2712 core = (i / 2) ? 2 : 1;
2713 rail = (i % 2) ? 1 : 0;
2715 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2719 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2720 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2724 b43_nphy_rssi_select(dev, 1, 2);
2727 b43_nphy_rssi_select(dev, 1, 0);
2730 b43_nphy_rssi_select(dev, 1, 1);
2733 b43_nphy_rssi_select(dev, 1, 1);
2739 b43_nphy_rssi_select(dev, 2, 2);
2742 b43_nphy_rssi_select(dev, 2, 0);
2745 b43_nphy_rssi_select(dev, 2, 1);
2749 b43_nphy_rssi_select(dev, 0, type);
2751 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2752 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2753 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2754 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2756 b43_nphy_classifier(dev, 7, class);
2757 b43_nphy_write_clip_detection(dev, clip_state);
2758 /* Specs don't say about reset here, but it makes wl and b43 dumps
2759 identical, it really seems wl performs this */
2760 b43_nphy_reset_cca(dev);
2763 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2764 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2771 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2773 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2775 if (dev->phy.rev >= 3) {
2776 b43_nphy_rev3_rssi_cal(dev);
2778 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2779 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2780 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2785 * Restore RSSI Calibration
2786 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2788 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2790 struct b43_phy_n *nphy = dev->phy.n;
2792 u16 *rssical_radio_regs = NULL;
2793 u16 *rssical_phy_regs = NULL;
2795 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2796 if (!nphy->rssical_chanspec_2G.center_freq)
2798 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2799 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2801 if (!nphy->rssical_chanspec_5G.center_freq)
2803 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2804 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2807 /* TODO use some definitions */
2808 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2809 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2811 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2812 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2813 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2814 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2816 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2817 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2818 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2819 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2821 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2822 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2823 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2824 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2827 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2828 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2830 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2831 if (dev->phy.rev >= 6) {
2832 if (dev->dev->chip_id == 47162)
2833 return txpwrctrl_tx_gain_ipa_rev5;
2834 return txpwrctrl_tx_gain_ipa_rev6;
2835 } else if (dev->phy.rev >= 5) {
2836 return txpwrctrl_tx_gain_ipa_rev5;
2838 return txpwrctrl_tx_gain_ipa;
2841 return txpwrctrl_tx_gain_ipa_5g;
2845 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2846 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2848 struct b43_phy_n *nphy = dev->phy.n;
2849 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2853 if (dev->phy.rev >= 3) {
2854 for (i = 0; i < 2; i++) {
2855 tmp = (i == 0) ? 0x2000 : 0x3000;
2858 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2859 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2860 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2861 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2862 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2863 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2864 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2865 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2866 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2867 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2868 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2870 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2871 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2872 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2873 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2874 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2875 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2876 if (nphy->ipa5g_on) {
2877 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2878 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2880 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2881 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2883 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2885 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2886 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2887 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2888 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2889 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2890 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2891 if (nphy->ipa2g_on) {
2892 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2893 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2894 (dev->phy.rev < 5) ? 0x11 : 0x01);
2896 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2897 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2900 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2901 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2902 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2905 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2906 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2908 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2909 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2911 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2912 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2914 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2915 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2917 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2918 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2920 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2921 B43_NPHY_BANDCTL_5GHZ)) {
2922 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2923 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2925 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2926 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2929 if (dev->phy.rev < 2) {
2930 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2931 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2933 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2934 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2939 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2940 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2941 struct nphy_txgains target,
2942 struct nphy_iqcal_params *params)
2947 if (dev->phy.rev >= 3) {
2948 params->txgm = target.txgm[core];
2949 params->pga = target.pga[core];
2950 params->pad = target.pad[core];
2951 params->ipa = target.ipa[core];
2952 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2953 (params->pad << 4) | (params->ipa);
2954 for (j = 0; j < 5; j++)
2955 params->ncorr[j] = 0x79;
2957 gain = (target.pad[core]) | (target.pga[core] << 4) |
2958 (target.txgm[core] << 8);
2960 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2962 for (i = 0; i < 9; i++)
2963 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2967 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2968 params->pga = tbl_iqcal_gainparams[indx][i][2];
2969 params->pad = tbl_iqcal_gainparams[indx][i][3];
2970 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2972 for (j = 0; j < 4; j++)
2973 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2977 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2978 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2980 struct b43_phy_n *nphy = dev->phy.n;
2984 u16 tmp = nphy->txcal_bbmult;
2989 for (i = 0; i < 18; i++) {
2990 scale = (ladder_lo[i].percent * tmp) / 100;
2991 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2992 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2994 scale = (ladder_iq[i].percent * tmp) / 100;
2995 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2996 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3000 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3001 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3004 for (i = 0; i < 15; i++)
3005 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3006 tbl_tx_filter_coef_rev4[2][i]);
3009 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3010 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3013 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
3014 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
3016 for (i = 0; i < 3; i++)
3017 for (j = 0; j < 15; j++)
3018 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3019 tbl_tx_filter_coef_rev4[i][j]);
3021 if (dev->phy.is_40mhz) {
3022 for (j = 0; j < 15; j++)
3023 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3024 tbl_tx_filter_coef_rev4[3][j]);
3025 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3026 for (j = 0; j < 15; j++)
3027 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3028 tbl_tx_filter_coef_rev4[5][j]);
3031 if (dev->phy.channel == 14)
3032 for (j = 0; j < 15; j++)
3033 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3034 tbl_tx_filter_coef_rev4[6][j]);
3037 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3038 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3040 struct b43_phy_n *nphy = dev->phy.n;
3043 struct nphy_txgains target;
3044 const u32 *table = NULL;
3046 if (!nphy->txpwrctrl) {
3049 if (nphy->hang_avoid)
3050 b43_nphy_stay_in_carrier_search(dev, true);
3051 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
3052 if (nphy->hang_avoid)
3053 b43_nphy_stay_in_carrier_search(dev, false);
3055 for (i = 0; i < 2; ++i) {
3056 if (dev->phy.rev >= 3) {
3057 target.ipa[i] = curr_gain[i] & 0x000F;
3058 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
3059 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3060 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3062 target.ipa[i] = curr_gain[i] & 0x0003;
3063 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3064 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3065 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3071 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3072 B43_NPHY_TXPCTL_STAT_BIDX) >>
3073 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3074 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3075 B43_NPHY_TXPCTL_STAT_BIDX) >>
3076 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3078 for (i = 0; i < 2; ++i) {
3079 if (dev->phy.rev >= 3) {
3080 enum ieee80211_band band =
3081 b43_current_band(dev->wl);
3083 if (b43_nphy_ipa(dev)) {
3084 table = b43_nphy_get_ipa_gain_table(dev);
3086 if (band == IEEE80211_BAND_5GHZ) {
3087 if (dev->phy.rev == 3)
3088 table = b43_ntab_tx_gain_rev3_5ghz;
3089 else if (dev->phy.rev == 4)
3090 table = b43_ntab_tx_gain_rev4_5ghz;
3092 table = b43_ntab_tx_gain_rev5plus_5ghz;
3094 table = b43_ntab_tx_gain_rev3plus_2ghz;
3098 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3099 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3100 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3101 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3103 table = b43_ntab_tx_gain_rev0_1_2;
3105 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3106 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3107 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3108 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3116 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3117 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3119 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3121 if (dev->phy.rev >= 3) {
3122 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3123 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3124 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3125 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3126 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3127 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3128 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3129 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3130 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3131 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3132 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3133 b43_nphy_reset_cca(dev);
3135 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3136 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3137 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3138 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3139 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3140 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3141 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3145 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3146 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3148 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3151 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3152 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3153 if (dev->phy.rev >= 3) {
3154 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3155 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3157 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3159 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3161 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3163 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3165 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3166 b43_phy_mask(dev, B43_NPHY_BBCFG,
3167 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3169 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3171 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3173 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3175 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3176 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3177 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3179 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3180 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3181 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3183 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3184 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3185 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3186 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3188 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3189 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3190 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3192 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3193 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3196 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3197 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3200 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3201 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3202 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3203 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3207 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3208 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3212 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3213 static void b43_nphy_save_cal(struct b43_wldev *dev)
3215 struct b43_phy_n *nphy = dev->phy.n;
3217 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3218 u16 *txcal_radio_regs = NULL;
3219 struct b43_chanspec *iqcal_chanspec;
3222 if (nphy->hang_avoid)
3223 b43_nphy_stay_in_carrier_search(dev, 1);
3225 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3226 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3227 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3228 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3229 table = nphy->cal_cache.txcal_coeffs_2G;
3231 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3232 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3233 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3234 table = nphy->cal_cache.txcal_coeffs_5G;
3237 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3238 /* TODO use some definitions */
3239 if (dev->phy.rev >= 3) {
3240 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3241 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3242 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3243 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3244 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3245 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3246 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3247 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3249 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3250 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3251 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3252 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3254 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3255 iqcal_chanspec->channel_type = dev->phy.channel_type;
3256 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3258 if (nphy->hang_avoid)
3259 b43_nphy_stay_in_carrier_search(dev, 0);
3262 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3263 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3265 struct b43_phy_n *nphy = dev->phy.n;
3272 u16 *txcal_radio_regs = NULL;
3273 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3275 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3276 if (!nphy->iqcal_chanspec_2G.center_freq)
3278 table = nphy->cal_cache.txcal_coeffs_2G;
3279 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3281 if (!nphy->iqcal_chanspec_5G.center_freq)
3283 table = nphy->cal_cache.txcal_coeffs_5G;
3284 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3287 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3289 for (i = 0; i < 4; i++) {
3290 if (dev->phy.rev >= 3)
3296 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3297 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3298 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3300 if (dev->phy.rev < 2)
3301 b43_nphy_tx_iq_workaround(dev);
3303 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3304 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3305 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3307 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3308 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3311 /* TODO use some definitions */
3312 if (dev->phy.rev >= 3) {
3313 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3314 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3315 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3316 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3317 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3318 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3319 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3320 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3322 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3323 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3324 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3325 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3327 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3330 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3331 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3332 struct nphy_txgains target,
3333 bool full, bool mphase)
3335 struct b43_phy_n *nphy = dev->phy.n;
3341 u16 tmp, core, type, count, max, numb, last = 0, cmd;
3349 struct nphy_iqcal_params params[2];
3350 bool updated[2] = { };
3352 b43_nphy_stay_in_carrier_search(dev, true);
3354 if (dev->phy.rev >= 4) {
3355 avoid = nphy->hang_avoid;
3356 nphy->hang_avoid = 0;
3359 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3361 for (i = 0; i < 2; i++) {
3362 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
3363 gain[i] = params[i].cal_gain;
3366 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3368 b43_nphy_tx_cal_radio_setup(dev);
3369 b43_nphy_tx_cal_phy_setup(dev);
3371 phy6or5x = dev->phy.rev >= 6 ||
3372 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3373 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3375 if (dev->phy.is_40mhz) {
3376 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3377 tbl_tx_iqlo_cal_loft_ladder_40);
3378 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3379 tbl_tx_iqlo_cal_iqimb_ladder_40);
3381 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3382 tbl_tx_iqlo_cal_loft_ladder_20);
3383 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3384 tbl_tx_iqlo_cal_iqimb_ladder_20);
3388 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3390 if (!dev->phy.is_40mhz)
3395 if (nphy->mphase_cal_phase_id > 2)
3396 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3397 0xFFFF, 0, true, false);
3399 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3402 if (nphy->mphase_cal_phase_id > 2) {
3403 table = nphy->mphase_txcal_bestcoeffs;
3405 if (dev->phy.rev < 3)
3408 if (!full && nphy->txiqlocal_coeffsvalid) {
3409 table = nphy->txiqlocal_bestc;
3411 if (dev->phy.rev < 3)
3415 if (dev->phy.rev >= 3) {
3416 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3417 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3419 table = tbl_tx_iqlo_cal_startcoefs;
3420 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3425 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3428 if (dev->phy.rev >= 3)
3429 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3431 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3433 if (dev->phy.rev >= 3)
3434 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3436 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3440 count = nphy->mphase_txcal_cmdidx;
3442 (u16)(count + nphy->mphase_txcal_numcmds));
3448 for (; count < numb; count++) {
3450 if (dev->phy.rev >= 3)
3451 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3453 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3455 if (dev->phy.rev >= 3)
3456 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3458 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3461 core = (cmd & 0x3000) >> 12;
3462 type = (cmd & 0x0F00) >> 8;
3464 if (phy6or5x && updated[core] == 0) {
3465 b43_nphy_update_tx_cal_ladder(dev, core);
3469 tmp = (params[core].ncorr[type] << 8) | 0x66;
3470 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3472 if (type == 1 || type == 3 || type == 4) {
3473 buffer[0] = b43_ntab_read(dev,
3474 B43_NTAB16(15, 69 + core));
3475 diq_start = buffer[0];
3477 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3481 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3482 for (i = 0; i < 2000; i++) {
3483 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3489 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3491 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3494 if (type == 1 || type == 3 || type == 4)
3495 buffer[0] = diq_start;
3499 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3501 last = (dev->phy.rev < 3) ? 6 : 7;
3503 if (!mphase || nphy->mphase_cal_phase_id == last) {
3504 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3505 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3506 if (dev->phy.rev < 3) {
3512 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3514 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3516 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3518 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3521 if (dev->phy.rev < 3)
3523 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3524 nphy->txiqlocal_bestc);
3525 nphy->txiqlocal_coeffsvalid = true;
3526 nphy->txiqlocal_chanspec.center_freq =
3527 dev->phy.channel_freq;
3528 nphy->txiqlocal_chanspec.channel_type =
3529 dev->phy.channel_type;
3532 if (dev->phy.rev < 3)
3534 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3535 nphy->mphase_txcal_bestcoeffs);
3538 b43_nphy_stop_playback(dev);
3539 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3542 b43_nphy_tx_cal_phy_cleanup(dev);
3543 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3545 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3546 b43_nphy_tx_iq_workaround(dev);
3548 if (dev->phy.rev >= 4)
3549 nphy->hang_avoid = avoid;
3551 b43_nphy_stay_in_carrier_search(dev, false);
3556 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3557 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3559 struct b43_phy_n *nphy = dev->phy.n;
3564 if (!nphy->txiqlocal_coeffsvalid ||
3565 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3566 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3569 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3570 for (i = 0; i < 4; i++) {
3571 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3578 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3579 nphy->txiqlocal_bestc);
3580 for (i = 0; i < 4; i++)
3582 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3584 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3585 &nphy->txiqlocal_bestc[5]);
3586 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3587 &nphy->txiqlocal_bestc[5]);
3591 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3592 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3593 struct nphy_txgains target, u8 type, bool debug)
3595 struct b43_phy_n *nphy = dev->phy.n;
3600 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3602 enum ieee80211_band band;
3606 u16 lna[3] = { 3, 3, 1 };
3607 u16 hpf1[3] = { 7, 2, 0 };
3608 u16 hpf2[3] = { 2, 0, 0 };
3612 struct nphy_iqcal_params cal_params[2];
3613 struct nphy_iq_est est;
3615 bool playtone = true;
3618 b43_nphy_stay_in_carrier_search(dev, 1);
3620 if (dev->phy.rev < 2)
3621 b43_nphy_reapply_tx_cal_coeffs(dev);
3622 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3623 for (i = 0; i < 2; i++) {
3624 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3625 cal_gain[i] = cal_params[i].cal_gain;
3627 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3629 for (i = 0; i < 2; i++) {
3631 rfctl[0] = B43_NPHY_RFCTL_INTC1;
3632 rfctl[1] = B43_NPHY_RFCTL_INTC2;
3633 afectl_core = B43_NPHY_AFECTL_C1;
3635 rfctl[0] = B43_NPHY_RFCTL_INTC2;
3636 rfctl[1] = B43_NPHY_RFCTL_INTC1;
3637 afectl_core = B43_NPHY_AFECTL_C2;
3640 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3641 tmp[2] = b43_phy_read(dev, afectl_core);
3642 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3643 tmp[4] = b43_phy_read(dev, rfctl[0]);
3644 tmp[5] = b43_phy_read(dev, rfctl[1]);
3646 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3647 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3648 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3649 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3651 b43_phy_set(dev, afectl_core, 0x0006);
3652 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3654 band = b43_current_band(dev->wl);
3656 if (nphy->rxcalparams & 0xFF000000) {
3657 if (band == IEEE80211_BAND_5GHZ)
3658 b43_phy_write(dev, rfctl[0], 0x140);
3660 b43_phy_write(dev, rfctl[0], 0x110);
3662 if (band == IEEE80211_BAND_5GHZ)
3663 b43_phy_write(dev, rfctl[0], 0x180);
3665 b43_phy_write(dev, rfctl[0], 0x120);
3668 if (band == IEEE80211_BAND_5GHZ)
3669 b43_phy_write(dev, rfctl[1], 0x148);
3671 b43_phy_write(dev, rfctl[1], 0x114);
3673 if (nphy->rxcalparams & 0x10000) {
3674 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3676 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3680 for (j = 0; j < 4; j++) {
3686 if (power[1] > 10000) {
3691 if (power[0] > 10000) {
3701 cur_lna = lna[index];
3702 cur_hpf1 = hpf1[index];
3703 cur_hpf2 = hpf2[index];
3704 cur_hpf += desired - hweight32(power[index]);
3705 cur_hpf = clamp_val(cur_hpf, 0, 10);
3712 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3714 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3716 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3717 b43_nphy_stop_playback(dev);
3720 ret = b43_nphy_tx_tone(dev, 4000,
3721 (nphy->rxcalparams & 0xFFFF),
3725 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3731 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3740 power[i] = ((real + imag) / 1024) + 1;
3742 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3744 b43_nphy_stop_playback(dev);
3751 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3752 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3753 b43_phy_write(dev, rfctl[1], tmp[5]);
3754 b43_phy_write(dev, rfctl[0], tmp[4]);
3755 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3756 b43_phy_write(dev, afectl_core, tmp[2]);
3757 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3763 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3764 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3765 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3767 b43_nphy_stay_in_carrier_search(dev, 0);
3772 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3773 struct nphy_txgains target, u8 type, bool debug)
3778 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3779 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3780 struct nphy_txgains target, u8 type, bool debug)
3782 if (dev->phy.rev >= 3)
3783 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3785 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3788 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3789 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3791 struct b43_phy *phy = &dev->phy;
3792 struct b43_phy_n *nphy = phy->n;
3793 /* u16 buf[16]; it's rev3+ */
3795 nphy->phyrxchain = mask;
3797 if (0 /* FIXME clk */)
3800 b43_mac_suspend(dev);
3802 if (nphy->hang_avoid)
3803 b43_nphy_stay_in_carrier_search(dev, true);
3805 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3806 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3808 if ((mask & 0x3) != 0x3) {
3809 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3810 if (dev->phy.rev >= 3) {
3814 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3815 if (dev->phy.rev >= 3) {
3820 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3822 if (nphy->hang_avoid)
3823 b43_nphy_stay_in_carrier_search(dev, false);
3825 b43_mac_enable(dev);
3830 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3832 int b43_phy_initn(struct b43_wldev *dev)
3834 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3835 struct b43_phy *phy = &dev->phy;
3836 struct b43_phy_n *nphy = phy->n;
3838 struct nphy_txgains target;
3840 enum ieee80211_band tmp2;
3844 bool do_cal = false;
3846 if ((dev->phy.rev >= 3) &&
3847 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3848 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3849 switch (dev->dev->bus_type) {
3850 #ifdef CONFIG_B43_BCMA
3852 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3853 BCMA_CC_CHIPCTL, 0x40);
3856 #ifdef CONFIG_B43_SSB
3858 chipco_set32(&dev->dev->sdev->bus->chipco,
3859 SSB_CHIPCO_CHIPCTL, 0x40);
3864 nphy->deaf_count = 0;
3865 b43_nphy_tables_init(dev);
3866 nphy->crsminpwr_adjusted = false;
3867 nphy->noisevars_adjusted = false;
3869 /* Clear all overrides */
3870 if (dev->phy.rev >= 3) {
3871 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3872 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3873 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3874 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3876 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3878 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3879 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3880 if (dev->phy.rev < 6) {
3881 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3882 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3884 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3885 ~(B43_NPHY_RFSEQMODE_CAOVER |
3886 B43_NPHY_RFSEQMODE_TROVER));
3887 if (dev->phy.rev >= 3)
3888 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3889 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3891 if (dev->phy.rev <= 2) {
3892 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3893 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3894 ~B43_NPHY_BPHY_CTL3_SCALE,
3895 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3897 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3898 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3900 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3901 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3902 dev->dev->board_type == 0x8B))
3903 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3905 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3906 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3907 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3908 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3910 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3911 b43_nphy_update_txrx_chain(dev);
3914 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3915 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3918 tmp2 = b43_current_band(dev->wl);
3919 if (b43_nphy_ipa(dev)) {
3920 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3921 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3922 nphy->papd_epsilon_offset[0] << 7);
3923 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3924 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3925 nphy->papd_epsilon_offset[1] << 7);
3926 b43_nphy_int_pa_set_tx_dig_filters(dev);
3927 } else if (phy->rev >= 5) {
3928 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3931 b43_nphy_workarounds(dev);
3933 /* Reset CCA, in init code it differs a little from standard way */
3934 b43_phy_force_clock(dev, 1);
3935 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3936 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3937 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3938 b43_phy_force_clock(dev, 0);
3940 b43_mac_phy_clock_set(dev, true);
3942 b43_nphy_pa_override(dev, false);
3943 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3944 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3945 b43_nphy_pa_override(dev, true);
3947 b43_nphy_classifier(dev, 0, 0);
3948 b43_nphy_read_clip_detection(dev, clip);
3949 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3950 b43_nphy_bphy_init(dev);
3952 tx_pwr_state = nphy->txpwrctrl;
3953 b43_nphy_tx_power_ctrl(dev, false);
3954 b43_nphy_tx_power_fix(dev);
3955 /* TODO N PHY TX Power Control Idle TSSI */
3956 /* TODO N PHY TX Power Control Setup */
3957 b43_nphy_tx_gain_table_upload(dev);
3959 if (nphy->phyrxchain != 3)
3960 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3961 if (nphy->mphase_cal_phase_id > 0)
3962 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3964 do_rssi_cal = false;
3965 if (phy->rev >= 3) {
3966 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3967 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3969 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3972 b43_nphy_rssi_cal(dev);
3974 b43_nphy_restore_rssi_cal(dev);
3976 b43_nphy_rssi_cal(dev);
3979 if (!((nphy->measure_hold & 0x6) != 0)) {
3980 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3981 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3983 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3989 target = b43_nphy_get_tx_gains(dev);
3991 if (nphy->antsel_type == 2)
3992 b43_nphy_superswitch_init(dev, true);
3993 if (nphy->perical != 2) {
3994 b43_nphy_rssi_cal(dev);
3995 if (phy->rev >= 3) {
3996 nphy->cal_orig_pwr_idx[0] =
3997 nphy->txpwrindex[0].index_internal;
3998 nphy->cal_orig_pwr_idx[1] =
3999 nphy->txpwrindex[1].index_internal;
4000 /* TODO N PHY Pre Calibrate TX Gain */
4001 target = b43_nphy_get_tx_gains(dev);
4003 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4004 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4005 b43_nphy_save_cal(dev);
4006 } else if (nphy->mphase_cal_phase_id == 0)
4007 ;/* N PHY Periodic Calibration with arg 3 */
4009 b43_nphy_restore_cal(dev);
4013 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
4014 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
4015 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4016 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4017 if (phy->rev >= 3 && phy->rev <= 6)
4018 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
4019 b43_nphy_tx_lp_fbw(dev);
4021 b43_nphy_spur_workaround(dev);
4026 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4027 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4029 struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;
4031 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4033 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4034 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4035 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4036 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4037 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4038 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4040 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4041 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4042 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4043 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4044 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4045 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4047 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4048 } else if (dev->dev->chip_id == 0x4716) {
4050 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4051 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4052 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4053 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4054 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4055 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4057 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4058 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4059 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4060 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4061 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4062 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4064 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
4065 } else if (dev->dev->chip_id == 0x4322 || dev->dev->chip_id == 0x4340 ||
4066 dev->dev->chip_id == 0x4341) {
4067 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4068 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4069 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4071 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4073 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4074 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4078 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4081 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
4082 static void b43_nphy_channel_setup(struct b43_wldev *dev,
4083 const struct b43_phy_n_sfo_cfg *e,
4084 struct ieee80211_channel *new_channel)
4086 struct b43_phy *phy = &dev->phy;
4087 struct b43_phy_n *nphy = dev->phy.n;
4088 int ch = new_channel->hw_value;
4094 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4095 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
4096 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4097 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4098 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4099 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4100 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
4101 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
4102 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4103 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4104 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4105 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
4106 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4109 b43_chantab_phy_upload(dev, e);
4111 if (new_channel->hw_value == 14) {
4112 b43_nphy_classifier(dev, 2, 0);
4113 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4115 b43_nphy_classifier(dev, 2, 2);
4116 if (new_channel->band == IEEE80211_BAND_2GHZ)
4117 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4120 if (!nphy->txpwrctrl)
4121 b43_nphy_tx_power_fix(dev);
4123 if (dev->phy.rev < 3)
4124 b43_nphy_adjust_lna_gain_table(dev);
4126 b43_nphy_tx_lp_fbw(dev);
4128 if (dev->phy.rev >= 3 &&
4129 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4131 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4133 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4134 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4136 } else { /* 40MHz */
4137 if (nphy->aband_spurwar_en &&
4138 (ch == 38 || ch == 102 || ch == 118))
4139 avoid = dev->dev->chip_id == 0x4716;
4142 b43_nphy_pmu_spur_avoid(dev, avoid);
4144 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4145 dev->dev->chip_id == 43225) {
4146 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4147 avoid ? 0x5341 : 0x8889);
4148 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4151 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4152 ; /* TODO: reset PLL */
4155 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4157 b43_phy_mask(dev, B43_NPHY_BBCFG,
4158 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4160 b43_nphy_reset_cca(dev);
4162 /* wl sets useless phy_isspuravoid here */
4165 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4168 b43_nphy_spur_workaround(dev);
4171 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
4172 static int b43_nphy_set_channel(struct b43_wldev *dev,
4173 struct ieee80211_channel *channel,
4174 enum nl80211_channel_type channel_type)
4176 struct b43_phy *phy = &dev->phy;
4178 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4179 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4183 if (dev->phy.rev >= 3) {
4184 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4185 channel->center_freq);
4189 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4195 /* Channel is set later in common code, but we need to set it on our
4196 own to let this function's subcalls work properly. */
4197 phy->channel = channel->hw_value;
4198 phy->channel_freq = channel->center_freq;
4200 if (b43_channel_type_is_40mhz(phy->channel_type) !=
4201 b43_channel_type_is_40mhz(channel_type))
4202 ; /* TODO: BMAC BW Set (channel_type) */
4204 if (channel_type == NL80211_CHAN_HT40PLUS)
4205 b43_phy_set(dev, B43_NPHY_RXCTL,
4206 B43_NPHY_RXCTL_BSELU20);
4207 else if (channel_type == NL80211_CHAN_HT40MINUS)
4208 b43_phy_mask(dev, B43_NPHY_RXCTL,
4209 ~B43_NPHY_RXCTL_BSELU20);
4211 if (dev->phy.rev >= 3) {
4212 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4213 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4214 b43_radio_2056_setup(dev, tabent_r3);
4215 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4217 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4218 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4219 b43_radio_2055_setup(dev, tabent_r2);
4220 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4226 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4228 struct b43_phy_n *nphy;
4230 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4238 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4240 struct b43_phy *phy = &dev->phy;
4241 struct b43_phy_n *nphy = phy->n;
4242 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4244 memset(nphy, 0, sizeof(*nphy));
4246 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4247 nphy->spur_avoid = (phy->rev >= 3) ?
4248 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4249 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4250 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4251 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4252 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4253 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4254 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4255 nphy->tx_pwr_idx[0] = 128;
4256 nphy->tx_pwr_idx[1] = 128;
4258 /* Hardware TX power control and 5GHz power gain */
4259 nphy->txpwrctrl = false;
4260 nphy->pwg_gain_5ghz = false;
4261 if (dev->phy.rev >= 3 ||
4262 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4263 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4264 nphy->txpwrctrl = true;
4265 nphy->pwg_gain_5ghz = true;
4266 } else if (sprom->revision >= 4) {
4267 if (dev->phy.rev >= 2 &&
4268 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4269 nphy->txpwrctrl = true;
4270 #ifdef CONFIG_B43_SSB
4271 if (dev->dev->bus_type == B43_BUS_SSB &&
4272 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4273 struct pci_dev *pdev =
4274 dev->dev->sdev->bus->host_pci;
4275 if (pdev->device == 0x4328 ||
4276 pdev->device == 0x432a)
4277 nphy->pwg_gain_5ghz = true;
4280 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4281 nphy->pwg_gain_5ghz = true;
4285 if (dev->phy.rev >= 3) {
4286 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4287 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4291 static void b43_nphy_op_free(struct b43_wldev *dev)
4293 struct b43_phy *phy = &dev->phy;
4294 struct b43_phy_n *nphy = phy->n;
4300 static int b43_nphy_op_init(struct b43_wldev *dev)
4302 return b43_phy_initn(dev);
4305 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4308 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4309 /* OFDM registers are onnly available on A/G-PHYs */
4310 b43err(dev->wl, "Invalid OFDM PHY access at "
4311 "0x%04X on N-PHY\n", offset);
4314 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4315 /* Ext-G registers are only available on G-PHYs */
4316 b43err(dev->wl, "Invalid EXT-G PHY access at "
4317 "0x%04X on N-PHY\n", offset);
4320 #endif /* B43_DEBUG */
4323 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4325 check_phyreg(dev, reg);
4326 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4327 return b43_read16(dev, B43_MMIO_PHY_DATA);
4330 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4332 check_phyreg(dev, reg);
4333 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4334 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4337 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4340 check_phyreg(dev, reg);
4341 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4342 b43_write16(dev, B43_MMIO_PHY_DATA,
4343 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4346 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4348 /* Register 1 is a 32-bit register. */
4349 B43_WARN_ON(reg == 1);
4350 /* N-PHY needs 0x100 for read access */
4353 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4354 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4357 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4359 /* Register 1 is a 32-bit register. */
4360 B43_WARN_ON(reg == 1);
4362 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4363 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4366 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4367 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4370 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4371 b43err(dev->wl, "MAC not suspended\n");
4374 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4375 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4376 if (dev->phy.rev >= 3) {
4377 b43_radio_mask(dev, 0x09, ~0x2);
4379 b43_radio_write(dev, 0x204D, 0);
4380 b43_radio_write(dev, 0x2053, 0);
4381 b43_radio_write(dev, 0x2058, 0);
4382 b43_radio_write(dev, 0x205E, 0);
4383 b43_radio_mask(dev, 0x2062, ~0xF0);
4384 b43_radio_write(dev, 0x2064, 0);
4386 b43_radio_write(dev, 0x304D, 0);
4387 b43_radio_write(dev, 0x3053, 0);
4388 b43_radio_write(dev, 0x3058, 0);
4389 b43_radio_write(dev, 0x305E, 0);
4390 b43_radio_mask(dev, 0x3062, ~0xF0);
4391 b43_radio_write(dev, 0x3064, 0);
4394 if (dev->phy.rev >= 3) {
4395 b43_radio_init2056(dev);
4396 b43_switch_channel(dev, dev->phy.channel);
4398 b43_radio_init2055(dev);
4403 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4404 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4406 u16 override = on ? 0x0 : 0x7FFF;
4407 u16 core = on ? 0xD : 0x00FD;
4409 if (dev->phy.rev >= 3) {
4411 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4412 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4413 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4414 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4416 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4417 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4418 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4419 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4422 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4426 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4427 unsigned int new_channel)
4429 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4430 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4432 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4433 if ((new_channel < 1) || (new_channel > 14))
4436 if (new_channel > 200)
4440 return b43_nphy_set_channel(dev, channel, channel_type);
4443 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4445 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4450 const struct b43_phy_operations b43_phyops_n = {
4451 .allocate = b43_nphy_op_allocate,
4452 .free = b43_nphy_op_free,
4453 .prepare_structs = b43_nphy_op_prepare_structs,
4454 .init = b43_nphy_op_init,
4455 .phy_read = b43_nphy_op_read,
4456 .phy_write = b43_nphy_op_write,
4457 .phy_maskset = b43_nphy_op_maskset,
4458 .radio_read = b43_nphy_op_radio_read,
4459 .radio_write = b43_nphy_op_radio_write,
4460 .software_rfkill = b43_nphy_op_software_rfkill,
4461 .switch_analog = b43_nphy_op_switch_analog,
4462 .switch_channel = b43_nphy_op_switch_channel,
4463 .get_default_chan = b43_nphy_op_get_default_chan,
4464 .recalc_txpower = b43_nphy_op_recalc_txpower,
4465 .adjust_txpower = b43_nphy_op_adjust_txpower,