4 #include <linux/version.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
10 #include <net/ieee80211.h>
11 #include <net/ieee80211softmac.h>
12 #include <asm/atomic.h>
16 #include "bcm43xx_debugfs.h"
17 #include "bcm43xx_leds.h"
18 #include "bcm43xx_sysfs.h"
21 #define PFX KBUILD_MODNAME ": "
23 #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
24 #define BCM43xx_IRQWAIT_MAX_RETRIES 50
26 #define BCM43xx_IO_SIZE 8192
28 /* Active Core PCI Configuration Register. */
29 #define BCM43xx_PCICFG_ACTIVE_CORE 0x80
30 /* SPROM control register. */
31 #define BCM43xx_PCICFG_SPROMCTL 0x88
32 /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
33 #define BCM43xx_PCICFG_ICR 0x94
36 #define BCM43xx_MMIO_DMA1_REASON 0x20
37 #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x24
38 #define BCM43xx_MMIO_DMA2_REASON 0x28
39 #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x2C
40 #define BCM43xx_MMIO_DMA3_REASON 0x30
41 #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x34
42 #define BCM43xx_MMIO_DMA4_REASON 0x38
43 #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x3C
44 #define BCM43xx_MMIO_STATUS_BITFIELD 0x120
45 #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
46 #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
47 #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
48 #define BCM43xx_MMIO_RAM_CONTROL 0x130
49 #define BCM43xx_MMIO_RAM_DATA 0x134
50 #define BCM43xx_MMIO_PS_STATUS 0x140
51 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
52 #define BCM43xx_MMIO_SHM_CONTROL 0x160
53 #define BCM43xx_MMIO_SHM_DATA 0x164
54 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
55 #define BCM43xx_MMIO_XMITSTAT_0 0x170
56 #define BCM43xx_MMIO_XMITSTAT_1 0x174
57 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
58 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
59 #define BCM43xx_MMIO_DMA1_BASE 0x200
60 #define BCM43xx_MMIO_DMA2_BASE 0x220
61 #define BCM43xx_MMIO_DMA3_BASE 0x240
62 #define BCM43xx_MMIO_DMA4_BASE 0x260
63 #define BCM43xx_MMIO_PIO1_BASE 0x300
64 #define BCM43xx_MMIO_PIO2_BASE 0x310
65 #define BCM43xx_MMIO_PIO3_BASE 0x320
66 #define BCM43xx_MMIO_PIO4_BASE 0x330
67 #define BCM43xx_MMIO_PHY_VER 0x3E0
68 #define BCM43xx_MMIO_PHY_RADIO 0x3E2
69 #define BCM43xx_MMIO_ANTENNA 0x3E8
70 #define BCM43xx_MMIO_CHANNEL 0x3F0
71 #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
72 #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
73 #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
74 #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
75 #define BCM43xx_MMIO_PHY_CONTROL 0x3FC
76 #define BCM43xx_MMIO_PHY_DATA 0x3FE
77 #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
78 #define BCM43xx_MMIO_MACFILTER_DATA 0x422
79 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
80 #define BCM43xx_MMIO_GPIO_CONTROL 0x49C
81 #define BCM43xx_MMIO_GPIO_MASK 0x49E
82 #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
83 #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
84 #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
85 #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
86 #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
89 #define BCM43xx_SPROM_BASE 0x1000
90 #define BCM43xx_SPROM_BOARDFLAGS2 0x1c
91 #define BCM43xx_SPROM_IL0MACADDR 0x24
92 #define BCM43xx_SPROM_ET0MACADDR 0x27
93 #define BCM43xx_SPROM_ET1MACADDR 0x2a
94 #define BCM43xx_SPROM_ETHPHY 0x2d
95 #define BCM43xx_SPROM_BOARDREV 0x2e
96 #define BCM43xx_SPROM_PA0B0 0x2f
97 #define BCM43xx_SPROM_PA0B1 0x30
98 #define BCM43xx_SPROM_PA0B2 0x31
99 #define BCM43xx_SPROM_WL0GPIO0 0x32
100 #define BCM43xx_SPROM_WL0GPIO2 0x33
101 #define BCM43xx_SPROM_MAXPWR 0x34
102 #define BCM43xx_SPROM_PA1B0 0x35
103 #define BCM43xx_SPROM_PA1B1 0x36
104 #define BCM43xx_SPROM_PA1B2 0x37
105 #define BCM43xx_SPROM_IDL_TSSI_TGT 0x38
106 #define BCM43xx_SPROM_BOARDFLAGS 0x39
107 #define BCM43xx_SPROM_ANTENNA_GAIN 0x3a
108 #define BCM43xx_SPROM_VERSION 0x3f
110 /* BCM43xx_SPROM_BOARDFLAGS values */
111 #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
112 #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
113 #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
114 #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
115 #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
116 #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
117 #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
118 #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
119 #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
120 #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
121 #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
122 #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
123 #define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
124 #define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
125 #define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
126 #define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
128 /* GPIO register offset, in both ChipCommon and PCI core. */
129 #define BCM43xx_GPIO_CONTROL 0x6c
132 #define BCM43xx_SHM_SHARED 0x0001
133 #define BCM43xx_SHM_WIRELESS 0x0002
134 #define BCM43xx_SHM_PCM 0x0003
135 #define BCM43xx_SHM_HWMAC 0x0004
136 #define BCM43xx_SHM_UCODE 0x0300
138 /* MacFilter offsets. */
139 #define BCM43xx_MACFILTER_SELF 0x0000
140 #define BCM43xx_MACFILTER_ASSOC 0x0003
142 /* Chipcommon registers. */
143 #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
144 #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
145 #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
146 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
147 #define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0
149 /* PCI core specific registers. */
150 #define BCM43xx_PCICORE_BCAST_ADDR 0x50
151 #define BCM43xx_PCICORE_BCAST_DATA 0x54
152 #define BCM43xx_PCICORE_SBTOPCI2 0x108
154 /* SBTOPCI2 values. */
155 #define BCM43xx_SBTOPCI2_PREFETCH 0x4
156 #define BCM43xx_SBTOPCI2_BURST 0x8
158 /* Chipcommon capabilities. */
159 #define BCM43xx_CAPABILITIES_PCTL 0x00040000
160 #define BCM43xx_CAPABILITIES_PLLMASK 0x00030000
161 #define BCM43xx_CAPABILITIES_PLLSHIFT 16
162 #define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700
163 #define BCM43xx_CAPABILITIES_FLASHSHIFT 8
164 #define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040
165 #define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020
166 #define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018
167 #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3
168 #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004
169 #define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003
172 #define BCM43xx_PCTL_IN 0xB0
173 #define BCM43xx_PCTL_OUT 0xB4
174 #define BCM43xx_PCTL_OUTENABLE 0xB8
175 #define BCM43xx_PCTL_XTAL_POWERUP 0x40
176 #define BCM43xx_PCTL_PLL_POWERDOWN 0x80
178 /* PowerControl Clock Modes */
179 #define BCM43xx_PCTL_CLK_FAST 0x00
180 #define BCM43xx_PCTL_CLK_SLOW 0x01
181 #define BCM43xx_PCTL_CLK_DYNAMIC 0x02
183 #define BCM43xx_PCTL_FORCE_SLOW 0x0800
184 #define BCM43xx_PCTL_FORCE_PLL 0x1000
185 #define BCM43xx_PCTL_DYN_XTAL 0x2000
188 #define BCM43xx_COREID_CHIPCOMMON 0x800
189 #define BCM43xx_COREID_ILINE20 0x801
190 #define BCM43xx_COREID_SDRAM 0x803
191 #define BCM43xx_COREID_PCI 0x804
192 #define BCM43xx_COREID_MIPS 0x805
193 #define BCM43xx_COREID_ETHERNET 0x806
194 #define BCM43xx_COREID_V90 0x807
195 #define BCM43xx_COREID_USB11_HOSTDEV 0x80a
196 #define BCM43xx_COREID_IPSEC 0x80b
197 #define BCM43xx_COREID_PCMCIA 0x80d
198 #define BCM43xx_COREID_EXT_IF 0x80f
199 #define BCM43xx_COREID_80211 0x812
200 #define BCM43xx_COREID_MIPS_3302 0x816
201 #define BCM43xx_COREID_USB11_HOST 0x817
202 #define BCM43xx_COREID_USB11_DEV 0x818
203 #define BCM43xx_COREID_USB20_HOST 0x819
204 #define BCM43xx_COREID_USB20_DEV 0x81a
205 #define BCM43xx_COREID_SDIO_HOST 0x81b
207 /* Core Information Registers */
208 #define BCM43xx_CIR_BASE 0xf00
209 #define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18)
210 #define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90)
211 #define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94)
212 #define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98)
213 #define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c)
214 #define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8)
215 #define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc)
217 /* Mask to get the Backplane Flag Number from SBTPSFLAG. */
218 #define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f
220 /* SBIMCONFIGLOW values/masks. */
221 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007
222 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0
223 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070
224 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4
225 #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000
226 #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16
228 /* sbtmstatelow state flags */
229 #define BCM43xx_SBTMSTATELOW_RESET 0x01
230 #define BCM43xx_SBTMSTATELOW_REJECT 0x02
231 #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000
232 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
234 /* sbtmstatehigh state flags */
235 #define BCM43xx_SBTMSTATEHIGH_SERROR 0x1
236 #define BCM43xx_SBTMSTATEHIGH_BUSY 0x4
238 /* sbimstate flags */
239 #define BCM43xx_SBIMSTATE_IB_ERROR 0x20000
240 #define BCM43xx_SBIMSTATE_TIMEOUT 0x40000
243 #define BCM43xx_PHYTYPE_A 0x00
244 #define BCM43xx_PHYTYPE_B 0x01
245 #define BCM43xx_PHYTYPE_G 0x02
248 #define BCM43xx_PHY_ILT_A_CTRL 0x0072
249 #define BCM43xx_PHY_ILT_A_DATA1 0x0073
250 #define BCM43xx_PHY_ILT_A_DATA2 0x0074
251 #define BCM43xx_PHY_G_LO_CONTROL 0x0810
252 #define BCM43xx_PHY_ILT_G_CTRL 0x0472
253 #define BCM43xx_PHY_ILT_G_DATA1 0x0473
254 #define BCM43xx_PHY_ILT_G_DATA2 0x0474
255 #define BCM43xx_PHY_A_PCTL 0x007B
256 #define BCM43xx_PHY_G_PCTL 0x0029
257 #define BCM43xx_PHY_A_CRS 0x0029
258 #define BCM43xx_PHY_RADIO_BITFIELD 0x0401
259 #define BCM43xx_PHY_G_CRS 0x0429
260 #define BCM43xx_PHY_NRSSILT_CTRL 0x0803
261 #define BCM43xx_PHY_NRSSILT_DATA 0x0804
264 #define BCM43xx_RADIOCTL_ID 0x01
267 #define BCM43xx_SBF_MAC_ENABLED 0x00000001
268 #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
269 #define BCM43xx_SBF_CORE_READY 0x00000004
270 #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
271 #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
272 #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
273 #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
274 #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
275 #define BCM43xx_SBF_MODE_AP 0x00040000
276 #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
277 #define BCM43xx_SBF_MODE_MONITOR 0x00400000
278 #define BCM43xx_SBF_MODE_PROMISC 0x01000000
279 #define BCM43xx_SBF_PS1 0x02000000
280 #define BCM43xx_SBF_PS2 0x04000000
281 #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
282 #define BCM43xx_SBF_TIME_UPDATE 0x10000000
283 #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
285 /* MicrocodeFlagsBitfield (addr + lo-word values?)*/
286 #define BCM43xx_UCODEFLAGS_OFFSET 0x005E
288 #define BCM43xx_UCODEFLAG_AUTODIV 0x0001
289 #define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002
290 #define BCM43xx_UCODEFLAG_UNKBPHY 0x0004
291 #define BCM43xx_UCODEFLAG_UNKGPHY 0x0020
292 #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040
293 #define BCM43xx_UCODEFLAG_JAPAN 0x0080
295 /* Generic-Interrupt reasons. */
296 #define BCM43xx_IRQ_READY (1 << 0)
297 #define BCM43xx_IRQ_BEACON (1 << 1)
298 #define BCM43xx_IRQ_PS (1 << 2)
299 #define BCM43xx_IRQ_REG124 (1 << 5)
300 #define BCM43xx_IRQ_PMQ (1 << 6)
301 #define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8)
302 #define BCM43xx_IRQ_XMIT_ERROR (1 << 11)
303 #define BCM43xx_IRQ_RX (1 << 15)
304 #define BCM43xx_IRQ_SCAN (1 << 16)
305 #define BCM43xx_IRQ_NOISE (1 << 18)
306 #define BCM43xx_IRQ_XMIT_STATUS (1 << 29)
308 #define BCM43xx_IRQ_ALL 0xffffffff
309 #define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \
310 BCM43xx_IRQ_REG124 | \
312 BCM43xx_IRQ_XMIT_ERROR | \
315 BCM43xx_IRQ_NOISE | \
316 BCM43xx_IRQ_XMIT_STATUS)
319 /* Initial default iw_mode */
320 #define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA
323 #define BCM43xx_BUSTYPE_PCI 0
324 /* Bus type Silicone Backplane Bus. */
325 #define BCM43xx_BUSTYPE_SB 1
326 /* Bus type PCMCIA. */
327 #define BCM43xx_BUSTYPE_PCMCIA 2
329 /* Threshold values. */
330 #define BCM43xx_MIN_RTS_THRESHOLD 1U
331 #define BCM43xx_MAX_RTS_THRESHOLD 2304U
332 #define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD
334 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
335 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
337 /* Max size of a security key */
338 #define BCM43xx_SEC_KEYSIZE 16
339 /* Security algorithms. */
341 BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
342 BCM43xx_SEC_ALGO_WEP,
343 BCM43xx_SEC_ALGO_UNKNOWN,
344 BCM43xx_SEC_ALGO_AES,
345 BCM43xx_SEC_ALGO_WEP104,
346 BCM43xx_SEC_ALGO_TKIP,
352 #ifdef CONFIG_BCM43XX_DEBUG
353 #define assert(expr) \
355 if (unlikely(!(expr))) { \
356 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
357 #expr, __FILE__, __LINE__, __FUNCTION__); \
361 #define assert(expr) do { /* nothing */ } while (0)
364 /* rate limited printk(). */
368 #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
369 /* rate limited printk() for debugging */
373 #ifdef CONFIG_BCM43XX_DEBUG
374 # define dprintkl printkl
376 # define dprintkl(f, x...) do { /* nothing */ } while (0)
379 /* Helper macro for if branches.
380 * An if branch marked with this macro is only taken in DEBUG mode.
382 * if (DEBUG_ONLY(foo == bar)) {
385 * In DEBUG mode, the branch will be taken if (foo == bar).
386 * In non-DEBUG mode, the branch will never be taken.
391 #ifdef CONFIG_BCM43XX_DEBUG
392 # define DEBUG_ONLY(x) (x)
394 # define DEBUG_ONLY(x) 0
397 /* debugging printk() */
401 #ifdef CONFIG_BCM43XX_DEBUG
402 # define dprintk(f, x...) do { printk(f ,##x); } while (0)
404 # define dprintk(f, x...) do { /* nothing */ } while (0)
410 struct bcm43xx_dmaring;
411 struct bcm43xx_pioqueue;
413 struct bcm43xx_initval {
417 } __attribute__((__packed__));
419 /* Values for bcm430x_sprominfo.locale */
421 BCM43xx_LOCALE_WORLD = 0,
422 BCM43xx_LOCALE_THAILAND,
423 BCM43xx_LOCALE_ISRAEL,
424 BCM43xx_LOCALE_JORDAN,
425 BCM43xx_LOCALE_CHINA,
426 BCM43xx_LOCALE_JAPAN,
427 BCM43xx_LOCALE_USA_CANADA_ANZ,
428 BCM43xx_LOCALE_EUROPE,
429 BCM43xx_LOCALE_USA_LOW,
430 BCM43xx_LOCALE_JAPAN_HIGH,
435 #define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */
436 struct bcm43xx_sprominfo {
461 u8 idle_tssi_tgt_aphy;
462 u8 idle_tssi_tgt_bgphy;
464 u16 antennagain_aphy;
465 u16 antennagain_bgphy;
468 /* Value pair to measure the LocalOscillator. */
469 struct bcm43xx_lopair {
474 #define BCM43xx_LO_COUNT (14*4)
476 struct bcm43xx_phyinfo {
481 u16 antenna_diversity;
487 is_locked:1, /* used in bcm43xx_phy_{un}lock() */
488 dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
489 /* LO Measurement Data.
490 * Use bcm43xx_get_lopair() to get a value.
492 struct bcm43xx_lopair *_lo_pairs;
494 /* TSSI to dBm table in use */
496 /* idle TSSI value */
499 /* Values from bcm43xx_calc_loopback_gain() */
500 u16 loopback_gain[2];
502 /* PHY lock for core.rev < 3
503 * This lock is only used by bcm43xx_phy_{un}lock()
509 struct bcm43xx_radioinfo {
514 /* Desired TX power in dBm Q5.2 */
516 /* TX Power control values. */
531 /* Current Interference Mitigation mode */
533 /* Stack of saved values from the Interference Mitigation code.
534 * Each value in the stack is layed out as follows:
536 * bit 12-15: register ID
538 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
540 #define BCM43xx_INTERFSTACK_SIZE 26
541 u32 interfstack[BCM43xx_INTERFSTACK_SIZE];
543 /* Saved values from the NRSSI Slope calculation */
546 /* In memory nrssi lookup table. */
549 /* current channel */
558 /* ACI (adjacent channel interference) flags. */
560 aci_wlan_automatic:1,
564 /* Data structures for DMA transmission, per 80211 core. */
566 struct bcm43xx_dmaring *tx_ring0;
567 struct bcm43xx_dmaring *tx_ring1;
568 struct bcm43xx_dmaring *tx_ring2;
569 struct bcm43xx_dmaring *tx_ring3;
570 struct bcm43xx_dmaring *rx_ring0;
571 struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */
574 /* Data structures for PIO transmission, per 80211 core. */
576 struct bcm43xx_pioqueue *queue0;
577 struct bcm43xx_pioqueue *queue1;
578 struct bcm43xx_pioqueue *queue2;
579 struct bcm43xx_pioqueue *queue3;
582 #define BCM43xx_MAX_80211_CORES 2
584 #ifdef CONFIG_BCM947XX
585 #define core_offset(bcm) (bcm)->current_core_offset
587 #define core_offset(bcm) 0
590 /* Generic information about a core. */
591 struct bcm43xx_coreinfo {
595 /** core_id ID number */
597 /** core_rev revision number */
599 /** Index number for _switch_core() */
603 /* Additional information for each 80211 core. */
604 struct bcm43xx_coreinfo_80211 {
606 struct bcm43xx_phyinfo phy;
608 struct bcm43xx_radioinfo radio;
611 struct bcm43xx_dma dma;
613 struct bcm43xx_pio pio;
617 /* Context information for a noise calculation (Link Quality). */
618 struct bcm43xx_noise_calculation {
619 struct bcm43xx_coreinfo *core_at_start;
621 u8 calculation_running:1;
626 struct bcm43xx_stats {
629 struct iw_statistics wstats;
630 /* Store the last TX/RX times here for updating the leds. */
631 unsigned long last_tx;
632 unsigned long last_rx;
640 struct bcm43xx_private {
641 struct bcm43xx_sysfs sysfs;
643 struct ieee80211_device *ieee;
644 struct ieee80211softmac_device *softmac;
646 struct net_device *net_dev;
647 struct pci_dev *pci_dev;
650 void __iomem *mmio_addr;
651 unsigned int mmio_len;
653 /* Do not use the lock directly. Use the bcm43xx_lock* helper
654 * functions, to be MMIO-safe. */
657 /* Driver status flags. */
658 u32 initialized:1, /* init_board() succeed */
659 was_initialized:1, /* for PCI suspend/resume. */
660 shutting_down:1, /* free_board() in progress */
661 __using_pio:1, /* Internal, use bcm43xx_using_pio(). */
662 bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */
663 reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */
664 powersaving:1, /* TRUE if we are in PowerSaving mode. FALSE otherwise. */
665 short_preamble:1, /* TRUE, if short preamble is enabled. */
666 firmware_norelease:1; /* Do not release the firmware. Used on suspend. */
668 struct bcm43xx_stats stats;
670 /* Bus type we are connected to.
671 * This is currently always BCM43xx_BUSTYPE_PCI
683 struct bcm43xx_sprominfo sprom;
684 #define BCM43xx_NR_LEDS 4
685 struct bcm43xx_led leds[BCM43xx_NR_LEDS];
687 /* The currently active core. */
688 struct bcm43xx_coreinfo *current_core;
689 #ifdef CONFIG_BCM947XX
690 /** current core memory offset */
691 u32 current_core_offset;
693 struct bcm43xx_coreinfo *active_80211_core;
694 /* coreinfo structs for all possible cores follow.
695 * Note that a core might not exist.
696 * So check the coreinfo flags before using it.
698 struct bcm43xx_coreinfo core_chipcommon;
699 struct bcm43xx_coreinfo core_pci;
700 struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
701 /* Additional information, specific to the 80211 cores. */
702 struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ];
703 /* Index of the current 80211 core. If current_core is not
704 * an 80211 core, this is -1.
706 int current_80211_core_idx;
707 /* Number of available 80211 cores. */
708 int nr_80211_available;
710 u32 chipcommon_capabilities;
712 /* Reason code of the last interrupt. */
715 /* saved irq enable/disable state bitfield. */
717 /* Link Quality calculation context. */
718 struct bcm43xx_noise_calculation noisecalc;
720 /* Threshold values. */
721 //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
724 /* Interrupt Service Routine tasklet (bottom-half) */
725 struct tasklet_struct isr_tasklet;
728 struct timer_list periodic_tasks;
729 unsigned int periodic_state;
731 struct work_struct restart_work;
733 /* Informational stuff. */
734 char nick[IW_ESSID_MAX_SIZE + 1];
736 /* encryption/decryption */
738 struct bcm43xx_key key[54];
742 const struct firmware *ucode;
743 const struct firmware *pcm;
744 const struct firmware *initvals0;
745 const struct firmware *initvals1;
747 /* Debugging stuff follows. */
748 #ifdef CONFIG_BCM43XX_DEBUG
749 struct bcm43xx_dfsentry *dfsentry;
753 /* bcm43xx_(un)lock() protect struct bcm43xx_private.
754 * Note that _NO_ MMIO writes are allowed. If you want to
755 * write to the device through MMIO in the critical section, use
756 * the *_mmio lock functions.
757 * MMIO read-access is allowed, though.
759 #define bcm43xx_lock(bcm, flags) spin_lock_irqsave(&(bcm)->_lock, flags)
760 #define bcm43xx_unlock(bcm, flags) spin_unlock_irqrestore(&(bcm)->_lock, flags)
761 /* bcm43xx_(un)lock_mmio() protect struct bcm43xx_private and MMIO.
762 * MMIO write-access to the device is allowed.
763 * All MMIO writes are flushed on unlock, so it is guaranteed to not
764 * interfere with other threads writing MMIO registers.
766 #define bcm43xx_lock_mmio(bcm, flags) bcm43xx_lock(bcm, flags)
767 #define bcm43xx_unlock_mmio(bcm, flags) do { mmiowb(); bcm43xx_unlock(bcm, flags); } while (0)
770 struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
772 return ieee80211softmac_priv(dev);
776 /* Helper function, which returns a boolean.
777 * TRUE, if PIO is used; FALSE, if DMA is used.
779 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
781 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
783 return bcm->__using_pio;
785 #elif defined(CONFIG_BCM43XX_DMA)
787 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
791 #elif defined(CONFIG_BCM43XX_PIO)
793 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
798 # error "Using neither DMA nor PIO? Confused..."
801 /* Helper functions to access data structures private to the 80211 cores.
802 * Note that we _must_ have an 80211 core mapped when calling
803 * any of these functions.
806 struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm)
808 assert(bcm43xx_using_pio(bcm));
809 assert(bcm->current_80211_core_idx >= 0);
810 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
811 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].pio);
814 struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm)
816 assert(!bcm43xx_using_pio(bcm));
817 assert(bcm->current_80211_core_idx >= 0);
818 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
819 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].dma);
822 struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm)
824 assert(bcm->current_80211_core_idx >= 0);
825 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
826 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].phy);
829 struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm)
831 assert(bcm->current_80211_core_idx >= 0);
832 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
833 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].radio);
836 /* Are we running in init_board() context? */
838 int bcm43xx_is_initializing(struct bcm43xx_private *bcm)
840 if (bcm->initialized)
842 if (bcm->shutting_down)
848 struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
849 u16 radio_attenuation,
850 u16 baseband_attenuation)
852 return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2));
857 u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
859 return ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
863 void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
865 iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset);
869 u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
871 return ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
875 void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
877 iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset);
881 int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
883 return pci_read_config_word(bcm->pci_dev, offset, value);
887 int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
889 return pci_read_config_dword(bcm->pci_dev, offset, value);
893 int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
895 return pci_write_config_word(bcm->pci_dev, offset, value);
899 int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
901 return pci_write_config_dword(bcm->pci_dev, offset, value);
904 /** Limit a value between two limits */
908 #define limit_value(value, min, max) \
910 typeof(value) __value = (value); \
911 typeof(value) __min = (min); \
912 typeof(value) __max = (max); \
913 if (__value < __min) \
915 else if (__value > __max) \
920 /** Helpers to print MAC addresses. */
921 #define BCM43xx_MACFMT "%02x:%02x:%02x:%02x:%02x:%02x"
922 #define BCM43xx_MACARG(x) ((u8*)(x))[0], ((u8*)(x))[1], \
923 ((u8*)(x))[2], ((u8*)(x))[3], \
924 ((u8*)(x))[4], ((u8*)(x))[5]
926 #endif /* BCM43xx_H_ */