2 * Copyright (c) 2014 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/list.h>
19 #include <linux/ssb/ssb_regs.h>
20 #include <linux/bcma/bcma.h>
21 #include <linux/bcma/bcma_regs.h>
25 #include <brcm_hw_ids.h>
26 #include <brcmu_utils.h>
27 #include <chipcommon.h>
31 /* SOC Interconnect types (aka chip types) */
35 /* PL-368 DMP definitions */
36 #define DMP_DESC_TYPE_MSK 0x0000000F
37 #define DMP_DESC_EMPTY 0x00000000
38 #define DMP_DESC_VALID 0x00000001
39 #define DMP_DESC_COMPONENT 0x00000001
40 #define DMP_DESC_MASTER_PORT 0x00000003
41 #define DMP_DESC_ADDRESS 0x00000005
42 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
43 #define DMP_DESC_EOT 0x0000000F
45 #define DMP_COMP_DESIGNER 0xFFF00000
46 #define DMP_COMP_DESIGNER_S 20
47 #define DMP_COMP_PARTNUM 0x000FFF00
48 #define DMP_COMP_PARTNUM_S 8
49 #define DMP_COMP_CLASS 0x000000F0
50 #define DMP_COMP_CLASS_S 4
51 #define DMP_COMP_REVISION 0xFF000000
52 #define DMP_COMP_REVISION_S 24
53 #define DMP_COMP_NUM_SWRAP 0x00F80000
54 #define DMP_COMP_NUM_SWRAP_S 19
55 #define DMP_COMP_NUM_MWRAP 0x0007C000
56 #define DMP_COMP_NUM_MWRAP_S 14
57 #define DMP_COMP_NUM_SPORT 0x00003E00
58 #define DMP_COMP_NUM_SPORT_S 9
59 #define DMP_COMP_NUM_MPORT 0x000001F0
60 #define DMP_COMP_NUM_MPORT_S 4
62 #define DMP_MASTER_PORT_UID 0x0000FF00
63 #define DMP_MASTER_PORT_UID_S 8
64 #define DMP_MASTER_PORT_NUM 0x000000F0
65 #define DMP_MASTER_PORT_NUM_S 4
67 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
68 #define DMP_SLAVE_ADDR_BASE_S 12
69 #define DMP_SLAVE_PORT_NUM 0x00000F00
70 #define DMP_SLAVE_PORT_NUM_S 8
71 #define DMP_SLAVE_TYPE 0x000000C0
72 #define DMP_SLAVE_TYPE_S 6
73 #define DMP_SLAVE_TYPE_SLAVE 0
74 #define DMP_SLAVE_TYPE_BRIDGE 1
75 #define DMP_SLAVE_TYPE_SWRAP 2
76 #define DMP_SLAVE_TYPE_MWRAP 3
77 #define DMP_SLAVE_SIZE_TYPE 0x00000030
78 #define DMP_SLAVE_SIZE_TYPE_S 4
79 #define DMP_SLAVE_SIZE_4K 0
80 #define DMP_SLAVE_SIZE_8K 1
81 #define DMP_SLAVE_SIZE_16K 2
82 #define DMP_SLAVE_SIZE_DESC 3
85 #define CIB_REV_MASK 0xff000000
86 #define CIB_REV_SHIFT 24
88 /* ARM CR4 core specific control flag bits */
89 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
91 /* D11 core specific control flag bits */
92 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
93 #define D11_BCMA_IOCTL_PHYRESET 0x0008
95 /* chip core base & ramsize */
97 /* SDIO device core, ID 0x829 */
98 #define BCM4329_CORE_BUS_BASE 0x18011000
99 /* internal memory core, ID 0x80e */
100 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
101 /* ARM Cortex M3 core, ID 0x82a */
102 #define BCM4329_CORE_ARM_BASE 0x18002000
103 #define BCM4329_RAMSIZE 0x48000
106 /* SDIO device core */
107 #define BCM43143_CORE_BUS_BASE 0x18002000
108 /* internal memory core */
109 #define BCM43143_CORE_SOCRAM_BASE 0x18004000
110 /* ARM Cortex M3 core, ID 0x82a */
111 #define BCM43143_CORE_ARM_BASE 0x18003000
112 #define BCM43143_RAMSIZE 0x70000
114 #define CORE_SB(base, field) \
115 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
116 #define SBCOREREV(sbidh) \
117 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
118 ((sbidh) & SSB_IDHIGH_RCLO))
122 u32 sbipsflag; /* initiator port ocp slave flag */
124 u32 sbtpsflag; /* target port ocp slave flag */
126 u32 sbtmerrloga; /* (sonics >= 2.3) */
128 u32 sbtmerrlog; /* (sonics >= 2.3) */
130 u32 sbadmatch3; /* address match3 */
132 u32 sbadmatch2; /* address match2 */
134 u32 sbadmatch1; /* address match1 */
136 u32 sbimstate; /* initiator agent state */
137 u32 sbintvec; /* interrupt mask */
138 u32 sbtmstatelow; /* target state */
139 u32 sbtmstatehigh; /* target state */
140 u32 sbbwa0; /* bandwidth allocation table0 */
142 u32 sbimconfiglow; /* initiator configuration */
143 u32 sbimconfighigh; /* initiator configuration */
144 u32 sbadmatch0; /* address match0 */
146 u32 sbtmconfiglow; /* target configuration */
147 u32 sbtmconfighigh; /* target configuration */
148 u32 sbbconfig; /* broadcast configuration */
150 u32 sbbstate; /* broadcast state */
152 u32 sbactcnfg; /* activate configuration */
154 u32 sbflagst; /* current sbflags */
156 u32 sbidlow; /* identification */
157 u32 sbidhigh; /* identification */
160 struct brcmf_core_priv {
161 struct brcmf_core pub;
163 struct list_head list;
164 struct brcmf_chip_priv *chip;
167 /* ARM CR4 core specific control flag bits */
168 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
170 /* D11 core specific control flag bits */
171 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
172 #define D11_BCMA_IOCTL_PHYRESET 0x0008
174 struct brcmf_chip_priv {
175 struct brcmf_chip pub;
176 const struct brcmf_buscore_ops *ops;
178 /* assured first core is chipcommon, second core is buscore */
179 struct list_head cores;
182 bool (*iscoreup)(struct brcmf_core_priv *core);
183 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
185 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
189 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
190 struct brcmf_core *core)
194 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
195 core->rev = SBCOREREV(regdata);
198 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
200 struct brcmf_chip_priv *ci;
205 address = CORE_SB(core->pub.base, sbtmstatelow);
206 regdata = ci->ops->read32(ci->ctx, address);
207 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
208 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
209 return SSB_TMSLOW_CLOCK == regdata;
212 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
214 struct brcmf_chip_priv *ci;
219 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
220 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
222 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
223 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
228 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
229 u32 prereset, u32 reset)
231 struct brcmf_chip_priv *ci;
235 base = core->pub.base;
236 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
237 if (val & SSB_TMSLOW_RESET)
240 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
241 if ((val & SSB_TMSLOW_CLOCK) != 0) {
243 * set target reject and spin until busy is clear
244 * (preserve core-specific bits)
246 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
247 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
248 val | SSB_TMSLOW_REJECT);
250 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
252 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
253 & SSB_TMSHIGH_BUSY), 100000);
255 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
256 if (val & SSB_TMSHIGH_BUSY)
257 brcmf_err("core state still busy\n");
259 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
260 if (val & SSB_IDLOW_INITIATOR) {
261 val = ci->ops->read32(ci->ctx,
262 CORE_SB(base, sbimstate));
263 val |= SSB_IMSTATE_REJECT;
264 ci->ops->write32(ci->ctx,
265 CORE_SB(base, sbimstate), val);
266 val = ci->ops->read32(ci->ctx,
267 CORE_SB(base, sbimstate));
269 SPINWAIT((ci->ops->read32(ci->ctx,
270 CORE_SB(base, sbimstate)) &
271 SSB_IMSTATE_BUSY), 100000);
274 /* set reset and reject while enabling the clocks */
275 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
276 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
277 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
278 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
281 /* clear the initiator reject bit */
282 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
283 if (val & SSB_IDLOW_INITIATOR) {
284 val = ci->ops->read32(ci->ctx,
285 CORE_SB(base, sbimstate));
286 val &= ~SSB_IMSTATE_REJECT;
287 ci->ops->write32(ci->ctx,
288 CORE_SB(base, sbimstate), val);
292 /* leave reset and reject asserted */
293 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
294 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
298 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
299 u32 prereset, u32 reset)
301 struct brcmf_chip_priv *ci;
306 /* if core is already in reset, skip reset */
307 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
308 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
309 goto in_reset_configure;
311 /* configure reset */
312 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
313 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
314 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
317 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
318 BCMA_RESET_CTL_RESET);
319 usleep_range(10, 20);
321 /* wait till reset is 1 */
322 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
323 BCMA_RESET_CTL_RESET, 300);
326 /* in-reset configure */
327 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
328 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
329 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
332 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
333 u32 reset, u32 postreset)
335 struct brcmf_chip_priv *ci;
340 base = core->pub.base;
342 * Must do the disable sequence first to work for
343 * arbitrary current core state.
345 brcmf_chip_sb_coredisable(core, 0, 0);
348 * Now do the initialization sequence.
349 * set reset while enabling the clock and
350 * forcing them on throughout the core
352 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
353 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
355 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
358 /* clear any serror */
359 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
360 if (regdata & SSB_TMSHIGH_SERR)
361 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
363 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
364 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
365 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
366 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
369 /* clear reset and allow it to propagate throughout the core */
370 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
371 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
372 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
375 /* leave clock enabled */
376 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
378 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
382 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
383 u32 reset, u32 postreset)
385 struct brcmf_chip_priv *ci;
390 /* must disable first to work for arbitrary current core state */
391 brcmf_chip_ai_coredisable(core, prereset, reset);
394 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
395 BCMA_RESET_CTL_RESET) {
396 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
400 usleep_range(40, 60);
403 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
404 postreset | BCMA_IOCTL_CLK);
405 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
408 static char *brcmf_chip_name(uint chipid, char *buf, uint len)
412 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
413 snprintf(buf, len, fmt, chipid);
417 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
418 u16 coreid, u32 base,
421 struct brcmf_core_priv *core;
423 core = kzalloc(sizeof(*core), GFP_KERNEL);
425 return ERR_PTR(-ENOMEM);
427 core->pub.id = coreid;
428 core->pub.base = base;
430 core->wrapbase = wrapbase;
432 list_add_tail(&core->list, &ci->cores);
437 /* safety check for chipinfo */
438 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
440 struct brcmf_core_priv *core;
441 bool need_socram = false;
442 bool has_socram = false;
445 list_for_each_entry(core, &ci->cores, list) {
446 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
447 idx++, core->pub.id, core->pub.rev, core->pub.base,
450 switch (core->pub.id) {
451 case BCMA_CORE_ARM_CM3:
454 case BCMA_CORE_INTERNAL_MEM:
457 case BCMA_CORE_ARM_CR4:
458 if (ci->pub.rambase == 0) {
459 brcmf_err("RAM base not provided with ARM CR4 core\n");
468 /* check RAM core presence for ARM CM3 core */
469 if (need_socram && !has_socram) {
470 brcmf_err("RAM core not provided with ARM CM3 core\n");
476 static inline int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
482 static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
484 switch (ci->pub.chip) {
485 case BCM4329_CHIP_ID:
486 ci->pub.ramsize = BCM4329_RAMSIZE;
488 case BCM43143_CHIP_ID:
489 ci->pub.ramsize = BCM43143_RAMSIZE;
491 case BCM43241_CHIP_ID:
492 ci->pub.ramsize = 0x90000;
494 case BCM4330_CHIP_ID:
495 ci->pub.ramsize = 0x48000;
497 case BCM4334_CHIP_ID:
498 ci->pub.ramsize = 0x80000;
500 case BCM4335_CHIP_ID:
501 ci->pub.ramsize = 0xc0000;
502 ci->pub.rambase = 0x180000;
504 case BCM43362_CHIP_ID:
505 ci->pub.ramsize = 0x3c000;
507 case BCM4339_CHIP_ID:
508 case BCM4354_CHIP_ID:
509 ci->pub.ramsize = 0xc0000;
510 ci->pub.rambase = 0x180000;
513 brcmf_err("unknown chip: %s\n", ci->pub.name);
518 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
523 /* read next descriptor */
524 val = ci->ops->read32(ci->ctx, *eromaddr);
530 /* determine descriptor type */
531 *type = (val & DMP_DESC_TYPE_MSK);
532 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
533 *type = DMP_DESC_ADDRESS;
538 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
539 u32 *regbase, u32 *wrapbase)
544 u8 stype, sztype, wraptype;
549 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
550 if (desc == DMP_DESC_MASTER_PORT) {
551 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
552 wraptype = DMP_SLAVE_TYPE_MWRAP;
553 } else if (desc == DMP_DESC_ADDRESS) {
554 /* revert erom address */
556 wraptype = DMP_SLAVE_TYPE_SWRAP;
563 /* locate address descriptor */
565 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
566 /* unexpected table end */
567 if (desc == DMP_DESC_EOT) {
571 } while (desc != DMP_DESC_ADDRESS);
573 /* skip upper 32-bit address descriptor */
574 if (val & DMP_DESC_ADDRSIZE_GT32)
575 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
577 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
579 /* next size descriptor can be skipped */
580 if (sztype == DMP_SLAVE_SIZE_DESC) {
581 val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
582 /* skip upper size descriptor if present */
583 if (val & DMP_DESC_ADDRSIZE_GT32)
584 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
587 /* only look for 4K register regions */
588 if (sztype != DMP_SLAVE_SIZE_4K)
591 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
593 /* only regular slave and wrapper */
594 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
595 *regbase = val & DMP_SLAVE_ADDR_BASE;
596 if (*wrapbase == 0 && stype == wraptype)
597 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
598 } while (*regbase == 0 || *wrapbase == 0);
604 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
606 struct brcmf_core *core;
611 u8 nmp, nsp, nmw, nsw, rev;
615 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
617 while (desc_type != DMP_DESC_EOT) {
618 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
619 if (!(val & DMP_DESC_VALID))
622 if (desc_type == DMP_DESC_EMPTY)
625 /* need a component descriptor */
626 if (desc_type != DMP_DESC_COMPONENT)
629 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
631 /* next descriptor must be component as well */
632 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
633 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
636 /* only look at cores with master port(s) */
637 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
638 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
639 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
640 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
641 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
643 /* need core with ports */
647 /* try to obtain register address info */
648 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
652 /* finally a core to be added */
653 core = brcmf_chip_add_core(ci, id, base, wrap);
655 return PTR_ERR(core);
663 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
665 struct brcmf_core *core;
670 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
671 * For different chiptypes or old sdio hosts w/o chipcommon,
672 * other ways of recognition should be added here.
674 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
675 ci->pub.chip = regdata & CID_ID_MASK;
676 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
677 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
679 brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
680 brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
681 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
684 if (socitype == SOCI_SB) {
685 if (ci->pub.chip != BCM4329_CHIP_ID) {
686 brcmf_err("SB chip is not supported\n");
689 ci->iscoreup = brcmf_chip_sb_iscoreup;
690 ci->coredisable = brcmf_chip_sb_coredisable;
691 ci->resetcore = brcmf_chip_sb_resetcore;
693 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
695 brcmf_chip_sb_corerev(ci, core);
696 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
697 BCM4329_CORE_BUS_BASE, 0);
698 brcmf_chip_sb_corerev(ci, core);
699 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
700 BCM4329_CORE_SOCRAM_BASE, 0);
701 brcmf_chip_sb_corerev(ci, core);
702 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
703 BCM4329_CORE_ARM_BASE, 0);
704 brcmf_chip_sb_corerev(ci, core);
706 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
707 brcmf_chip_sb_corerev(ci, core);
708 } else if (socitype == SOCI_AI) {
709 ci->iscoreup = brcmf_chip_ai_iscoreup;
710 ci->coredisable = brcmf_chip_ai_coredisable;
711 ci->resetcore = brcmf_chip_ai_resetcore;
713 brcmf_chip_dmp_erom_scan(ci);
715 brcmf_err("chip backplane type %u is not supported\n",
720 brcmf_chip_get_raminfo(ci);
722 return brcmf_chip_cores_check(ci);
725 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
727 struct brcmf_core *core;
728 struct brcmf_core_priv *cr4;
732 core = brcmf_chip_get_core(&chip->pub, id);
737 case BCMA_CORE_ARM_CM3:
738 brcmf_chip_coredisable(core, 0, 0);
740 case BCMA_CORE_ARM_CR4:
741 cr4 = container_of(core, struct brcmf_core_priv, pub);
743 /* clear all IOCTL bits except HALT bit */
744 val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
745 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
746 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
747 ARMCR4_BCMA_IOCTL_CPUHALT);
750 brcmf_err("unknown id: %u\n", id);
755 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
757 struct brcmf_chip *pub;
758 struct brcmf_core_priv *cc;
764 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
767 /* get chipcommon capabilites */
768 pub->cc_caps = chip->ops->read32(chip->ctx,
769 CORE_CC_REG(base, capabilities));
771 /* get pmu caps & rev */
772 if (pub->cc_caps & CC_CAP_PMU) {
773 val = chip->ops->read32(chip->ctx,
774 CORE_CC_REG(base, pmucapabilities));
775 pub->pmurev = val & PCAP_REV_MASK;
779 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
780 cc->pub.rev, pub->pmurev, pub->pmucaps);
782 /* execute bus core specific setup */
783 if (chip->ops->setup)
784 ret = chip->ops->setup(chip->ctx, pub);
787 * Make sure any on-chip ARM is off (in case strapping is wrong),
788 * or downloaded code was already running.
790 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
791 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
795 struct brcmf_chip *brcmf_chip_attach(void *ctx,
796 const struct brcmf_buscore_ops *ops)
798 struct brcmf_chip_priv *chip;
801 if (WARN_ON(!ops->read32))
803 if (WARN_ON(!ops->write32))
805 if (WARN_ON(!ops->prepare))
807 if (WARN_ON(!ops->exit_dl))
810 return ERR_PTR(-EINVAL);
812 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
814 return ERR_PTR(-ENOMEM);
816 INIT_LIST_HEAD(&chip->cores);
821 err = ops->prepare(ctx);
825 err = brcmf_chip_recognition(chip);
829 err = brcmf_chip_setup(chip);
836 brcmf_chip_detach(&chip->pub);
840 void brcmf_chip_detach(struct brcmf_chip *pub)
842 struct brcmf_chip_priv *chip;
843 struct brcmf_core_priv *core;
844 struct brcmf_core_priv *tmp;
846 chip = container_of(pub, struct brcmf_chip_priv, pub);
847 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
848 list_del(&core->list);
854 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
856 struct brcmf_chip_priv *chip;
857 struct brcmf_core_priv *core;
859 chip = container_of(pub, struct brcmf_chip_priv, pub);
860 list_for_each_entry(core, &chip->cores, list)
861 if (core->pub.id == coreid)
867 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
869 struct brcmf_chip_priv *chip;
870 struct brcmf_core_priv *cc;
872 chip = container_of(pub, struct brcmf_chip_priv, pub);
873 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
874 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
875 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
879 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
881 struct brcmf_core_priv *core;
883 core = container_of(pub, struct brcmf_core_priv, pub);
884 return core->chip->iscoreup(core);
887 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
889 struct brcmf_core_priv *core;
891 core = container_of(pub, struct brcmf_core_priv, pub);
892 core->chip->coredisable(core, prereset, reset);
895 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
898 struct brcmf_core_priv *core;
900 core = container_of(pub, struct brcmf_core_priv, pub);
901 core->chip->resetcore(core, prereset, reset, postreset);
905 brcmf_chip_cm3_enterdl(struct brcmf_chip_priv *chip)
907 struct brcmf_core *core;
909 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
910 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
911 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
912 D11_BCMA_IOCTL_PHYCLOCKEN,
913 D11_BCMA_IOCTL_PHYCLOCKEN,
914 D11_BCMA_IOCTL_PHYCLOCKEN);
915 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
916 brcmf_chip_resetcore(core, 0, 0, 0);
919 static bool brcmf_chip_cm3_exitdl(struct brcmf_chip_priv *chip)
921 struct brcmf_core *core;
923 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
924 if (!brcmf_chip_iscoreup(core)) {
925 brcmf_err("SOCRAM core is down after reset?\n");
929 chip->ops->exit_dl(chip->ctx, &chip->pub, 0);
931 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
932 brcmf_chip_resetcore(core, 0, 0, 0);
938 brcmf_chip_cr4_enterdl(struct brcmf_chip_priv *chip)
940 struct brcmf_core *core;
942 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
944 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
945 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
946 D11_BCMA_IOCTL_PHYCLOCKEN,
947 D11_BCMA_IOCTL_PHYCLOCKEN,
948 D11_BCMA_IOCTL_PHYCLOCKEN);
951 static bool brcmf_chip_cr4_exitdl(struct brcmf_chip_priv *chip, u32 rstvec)
953 struct brcmf_core *core;
955 chip->ops->exit_dl(chip->ctx, &chip->pub, rstvec);
958 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
959 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
964 void brcmf_chip_enter_download(struct brcmf_chip *pub)
966 struct brcmf_chip_priv *chip;
967 struct brcmf_core *arm;
969 brcmf_dbg(TRACE, "Enter\n");
971 chip = container_of(pub, struct brcmf_chip_priv, pub);
972 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
974 brcmf_chip_cr4_enterdl(chip);
978 brcmf_chip_cm3_enterdl(chip);
981 bool brcmf_chip_exit_download(struct brcmf_chip *pub, u32 rstvec)
983 struct brcmf_chip_priv *chip;
984 struct brcmf_core *arm;
986 brcmf_dbg(TRACE, "Enter\n");
988 chip = container_of(pub, struct brcmf_chip_priv, pub);
989 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
991 return brcmf_chip_cr4_exitdl(chip, rstvec);
993 return brcmf_chip_cm3_exitdl(chip);
996 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
998 u32 base, addr, reg, pmu_cc3_mask = ~0;
999 struct brcmf_chip_priv *chip;
1001 brcmf_dbg(TRACE, "Enter\n");
1003 /* old chips with PMU version less than 17 don't support save restore */
1004 if (pub->pmurev < 17)
1007 base = brcmf_chip_get_chipcommon(pub)->base;
1008 chip = container_of(pub, struct brcmf_chip_priv, pub);
1010 switch (pub->chip) {
1011 case BCM4354_CHIP_ID:
1012 /* explicitly check SR engine enable bit */
1013 pmu_cc3_mask = BIT(2);
1015 case BCM43241_CHIP_ID:
1016 case BCM4335_CHIP_ID:
1017 case BCM4339_CHIP_ID:
1018 /* read PMU chipcontrol register 3 */
1019 addr = CORE_CC_REG(base, chipcontrol_addr);
1020 chip->ops->write32(chip->ctx, addr, 3);
1021 addr = CORE_CC_REG(base, chipcontrol_data);
1022 reg = chip->ops->read32(chip->ctx, addr);
1023 return (reg & pmu_cc3_mask) != 0;
1025 addr = CORE_CC_REG(base, pmucapabilities_ext);
1026 reg = chip->ops->read32(chip->ctx, addr);
1027 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1030 addr = CORE_CC_REG(base, retention_ctl);
1031 reg = chip->ops->read32(chip->ctx, addr);
1032 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1033 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;