2 * Copyright (c) 2014 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/list.h>
19 #include <linux/ssb/ssb_regs.h>
20 #include <linux/bcma/bcma.h>
21 #include <linux/bcma/bcma_regs.h>
25 #include <brcm_hw_ids.h>
26 #include <brcmu_utils.h>
27 #include <chipcommon.h>
31 /* SOC Interconnect types (aka chip types) */
35 /* PL-368 DMP definitions */
36 #define DMP_DESC_TYPE_MSK 0x0000000F
37 #define DMP_DESC_EMPTY 0x00000000
38 #define DMP_DESC_VALID 0x00000001
39 #define DMP_DESC_COMPONENT 0x00000001
40 #define DMP_DESC_MASTER_PORT 0x00000003
41 #define DMP_DESC_ADDRESS 0x00000005
42 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
43 #define DMP_DESC_EOT 0x0000000F
45 #define DMP_COMP_DESIGNER 0xFFF00000
46 #define DMP_COMP_DESIGNER_S 20
47 #define DMP_COMP_PARTNUM 0x000FFF00
48 #define DMP_COMP_PARTNUM_S 8
49 #define DMP_COMP_CLASS 0x000000F0
50 #define DMP_COMP_CLASS_S 4
51 #define DMP_COMP_REVISION 0xFF000000
52 #define DMP_COMP_REVISION_S 24
53 #define DMP_COMP_NUM_SWRAP 0x00F80000
54 #define DMP_COMP_NUM_SWRAP_S 19
55 #define DMP_COMP_NUM_MWRAP 0x0007C000
56 #define DMP_COMP_NUM_MWRAP_S 14
57 #define DMP_COMP_NUM_SPORT 0x00003E00
58 #define DMP_COMP_NUM_SPORT_S 9
59 #define DMP_COMP_NUM_MPORT 0x000001F0
60 #define DMP_COMP_NUM_MPORT_S 4
62 #define DMP_MASTER_PORT_UID 0x0000FF00
63 #define DMP_MASTER_PORT_UID_S 8
64 #define DMP_MASTER_PORT_NUM 0x000000F0
65 #define DMP_MASTER_PORT_NUM_S 4
67 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
68 #define DMP_SLAVE_ADDR_BASE_S 12
69 #define DMP_SLAVE_PORT_NUM 0x00000F00
70 #define DMP_SLAVE_PORT_NUM_S 8
71 #define DMP_SLAVE_TYPE 0x000000C0
72 #define DMP_SLAVE_TYPE_S 6
73 #define DMP_SLAVE_TYPE_SLAVE 0
74 #define DMP_SLAVE_TYPE_BRIDGE 1
75 #define DMP_SLAVE_TYPE_SWRAP 2
76 #define DMP_SLAVE_TYPE_MWRAP 3
77 #define DMP_SLAVE_SIZE_TYPE 0x00000030
78 #define DMP_SLAVE_SIZE_TYPE_S 4
79 #define DMP_SLAVE_SIZE_4K 0
80 #define DMP_SLAVE_SIZE_8K 1
81 #define DMP_SLAVE_SIZE_16K 2
82 #define DMP_SLAVE_SIZE_DESC 3
85 #define CIB_REV_MASK 0xff000000
86 #define CIB_REV_SHIFT 24
88 /* ARM CR4 core specific control flag bits */
89 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
91 /* D11 core specific control flag bits */
92 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
93 #define D11_BCMA_IOCTL_PHYRESET 0x0008
95 /* chip core base & ramsize */
97 /* SDIO device core, ID 0x829 */
98 #define BCM4329_CORE_BUS_BASE 0x18011000
99 /* internal memory core, ID 0x80e */
100 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
101 /* ARM Cortex M3 core, ID 0x82a */
102 #define BCM4329_CORE_ARM_BASE 0x18002000
103 #define BCM4329_RAMSIZE 0x48000
105 #define BCM43143_RAMSIZE 0x70000
107 #define CORE_SB(base, field) \
108 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
109 #define SBCOREREV(sbidh) \
110 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
111 ((sbidh) & SSB_IDHIGH_RCLO))
115 u32 sbipsflag; /* initiator port ocp slave flag */
117 u32 sbtpsflag; /* target port ocp slave flag */
119 u32 sbtmerrloga; /* (sonics >= 2.3) */
121 u32 sbtmerrlog; /* (sonics >= 2.3) */
123 u32 sbadmatch3; /* address match3 */
125 u32 sbadmatch2; /* address match2 */
127 u32 sbadmatch1; /* address match1 */
129 u32 sbimstate; /* initiator agent state */
130 u32 sbintvec; /* interrupt mask */
131 u32 sbtmstatelow; /* target state */
132 u32 sbtmstatehigh; /* target state */
133 u32 sbbwa0; /* bandwidth allocation table0 */
135 u32 sbimconfiglow; /* initiator configuration */
136 u32 sbimconfighigh; /* initiator configuration */
137 u32 sbadmatch0; /* address match0 */
139 u32 sbtmconfiglow; /* target configuration */
140 u32 sbtmconfighigh; /* target configuration */
141 u32 sbbconfig; /* broadcast configuration */
143 u32 sbbstate; /* broadcast state */
145 u32 sbactcnfg; /* activate configuration */
147 u32 sbflagst; /* current sbflags */
149 u32 sbidlow; /* identification */
150 u32 sbidhigh; /* identification */
153 struct brcmf_core_priv {
154 struct brcmf_core pub;
156 struct list_head list;
157 struct brcmf_chip_priv *chip;
160 struct brcmf_chip_priv {
161 struct brcmf_chip pub;
162 const struct brcmf_buscore_ops *ops;
164 /* assured first core is chipcommon, second core is buscore */
165 struct list_head cores;
168 bool (*iscoreup)(struct brcmf_core_priv *core);
169 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
171 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
175 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
176 struct brcmf_core *core)
180 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
181 core->rev = SBCOREREV(regdata);
184 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
186 struct brcmf_chip_priv *ci;
191 address = CORE_SB(core->pub.base, sbtmstatelow);
192 regdata = ci->ops->read32(ci->ctx, address);
193 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
194 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
195 return SSB_TMSLOW_CLOCK == regdata;
198 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
200 struct brcmf_chip_priv *ci;
205 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
206 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
208 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
209 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
214 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
215 u32 prereset, u32 reset)
217 struct brcmf_chip_priv *ci;
221 base = core->pub.base;
222 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
223 if (val & SSB_TMSLOW_RESET)
226 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
227 if ((val & SSB_TMSLOW_CLOCK) != 0) {
229 * set target reject and spin until busy is clear
230 * (preserve core-specific bits)
232 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
233 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
234 val | SSB_TMSLOW_REJECT);
236 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
238 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
239 & SSB_TMSHIGH_BUSY), 100000);
241 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
242 if (val & SSB_TMSHIGH_BUSY)
243 brcmf_err("core state still busy\n");
245 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
246 if (val & SSB_IDLOW_INITIATOR) {
247 val = ci->ops->read32(ci->ctx,
248 CORE_SB(base, sbimstate));
249 val |= SSB_IMSTATE_REJECT;
250 ci->ops->write32(ci->ctx,
251 CORE_SB(base, sbimstate), val);
252 val = ci->ops->read32(ci->ctx,
253 CORE_SB(base, sbimstate));
255 SPINWAIT((ci->ops->read32(ci->ctx,
256 CORE_SB(base, sbimstate)) &
257 SSB_IMSTATE_BUSY), 100000);
260 /* set reset and reject while enabling the clocks */
261 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
262 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
263 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
264 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
267 /* clear the initiator reject bit */
268 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
269 if (val & SSB_IDLOW_INITIATOR) {
270 val = ci->ops->read32(ci->ctx,
271 CORE_SB(base, sbimstate));
272 val &= ~SSB_IMSTATE_REJECT;
273 ci->ops->write32(ci->ctx,
274 CORE_SB(base, sbimstate), val);
278 /* leave reset and reject asserted */
279 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
280 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
284 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
285 u32 prereset, u32 reset)
287 struct brcmf_chip_priv *ci;
292 /* if core is already in reset, skip reset */
293 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
294 if ((regdata & BCMA_RESET_CTL_RESET) != 0)
295 goto in_reset_configure;
297 /* configure reset */
298 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
299 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
300 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
303 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
304 BCMA_RESET_CTL_RESET);
305 usleep_range(10, 20);
307 /* wait till reset is 1 */
308 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
309 BCMA_RESET_CTL_RESET, 300);
312 /* in-reset configure */
313 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
314 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
315 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
318 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
319 u32 reset, u32 postreset)
321 struct brcmf_chip_priv *ci;
326 base = core->pub.base;
328 * Must do the disable sequence first to work for
329 * arbitrary current core state.
331 brcmf_chip_sb_coredisable(core, 0, 0);
334 * Now do the initialization sequence.
335 * set reset while enabling the clock and
336 * forcing them on throughout the core
338 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
339 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
341 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
344 /* clear any serror */
345 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
346 if (regdata & SSB_TMSHIGH_SERR)
347 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
349 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
350 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
351 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
352 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
355 /* clear reset and allow it to propagate throughout the core */
356 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
357 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
358 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
361 /* leave clock enabled */
362 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
364 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
368 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
369 u32 reset, u32 postreset)
371 struct brcmf_chip_priv *ci;
376 /* must disable first to work for arbitrary current core state */
377 brcmf_chip_ai_coredisable(core, prereset, reset);
380 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
381 BCMA_RESET_CTL_RESET) {
382 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
386 usleep_range(40, 60);
389 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
390 postreset | BCMA_IOCTL_CLK);
391 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
394 static char *brcmf_chip_name(uint chipid, char *buf, uint len)
398 fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
399 snprintf(buf, len, fmt, chipid);
403 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
404 u16 coreid, u32 base,
407 struct brcmf_core_priv *core;
409 core = kzalloc(sizeof(*core), GFP_KERNEL);
411 return ERR_PTR(-ENOMEM);
413 core->pub.id = coreid;
414 core->pub.base = base;
416 core->wrapbase = wrapbase;
418 list_add_tail(&core->list, &ci->cores);
422 /* safety check for chipinfo */
423 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
425 struct brcmf_core_priv *core;
426 bool need_socram = false;
427 bool has_socram = false;
428 bool cpu_found = false;
431 list_for_each_entry(core, &ci->cores, list) {
432 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
433 idx++, core->pub.id, core->pub.rev, core->pub.base,
436 switch (core->pub.id) {
437 case BCMA_CORE_ARM_CM3:
441 case BCMA_CORE_INTERNAL_MEM:
444 case BCMA_CORE_ARM_CR4:
446 if (ci->pub.rambase == 0) {
447 brcmf_err("RAM base not provided with ARM CR4 core\n");
457 brcmf_err("CPU core not detected\n");
460 /* check RAM core presence for ARM CM3 core */
461 if (need_socram && !has_socram) {
462 brcmf_err("RAM core not provided with ARM CM3 core\n");
465 if (!ci->pub.ramsize) {
466 brcmf_err("RAM size is undetermined\n");
472 static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
474 switch (ci->pub.chip) {
475 case BRCM_CC_4329_CHIP_ID:
476 ci->pub.ramsize = BCM4329_RAMSIZE;
478 case BRCM_CC_43143_CHIP_ID:
479 ci->pub.ramsize = BCM43143_RAMSIZE;
481 case BRCM_CC_43241_CHIP_ID:
482 ci->pub.ramsize = 0x90000;
484 case BRCM_CC_4330_CHIP_ID:
485 ci->pub.ramsize = 0x48000;
487 case BRCM_CC_4334_CHIP_ID:
488 case BRCM_CC_43340_CHIP_ID:
489 ci->pub.ramsize = 0x80000;
491 case BRCM_CC_4335_CHIP_ID:
492 ci->pub.ramsize = 0xc0000;
493 ci->pub.rambase = 0x180000;
495 case BRCM_CC_43362_CHIP_ID:
496 ci->pub.ramsize = 0x3c000;
498 case BRCM_CC_4345_CHIP_ID:
499 ci->pub.ramsize = 0xc8000;
500 ci->pub.rambase = 0x198000;
502 case BRCM_CC_4339_CHIP_ID:
503 case BRCM_CC_4354_CHIP_ID:
504 case BRCM_CC_4356_CHIP_ID:
505 case BRCM_CC_43567_CHIP_ID:
506 case BRCM_CC_43569_CHIP_ID:
507 case BRCM_CC_43570_CHIP_ID:
508 ci->pub.ramsize = 0xc0000;
509 ci->pub.rambase = 0x180000;
511 case BRCM_CC_43602_CHIP_ID:
512 ci->pub.ramsize = 0xf0000;
513 ci->pub.rambase = 0x180000;
516 brcmf_err("unknown chip: %s\n", ci->pub.name);
521 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
526 /* read next descriptor */
527 val = ci->ops->read32(ci->ctx, *eromaddr);
533 /* determine descriptor type */
534 *type = (val & DMP_DESC_TYPE_MSK);
535 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
536 *type = DMP_DESC_ADDRESS;
541 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
542 u32 *regbase, u32 *wrapbase)
547 u8 stype, sztype, wraptype;
552 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
553 if (desc == DMP_DESC_MASTER_PORT) {
554 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
555 wraptype = DMP_SLAVE_TYPE_MWRAP;
556 } else if (desc == DMP_DESC_ADDRESS) {
557 /* revert erom address */
559 wraptype = DMP_SLAVE_TYPE_SWRAP;
566 /* locate address descriptor */
568 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
569 /* unexpected table end */
570 if (desc == DMP_DESC_EOT) {
574 } while (desc != DMP_DESC_ADDRESS);
576 /* skip upper 32-bit address descriptor */
577 if (val & DMP_DESC_ADDRSIZE_GT32)
578 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
580 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
582 /* next size descriptor can be skipped */
583 if (sztype == DMP_SLAVE_SIZE_DESC) {
584 val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
585 /* skip upper size descriptor if present */
586 if (val & DMP_DESC_ADDRSIZE_GT32)
587 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
590 /* only look for 4K register regions */
591 if (sztype != DMP_SLAVE_SIZE_4K)
594 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
596 /* only regular slave and wrapper */
597 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
598 *regbase = val & DMP_SLAVE_ADDR_BASE;
599 if (*wrapbase == 0 && stype == wraptype)
600 *wrapbase = val & DMP_SLAVE_ADDR_BASE;
601 } while (*regbase == 0 || *wrapbase == 0);
607 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
609 struct brcmf_core *core;
614 u8 nmp, nsp, nmw, nsw, rev;
618 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
620 while (desc_type != DMP_DESC_EOT) {
621 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
622 if (!(val & DMP_DESC_VALID))
625 if (desc_type == DMP_DESC_EMPTY)
628 /* need a component descriptor */
629 if (desc_type != DMP_DESC_COMPONENT)
632 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
634 /* next descriptor must be component as well */
635 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
636 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
639 /* only look at cores with master port(s) */
640 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
641 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
642 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
643 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
644 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
646 /* need core with ports */
650 /* try to obtain register address info */
651 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
655 /* finally a core to be added */
656 core = brcmf_chip_add_core(ci, id, base, wrap);
658 return PTR_ERR(core);
666 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
668 struct brcmf_core *core;
673 * Chipid is assume to be at offset 0 from SI_ENUM_BASE
674 * For different chiptypes or old sdio hosts w/o chipcommon,
675 * other ways of recognition should be added here.
677 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
678 ci->pub.chip = regdata & CID_ID_MASK;
679 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
680 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
682 brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
683 brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
684 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
687 if (socitype == SOCI_SB) {
688 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
689 brcmf_err("SB chip is not supported\n");
692 ci->iscoreup = brcmf_chip_sb_iscoreup;
693 ci->coredisable = brcmf_chip_sb_coredisable;
694 ci->resetcore = brcmf_chip_sb_resetcore;
696 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
698 brcmf_chip_sb_corerev(ci, core);
699 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
700 BCM4329_CORE_BUS_BASE, 0);
701 brcmf_chip_sb_corerev(ci, core);
702 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
703 BCM4329_CORE_SOCRAM_BASE, 0);
704 brcmf_chip_sb_corerev(ci, core);
705 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
706 BCM4329_CORE_ARM_BASE, 0);
707 brcmf_chip_sb_corerev(ci, core);
709 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
710 brcmf_chip_sb_corerev(ci, core);
711 } else if (socitype == SOCI_AI) {
712 ci->iscoreup = brcmf_chip_ai_iscoreup;
713 ci->coredisable = brcmf_chip_ai_coredisable;
714 ci->resetcore = brcmf_chip_ai_resetcore;
716 brcmf_chip_dmp_erom_scan(ci);
718 brcmf_err("chip backplane type %u is not supported\n",
723 brcmf_chip_get_raminfo(ci);
725 return brcmf_chip_cores_check(ci);
728 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
730 struct brcmf_core *core;
731 struct brcmf_core_priv *cr4;
735 core = brcmf_chip_get_core(&chip->pub, id);
740 case BCMA_CORE_ARM_CM3:
741 brcmf_chip_coredisable(core, 0, 0);
743 case BCMA_CORE_ARM_CR4:
744 cr4 = container_of(core, struct brcmf_core_priv, pub);
746 /* clear all IOCTL bits except HALT bit */
747 val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
748 val &= ARMCR4_BCMA_IOCTL_CPUHALT;
749 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
750 ARMCR4_BCMA_IOCTL_CPUHALT);
753 brcmf_err("unknown id: %u\n", id);
758 static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
760 struct brcmf_chip *pub;
761 struct brcmf_core_priv *cc;
767 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
770 /* get chipcommon capabilites */
771 pub->cc_caps = chip->ops->read32(chip->ctx,
772 CORE_CC_REG(base, capabilities));
774 /* get pmu caps & rev */
775 if (pub->cc_caps & CC_CAP_PMU) {
776 val = chip->ops->read32(chip->ctx,
777 CORE_CC_REG(base, pmucapabilities));
778 pub->pmurev = val & PCAP_REV_MASK;
782 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
783 cc->pub.rev, pub->pmurev, pub->pmucaps);
785 /* execute bus core specific setup */
786 if (chip->ops->setup)
787 ret = chip->ops->setup(chip->ctx, pub);
790 * Make sure any on-chip ARM is off (in case strapping is wrong),
791 * or downloaded code was already running.
793 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
794 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
798 struct brcmf_chip *brcmf_chip_attach(void *ctx,
799 const struct brcmf_buscore_ops *ops)
801 struct brcmf_chip_priv *chip;
804 if (WARN_ON(!ops->read32))
806 if (WARN_ON(!ops->write32))
808 if (WARN_ON(!ops->prepare))
810 if (WARN_ON(!ops->exit_dl))
813 return ERR_PTR(-EINVAL);
815 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
817 return ERR_PTR(-ENOMEM);
819 INIT_LIST_HEAD(&chip->cores);
824 err = ops->prepare(ctx);
828 err = brcmf_chip_recognition(chip);
832 err = brcmf_chip_setup(chip);
839 brcmf_chip_detach(&chip->pub);
843 void brcmf_chip_detach(struct brcmf_chip *pub)
845 struct brcmf_chip_priv *chip;
846 struct brcmf_core_priv *core;
847 struct brcmf_core_priv *tmp;
849 chip = container_of(pub, struct brcmf_chip_priv, pub);
850 list_for_each_entry_safe(core, tmp, &chip->cores, list) {
851 list_del(&core->list);
857 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
859 struct brcmf_chip_priv *chip;
860 struct brcmf_core_priv *core;
862 chip = container_of(pub, struct brcmf_chip_priv, pub);
863 list_for_each_entry(core, &chip->cores, list)
864 if (core->pub.id == coreid)
870 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
872 struct brcmf_chip_priv *chip;
873 struct brcmf_core_priv *cc;
875 chip = container_of(pub, struct brcmf_chip_priv, pub);
876 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
877 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
878 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
882 bool brcmf_chip_iscoreup(struct brcmf_core *pub)
884 struct brcmf_core_priv *core;
886 core = container_of(pub, struct brcmf_core_priv, pub);
887 return core->chip->iscoreup(core);
890 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
892 struct brcmf_core_priv *core;
894 core = container_of(pub, struct brcmf_core_priv, pub);
895 core->chip->coredisable(core, prereset, reset);
898 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
901 struct brcmf_core_priv *core;
903 core = container_of(pub, struct brcmf_core_priv, pub);
904 core->chip->resetcore(core, prereset, reset, postreset);
908 brcmf_chip_cm3_enterdl(struct brcmf_chip_priv *chip)
910 struct brcmf_core *core;
912 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
913 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
914 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
915 D11_BCMA_IOCTL_PHYCLOCKEN,
916 D11_BCMA_IOCTL_PHYCLOCKEN,
917 D11_BCMA_IOCTL_PHYCLOCKEN);
918 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
919 brcmf_chip_resetcore(core, 0, 0, 0);
922 static bool brcmf_chip_cm3_exitdl(struct brcmf_chip_priv *chip)
924 struct brcmf_core *core;
926 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
927 if (!brcmf_chip_iscoreup(core)) {
928 brcmf_err("SOCRAM core is down after reset?\n");
932 chip->ops->exit_dl(chip->ctx, &chip->pub, 0);
934 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
935 brcmf_chip_resetcore(core, 0, 0, 0);
941 brcmf_chip_cr4_enterdl(struct brcmf_chip_priv *chip)
943 struct brcmf_core *core;
945 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
947 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
948 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
949 D11_BCMA_IOCTL_PHYCLOCKEN,
950 D11_BCMA_IOCTL_PHYCLOCKEN,
951 D11_BCMA_IOCTL_PHYCLOCKEN);
954 static bool brcmf_chip_cr4_exitdl(struct brcmf_chip_priv *chip, u32 rstvec)
956 struct brcmf_core *core;
958 chip->ops->exit_dl(chip->ctx, &chip->pub, rstvec);
961 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
962 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
967 void brcmf_chip_enter_download(struct brcmf_chip *pub)
969 struct brcmf_chip_priv *chip;
970 struct brcmf_core *arm;
972 brcmf_dbg(TRACE, "Enter\n");
974 chip = container_of(pub, struct brcmf_chip_priv, pub);
975 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
977 brcmf_chip_cr4_enterdl(chip);
981 brcmf_chip_cm3_enterdl(chip);
984 bool brcmf_chip_exit_download(struct brcmf_chip *pub, u32 rstvec)
986 struct brcmf_chip_priv *chip;
987 struct brcmf_core *arm;
989 brcmf_dbg(TRACE, "Enter\n");
991 chip = container_of(pub, struct brcmf_chip_priv, pub);
992 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
994 return brcmf_chip_cr4_exitdl(chip, rstvec);
996 return brcmf_chip_cm3_exitdl(chip);
999 bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
1001 u32 base, addr, reg, pmu_cc3_mask = ~0;
1002 struct brcmf_chip_priv *chip;
1004 brcmf_dbg(TRACE, "Enter\n");
1006 /* old chips with PMU version less than 17 don't support save restore */
1007 if (pub->pmurev < 17)
1010 base = brcmf_chip_get_chipcommon(pub)->base;
1011 chip = container_of(pub, struct brcmf_chip_priv, pub);
1013 switch (pub->chip) {
1014 case BRCM_CC_4354_CHIP_ID:
1015 /* explicitly check SR engine enable bit */
1016 pmu_cc3_mask = BIT(2);
1018 case BRCM_CC_43241_CHIP_ID:
1019 case BRCM_CC_4335_CHIP_ID:
1020 case BRCM_CC_4339_CHIP_ID:
1021 /* read PMU chipcontrol register 3 */
1022 addr = CORE_CC_REG(base, chipcontrol_addr);
1023 chip->ops->write32(chip->ctx, addr, 3);
1024 addr = CORE_CC_REG(base, chipcontrol_data);
1025 reg = chip->ops->read32(chip->ctx, addr);
1026 return (reg & pmu_cc3_mask) != 0;
1028 addr = CORE_CC_REG(base, pmucapabilities_ext);
1029 reg = chip->ops->read32(chip->ctx, addr);
1030 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
1033 addr = CORE_CC_REG(base, retention_ctl);
1034 reg = chip->ops->read32(chip->ctx, addr);
1035 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
1036 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;