2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_ids.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/card.h>
29 #include <linux/semaphore.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/bcma/bcma.h>
33 #include <linux/debugfs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/platform_data/brcmfmac-sdio.h>
36 #include <linux/moduleparam.h>
37 #include <asm/unaligned.h>
39 #include <brcmu_wifi.h>
40 #include <brcmu_utils.h>
41 #include <brcm_hw_ids.h>
47 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
48 #define CTL_DONE_TIMEOUT 2000 /* In milli second */
52 #define BRCMF_TRAP_INFO_SIZE 80
54 #define CBUF_LEN (128)
56 /* Device console log buffer state */
57 #define CONSOLE_BUFFER_MAX 2024
60 __le32 buf; /* Can't be pointer on (64-bit) hosts */
63 char *_buf_compat; /* Redundant pointer for backward compat. */
68 * When there is no UART (e.g. Quickturn),
69 * the host should write a complete
70 * input line directly into cbuf and then write
71 * the length into vcons_in.
72 * This may also be used when there is a real UART
73 * (at risk of conflicting with
74 * the real UART). vcons_out is currently unused.
79 /* Output (logging) buffer
80 * Console output is written to a ring buffer log_buf at index log_idx.
81 * The host may read the output when it sees log_idx advance.
82 * Output will be lost if the output wraps around faster than the host
85 struct rte_log_le log_le;
87 /* Console input line buffer
88 * Characters are read one at a time into cbuf
89 * until <CR> is received, then
90 * the buffer is processed as a command line.
91 * Also used for virtual UART.
98 #include <chipcommon.h>
102 #include "tracepoint.h"
104 #define TXQLEN 2048 /* bulk tx queue length */
105 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
106 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
109 #define TXRETRIES 2 /* # of retries for tx frames */
111 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
114 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
117 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
119 #define MEMBLOCK 2048 /* Block size used for downloading
121 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
122 biggest possible glom */
124 #define BRCMF_FIRSTREAD (1 << 6)
127 /* SBSDIO_DEVICE_CTL */
129 /* 1: device will assert busy signal when receiving CMD53 */
130 #define SBSDIO_DEVCTL_SETBUSY 0x01
131 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
132 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
133 /* 1: mask all interrupts to host except the chipActive (rev 8) */
134 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
135 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
136 * sdio bus power cycle to clear (rev 9) */
137 #define SBSDIO_DEVCTL_PADS_ISO 0x08
138 /* Force SD->SB reset mapping (rev 11) */
139 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
140 /* Determined by CoreControl bit */
141 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
142 /* Force backplane reset */
143 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
144 /* Force no backplane reset */
145 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
147 /* direct(mapped) cis space */
149 /* MAPPED common CIS address */
150 #define SBSDIO_CIS_BASE_COMMON 0x1000
151 /* maximum bytes in one CIS */
152 #define SBSDIO_CIS_SIZE_LIMIT 0x200
153 /* cis offset addr is < 17 bits */
154 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
156 /* manfid tuple length, include tuple, link bytes */
157 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
159 #define CORE_BUS_REG(base, field) \
160 (base + offsetof(struct sdpcmd_regs, field))
162 /* SDIO function 1 register CHIPCLKCSR */
163 /* Force ALP request to backplane */
164 #define SBSDIO_FORCE_ALP 0x01
165 /* Force HT request to backplane */
166 #define SBSDIO_FORCE_HT 0x02
167 /* Force ILP request to backplane */
168 #define SBSDIO_FORCE_ILP 0x04
169 /* Make ALP ready (power up xtal) */
170 #define SBSDIO_ALP_AVAIL_REQ 0x08
171 /* Make HT ready (power up PLL) */
172 #define SBSDIO_HT_AVAIL_REQ 0x10
173 /* Squelch clock requests from HW */
174 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
175 /* Status: ALP is ready */
176 #define SBSDIO_ALP_AVAIL 0x40
177 /* Status: HT is ready */
178 #define SBSDIO_HT_AVAIL 0x80
179 #define SBSDIO_CSR_MASK 0x1F
180 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
181 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
182 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
183 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
184 #define SBSDIO_CLKAV(regval, alponly) \
185 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
189 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
190 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
191 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
192 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
193 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
194 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
195 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
196 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
197 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
198 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
199 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
200 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
201 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
202 #define I_PC (1 << 10) /* descriptor error */
203 #define I_PD (1 << 11) /* data error */
204 #define I_DE (1 << 12) /* Descriptor protocol Error */
205 #define I_RU (1 << 13) /* Receive descriptor Underflow */
206 #define I_RO (1 << 14) /* Receive fifo Overflow */
207 #define I_XU (1 << 15) /* Transmit fifo Underflow */
208 #define I_RI (1 << 16) /* Receive Interrupt */
209 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
210 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
211 #define I_XI (1 << 24) /* Transmit Interrupt */
212 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
213 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
214 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
215 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
216 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
217 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
218 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
219 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
220 #define I_DMA (I_RI | I_XI | I_ERRORS)
223 #define CC_CISRDY (1 << 0) /* CIS Ready */
224 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
225 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
226 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
227 #define CC_XMTDATAAVAIL_MODE (1 << 4)
228 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
232 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
233 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
234 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237 * Software allocation of To SB Mailbox resources
240 /* tosbmailbox bits corresponding to intstatus bits */
241 #define SMB_NAK (1 << 0) /* Frame NAK */
242 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
243 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
244 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
246 /* tosbmailboxdata */
247 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250 * Software allocation of To Host Mailbox resources
254 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
255 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
256 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
257 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
259 /* tohostmailboxdata */
260 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
261 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
262 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
263 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
265 #define HMB_DATA_FCDATA_MASK 0xff000000
266 #define HMB_DATA_FCDATA_SHIFT 24
268 #define HMB_DATA_VERSION_MASK 0x00ff0000
269 #define HMB_DATA_VERSION_SHIFT 16
272 * Software-defined protocol header
275 /* Current protocol version */
276 #define SDPCM_PROT_VERSION 4
279 * Shared structure between dongle and the host.
280 * The structure contains pointers to trap or assert information.
282 #define SDPCM_SHARED_VERSION 0x0003
283 #define SDPCM_SHARED_VERSION_MASK 0x00FF
284 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
285 #define SDPCM_SHARED_ASSERT 0x0200
286 #define SDPCM_SHARED_TRAP 0x0400
288 /* Space for header read, limit for data packets */
289 #define MAX_HDR_READ (1 << 6)
290 #define MAX_RX_DATASZ 2048
292 /* Bump up limit on waiting for HT to account for first startup;
293 * if the image is doing a CRC calculation before programming the PMU
294 * for HT availability, it could take a couple hundred ms more, so
295 * max out at a 1 second (1000000us).
297 #undef PMU_MAX_TRANSITION_DLY
298 #define PMU_MAX_TRANSITION_DLY 1000000
300 /* Value for ChipClockCSR during initial setup */
301 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
302 SBSDIO_ALP_AVAIL_REQ)
304 /* Flags for SDH calls */
305 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
307 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
310 #define BRCMF_IDLE_INTERVAL 1
312 #define KSO_WAIT_US 50
313 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316 * Conversion of 802.1D priority to precedence level
318 static uint prio2prec(u32 prio)
320 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
325 /* Device console log buffer state */
326 struct brcmf_console {
327 uint count; /* Poll interval msec counter */
328 uint log_addr; /* Log struct address (fixed) */
329 struct rte_log_le log_le; /* Log struct (host copy) */
330 uint bufsize; /* Size of log buffer */
331 u8 *buf; /* Log buffer (host copy) */
332 uint last; /* Last buffer read index */
335 struct brcmf_trap_info {
349 __le32 r9; /* sb/v6 */
350 __le32 r10; /* sl/v7 */
351 __le32 r11; /* fp/v8 */
359 struct sdpcm_shared {
363 u32 assert_file_addr;
365 u32 console_addr; /* Address of struct rte_console */
371 struct sdpcm_shared_le {
374 __le32 assert_exp_addr;
375 __le32 assert_file_addr;
377 __le32 console_addr; /* Address of struct rte_console */
378 __le32 msgtrace_addr;
383 /* dongle SDIO bus specific header info */
384 struct brcmf_sdio_hdrinfo {
396 * hold counter variables
398 struct brcmf_sdio_count {
399 uint intrcount; /* Count of device interrupt callbacks */
400 uint lastintrs; /* Count as of last watchdog timer */
401 uint pollcnt; /* Count of active polls */
402 uint regfails; /* Count of R_REG failures */
403 uint tx_sderrs; /* Count of tx attempts with sd errors */
404 uint fcqueued; /* Tx packets that got queued */
405 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
406 uint rx_toolong; /* Receive frames too long to receive */
407 uint rxc_errors; /* SDIO errors when reading control frames */
408 uint rx_hdrfail; /* SDIO errors on header reads */
409 uint rx_badhdr; /* Bad received headers (roosync?) */
410 uint rx_badseq; /* Mismatched rx sequence number */
411 uint fc_rcvd; /* Number of flow-control events received */
412 uint fc_xoff; /* Number which turned on flow-control */
413 uint fc_xon; /* Number which turned off flow-control */
414 uint rxglomfail; /* Failed deglom attempts */
415 uint rxglomframes; /* Number of glom frames (superframes) */
416 uint rxglompkts; /* Number of packets from glom frames */
417 uint f2rxhdrs; /* Number of header reads */
418 uint f2rxdata; /* Number of frame data reads */
419 uint f2txdata; /* Number of f2 frame writes */
420 uint f1regdata; /* Number of f1 register accesses */
421 uint tickcnt; /* Number of watchdog been schedule */
422 ulong tx_ctlerrs; /* Err of sending ctrl frames */
423 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
424 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
425 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
426 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
429 /* misc chip info needed by some of the routines */
430 /* Private data for SDIO bus interaction */
432 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
433 struct brcmf_chip *ci; /* Chip info struct */
435 u32 hostintmask; /* Copy of Host Interrupt Mask */
436 atomic_t intstatus; /* Intstatus bits (events) pending */
437 atomic_t fcstate; /* State of dongle flow-control */
439 uint blocksize; /* Block size of SDIO transfers */
440 uint roundup; /* Max roundup limit */
442 struct pktq txq; /* Queue length used for flow-control */
443 u8 flowcontrol; /* per prio flow control bitmask */
444 u8 tx_seq; /* Transmit sequence number (next) */
445 u8 tx_max; /* Maximum transmit sequence allowed */
447 u8 *hdrbuf; /* buffer for handling rx frame */
448 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
449 u8 rx_seq; /* Receive sequence number (expected) */
450 struct brcmf_sdio_hdrinfo cur_read;
451 /* info of current read frame */
452 bool rxskip; /* Skip receive (awaiting NAK ACK) */
453 bool rxpending; /* Data frame pending in dongle */
455 uint rxbound; /* Rx frames to read before resched */
456 uint txbound; /* Tx frames to send before resched */
459 struct sk_buff *glomd; /* Packet containing glomming descriptor */
460 struct sk_buff_head glom; /* Packet list for glommed superframe */
461 uint glomerr; /* Glom packet read errors */
463 u8 *rxbuf; /* Buffer for receiving control packets */
464 uint rxblen; /* Allocated length of rxbuf */
465 u8 *rxctl; /* Aligned pointer into rxbuf */
466 u8 *rxctl_orig; /* pointer for freeing rxctl */
467 uint rxlen; /* Length of valid data in buffer */
468 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
470 u8 sdpcm_ver; /* Bus protocol reported by dongle */
472 bool intr; /* Use interrupts */
473 bool poll; /* Use polling */
474 atomic_t ipend; /* Device interrupt is pending */
475 uint spurious; /* Count of spurious interrupts */
476 uint pollrate; /* Ticks between device polls */
477 uint polltick; /* Tick counter */
480 uint console_interval;
481 struct brcmf_console console; /* Console output polling support */
482 uint console_addr; /* Console address from shared struct */
485 uint clkstate; /* State of sd and backplane clock(s) */
486 s32 idletime; /* Control for activity timeout */
487 s32 idlecount; /* Activity timeout counter */
488 s32 idleclock; /* How to set bus driver when idle */
489 bool rxflow_mode; /* Rx flow control mode */
490 bool rxflow; /* Is rx flow control on */
491 bool alp_only; /* Don't use HT clock (ALP only) */
495 bool ctrl_frame_stat;
498 spinlock_t txq_lock; /* protect bus->txq */
499 wait_queue_head_t ctrl_wait;
500 wait_queue_head_t dcmd_resp_wait;
502 struct timer_list timer;
503 struct completion watchdog_wait;
504 struct task_struct *watchdog_tsk;
508 struct workqueue_struct *brcmf_wq;
509 struct work_struct datawork;
513 bool txoff; /* Transmit flow-controlled */
514 struct brcmf_sdio_count sdcnt;
515 bool sr_enabled; /* SaveRestore enabled */
518 u8 tx_hdrlen; /* sdio bus header length for tx packet */
519 bool txglom; /* host tx glomming enable flag */
520 u16 head_align; /* buffer pointer alignment */
521 u16 sgentry_align; /* scatter-gather buffer alignment */
527 #define CLK_PENDING 2
531 static int qcount[NUMPRIO];
534 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
536 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
538 /* Retry count for register access failures */
539 static const uint retry_limit = 2;
541 /* Limit on rounding up frames */
542 static const uint max_roundup = 512;
546 enum brcmf_sdio_frmtype {
547 BRCMF_SDIO_FT_NORMAL,
552 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
554 /* SDIO Pad drive strength to select value mappings */
555 struct sdiod_drive_str {
556 u8 strength; /* Pad Drive Strength in mA */
557 u8 sel; /* Chip-specific select value */
560 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
561 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
572 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
573 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
583 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
584 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
590 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
591 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
598 #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
599 #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
600 #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
601 #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
602 #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
603 #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
604 #define BCM43241B5_FIRMWARE_NAME "brcm/brcmfmac43241b5-sdio.bin"
605 #define BCM43241B5_NVRAM_NAME "brcm/brcmfmac43241b5-sdio.txt"
606 #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
607 #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
608 #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
609 #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
610 #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
611 #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
612 #define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin"
613 #define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt"
614 #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
615 #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
616 #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
617 #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
618 #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
619 #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
620 #define BCM43430_FIRMWARE_NAME "brcm/brcmfmac43430-sdio.bin"
621 #define BCM43430_NVRAM_NAME "brcm/brcmfmac43430-sdio.txt"
622 #define BCM43455_FIRMWARE_NAME "brcm/brcmfmac43455-sdio.bin"
623 #define BCM43455_NVRAM_NAME "brcm/brcmfmac43455-sdio.txt"
624 #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin"
625 #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt"
627 MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
628 MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
629 MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
630 MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
631 MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
632 MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
633 MODULE_FIRMWARE(BCM43241B5_FIRMWARE_NAME);
634 MODULE_FIRMWARE(BCM43241B5_NVRAM_NAME);
635 MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
636 MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
637 MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
638 MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
639 MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
640 MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
641 MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME);
642 MODULE_FIRMWARE(BCM43340_NVRAM_NAME);
643 MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
644 MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
645 MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
646 MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
647 MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
648 MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
649 MODULE_FIRMWARE(BCM43430_FIRMWARE_NAME);
650 MODULE_FIRMWARE(BCM43430_NVRAM_NAME);
651 MODULE_FIRMWARE(BCM43455_FIRMWARE_NAME);
652 MODULE_FIRMWARE(BCM43455_NVRAM_NAME);
653 MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME);
654 MODULE_FIRMWARE(BCM4354_NVRAM_NAME);
656 struct brcmf_firmware_names {
663 enum brcmf_firmware_type {
668 #define BRCMF_FIRMWARE_NVRAM(name) \
669 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
671 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
672 { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
673 { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
674 { BRCM_CC_43241_CHIP_ID, 0x00000020, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
675 { BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43241B5) },
676 { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
677 { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
678 { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
679 { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
680 { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
681 { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
682 { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) },
683 { BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43430) },
684 { BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43455) },
685 { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) }
688 static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci,
689 struct brcmf_sdio_dev *sdiodev)
694 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
695 if (brcmf_fwname_data[i].chipid == ci->chip &&
696 brcmf_fwname_data[i].revmsk & BIT(ci->chiprev))
700 if (i == ARRAY_SIZE(brcmf_fwname_data)) {
701 brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev);
705 /* check if firmware path is provided by module parameter */
706 if (brcmf_firmware_path[0] != '\0') {
707 strlcpy(sdiodev->fw_name, brcmf_firmware_path,
708 sizeof(sdiodev->fw_name));
709 strlcpy(sdiodev->nvram_name, brcmf_firmware_path,
710 sizeof(sdiodev->nvram_name));
712 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
714 strlcat(sdiodev->fw_name, "/",
715 sizeof(sdiodev->fw_name));
716 strlcat(sdiodev->nvram_name, "/",
717 sizeof(sdiodev->nvram_name));
720 strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin,
721 sizeof(sdiodev->fw_name));
722 strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv,
723 sizeof(sdiodev->nvram_name));
728 static void pkt_align(struct sk_buff *p, int len, int align)
731 datalign = (unsigned long)(p->data);
732 datalign = roundup(datalign, (align)) - datalign;
734 skb_pull(p, datalign);
738 /* To check if there's window offered */
739 static bool data_ok(struct brcmf_sdio *bus)
741 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
742 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
746 * Reads a register in the SDIO hardware block. This block occupies a series of
747 * adresses on the 32 bit backplane bus.
749 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
751 struct brcmf_core *core;
754 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
755 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
760 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
762 struct brcmf_core *core;
765 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
766 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
772 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
774 u8 wr_val = 0, rd_val, cmp_val, bmask;
778 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
780 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
781 /* 1st KSO write goes to AOS wake up core if device is asleep */
782 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
786 /* device WAKEUP through KSO:
787 * write bit 0 & read back until
788 * both bits 0 (kso bit) & 1 (dev on status) are set
790 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
791 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
793 usleep_range(2000, 3000);
795 /* Put device to sleep, turn off KSO */
797 /* only check for bit0, bit1(dev on status) may not
798 * get cleared right away
800 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
804 /* reliable KSO bit set/clr:
805 * the sdiod sleep write access is synced to PMU 32khz clk
806 * just one write attempt may fail,
807 * read it back until it matches written value
809 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
811 if (((rd_val & bmask) == cmp_val) && !err)
815 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
817 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
820 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
823 if (try_cnt > MAX_KSO_ATTEMPTS)
824 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
829 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
831 /* Turn backplane clock on or off */
832 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
835 u8 clkctl, clkreq, devctl;
836 unsigned long timeout;
838 brcmf_dbg(SDIO, "Enter\n");
842 if (bus->sr_enabled) {
843 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
848 /* Request HT Avail */
850 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
852 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
855 brcmf_err("HT Avail request error: %d\n", err);
859 /* Check current status */
860 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
861 SBSDIO_FUNC1_CHIPCLKCSR, &err);
863 brcmf_err("HT Avail read error: %d\n", err);
867 /* Go to pending and await interrupt if appropriate */
868 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
869 /* Allow only clock-available interrupt */
870 devctl = brcmf_sdiod_regrb(bus->sdiodev,
871 SBSDIO_DEVICE_CTL, &err);
873 brcmf_err("Devctl error setting CA: %d\n",
878 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
879 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
881 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
882 bus->clkstate = CLK_PENDING;
885 } else if (bus->clkstate == CLK_PENDING) {
886 /* Cancel CA-only interrupt filter */
887 devctl = brcmf_sdiod_regrb(bus->sdiodev,
888 SBSDIO_DEVICE_CTL, &err);
889 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
890 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
894 /* Otherwise, wait here (polling) for HT Avail */
896 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
897 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
898 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
899 SBSDIO_FUNC1_CHIPCLKCSR,
901 if (time_after(jiffies, timeout))
904 usleep_range(5000, 10000);
907 brcmf_err("HT Avail request error: %d\n", err);
910 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
911 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
912 PMU_MAX_TRANSITION_DLY, clkctl);
916 /* Mark clock available */
917 bus->clkstate = CLK_AVAIL;
918 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
921 if (!bus->alp_only) {
922 if (SBSDIO_ALPONLY(clkctl))
923 brcmf_err("HT Clock should be on\n");
925 #endif /* defined (DEBUG) */
930 if (bus->clkstate == CLK_PENDING) {
931 /* Cancel CA-only interrupt filter */
932 devctl = brcmf_sdiod_regrb(bus->sdiodev,
933 SBSDIO_DEVICE_CTL, &err);
934 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
935 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
939 bus->clkstate = CLK_SDONLY;
940 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
942 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
944 brcmf_err("Failed access turning clock off: %d\n",
952 /* Change idle/active SD state */
953 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
955 brcmf_dbg(SDIO, "Enter\n");
958 bus->clkstate = CLK_SDONLY;
960 bus->clkstate = CLK_NONE;
965 /* Transition SD and backplane clock readiness */
966 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
969 uint oldstate = bus->clkstate;
972 brcmf_dbg(SDIO, "Enter\n");
974 /* Early exit if we're already there */
975 if (bus->clkstate == target)
980 /* Make sure SD clock is available */
981 if (bus->clkstate == CLK_NONE)
982 brcmf_sdio_sdclk(bus, true);
983 /* Now request HT Avail on the backplane */
984 brcmf_sdio_htclk(bus, true, pendok);
988 /* Remove HT request, or bring up SD clock */
989 if (bus->clkstate == CLK_NONE)
990 brcmf_sdio_sdclk(bus, true);
991 else if (bus->clkstate == CLK_AVAIL)
992 brcmf_sdio_htclk(bus, false, false);
994 brcmf_err("request for %d -> %d\n",
995 bus->clkstate, target);
999 /* Make sure to remove HT request */
1000 if (bus->clkstate == CLK_AVAIL)
1001 brcmf_sdio_htclk(bus, false, false);
1002 /* Now remove the SD clock */
1003 brcmf_sdio_sdclk(bus, false);
1007 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
1014 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
1019 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
1020 (sleep ? "SLEEP" : "WAKE"),
1021 (bus->sleeping ? "SLEEP" : "WAKE"));
1023 /* If SR is enabled control bus state with KSO */
1024 if (bus->sr_enabled) {
1025 /* Done if we're already in the requested state */
1026 if (sleep == bus->sleeping)
1029 /* Going to sleep */
1031 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
1032 SBSDIO_FUNC1_CHIPCLKCSR,
1034 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
1035 brcmf_dbg(SDIO, "no clock, set ALP\n");
1036 brcmf_sdiod_regwb(bus->sdiodev,
1037 SBSDIO_FUNC1_CHIPCLKCSR,
1038 SBSDIO_ALP_AVAIL_REQ, &err);
1040 err = brcmf_sdio_kso_control(bus, false);
1042 err = brcmf_sdio_kso_control(bus, true);
1045 brcmf_err("error while changing bus sleep state %d\n",
1052 /* control clocks */
1054 if (!bus->sr_enabled)
1055 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1057 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1058 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
1060 bus->sleeping = sleep;
1061 brcmf_dbg(SDIO, "new state %s\n",
1062 (sleep ? "SLEEP" : "WAKE"));
1064 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1070 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1072 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1075 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1076 struct sdpcm_shared *sh)
1081 struct sdpcm_shared_le sh_le;
1084 sdio_claim_host(bus->sdiodev->func[1]);
1085 brcmf_sdio_bus_sleep(bus, false, false);
1088 * Read last word in socram to determine
1089 * address of sdpcm_shared structure
1091 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1092 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1093 shaddr -= bus->ci->srsize;
1094 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1100 * Check if addr is valid.
1101 * NVRAM length at the end of memory should have been overwritten.
1103 addr = le32_to_cpu(addr_le);
1104 if (!brcmf_sdio_valid_shared_address(addr)) {
1105 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1110 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1112 /* Read hndrte_shared structure */
1113 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1114 sizeof(struct sdpcm_shared_le));
1118 sdio_release_host(bus->sdiodev->func[1]);
1121 sh->flags = le32_to_cpu(sh_le.flags);
1122 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1123 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1124 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1125 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1126 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1127 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1129 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1130 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1131 SDPCM_SHARED_VERSION,
1132 sh->flags & SDPCM_SHARED_VERSION_MASK);
1138 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1140 sdio_release_host(bus->sdiodev->func[1]);
1144 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1146 struct sdpcm_shared sh;
1148 if (brcmf_sdio_readshared(bus, &sh) == 0)
1149 bus->console_addr = sh.console_addr;
1152 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1157 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1164 brcmf_dbg(SDIO, "Enter\n");
1166 /* Read mailbox data and ack that we did so */
1167 ret = r_sdreg32(bus, &hmb_data,
1168 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1171 w_sdreg32(bus, SMB_INT_ACK,
1172 offsetof(struct sdpcmd_regs, tosbmailbox));
1173 bus->sdcnt.f1regdata += 2;
1175 /* Dongle recomposed rx frames, accept them again */
1176 if (hmb_data & HMB_DATA_NAKHANDLED) {
1177 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1180 brcmf_err("unexpected NAKHANDLED!\n");
1182 bus->rxskip = false;
1183 intstatus |= I_HMB_FRAME_IND;
1187 * DEVREADY does not occur with gSPI.
1189 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1191 (hmb_data & HMB_DATA_VERSION_MASK) >>
1192 HMB_DATA_VERSION_SHIFT;
1193 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1194 brcmf_err("Version mismatch, dongle reports %d, "
1196 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1198 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1202 * Retrieve console state address now that firmware should have
1205 brcmf_sdio_get_console_addr(bus);
1209 * Flow Control has been moved into the RX headers and this out of band
1210 * method isn't used any more.
1211 * remaining backward compatible with older dongles.
1213 if (hmb_data & HMB_DATA_FC) {
1214 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1215 HMB_DATA_FCDATA_SHIFT;
1217 if (fcbits & ~bus->flowcontrol)
1218 bus->sdcnt.fc_xoff++;
1220 if (bus->flowcontrol & ~fcbits)
1221 bus->sdcnt.fc_xon++;
1223 bus->sdcnt.fc_rcvd++;
1224 bus->flowcontrol = fcbits;
1227 /* Shouldn't be any others */
1228 if (hmb_data & ~(HMB_DATA_DEVREADY |
1229 HMB_DATA_NAKHANDLED |
1232 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1233 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1239 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1246 brcmf_err("%sterminate frame%s\n",
1247 abort ? "abort command, " : "",
1248 rtx ? ", send NAK" : "");
1251 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1253 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1255 bus->sdcnt.f1regdata++;
1257 /* Wait until the packet has been flushed (device/FIFO stable) */
1258 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1259 hi = brcmf_sdiod_regrb(bus->sdiodev,
1260 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1261 lo = brcmf_sdiod_regrb(bus->sdiodev,
1262 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1263 bus->sdcnt.f1regdata += 2;
1265 if ((hi == 0) && (lo == 0))
1268 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1269 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1270 lastrbc, (hi << 8) + lo);
1272 lastrbc = (hi << 8) + lo;
1276 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1278 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1282 err = w_sdreg32(bus, SMB_NAK,
1283 offsetof(struct sdpcmd_regs, tosbmailbox));
1285 bus->sdcnt.f1regdata++;
1290 /* Clear partial in any case */
1291 bus->cur_read.len = 0;
1294 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1296 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1299 /* On failure, abort the command and terminate the frame */
1300 brcmf_err("sdio error, abort command and terminate frame\n");
1301 bus->sdcnt.tx_sderrs++;
1303 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1304 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1305 bus->sdcnt.f1regdata++;
1307 for (i = 0; i < 3; i++) {
1308 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1309 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1310 bus->sdcnt.f1regdata += 2;
1311 if ((hi == 0) && (lo == 0))
1316 /* return total length of buffer chain */
1317 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1323 skb_queue_walk(&bus->glom, p)
1328 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1330 struct sk_buff *cur, *next;
1332 skb_queue_walk_safe(&bus->glom, cur, next) {
1333 skb_unlink(cur, &bus->glom);
1334 brcmu_pkt_buf_free_skb(cur);
1339 * brcmfmac sdio bus specific header
1340 * This is the lowest layer header wrapped on the packets transmitted between
1341 * host and WiFi dongle which contains information needed for SDIO core and
1344 * It consists of 3 parts: hardware header, hardware extension header and
1346 * hardware header (frame tag) - 4 bytes
1347 * Byte 0~1: Frame length
1348 * Byte 2~3: Checksum, bit-wise inverse of frame length
1349 * hardware extension header - 8 bytes
1350 * Tx glom mode only, N/A for Rx or normal Tx
1351 * Byte 0~1: Packet length excluding hw frame tag
1353 * Byte 3: Frame flags, bit 0: last frame indication
1354 * Byte 4~5: Reserved
1355 * Byte 6~7: Tail padding length
1356 * software header - 8 bytes
1357 * Byte 0: Rx/Tx sequence number
1358 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1359 * Byte 2: Length of next data frame, reserved for Tx
1360 * Byte 3: Data offset
1361 * Byte 4: Flow control bits, reserved for Tx
1362 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1363 * Byte 6~7: Reserved
1365 #define SDPCM_HWHDR_LEN 4
1366 #define SDPCM_HWEXT_LEN 8
1367 #define SDPCM_SWHDR_LEN 8
1368 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1369 /* software header */
1370 #define SDPCM_SEQ_MASK 0x000000ff
1371 #define SDPCM_SEQ_WRAP 256
1372 #define SDPCM_CHANNEL_MASK 0x00000f00
1373 #define SDPCM_CHANNEL_SHIFT 8
1374 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1375 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1376 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1377 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1378 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1379 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1380 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1381 #define SDPCM_NEXTLEN_SHIFT 16
1382 #define SDPCM_DOFFSET_MASK 0xff000000
1383 #define SDPCM_DOFFSET_SHIFT 24
1384 #define SDPCM_FCMASK_MASK 0x000000ff
1385 #define SDPCM_WINDOW_MASK 0x0000ff00
1386 #define SDPCM_WINDOW_SHIFT 8
1388 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1391 hdrvalue = *(u32 *)swheader;
1392 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1395 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1396 struct brcmf_sdio_hdrinfo *rd,
1397 enum brcmf_sdio_frmtype type)
1400 u8 rx_seq, fc, tx_seq_max;
1403 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1406 len = get_unaligned_le16(header);
1407 checksum = get_unaligned_le16(header + sizeof(u16));
1408 /* All zero means no more to read */
1409 if (!(len | checksum)) {
1410 bus->rxpending = false;
1413 if ((u16)(~(len ^ checksum))) {
1414 brcmf_err("HW header checksum error\n");
1415 bus->sdcnt.rx_badhdr++;
1416 brcmf_sdio_rxfail(bus, false, false);
1419 if (len < SDPCM_HDRLEN) {
1420 brcmf_err("HW header length error\n");
1423 if (type == BRCMF_SDIO_FT_SUPER &&
1424 (roundup(len, bus->blocksize) != rd->len)) {
1425 brcmf_err("HW superframe header length error\n");
1428 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1429 brcmf_err("HW subframe header length error\n");
1434 /* software header */
1435 header += SDPCM_HWHDR_LEN;
1436 swheader = le32_to_cpu(*(__le32 *)header);
1437 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1438 brcmf_err("Glom descriptor found in superframe head\n");
1442 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1443 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1444 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1445 type != BRCMF_SDIO_FT_SUPER) {
1446 brcmf_err("HW header length too long\n");
1447 bus->sdcnt.rx_toolong++;
1448 brcmf_sdio_rxfail(bus, false, false);
1452 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1453 brcmf_err("Wrong channel for superframe\n");
1457 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1458 rd->channel != SDPCM_EVENT_CHANNEL) {
1459 brcmf_err("Wrong channel for subframe\n");
1463 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1464 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1465 brcmf_err("seq %d: bad data offset\n", rx_seq);
1466 bus->sdcnt.rx_badhdr++;
1467 brcmf_sdio_rxfail(bus, false, false);
1471 if (rd->seq_num != rx_seq) {
1472 brcmf_err("seq %d: sequence number error, expect %d\n",
1473 rx_seq, rd->seq_num);
1474 bus->sdcnt.rx_badseq++;
1475 rd->seq_num = rx_seq;
1477 /* no need to check the reset for subframe */
1478 if (type == BRCMF_SDIO_FT_SUB)
1480 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1481 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1482 /* only warm for NON glom packet */
1483 if (rd->channel != SDPCM_GLOM_CHANNEL)
1484 brcmf_err("seq %d: next length error\n", rx_seq);
1487 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1488 fc = swheader & SDPCM_FCMASK_MASK;
1489 if (bus->flowcontrol != fc) {
1490 if (~bus->flowcontrol & fc)
1491 bus->sdcnt.fc_xoff++;
1492 if (bus->flowcontrol & ~fc)
1493 bus->sdcnt.fc_xon++;
1494 bus->sdcnt.fc_rcvd++;
1495 bus->flowcontrol = fc;
1497 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1498 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1499 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1500 tx_seq_max = bus->tx_seq + 2;
1502 bus->tx_max = tx_seq_max;
1507 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1509 *(__le16 *)header = cpu_to_le16(frm_length);
1510 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1513 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1514 struct brcmf_sdio_hdrinfo *hd_info)
1519 brcmf_sdio_update_hwhdr(header, hd_info->len);
1520 hdr_offset = SDPCM_HWHDR_LEN;
1523 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1524 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1525 hdrval = (u16)hd_info->tail_pad << 16;
1526 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1527 hdr_offset += SDPCM_HWEXT_LEN;
1530 hdrval = hd_info->seq_num;
1531 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1533 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1535 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1536 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1537 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1540 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1545 struct sk_buff *pfirst, *pnext;
1550 struct brcmf_sdio_hdrinfo rd_new;
1552 /* If packets, issue read(s) and send up packet chain */
1553 /* Return sequence numbers consumed? */
1555 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1556 bus->glomd, skb_peek(&bus->glom));
1558 /* If there's a descriptor, generate the packet chain */
1560 pfirst = pnext = NULL;
1561 dlen = (u16) (bus->glomd->len);
1562 dptr = bus->glomd->data;
1563 if (!dlen || (dlen & 1)) {
1564 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1569 for (totlen = num = 0; dlen; num++) {
1570 /* Get (and move past) next length */
1571 sublen = get_unaligned_le16(dptr);
1572 dlen -= sizeof(u16);
1573 dptr += sizeof(u16);
1574 if ((sublen < SDPCM_HDRLEN) ||
1575 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1576 brcmf_err("descriptor len %d bad: %d\n",
1581 if (sublen % bus->sgentry_align) {
1582 brcmf_err("sublen %d not multiple of %d\n",
1583 sublen, bus->sgentry_align);
1587 /* For last frame, adjust read len so total
1588 is a block multiple */
1591 (roundup(totlen, bus->blocksize) - totlen);
1592 totlen = roundup(totlen, bus->blocksize);
1595 /* Allocate/chain packet for next subframe */
1596 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1597 if (pnext == NULL) {
1598 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1602 skb_queue_tail(&bus->glom, pnext);
1604 /* Adhere to start alignment requirements */
1605 pkt_align(pnext, sublen, bus->sgentry_align);
1608 /* If all allocations succeeded, save packet chain
1611 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1613 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1614 totlen != bus->cur_read.len) {
1615 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1616 bus->cur_read.len, totlen, rxseq);
1618 pfirst = pnext = NULL;
1620 brcmf_sdio_free_glom(bus);
1624 /* Done with descriptor packet */
1625 brcmu_pkt_buf_free_skb(bus->glomd);
1627 bus->cur_read.len = 0;
1630 /* Ok -- either we just generated a packet chain,
1631 or had one from before */
1632 if (!skb_queue_empty(&bus->glom)) {
1633 if (BRCMF_GLOM_ON()) {
1634 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1635 skb_queue_walk(&bus->glom, pnext) {
1636 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1637 pnext, (u8 *) (pnext->data),
1638 pnext->len, pnext->len);
1642 pfirst = skb_peek(&bus->glom);
1643 dlen = (u16) brcmf_sdio_glom_len(bus);
1645 /* Do an SDIO read for the superframe. Configurable iovar to
1646 * read directly into the chained packet, or allocate a large
1647 * packet and and copy into the chain.
1649 sdio_claim_host(bus->sdiodev->func[1]);
1650 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1652 sdio_release_host(bus->sdiodev->func[1]);
1653 bus->sdcnt.f2rxdata++;
1655 /* On failure, kill the superframe, allow a couple retries */
1657 brcmf_err("glom read of %d bytes failed: %d\n",
1660 sdio_claim_host(bus->sdiodev->func[1]);
1661 if (bus->glomerr++ < 3) {
1662 brcmf_sdio_rxfail(bus, true, true);
1665 brcmf_sdio_rxfail(bus, true, false);
1666 bus->sdcnt.rxglomfail++;
1667 brcmf_sdio_free_glom(bus);
1669 sdio_release_host(bus->sdiodev->func[1]);
1673 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1674 pfirst->data, min_t(int, pfirst->len, 48),
1677 rd_new.seq_num = rxseq;
1679 sdio_claim_host(bus->sdiodev->func[1]);
1680 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1681 BRCMF_SDIO_FT_SUPER);
1682 sdio_release_host(bus->sdiodev->func[1]);
1683 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1685 /* Remove superframe header, remember offset */
1686 skb_pull(pfirst, rd_new.dat_offset);
1687 sfdoff = rd_new.dat_offset;
1690 /* Validate all the subframe headers */
1691 skb_queue_walk(&bus->glom, pnext) {
1692 /* leave when invalid subframe is found */
1696 rd_new.len = pnext->len;
1697 rd_new.seq_num = rxseq++;
1698 sdio_claim_host(bus->sdiodev->func[1]);
1699 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1701 sdio_release_host(bus->sdiodev->func[1]);
1702 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1703 pnext->data, 32, "subframe:\n");
1709 /* Terminate frame on error, request
1711 sdio_claim_host(bus->sdiodev->func[1]);
1712 if (bus->glomerr++ < 3) {
1713 /* Restore superframe header space */
1714 skb_push(pfirst, sfdoff);
1715 brcmf_sdio_rxfail(bus, true, true);
1718 brcmf_sdio_rxfail(bus, true, false);
1719 bus->sdcnt.rxglomfail++;
1720 brcmf_sdio_free_glom(bus);
1722 sdio_release_host(bus->sdiodev->func[1]);
1723 bus->cur_read.len = 0;
1727 /* Basic SD framing looks ok - process each packet (header) */
1729 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1730 dptr = (u8 *) (pfirst->data);
1731 sublen = get_unaligned_le16(dptr);
1732 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1734 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1736 "Rx Subframe Data:\n");
1738 __skb_trim(pfirst, sublen);
1739 skb_pull(pfirst, doff);
1741 if (pfirst->len == 0) {
1742 skb_unlink(pfirst, &bus->glom);
1743 brcmu_pkt_buf_free_skb(pfirst);
1747 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1749 min_t(int, pfirst->len, 32),
1750 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1751 bus->glom.qlen, pfirst, pfirst->data,
1752 pfirst->len, pfirst->next,
1754 skb_unlink(pfirst, &bus->glom);
1755 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1756 bus->sdcnt.rxglompkts++;
1759 bus->sdcnt.rxglomframes++;
1764 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1767 DECLARE_WAITQUEUE(wait, current);
1768 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1770 /* Wait until control frame is available */
1771 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1772 set_current_state(TASK_INTERRUPTIBLE);
1774 while (!(*condition) && (!signal_pending(current) && timeout))
1775 timeout = schedule_timeout(timeout);
1777 if (signal_pending(current))
1780 set_current_state(TASK_RUNNING);
1781 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1786 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1788 if (waitqueue_active(&bus->dcmd_resp_wait))
1789 wake_up_interruptible(&bus->dcmd_resp_wait);
1794 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1797 u8 *buf = NULL, *rbuf;
1800 brcmf_dbg(TRACE, "Enter\n");
1803 buf = vzalloc(bus->rxblen);
1808 pad = ((unsigned long)rbuf % bus->head_align);
1810 rbuf += (bus->head_align - pad);
1812 /* Copy the already-read portion over */
1813 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1814 if (len <= BRCMF_FIRSTREAD)
1817 /* Raise rdlen to next SDIO block to avoid tail command */
1818 rdlen = len - BRCMF_FIRSTREAD;
1819 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1820 pad = bus->blocksize - (rdlen % bus->blocksize);
1821 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1822 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1824 } else if (rdlen % bus->head_align) {
1825 rdlen += bus->head_align - (rdlen % bus->head_align);
1828 /* Drop if the read is too big or it exceeds our maximum */
1829 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1830 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1831 rdlen, bus->sdiodev->bus_if->maxctl);
1832 brcmf_sdio_rxfail(bus, false, false);
1836 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1837 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1838 len, len - doff, bus->sdiodev->bus_if->maxctl);
1839 bus->sdcnt.rx_toolong++;
1840 brcmf_sdio_rxfail(bus, false, false);
1844 /* Read remain of frame body */
1845 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1846 bus->sdcnt.f2rxdata++;
1848 /* Control frame failures need retransmission */
1850 brcmf_err("read %d control bytes failed: %d\n",
1852 bus->sdcnt.rxc_errors++;
1853 brcmf_sdio_rxfail(bus, true, true);
1856 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1860 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1861 buf, len, "RxCtrl:\n");
1863 /* Point to valid data and indicate its length */
1864 spin_lock_bh(&bus->rxctl_lock);
1866 brcmf_err("last control frame is being processed.\n");
1867 spin_unlock_bh(&bus->rxctl_lock);
1871 bus->rxctl = buf + doff;
1872 bus->rxctl_orig = buf;
1873 bus->rxlen = len - doff;
1874 spin_unlock_bh(&bus->rxctl_lock);
1877 /* Awake any waiters */
1878 brcmf_sdio_dcmd_resp_wake(bus);
1881 /* Pad read to blocksize for efficiency */
1882 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1884 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1885 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1886 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1887 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1889 } else if (*rdlen % bus->head_align) {
1890 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1894 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1896 struct sk_buff *pkt; /* Packet for event or data frames */
1897 u16 pad; /* Number of pad bytes to read */
1898 uint rxleft = 0; /* Remaining number of frames allowed */
1899 int ret; /* Return code from calls */
1900 uint rxcount = 0; /* Total frames read */
1901 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1904 brcmf_dbg(TRACE, "Enter\n");
1906 /* Not finished unless we encounter no more frames indication */
1907 bus->rxpending = true;
1909 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1910 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1911 rd->seq_num++, rxleft--) {
1913 /* Handle glomming separately */
1914 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1916 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1917 bus->glomd, skb_peek(&bus->glom));
1918 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1919 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1920 rd->seq_num += cnt - 1;
1921 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1925 rd->len_left = rd->len;
1926 /* read header first for unknow frame length */
1927 sdio_claim_host(bus->sdiodev->func[1]);
1929 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1930 bus->rxhdr, BRCMF_FIRSTREAD);
1931 bus->sdcnt.f2rxhdrs++;
1933 brcmf_err("RXHEADER FAILED: %d\n",
1935 bus->sdcnt.rx_hdrfail++;
1936 brcmf_sdio_rxfail(bus, true, true);
1937 sdio_release_host(bus->sdiodev->func[1]);
1941 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1942 bus->rxhdr, SDPCM_HDRLEN,
1945 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1946 BRCMF_SDIO_FT_NORMAL)) {
1947 sdio_release_host(bus->sdiodev->func[1]);
1948 if (!bus->rxpending)
1954 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1955 brcmf_sdio_read_control(bus, bus->rxhdr,
1958 /* prepare the descriptor for the next read */
1959 rd->len = rd->len_nxtfrm << 4;
1961 /* treat all packet as event if we don't know */
1962 rd->channel = SDPCM_EVENT_CHANNEL;
1963 sdio_release_host(bus->sdiodev->func[1]);
1966 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1967 rd->len - BRCMF_FIRSTREAD : 0;
1968 head_read = BRCMF_FIRSTREAD;
1971 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1973 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1976 /* Give up on data, request rtx of events */
1977 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1978 brcmf_sdio_rxfail(bus, false,
1979 RETRYCHAN(rd->channel));
1980 sdio_release_host(bus->sdiodev->func[1]);
1983 skb_pull(pkt, head_read);
1984 pkt_align(pkt, rd->len_left, bus->head_align);
1986 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1987 bus->sdcnt.f2rxdata++;
1988 sdio_release_host(bus->sdiodev->func[1]);
1991 brcmf_err("read %d bytes from channel %d failed: %d\n",
1992 rd->len, rd->channel, ret);
1993 brcmu_pkt_buf_free_skb(pkt);
1994 sdio_claim_host(bus->sdiodev->func[1]);
1995 brcmf_sdio_rxfail(bus, true,
1996 RETRYCHAN(rd->channel));
1997 sdio_release_host(bus->sdiodev->func[1]);
2002 skb_push(pkt, head_read);
2003 memcpy(pkt->data, bus->rxhdr, head_read);
2006 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
2007 rd_new.seq_num = rd->seq_num;
2008 sdio_claim_host(bus->sdiodev->func[1]);
2009 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
2010 BRCMF_SDIO_FT_NORMAL)) {
2012 brcmu_pkt_buf_free_skb(pkt);
2014 bus->sdcnt.rx_readahead_cnt++;
2015 if (rd->len != roundup(rd_new.len, 16)) {
2016 brcmf_err("frame length mismatch:read %d, should be %d\n",
2018 roundup(rd_new.len, 16) >> 4);
2020 brcmf_sdio_rxfail(bus, true, true);
2021 sdio_release_host(bus->sdiodev->func[1]);
2022 brcmu_pkt_buf_free_skb(pkt);
2025 sdio_release_host(bus->sdiodev->func[1]);
2026 rd->len_nxtfrm = rd_new.len_nxtfrm;
2027 rd->channel = rd_new.channel;
2028 rd->dat_offset = rd_new.dat_offset;
2030 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
2033 bus->rxhdr, SDPCM_HDRLEN,
2036 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2037 brcmf_err("readahead on control packet %d?\n",
2039 /* Force retry w/normal header read */
2041 sdio_claim_host(bus->sdiodev->func[1]);
2042 brcmf_sdio_rxfail(bus, false, true);
2043 sdio_release_host(bus->sdiodev->func[1]);
2044 brcmu_pkt_buf_free_skb(pkt);
2049 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2050 pkt->data, rd->len, "Rx Data:\n");
2052 /* Save superframe descriptor and allocate packet frame */
2053 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2054 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2055 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2057 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2060 __skb_trim(pkt, rd->len);
2061 skb_pull(pkt, SDPCM_HDRLEN);
2064 brcmf_err("%s: glom superframe w/o "
2065 "descriptor!\n", __func__);
2066 sdio_claim_host(bus->sdiodev->func[1]);
2067 brcmf_sdio_rxfail(bus, false, false);
2068 sdio_release_host(bus->sdiodev->func[1]);
2070 /* prepare the descriptor for the next read */
2071 rd->len = rd->len_nxtfrm << 4;
2073 /* treat all packet as event if we don't know */
2074 rd->channel = SDPCM_EVENT_CHANNEL;
2078 /* Fill in packet len and prio, deliver upward */
2079 __skb_trim(pkt, rd->len);
2080 skb_pull(pkt, rd->dat_offset);
2082 /* prepare the descriptor for the next read */
2083 rd->len = rd->len_nxtfrm << 4;
2085 /* treat all packet as event if we don't know */
2086 rd->channel = SDPCM_EVENT_CHANNEL;
2088 if (pkt->len == 0) {
2089 brcmu_pkt_buf_free_skb(pkt);
2093 brcmf_rx_frame(bus->sdiodev->dev, pkt);
2096 rxcount = maxframes - rxleft;
2097 /* Message if we hit the limit */
2099 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2101 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2102 /* Back off rxseq if awaiting rtx, update rx_seq */
2105 bus->rx_seq = rd->seq_num;
2111 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2113 if (waitqueue_active(&bus->ctrl_wait))
2114 wake_up_interruptible(&bus->ctrl_wait);
2118 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2123 dat_buf = (u8 *)(pkt->data);
2125 /* Check head padding */
2126 head_pad = ((unsigned long)dat_buf % bus->head_align);
2128 if (skb_headroom(pkt) < head_pad) {
2129 bus->sdiodev->bus_if->tx_realloc++;
2131 if (skb_cow(pkt, head_pad))
2134 skb_push(pkt, head_pad);
2135 dat_buf = (u8 *)(pkt->data);
2136 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2142 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2145 /* flag marking a dummy skb added for DMA alignment requirement */
2146 #define ALIGN_SKB_FLAG 0x8000
2147 /* bit mask of data length chopped from the previous packet */
2148 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2150 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2151 struct sk_buff_head *pktq,
2152 struct sk_buff *pkt, u16 total_len)
2154 struct brcmf_sdio_dev *sdiodev;
2155 struct sk_buff *pkt_pad;
2156 u16 tail_pad, tail_chop, chain_pad;
2157 unsigned int blksize;
2161 sdiodev = bus->sdiodev;
2162 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2163 /* sg entry alignment should be a divisor of block size */
2164 WARN_ON(blksize % bus->sgentry_align);
2166 /* Check tail padding */
2167 lastfrm = skb_queue_is_last(pktq, pkt);
2169 tail_chop = pkt->len % bus->sgentry_align;
2171 tail_pad = bus->sgentry_align - tail_chop;
2172 chain_pad = (total_len + tail_pad) % blksize;
2173 if (lastfrm && chain_pad)
2174 tail_pad += blksize - chain_pad;
2175 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2176 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2178 if (pkt_pad == NULL)
2180 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2181 if (unlikely(ret < 0)) {
2185 memcpy(pkt_pad->data,
2186 pkt->data + pkt->len - tail_chop,
2188 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2189 skb_trim(pkt, pkt->len - tail_chop);
2190 skb_trim(pkt_pad, tail_pad + tail_chop);
2191 __skb_queue_after(pktq, pkt, pkt_pad);
2193 ntail = pkt->data_len + tail_pad -
2194 (pkt->end - pkt->tail);
2195 if (skb_cloned(pkt) || ntail > 0)
2196 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2198 if (skb_linearize(pkt))
2200 __skb_put(pkt, tail_pad);
2207 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2208 * @bus: brcmf_sdio structure pointer
2209 * @pktq: packet list pointer
2210 * @chan: virtual channel to transmit the packet
2212 * Processes to be applied to the packet
2213 * - Align data buffer pointer
2214 * - Align data buffer length
2216 * Return: negative value if there is error
2219 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2222 u16 head_pad, total_len;
2223 struct sk_buff *pkt_next;
2226 struct brcmf_sdio_hdrinfo hd_info = {0};
2228 txseq = bus->tx_seq;
2230 skb_queue_walk(pktq, pkt_next) {
2231 /* alignment packet inserted in previous
2232 * loop cycle can be skipped as it is
2233 * already properly aligned and does not
2234 * need an sdpcm header.
2236 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2239 /* align packet data pointer */
2240 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2243 head_pad = (u16)ret;
2245 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2247 total_len += pkt_next->len;
2249 hd_info.len = pkt_next->len;
2250 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2251 if (bus->txglom && pktq->qlen > 1) {
2252 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2253 pkt_next, total_len);
2256 hd_info.tail_pad = (u16)ret;
2257 total_len += (u16)ret;
2260 hd_info.channel = chan;
2261 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2262 hd_info.seq_num = txseq++;
2264 /* Now fill the header */
2265 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2267 if (BRCMF_BYTES_ON() &&
2268 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2269 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2270 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2272 else if (BRCMF_HDRS_ON())
2273 brcmf_dbg_hex_dump(true, pkt_next->data,
2274 head_pad + bus->tx_hdrlen,
2277 /* Hardware length tag of the first packet should be total
2278 * length of the chain (including padding)
2281 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2286 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2287 * @bus: brcmf_sdio structure pointer
2288 * @pktq: packet list pointer
2290 * Processes to be applied to the packet
2291 * - Remove head padding
2292 * - Remove tail padding
2295 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2300 u16 dummy_flags, chop_len;
2301 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2303 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2304 dummy_flags = *(u16 *)(pkt_next->cb);
2305 if (dummy_flags & ALIGN_SKB_FLAG) {
2306 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2308 pkt_prev = pkt_next->prev;
2309 skb_put(pkt_prev, chop_len);
2311 __skb_unlink(pkt_next, pktq);
2312 brcmu_pkt_buf_free_skb(pkt_next);
2314 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2315 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2316 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2317 SDPCM_DOFFSET_SHIFT;
2318 skb_pull(pkt_next, dat_offset);
2320 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2321 skb_trim(pkt_next, pkt_next->len - tail_pad);
2327 /* Writes a HW/SW header into the packet and sends it. */
2328 /* Assumes: (a) header space already there, (b) caller holds lock */
2329 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2333 struct sk_buff *pkt_next, *tmp;
2335 brcmf_dbg(TRACE, "Enter\n");
2337 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2341 sdio_claim_host(bus->sdiodev->func[1]);
2342 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2343 bus->sdcnt.f2txdata++;
2346 brcmf_sdio_txfail(bus);
2348 sdio_release_host(bus->sdiodev->func[1]);
2351 brcmf_sdio_txpkt_postp(bus, pktq);
2353 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2354 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2355 __skb_unlink(pkt_next, pktq);
2356 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2361 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2363 struct sk_buff *pkt;
2364 struct sk_buff_head pktq;
2366 int ret = 0, prec_out, i;
2368 u8 tx_prec_map, pkt_num;
2370 brcmf_dbg(TRACE, "Enter\n");
2372 tx_prec_map = ~bus->flowcontrol;
2374 /* Send frames until the limit or some other event */
2375 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2378 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2379 bus->sdiodev->txglomsz);
2380 pkt_num = min_t(u32, pkt_num,
2381 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2382 __skb_queue_head_init(&pktq);
2383 spin_lock_bh(&bus->txq_lock);
2384 for (i = 0; i < pkt_num; i++) {
2385 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2389 __skb_queue_tail(&pktq, pkt);
2391 spin_unlock_bh(&bus->txq_lock);
2395 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2399 /* In poll mode, need to check for other events */
2401 /* Check device status, signal pending interrupt */
2402 sdio_claim_host(bus->sdiodev->func[1]);
2403 ret = r_sdreg32(bus, &intstatus,
2404 offsetof(struct sdpcmd_regs,
2406 sdio_release_host(bus->sdiodev->func[1]);
2407 bus->sdcnt.f2txdata++;
2410 if (intstatus & bus->hostintmask)
2411 atomic_set(&bus->ipend, 1);
2415 /* Deflow-control stack if needed */
2416 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2417 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2419 brcmf_txflowblock(bus->sdiodev->dev, false);
2425 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2430 struct brcmf_sdio_hdrinfo hd_info = {0};
2433 brcmf_dbg(TRACE, "Enter\n");
2435 /* Back the pointer to make room for bus header */
2436 frame -= bus->tx_hdrlen;
2437 len += bus->tx_hdrlen;
2439 /* Add alignment padding (optional for ctl frames) */
2440 doff = ((unsigned long)frame % bus->head_align);
2444 memset(frame + bus->tx_hdrlen, 0, doff);
2447 /* Round send length to next SDIO block */
2449 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2450 pad = bus->blocksize - (len % bus->blocksize);
2451 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2453 } else if (len % bus->head_align) {
2454 pad = bus->head_align - (len % bus->head_align);
2458 hd_info.len = len - pad;
2459 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2460 hd_info.dat_offset = doff + bus->tx_hdrlen;
2461 hd_info.seq_num = bus->tx_seq;
2462 hd_info.lastfrm = true;
2463 hd_info.tail_pad = pad;
2464 brcmf_sdio_hdpack(bus, frame, &hd_info);
2467 brcmf_sdio_update_hwhdr(frame, len);
2469 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2470 frame, len, "Tx Frame:\n");
2471 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2473 frame, min_t(u16, len, 16), "TxHdr:\n");
2476 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2479 brcmf_sdio_txfail(bus);
2481 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2482 } while (ret < 0 && retries++ < TXRETRIES);
2487 static void brcmf_sdio_bus_stop(struct device *dev)
2489 u32 local_hostintmask;
2492 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2493 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2494 struct brcmf_sdio *bus = sdiodev->bus;
2496 brcmf_dbg(TRACE, "Enter\n");
2498 if (bus->watchdog_tsk) {
2499 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2500 kthread_stop(bus->watchdog_tsk);
2501 bus->watchdog_tsk = NULL;
2504 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2505 sdio_claim_host(sdiodev->func[1]);
2507 /* Enable clock for device interrupts */
2508 brcmf_sdio_bus_sleep(bus, false, false);
2510 /* Disable and clear interrupts at the chip level also */
2511 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2512 local_hostintmask = bus->hostintmask;
2513 bus->hostintmask = 0;
2515 /* Force backplane clocks to assure F2 interrupt propagates */
2516 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2519 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2520 (saveclk | SBSDIO_FORCE_HT), &err);
2522 brcmf_err("Failed to force clock for F2: err %d\n",
2525 /* Turn off the bus (F2), free any pending packets */
2526 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2527 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2529 /* Clear any pending interrupts now that F2 is disabled */
2530 w_sdreg32(bus, local_hostintmask,
2531 offsetof(struct sdpcmd_regs, intstatus));
2533 sdio_release_host(sdiodev->func[1]);
2535 /* Clear the data packet queues */
2536 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2538 /* Clear any held glomming stuff */
2539 brcmu_pkt_buf_free_skb(bus->glomd);
2540 brcmf_sdio_free_glom(bus);
2542 /* Clear rx control and wake any waiters */
2543 spin_lock_bh(&bus->rxctl_lock);
2545 spin_unlock_bh(&bus->rxctl_lock);
2546 brcmf_sdio_dcmd_resp_wake(bus);
2548 /* Reset some F2 state stuff */
2549 bus->rxskip = false;
2550 bus->tx_seq = bus->rx_seq = 0;
2553 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2555 unsigned long flags;
2557 if (bus->sdiodev->oob_irq_requested) {
2558 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2559 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2560 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2561 bus->sdiodev->irq_en = true;
2563 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2567 static void atomic_orr(int val, atomic_t *v)
2571 old_val = atomic_read(v);
2572 while (atomic_cmpxchg(v, old_val, val | old_val) != old_val)
2573 old_val = atomic_read(v);
2576 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2578 struct brcmf_core *buscore;
2583 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2584 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2586 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2587 bus->sdcnt.f1regdata++;
2591 val &= bus->hostintmask;
2592 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2594 /* Clear interrupts */
2596 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2597 bus->sdcnt.f1regdata++;
2598 atomic_orr(val, &bus->intstatus);
2604 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2607 unsigned long intstatus;
2608 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2609 uint framecnt; /* Temporary counter of tx/rx frames */
2612 brcmf_dbg(TRACE, "Enter\n");
2614 sdio_claim_host(bus->sdiodev->func[1]);
2616 /* If waiting for HTAVAIL, check status */
2617 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2618 u8 clkctl, devctl = 0;
2621 /* Check for inconsistent device control */
2622 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2623 SBSDIO_DEVICE_CTL, &err);
2626 /* Read CSR, if clock on switch to AVAIL, else ignore */
2627 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2628 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2630 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2633 if (SBSDIO_HTAV(clkctl)) {
2634 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2635 SBSDIO_DEVICE_CTL, &err);
2636 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2637 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2639 bus->clkstate = CLK_AVAIL;
2643 /* Make sure backplane clock is on */
2644 brcmf_sdio_bus_sleep(bus, false, true);
2646 /* Pending interrupt indicates new device status */
2647 if (atomic_read(&bus->ipend) > 0) {
2648 atomic_set(&bus->ipend, 0);
2649 err = brcmf_sdio_intr_rstatus(bus);
2652 /* Start with leftover status bits */
2653 intstatus = atomic_xchg(&bus->intstatus, 0);
2655 /* Handle flow-control change: read new state in case our ack
2656 * crossed another change interrupt. If change still set, assume
2657 * FC ON for safety, let next loop through do the debounce.
2659 if (intstatus & I_HMB_FC_CHANGE) {
2660 intstatus &= ~I_HMB_FC_CHANGE;
2661 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2662 offsetof(struct sdpcmd_regs, intstatus));
2664 err = r_sdreg32(bus, &newstatus,
2665 offsetof(struct sdpcmd_regs, intstatus));
2666 bus->sdcnt.f1regdata += 2;
2667 atomic_set(&bus->fcstate,
2668 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2669 intstatus |= (newstatus & bus->hostintmask);
2672 /* Handle host mailbox indication */
2673 if (intstatus & I_HMB_HOST_INT) {
2674 intstatus &= ~I_HMB_HOST_INT;
2675 intstatus |= brcmf_sdio_hostmail(bus);
2678 sdio_release_host(bus->sdiodev->func[1]);
2680 /* Generally don't ask for these, can get CRC errors... */
2681 if (intstatus & I_WR_OOSYNC) {
2682 brcmf_err("Dongle reports WR_OOSYNC\n");
2683 intstatus &= ~I_WR_OOSYNC;
2686 if (intstatus & I_RD_OOSYNC) {
2687 brcmf_err("Dongle reports RD_OOSYNC\n");
2688 intstatus &= ~I_RD_OOSYNC;
2691 if (intstatus & I_SBINT) {
2692 brcmf_err("Dongle reports SBINT\n");
2693 intstatus &= ~I_SBINT;
2696 /* Would be active due to wake-wlan in gSPI */
2697 if (intstatus & I_CHIPACTIVE) {
2698 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2699 intstatus &= ~I_CHIPACTIVE;
2702 /* Ignore frame indications if rxskip is set */
2704 intstatus &= ~I_HMB_FRAME_IND;
2706 /* On frame indication, read available frames */
2707 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2708 brcmf_sdio_readframes(bus, bus->rxbound);
2709 if (!bus->rxpending)
2710 intstatus &= ~I_HMB_FRAME_IND;
2713 /* Keep still-pending events for next scheduling */
2715 atomic_orr(intstatus, &bus->intstatus);
2717 brcmf_sdio_clrintr(bus);
2719 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2721 sdio_claim_host(bus->sdiodev->func[1]);
2722 if (bus->ctrl_frame_stat) {
2723 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2724 bus->ctrl_frame_len);
2725 bus->ctrl_frame_err = err;
2727 bus->ctrl_frame_stat = false;
2729 sdio_release_host(bus->sdiodev->func[1]);
2730 brcmf_sdio_wait_event_wakeup(bus);
2732 /* Send queued frames (limit 1 if rx may still be pending) */
2733 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2734 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2736 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2738 brcmf_sdio_sendfromq(bus, framecnt);
2741 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2742 brcmf_err("failed backplane access over SDIO, halting operation\n");
2743 atomic_set(&bus->intstatus, 0);
2744 if (bus->ctrl_frame_stat) {
2745 sdio_claim_host(bus->sdiodev->func[1]);
2746 if (bus->ctrl_frame_stat) {
2747 bus->ctrl_frame_err = -ENODEV;
2749 bus->ctrl_frame_stat = false;
2750 brcmf_sdio_wait_event_wakeup(bus);
2752 sdio_release_host(bus->sdiodev->func[1]);
2754 } else if (atomic_read(&bus->intstatus) ||
2755 atomic_read(&bus->ipend) > 0 ||
2756 (!atomic_read(&bus->fcstate) &&
2757 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2759 bus->dpc_triggered = true;
2763 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2765 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2766 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2767 struct brcmf_sdio *bus = sdiodev->bus;
2772 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2775 int eprec = -1; /* precedence to evict from */
2777 /* Fast case, precedence queue is not full and we are also not
2778 * exceeding total queue length
2780 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2781 brcmu_pktq_penq(q, prec, pkt);
2785 /* Determine precedence from which to evict packet, if any */
2786 if (pktq_pfull(q, prec)) {
2788 } else if (pktq_full(q)) {
2789 p = brcmu_pktq_peek_tail(q, &eprec);
2794 /* Evict if needed */
2796 /* Detect queueing to unconfigured precedence */
2798 return false; /* refuse newer (incoming) packet */
2799 /* Evict packet according to discard policy */
2800 p = brcmu_pktq_pdeq_tail(q, eprec);
2802 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2803 brcmu_pkt_buf_free_skb(p);
2807 p = brcmu_pktq_penq(q, prec, pkt);
2809 brcmf_err("brcmu_pktq_penq() failed\n");
2814 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2818 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2819 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2820 struct brcmf_sdio *bus = sdiodev->bus;
2822 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2824 /* Add space for the header */
2825 skb_push(pkt, bus->tx_hdrlen);
2826 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2828 prec = prio2prec((pkt->priority & PRIOMASK));
2830 /* Check for existing queue, current flow-control,
2831 pending event, or pending clock */
2832 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2833 bus->sdcnt.fcqueued++;
2835 /* Priority based enq */
2836 spin_lock_bh(&bus->txq_lock);
2837 /* reset bus_flags in packet cb */
2838 *(u16 *)(pkt->cb) = 0;
2839 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2840 skb_pull(pkt, bus->tx_hdrlen);
2841 brcmf_err("out of bus->txq !!!\n");
2847 if (pktq_len(&bus->txq) >= TXHI) {
2849 brcmf_txflowblock(dev, true);
2851 spin_unlock_bh(&bus->txq_lock);
2854 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2855 qcount[prec] = pktq_plen(&bus->txq, prec);
2858 brcmf_sdio_trigger_dpc(bus);
2863 #define CONSOLE_LINE_MAX 192
2865 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2867 struct brcmf_console *c = &bus->console;
2868 u8 line[CONSOLE_LINE_MAX], ch;
2872 /* Don't do anything until FWREADY updates console address */
2873 if (bus->console_addr == 0)
2876 /* Read console log struct */
2877 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2878 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2883 /* Allocate console buffer (one time only) */
2884 if (c->buf == NULL) {
2885 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2886 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2891 idx = le32_to_cpu(c->log_le.idx);
2893 /* Protect against corrupt value */
2894 if (idx > c->bufsize)
2897 /* Skip reading the console buffer if the index pointer
2902 /* Read the console buffer */
2903 addr = le32_to_cpu(c->log_le.buf);
2904 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2908 while (c->last != idx) {
2909 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2910 if (c->last == idx) {
2911 /* This would output a partial line.
2913 * the buffer pointer and output this
2914 * line next time around.
2919 c->last = c->bufsize - n;
2922 ch = c->buf[c->last];
2923 c->last = (c->last + 1) % c->bufsize;
2930 if (line[n - 1] == '\r')
2933 pr_debug("CONSOLE: %s\n", line);
2943 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2945 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2946 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2947 struct brcmf_sdio *bus = sdiodev->bus;
2950 brcmf_dbg(TRACE, "Enter\n");
2953 bus->ctrl_frame_buf = msg;
2954 bus->ctrl_frame_len = msglen;
2956 bus->ctrl_frame_stat = true;
2958 brcmf_sdio_trigger_dpc(bus);
2959 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2960 msecs_to_jiffies(CTL_DONE_TIMEOUT));
2962 if (bus->ctrl_frame_stat) {
2963 sdio_claim_host(bus->sdiodev->func[1]);
2964 if (bus->ctrl_frame_stat) {
2965 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2966 bus->ctrl_frame_stat = false;
2969 sdio_release_host(bus->sdiodev->func[1]);
2972 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2973 bus->ctrl_frame_err);
2975 ret = bus->ctrl_frame_err;
2979 bus->sdcnt.tx_ctlerrs++;
2981 bus->sdcnt.tx_ctlpkts++;
2987 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2988 struct sdpcm_shared *sh)
2990 u32 addr, console_ptr, console_size, console_index;
2991 char *conbuf = NULL;
2995 /* obtain console information from device memory */
2996 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2997 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2998 (u8 *)&sh_val, sizeof(u32));
3001 console_ptr = le32_to_cpu(sh_val);
3003 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
3004 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3005 (u8 *)&sh_val, sizeof(u32));
3008 console_size = le32_to_cpu(sh_val);
3010 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
3011 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
3012 (u8 *)&sh_val, sizeof(u32));
3015 console_index = le32_to_cpu(sh_val);
3017 /* allocate buffer for console data */
3018 if (console_size <= CONSOLE_BUFFER_MAX)
3019 conbuf = vzalloc(console_size+1);
3024 /* obtain the console data from device */
3025 conbuf[console_size] = '\0';
3026 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3031 rv = seq_write(seq, conbuf + console_index,
3032 console_size - console_index);
3036 if (console_index > 0)
3037 rv = seq_write(seq, conbuf, console_index - 1);
3044 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3045 struct sdpcm_shared *sh)
3048 struct brcmf_trap_info tr;
3050 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3051 brcmf_dbg(INFO, "no trap in firmware\n");
3055 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3056 sizeof(struct brcmf_trap_info));
3061 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3062 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3063 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3064 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3065 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3066 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3067 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3068 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3069 le32_to_cpu(tr.pc), sh->trap_addr,
3070 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3071 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3072 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3073 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3078 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3079 struct sdpcm_shared *sh)
3082 char file[80] = "?";
3083 char expr[80] = "<???>";
3085 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3086 brcmf_dbg(INFO, "firmware not built with -assert\n");
3088 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3089 brcmf_dbg(INFO, "no assert in dongle\n");
3093 sdio_claim_host(bus->sdiodev->func[1]);
3094 if (sh->assert_file_addr != 0) {
3095 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3096 sh->assert_file_addr, (u8 *)file, 80);
3100 if (sh->assert_exp_addr != 0) {
3101 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3102 sh->assert_exp_addr, (u8 *)expr, 80);
3106 sdio_release_host(bus->sdiodev->func[1]);
3108 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3109 file, sh->assert_line, expr);
3113 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3116 struct sdpcm_shared sh;
3118 error = brcmf_sdio_readshared(bus, &sh);
3123 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3124 brcmf_dbg(INFO, "firmware not built with -assert\n");
3125 else if (sh.flags & SDPCM_SHARED_ASSERT)
3126 brcmf_err("assertion in dongle\n");
3128 if (sh.flags & SDPCM_SHARED_TRAP)
3129 brcmf_err("firmware trap in dongle\n");
3134 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3137 struct sdpcm_shared sh;
3139 error = brcmf_sdio_readshared(bus, &sh);
3143 error = brcmf_sdio_assert_info(seq, bus, &sh);
3147 error = brcmf_sdio_trap_info(seq, bus, &sh);
3151 error = brcmf_sdio_dump_console(seq, bus, &sh);
3157 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3159 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3160 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3162 return brcmf_sdio_died_dump(seq, bus);
3165 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3167 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3168 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3169 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3172 "intrcount: %u\nlastintrs: %u\n"
3173 "pollcnt: %u\nregfails: %u\n"
3174 "tx_sderrs: %u\nfcqueued: %u\n"
3175 "rxrtx: %u\nrx_toolong: %u\n"
3176 "rxc_errors: %u\nrx_hdrfail: %u\n"
3177 "rx_badhdr: %u\nrx_badseq: %u\n"
3178 "fc_rcvd: %u\nfc_xoff: %u\n"
3179 "fc_xon: %u\nrxglomfail: %u\n"
3180 "rxglomframes: %u\nrxglompkts: %u\n"
3181 "f2rxhdrs: %u\nf2rxdata: %u\n"
3182 "f2txdata: %u\nf1regdata: %u\n"
3183 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3184 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3185 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3186 sdcnt->intrcount, sdcnt->lastintrs,
3187 sdcnt->pollcnt, sdcnt->regfails,
3188 sdcnt->tx_sderrs, sdcnt->fcqueued,
3189 sdcnt->rxrtx, sdcnt->rx_toolong,
3190 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3191 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3192 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3193 sdcnt->fc_xon, sdcnt->rxglomfail,
3194 sdcnt->rxglomframes, sdcnt->rxglompkts,
3195 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3196 sdcnt->f2txdata, sdcnt->f1regdata,
3197 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3198 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3199 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3204 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3206 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3207 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3209 if (IS_ERR_OR_NULL(dentry))
3212 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3213 brcmf_debugfs_add_entry(drvr, "counters",
3214 brcmf_debugfs_sdio_count_read);
3215 debugfs_create_u32("console_interval", 0644, dentry,
3216 &bus->console_interval);
3219 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3224 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3230 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3236 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3237 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3238 struct brcmf_sdio *bus = sdiodev->bus;
3240 brcmf_dbg(TRACE, "Enter\n");
3242 /* Wait until control frame is available */
3243 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3245 spin_lock_bh(&bus->rxctl_lock);
3247 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3249 buf = bus->rxctl_orig;
3250 bus->rxctl_orig = NULL;
3252 spin_unlock_bh(&bus->rxctl_lock);
3256 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3258 } else if (timeleft == 0) {
3259 brcmf_err("resumed on timeout\n");
3260 brcmf_sdio_checkdied(bus);
3261 } else if (pending) {
3262 brcmf_dbg(CTL, "cancelled\n");
3263 return -ERESTARTSYS;
3265 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3266 brcmf_sdio_checkdied(bus);
3270 bus->sdcnt.rx_ctlpkts++;
3272 bus->sdcnt.rx_ctlerrs++;
3274 return rxlen ? (int)rxlen : -ETIMEDOUT;
3279 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3280 u8 *ram_data, uint ram_sz)
3289 /* read back and verify */
3290 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3292 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3293 /* do not proceed while no memory but */
3299 while (offset < ram_sz) {
3300 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3302 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3304 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3308 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3309 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3324 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3325 u8 *ram_data, uint ram_sz)
3331 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3332 const struct firmware *fw)
3336 brcmf_dbg(TRACE, "Enter\n");
3338 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3339 (u8 *)fw->data, fw->size);
3341 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3342 err, (int)fw->size, bus->ci->rambase);
3343 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3344 (u8 *)fw->data, fw->size))
3350 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3351 void *vars, u32 varsz)
3356 brcmf_dbg(TRACE, "Enter\n");
3358 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3359 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3361 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3362 err, varsz, address);
3363 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3369 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3370 const struct firmware *fw,
3371 void *nvram, u32 nvlen)
3373 int bcmerror = -EFAULT;
3376 sdio_claim_host(bus->sdiodev->func[1]);
3377 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3379 rstvec = get_unaligned_le32(fw->data);
3380 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3382 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3383 release_firmware(fw);
3385 brcmf_err("dongle image file download failed\n");
3386 brcmf_fw_nvram_free(nvram);
3390 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3391 brcmf_fw_nvram_free(nvram);
3393 brcmf_err("dongle nvram file download failed\n");
3397 /* Take arm out of reset */
3398 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3399 brcmf_err("error getting out of ARM core reset\n");
3403 /* Allow full data communication using DPC from now on. */
3404 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3408 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3409 sdio_release_host(bus->sdiodev->func[1]);
3413 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3418 brcmf_dbg(TRACE, "Enter\n");
3420 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3422 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3426 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3427 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3429 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3433 /* Add CMD14 Support */
3434 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3435 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3436 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3439 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3443 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3444 SBSDIO_FORCE_HT, &err);
3446 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3451 bus->sr_enabled = true;
3452 brcmf_dbg(INFO, "SR enabled\n");
3455 /* enable KSO bit */
3456 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3461 brcmf_dbg(TRACE, "Enter\n");
3463 /* KSO bit added in SDIO core rev 12 */
3464 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3467 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3469 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3473 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3474 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3475 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3476 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3479 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3488 static int brcmf_sdio_bus_preinit(struct device *dev)
3490 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3491 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3492 struct brcmf_sdio *bus = sdiodev->bus;
3497 /* the commands below use the terms tx and rx from
3498 * a device perspective, ie. bus:txglom affects the
3499 * bus transfers from device to host.
3501 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3502 /* for sdio core rev < 12, disable txgloming */
3504 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3507 /* otherwise, set txglomalign */
3510 value = sdiodev->pdata->sd_sgentry_align;
3511 /* SDIO ADMA requires at least 32 bit alignment */
3512 value = max_t(u32, value, 4);
3513 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3520 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3521 if (sdiodev->sg_support) {
3522 bus->txglom = false;
3524 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3525 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3526 &value, sizeof(u32));
3528 /* bus:rxglom is allowed to fail */
3532 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3535 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3541 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3543 if (!bus->dpc_triggered) {
3544 bus->dpc_triggered = true;
3545 queue_work(bus->brcmf_wq, &bus->datawork);
3549 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3551 brcmf_dbg(TRACE, "Enter\n");
3554 brcmf_err("bus is null pointer, exiting\n");
3558 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) {
3559 brcmf_err("bus is down. we have nothing to do\n");
3562 /* Count the interrupt call */
3563 bus->sdcnt.intrcount++;
3565 atomic_set(&bus->ipend, 1);
3567 if (brcmf_sdio_intr_rstatus(bus)) {
3568 brcmf_err("failed backplane access\n");
3571 /* Disable additional interrupts (is this needed now)? */
3573 brcmf_err("isr w/o interrupt configured!\n");
3575 bus->dpc_triggered = true;
3576 queue_work(bus->brcmf_wq, &bus->datawork);
3579 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3581 brcmf_dbg(TIMER, "Enter\n");
3583 /* Poll period: check device if appropriate. */
3584 if (!bus->sr_enabled &&
3585 bus->poll && (++bus->polltick >= bus->pollrate)) {
3588 /* Reset poll tick */
3591 /* Check device if no interrupts */
3593 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3595 if (!bus->dpc_triggered) {
3598 sdio_claim_host(bus->sdiodev->func[1]);
3599 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3602 sdio_release_host(bus->sdiodev->func[1]);
3603 intstatus = devpend & (INTR_STATUS_FUNC1 |
3607 /* If there is something, make like the ISR and
3610 bus->sdcnt.pollcnt++;
3611 atomic_set(&bus->ipend, 1);
3613 bus->dpc_triggered = true;
3614 queue_work(bus->brcmf_wq, &bus->datawork);
3618 /* Update interrupt tracking */
3619 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3622 /* Poll for console output periodically */
3623 if (bus->sdiodev->state == BRCMF_SDIOD_DATA &&
3624 bus->console_interval != 0) {
3625 bus->console.count += BRCMF_WD_POLL_MS;
3626 if (bus->console.count >= bus->console_interval) {
3627 bus->console.count -= bus->console_interval;
3628 sdio_claim_host(bus->sdiodev->func[1]);
3629 /* Make sure backplane clock is on */
3630 brcmf_sdio_bus_sleep(bus, false, false);
3631 if (brcmf_sdio_readconsole(bus) < 0)
3633 bus->console_interval = 0;
3634 sdio_release_host(bus->sdiodev->func[1]);
3639 /* On idle timeout clear activity flag and/or turn off clock */
3640 if (!bus->dpc_triggered) {
3642 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3643 (bus->clkstate == CLK_AVAIL)) {
3645 if (bus->idlecount > bus->idletime) {
3646 brcmf_dbg(SDIO, "idle\n");
3647 sdio_claim_host(bus->sdiodev->func[1]);
3648 brcmf_sdio_wd_timer(bus, 0);
3650 brcmf_sdio_bus_sleep(bus, true, false);
3651 sdio_release_host(bus->sdiodev->func[1]);
3661 static void brcmf_sdio_dataworker(struct work_struct *work)
3663 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3666 bus->dpc_running = true;
3668 while (ACCESS_ONCE(bus->dpc_triggered)) {
3669 bus->dpc_triggered = false;
3670 brcmf_sdio_dpc(bus);
3673 bus->dpc_running = false;
3674 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3675 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3676 brcmf_sdiod_try_freeze(bus->sdiodev);
3677 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3682 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3683 struct brcmf_chip *ci, u32 drivestrength)
3685 const struct sdiod_drive_str *str_tab = NULL;
3690 u32 drivestrength_sel = 0;
3694 if (!(ci->cc_caps & CC_CAP_PMU))
3697 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3698 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3699 str_tab = sdiod_drvstr_tab1_1v8;
3700 str_mask = 0x00003800;
3703 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3704 str_tab = sdiod_drvstr_tab6_1v8;
3705 str_mask = 0x00001800;
3708 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3709 /* note: 43143 does not support tristate */
3710 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3711 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3712 str_tab = sdiod_drvstr_tab2_3v3;
3713 str_mask = 0x00000007;
3716 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3717 ci->name, drivestrength);
3719 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3720 str_tab = sdiod_drive_strength_tab5_1v8;
3721 str_mask = 0x00003800;
3725 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3726 ci->name, ci->chiprev, ci->pmurev);
3730 if (str_tab != NULL) {
3731 for (i = 0; str_tab[i].strength != 0; i++) {
3732 if (drivestrength >= str_tab[i].strength) {
3733 drivestrength_sel = str_tab[i].sel;
3737 base = brcmf_chip_get_chipcommon(ci)->base;
3738 addr = CORE_CC_REG(base, chipcontrol_addr);
3739 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3740 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3741 cc_data_temp &= ~str_mask;
3742 drivestrength_sel <<= str_shift;
3743 cc_data_temp |= drivestrength_sel;
3744 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3746 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3747 str_tab[i].strength, drivestrength, cc_data_temp);
3751 static int brcmf_sdio_buscoreprep(void *ctx)
3753 struct brcmf_sdio_dev *sdiodev = ctx;
3757 /* Try forcing SDIO core to do ALPAvail request only */
3758 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3759 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3761 brcmf_err("error writing for HT off\n");
3765 /* If register supported, wait for ALPAvail and then force ALP */
3766 /* This may take up to 15 milliseconds */
3767 clkval = brcmf_sdiod_regrb(sdiodev,
3768 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3770 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3771 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3776 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3777 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3778 !SBSDIO_ALPAV(clkval)),
3779 PMU_MAX_TRANSITION_DLY);
3780 if (!SBSDIO_ALPAV(clkval)) {
3781 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3786 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3787 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3790 /* Also, disable the extra SDIO pull-ups */
3791 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3796 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3799 struct brcmf_sdio_dev *sdiodev = ctx;
3800 struct brcmf_core *core;
3803 /* clear all interrupts */
3804 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3805 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3806 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3809 /* Write reset vector to address 0 */
3810 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3814 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3816 struct brcmf_sdio_dev *sdiodev = ctx;
3819 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3820 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3821 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3822 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3824 val &= ~CID_ID_MASK;
3825 val |= BRCM_CC_4339_CHIP_ID;
3831 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3833 struct brcmf_sdio_dev *sdiodev = ctx;
3835 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3838 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3839 .prepare = brcmf_sdio_buscoreprep,
3840 .activate = brcmf_sdio_buscore_activate,
3841 .read32 = brcmf_sdio_buscore_read32,
3842 .write32 = brcmf_sdio_buscore_write32,
3846 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3854 sdio_claim_host(bus->sdiodev->func[1]);
3856 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3857 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3860 * Force PLL off until brcmf_chip_attach()
3861 * programs PLL control regs
3864 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3865 BRCMF_INIT_CLKCTL1, &err);
3867 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
3868 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3870 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3871 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3872 err, BRCMF_INIT_CLKCTL1, clkctl);
3876 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
3877 if (IS_ERR(bus->ci)) {
3878 brcmf_err("brcmf_chip_attach failed!\n");
3883 if (brcmf_sdio_kso_init(bus)) {
3884 brcmf_err("error enabling KSO\n");
3888 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3889 drivestrength = bus->sdiodev->pdata->drive_strength;
3891 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3892 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3894 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3895 reg_val = brcmf_sdiod_regrb(bus->sdiodev,
3896 SDIO_CCCR_BRCM_CARDCTRL, &err);
3900 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3902 brcmf_sdiod_regwb(bus->sdiodev,
3903 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3907 /* set PMUControl so a backplane reset does PMU state reload */
3908 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
3910 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
3914 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3916 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
3920 sdio_release_host(bus->sdiodev->func[1]);
3922 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3924 /* allocate header buffer */
3925 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3928 /* Locate an appropriately-aligned portion of hdrbuf */
3929 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3932 /* Set the poll and/or interrupt flags */
3941 sdio_release_host(bus->sdiodev->func[1]);
3946 brcmf_sdio_watchdog_thread(void *data)
3948 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3951 allow_signal(SIGTERM);
3952 /* Run until signal received */
3953 brcmf_sdiod_freezer_count(bus->sdiodev);
3955 if (kthread_should_stop())
3957 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3958 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3959 brcmf_sdiod_freezer_count(bus->sdiodev);
3960 brcmf_sdiod_try_freeze(bus->sdiodev);
3962 brcmf_sdio_bus_watchdog(bus);
3963 /* Count the tick for reference */
3964 bus->sdcnt.tickcnt++;
3965 reinit_completion(&bus->watchdog_wait);
3973 brcmf_sdio_watchdog(unsigned long data)
3975 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3977 if (bus->watchdog_tsk) {
3978 complete(&bus->watchdog_wait);
3979 /* Reschedule the watchdog */
3980 if (bus->wd_timer_valid)
3981 mod_timer(&bus->timer,
3982 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
3986 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3987 .stop = brcmf_sdio_bus_stop,
3988 .preinit = brcmf_sdio_bus_preinit,
3989 .txdata = brcmf_sdio_bus_txdata,
3990 .txctl = brcmf_sdio_bus_txctl,
3991 .rxctl = brcmf_sdio_bus_rxctl,
3992 .gettxq = brcmf_sdio_bus_gettxq,
3993 .wowl_config = brcmf_sdio_wowl_config
3996 static void brcmf_sdio_firmware_callback(struct device *dev,
3997 const struct firmware *code,
3998 void *nvram, u32 nvram_len)
4000 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
4001 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
4002 struct brcmf_sdio *bus = sdiodev->bus;
4006 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
4011 /* try to download image and nvram to the dongle */
4012 bus->alp_only = true;
4013 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4016 bus->alp_only = false;
4018 /* Start the watchdog timer */
4019 bus->sdcnt.tickcnt = 0;
4020 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
4022 sdio_claim_host(sdiodev->func[1]);
4024 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4025 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4026 if (bus->clkstate != CLK_AVAIL)
4029 /* Force clocks on backplane to be sure F2 interrupt propagates */
4030 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4032 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4033 (saveclk | SBSDIO_FORCE_HT), &err);
4036 brcmf_err("Failed to force clock for F2: err %d\n", err);
4040 /* Enable function 2 (frame transfers) */
4041 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4042 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4043 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4046 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4048 /* If F2 successfully enabled, set core and enable interrupts */
4050 /* Set up the interrupt mask and enable interrupts */
4051 bus->hostintmask = HOSTINTMASK;
4052 w_sdreg32(bus, bus->hostintmask,
4053 offsetof(struct sdpcmd_regs, hostintmask));
4055 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4057 /* Disable F2 again */
4058 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4062 if (brcmf_chip_sr_capable(bus->ci)) {
4063 brcmf_sdio_sr_init(bus);
4065 /* Restore previous clock setting */
4066 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4071 err = brcmf_sdiod_intr_register(sdiodev);
4073 brcmf_err("intr register failed:%d\n", err);
4076 /* If we didn't come up, turn off backplane clock */
4078 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4080 sdio_release_host(sdiodev->func[1]);
4082 err = brcmf_bus_start(dev);
4084 brcmf_err("dongle is not responding\n");
4090 sdio_release_host(sdiodev->func[1]);
4092 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4093 device_release_driver(dev);
4096 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4099 struct brcmf_sdio *bus;
4100 struct workqueue_struct *wq;
4102 brcmf_dbg(TRACE, "Enter\n");
4104 /* Allocate private bus interface state */
4105 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4109 bus->sdiodev = sdiodev;
4111 skb_queue_head_init(&bus->glom);
4112 bus->txbound = BRCMF_TXBOUND;
4113 bus->rxbound = BRCMF_RXBOUND;
4114 bus->txminmax = BRCMF_TXMINMAX;
4115 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4117 /* platform specific configuration:
4118 * alignments must be at least 4 bytes for ADMA
4120 bus->head_align = ALIGNMENT;
4121 bus->sgentry_align = ALIGNMENT;
4122 if (sdiodev->pdata) {
4123 if (sdiodev->pdata->sd_head_align > ALIGNMENT)
4124 bus->head_align = sdiodev->pdata->sd_head_align;
4125 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
4126 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
4129 /* single-threaded workqueue */
4130 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4131 dev_name(&sdiodev->func[1]->dev));
4133 brcmf_err("insufficient memory to create txworkqueue\n");
4136 brcmf_sdiod_freezer_count(sdiodev);
4137 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4140 /* attempt to attach to the dongle */
4141 if (!(brcmf_sdio_probe_attach(bus))) {
4142 brcmf_err("brcmf_sdio_probe_attach failed\n");
4146 spin_lock_init(&bus->rxctl_lock);
4147 spin_lock_init(&bus->txq_lock);
4148 init_waitqueue_head(&bus->ctrl_wait);
4149 init_waitqueue_head(&bus->dcmd_resp_wait);
4151 /* Set up the watchdog timer */
4152 init_timer(&bus->timer);
4153 bus->timer.data = (unsigned long)bus;
4154 bus->timer.function = brcmf_sdio_watchdog;
4156 /* Initialize watchdog thread */
4157 init_completion(&bus->watchdog_wait);
4158 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4159 bus, "brcmf_wdog/%s",
4160 dev_name(&sdiodev->func[1]->dev));
4161 if (IS_ERR(bus->watchdog_tsk)) {
4162 pr_warn("brcmf_watchdog thread failed to start\n");
4163 bus->watchdog_tsk = NULL;
4165 /* Initialize DPC thread */
4166 bus->dpc_triggered = false;
4167 bus->dpc_running = false;
4169 /* Assign bus interface call back */
4170 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4171 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4172 bus->sdiodev->bus_if->chip = bus->ci->chip;
4173 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4175 /* default sdio bus header length for tx packet */
4176 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4178 /* Attach to the common layer, reserve hdr space */
4179 ret = brcmf_attach(bus->sdiodev->dev);
4181 brcmf_err("brcmf_attach failed\n");
4185 /* Query the F2 block size, set roundup accordingly */
4186 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4187 bus->roundup = min(max_roundup, bus->blocksize);
4189 /* Allocate buffers */
4190 if (bus->sdiodev->bus_if->maxctl) {
4191 bus->sdiodev->bus_if->maxctl += bus->roundup;
4193 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4194 ALIGNMENT) + bus->head_align;
4195 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4196 if (!(bus->rxbuf)) {
4197 brcmf_err("rxbuf allocation failed\n");
4202 sdio_claim_host(bus->sdiodev->func[1]);
4204 /* Disable F2 to clear any intermediate frame state on the dongle */
4205 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4207 bus->rxflow = false;
4209 /* Done with backplane-dependent accesses, can drop clock... */
4210 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4212 sdio_release_host(bus->sdiodev->func[1]);
4214 /* ...and initialize clock/power states */
4215 bus->clkstate = CLK_SDONLY;
4216 bus->idletime = BRCMF_IDLE_INTERVAL;
4217 bus->idleclock = BRCMF_IDLE_ACTIVE;
4220 bus->sr_enabled = false;
4222 brcmf_sdio_debugfs_create(bus);
4223 brcmf_dbg(INFO, "completed!!\n");
4225 ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev);
4229 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4230 sdiodev->fw_name, sdiodev->nvram_name,
4231 brcmf_sdio_firmware_callback);
4233 brcmf_err("async firmware request failed: %d\n", ret);
4240 brcmf_sdio_remove(bus);
4244 /* Detach and free everything */
4245 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4247 brcmf_dbg(TRACE, "Enter\n");
4250 /* De-register interrupt handler */
4251 brcmf_sdiod_intr_unregister(bus->sdiodev);
4253 brcmf_detach(bus->sdiodev->dev);
4255 cancel_work_sync(&bus->datawork);
4257 destroy_workqueue(bus->brcmf_wq);
4260 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4261 sdio_claim_host(bus->sdiodev->func[1]);
4262 brcmf_sdio_wd_timer(bus, 0);
4263 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4264 /* Leave the device in state where it is
4265 * 'passive'. This is done by resetting all
4269 brcmf_chip_set_passive(bus->ci);
4270 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4271 sdio_release_host(bus->sdiodev->func[1]);
4273 brcmf_chip_detach(bus->ci);
4281 brcmf_dbg(TRACE, "Disconnected\n");
4284 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4286 /* Totally stop the timer */
4287 if (!wdtick && bus->wd_timer_valid) {
4288 del_timer_sync(&bus->timer);
4289 bus->wd_timer_valid = false;
4290 bus->save_ms = wdtick;
4294 /* don't start the wd until fw is loaded */
4295 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4299 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4300 if (bus->wd_timer_valid)
4301 /* Stop timer and restart at new value */
4302 del_timer_sync(&bus->timer);
4304 /* Create timer again when watchdog period is
4305 dynamically changed or in the first instance
4307 bus->timer.expires =
4308 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS);
4309 add_timer(&bus->timer);
4312 /* Re arm the timer, at last watchdog period */
4313 mod_timer(&bus->timer,
4314 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
4317 bus->wd_timer_valid = true;
4318 bus->save_ms = wdtick;
4322 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4326 sdio_claim_host(bus->sdiodev->func[1]);
4327 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4328 sdio_release_host(bus->sdiodev->func[1]);