2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/skbuff.h>
26 #define SDIOD_FBR_SIZE 0x100
29 #define SDIO_FUNC_ENABLE_1 0x02
30 #define SDIO_FUNC_ENABLE_2 0x04
33 #define SDIO_FUNC_READY_1 0x02
34 #define SDIO_FUNC_READY_2 0x04
37 #define INTR_STATUS_FUNC1 0x2
38 #define INTR_STATUS_FUNC2 0x4
40 /* Maximum number of I/O funcs */
41 #define SDIOD_MAX_IOFUNCS 7
43 /* mask of register map */
44 #define REG_F0_REG_MASK 0x7FF
45 #define REG_F1_MISC_MASK 0x1FFFF
47 /* as of sdiod rev 0, supports 3 functions */
48 #define SBSDIO_NUM_FUNCTION 3
50 /* function 0 vendor specific CCCR registers */
51 #define SDIO_CCCR_BRCM_CARDCAP 0xf0
52 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
53 #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
54 #define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
55 #define SDIO_CCCR_BRCM_CARDCTRL 0xf1
56 #define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
57 #define SDIO_CCCR_BRCM_SEPINT 0xf2
59 #define SDIO_SEPINT_MASK 0x01
60 #define SDIO_SEPINT_OE 0x02
61 #define SDIO_SEPINT_ACT_HI 0x04
63 /* function 1 miscellaneous registers */
65 /* sprom command and status */
66 #define SBSDIO_SPROM_CS 0x10000
67 /* sprom info register */
68 #define SBSDIO_SPROM_INFO 0x10001
69 /* sprom indirect access data byte 0 */
70 #define SBSDIO_SPROM_DATA_LOW 0x10002
71 /* sprom indirect access data byte 1 */
72 #define SBSDIO_SPROM_DATA_HIGH 0x10003
73 /* sprom indirect access addr byte 0 */
74 #define SBSDIO_SPROM_ADDR_LOW 0x10004
75 /* sprom indirect access addr byte 0 */
76 #define SBSDIO_SPROM_ADDR_HIGH 0x10005
77 /* xtal_pu (gpio) output */
78 #define SBSDIO_CHIP_CTRL_DATA 0x10006
79 /* xtal_pu (gpio) enable */
80 #define SBSDIO_CHIP_CTRL_EN 0x10007
81 /* rev < 7, watermark for sdio device */
82 #define SBSDIO_WATERMARK 0x10008
83 /* control busy signal generation */
84 #define SBSDIO_DEVICE_CTL 0x10009
86 /* SB Address Window Low (b15) */
87 #define SBSDIO_FUNC1_SBADDRLOW 0x1000A
88 /* SB Address Window Mid (b23:b16) */
89 #define SBSDIO_FUNC1_SBADDRMID 0x1000B
90 /* SB Address Window High (b31:b24) */
91 #define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
92 /* Frame Control (frame term/abort) */
93 #define SBSDIO_FUNC1_FRAMECTRL 0x1000D
94 /* ChipClockCSR (ALP/HT ctl/status) */
95 #define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
96 /* SdioPullUp (on cmd, d0-d2) */
97 #define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
98 /* Write Frame Byte Count Low */
99 #define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
100 /* Write Frame Byte Count High */
101 #define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
102 /* Read Frame Byte Count Low */
103 #define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
104 /* Read Frame Byte Count High */
105 #define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
106 /* MesBusyCtl (rev 11) */
107 #define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
108 /* Sdio Core Rev 12 */
109 #define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
110 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
111 #define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
112 #define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
113 #define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
114 #define SBSDIO_FUNC1_SLEEPCSR 0x1001F
115 #define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
116 #define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
117 #define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
118 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
119 #define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
121 #define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
122 #define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
124 /* function 1 OCP space */
126 /* sb offset addr is <= 15 bits, 32k */
127 #define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
128 #define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
129 /* with b15, maps to 32-bit SB access */
130 #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
132 /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
134 #define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
135 #define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
136 #define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
137 /* Address bits from SBADDR regs */
138 #define SBSDIO_SBWINDOW_MASK 0xffff8000
140 #define SDIOH_READ 0 /* Read request */
141 #define SDIOH_WRITE 1 /* Write request */
143 #define SDIOH_DATA_FIX 0 /* Fixed addressing */
144 #define SDIOH_DATA_INC 1 /* Incremental addressing */
146 /* internal return code */
150 /* Packet alignment for most efficient SDIO (can change based on platform) */
151 #define BRCMF_SDALIGN (1 << 6)
153 /* watchdog polling interval in ms */
154 #define BRCMF_WD_POLL_MS 10
164 struct brcmf_sdio_dev {
165 struct sdio_func *func[SDIO_MAX_FUNCS];
166 u8 num_funcs; /* Supported funcs on client */
167 u32 sbwad; /* Save backplane window address */
168 struct brcmf_sdio *bus;
169 atomic_t suspend; /* suspend flag */
170 wait_queue_head_t request_word_wait;
171 wait_queue_head_t request_buffer_wait;
173 struct brcmf_bus *bus_if;
174 struct brcmfmac_sdio_platform_data *pdata;
175 bool oob_irq_requested;
176 bool irq_en; /* irq enable flags */
177 spinlock_t irq_en_lock;
178 bool irq_wake; /* irq wake enable flags */
180 uint max_request_size;
181 ushort max_segment_count;
182 uint max_segment_size;
184 struct sg_table sgtable;
187 /* sdio core registers */
189 u32 corecontrol; /* 0x00, rev8 */
190 u32 corestatus; /* rev8 */
192 u32 biststatus; /* rev8 */
195 u16 pcmciamesportaladdr; /* 0x010, rev8 */
197 u16 pcmciamesportalmask; /* rev8 */
199 u16 pcmciawrframebc; /* rev8 */
201 u16 pcmciaunderflowtimer; /* rev8 */
205 u32 intstatus; /* 0x020, rev8 */
206 u32 hostintmask; /* rev8 */
207 u32 intmask; /* rev8 */
208 u32 sbintstatus; /* rev8 */
209 u32 sbintmask; /* rev8 */
210 u32 funcintmask; /* rev4 */
212 u32 tosbmailbox; /* 0x040, rev8 */
213 u32 tohostmailbox; /* rev8 */
214 u32 tosbmailboxdata; /* rev8 */
215 u32 tohostmailboxdata; /* rev8 */
217 /* synchronized access to registers in SDIO clock domain */
218 u32 sdioaccess; /* 0x050, rev8 */
221 /* PCMCIA frame control */
222 u8 pcmciaframectrl; /* 0x060, rev8 */
224 u8 pcmciawatermark; /* rev8 */
227 /* interrupt batching control */
228 u32 intrcvlazy; /* 0x100, rev8 */
232 u32 cmd52rd; /* 0x110, rev8 */
233 u32 cmd52wr; /* rev8 */
234 u32 cmd53rd; /* rev8 */
235 u32 cmd53wr; /* rev8 */
236 u32 abort; /* rev8 */
237 u32 datacrcerror; /* rev8 */
238 u32 rdoutofsync; /* rev8 */
239 u32 wroutofsync; /* rev8 */
240 u32 writebusy; /* rev8 */
241 u32 readwait; /* rev8 */
242 u32 readterm; /* rev8 */
243 u32 writeterm; /* rev8 */
245 u32 clockctlstatus; /* rev8 */
248 u32 PAD[128]; /* DMA engines */
250 /* SDIO/PCMCIA CIS region */
251 char cis[512]; /* 0x400-0x5ff, rev6 */
253 /* PCMCIA function control registers */
254 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
257 /* PCMCIA backplane access */
258 u16 backplanecsr; /* 0x76E, rev6 */
259 u16 backplaneaddr0; /* rev6 */
260 u16 backplaneaddr1; /* rev6 */
261 u16 backplaneaddr2; /* rev6 */
262 u16 backplaneaddr3; /* rev6 */
263 u16 backplanedata0; /* rev6 */
264 u16 backplanedata1; /* rev6 */
265 u16 backplanedata2; /* rev6 */
266 u16 backplanedata3; /* rev6 */
269 /* sprom "size" & "blank" info */
270 u16 spromstatus; /* 0x7BE, rev2 */
276 /* Register/deregister interrupt handler. */
277 int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
278 int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
280 /* sdio device register access interface */
281 u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
282 u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
283 void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
285 void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
288 /* Buffer transfer to/from device (client) core via cmd53.
289 * fn: function number
290 * flags: backplane width, address increment, sync/async
291 * buf: pointer to memory data buffer
292 * nbytes: number of bytes to transfer to/from buf
293 * pkt: pointer to packet associated with buf (if any)
294 * complete: callback function for command completion (async only)
295 * handle: handle for completion callback (first arg in callback)
296 * Returns 0 or error code.
297 * NOTE: Async operation is not currently supported.
299 int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
300 struct sk_buff_head *pktq);
301 int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
303 int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
304 int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
305 int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
306 struct sk_buff_head *pktq, uint totlen);
310 /* Four-byte target (backplane) width (vs. two-byte) */
311 #define SDIO_REQ_4BYTE 0x1
312 /* Fixed address (FIFO) (vs. incrementing address) */
313 #define SDIO_REQ_FIXED 0x2
315 /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
316 * rw: read or write (0/1)
317 * addr: direct SDIO address
318 * buf: pointer to memory data buffer
319 * nbytes: number of bytes to transfer to/from buf
320 * Returns 0 or error code.
322 int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
323 u8 *data, uint size);
325 /* Issue an abort to the specified function */
326 int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
328 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
329 void brcmf_sdio_remove(struct brcmf_sdio *bus);
330 void brcmf_sdio_isr(struct brcmf_sdio *bus);
332 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
334 #endif /* _BRCM_SDH_H_ */