drivers/net/wireless/brcm80211/brcmsmac/main.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  12  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  14  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  15  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/pci_ids.h>
  21 #include <linux/if_ether.h>
  22 #include <net/cfg80211.h>
  23 #include <net/mac80211.h>
  24 #include <brcm_hw_ids.h>
  25 #include <aiutils.h>
  26 #include <chipcommon.h>
  27 #include "rate.h"
  28 #include "scb.h"
  29 #include "phy/phy_hal.h"
  30 #include "channel.h"
  31 #include "antsel.h"
  32 #include "stf.h"
  33 #include "ampdu.h"
  34 #include "mac80211_if.h"
  35 #include "ucode_loader.h"
  36 #include "main.h"
  37 #include "soc.h"
  38 #include "dma.h"
  39 #include "debug.h"
  40 #include "brcms_trace_events.h"
  41
  42 /* watchdog timer, in unit of ms */
  43 #define TIMER_INTERVAL_WATCHDOG         1000
  44 /* radio monitor timer, in unit of ms */
  45 #define TIMER_INTERVAL_RADIOCHK         800
  46
  47 /* beacon interval, in unit of 1024TU */
  48 #define BEACON_INTERVAL_DEFAULT         100
  49
  50 /* n-mode support capability */
  51 /* 2x2 includes both 1x1 & 2x2 devices
  52  * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
  53  * control it independently
  54  */
  55 #define WL_11N_2x2                      1
  56 #define WL_11N_3x3                      3
  57 #define WL_11N_4x4                      4
  58
  59 #define EDCF_ACI_MASK                   0x60
  60 #define EDCF_ACI_SHIFT                  5
  61 #define EDCF_ECWMIN_MASK                0x0f
  62 #define EDCF_ECWMAX_SHIFT               4
  63 #define EDCF_AIFSN_MASK                 0x0f
  64 #define EDCF_AIFSN_MAX                  15
  65 #define EDCF_ECWMAX_MASK                0xf0
  66
  67 #define EDCF_AC_BE_TXOP_STA             0x0000
  68 #define EDCF_AC_BK_TXOP_STA             0x0000
  69 #define EDCF_AC_VO_ACI_STA              0x62
  70 #define EDCF_AC_VO_ECW_STA              0x32
  71 #define EDCF_AC_VI_ACI_STA              0x42
  72 #define EDCF_AC_VI_ECW_STA              0x43
  73 #define EDCF_AC_BK_ECW_STA              0xA4
  74 #define EDCF_AC_VI_TXOP_STA             0x005e
  75 #define EDCF_AC_VO_TXOP_STA             0x002f
  76 #define EDCF_AC_BE_ACI_STA              0x03
  77 #define EDCF_AC_BE_ECW_STA              0xA4
  78 #define EDCF_AC_BK_ACI_STA              0x27
  79 #define EDCF_AC_VO_TXOP_AP              0x002f
  80
  81 #define EDCF_TXOP2USEC(txop)            ((txop) << 5)
  82 #define EDCF_ECW2CW(exp)                ((1 << (exp)) - 1)
  83
  84 #define APHY_SYMBOL_TIME                4
  85 #define APHY_PREAMBLE_TIME              16
  86 #define APHY_SIGNAL_TIME                4
  87 #define APHY_SIFS_TIME                  16
  88 #define APHY_SERVICE_NBITS              16
  89 #define APHY_TAIL_NBITS                 6
  90 #define BPHY_SIFS_TIME                  10
  91 #define BPHY_PLCP_SHORT_TIME            96
  92
  93 #define PREN_PREAMBLE                   24
  94 #define PREN_MM_EXT                     12
  95 #define PREN_PREAMBLE_EXT               4
  96
  97 #define DOT11_MAC_HDR_LEN               24
  98 #define DOT11_ACK_LEN                   10
  99 #define DOT11_BA_LEN                    4
 100 #define DOT11_OFDM_SIGNAL_EXTENSION     6
 101 #define DOT11_MIN_FRAG_LEN              256
 102 #define DOT11_RTS_LEN                   16
 103 #define DOT11_CTS_LEN                   10
 104 #define DOT11_BA_BITMAP_LEN             128
 105 #define DOT11_MAXNUMFRAGS               16
 106 #define DOT11_MAX_FRAG_LEN              2346
 107
 108 #define BPHY_PLCP_TIME                  192
 109 #define RIFS_11N_TIME                   2
 110
 111 /* length of the BCN template area */
 112 #define BCN_TMPL_LEN                    512
 113
 114 /* brcms_bss_info flag bit values */
 115 #define BRCMS_BSS_HT                    0x0020  /* BSS is HT (MIMO) capable */
 116
 117 /* chip rx buffer offset */
 118 #define BRCMS_HWRXOFF                   38
 119
 120 /* rfdisable delay timer 500 ms, runs of ALP clock */
 121 #define RFDISABLE_DEFAULT               10000000
 122
 123 #define BRCMS_TEMPSENSE_PERIOD          10      /* 10 second timeout */
 124
 125 /* synthpu_dly times in us */
 126 #define SYNTHPU_DLY_APHY_US             3700
 127 #define SYNTHPU_DLY_BPHY_US             1050
 128 #define SYNTHPU_DLY_NPHY_US             2048
 129 #define SYNTHPU_DLY_LPPHY_US            300
 130
 131 #define ANTCNT                          10      /* vanilla M_MAX_ANTCNT val */
 132
 133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
 134 #define EDCF_SHORT_S                    0
 135 #define EDCF_SFB_S                      4
 136 #define EDCF_LONG_S                     8
 137 #define EDCF_LFB_S                      12
 138 #define EDCF_SHORT_M                    BITFIELD_MASK(4)
 139 #define EDCF_SFB_M                      BITFIELD_MASK(4)
 140 #define EDCF_LONG_M                     BITFIELD_MASK(4)
 141 #define EDCF_LFB_M                      BITFIELD_MASK(4)
 142
 143 #define RETRY_SHORT_DEF                 7       /* Default Short retry Limit */
 144 #define RETRY_SHORT_MAX                 255     /* Maximum Short retry Limit */
 145 #define RETRY_LONG_DEF                  4       /* Default Long retry count */
 146 #define RETRY_SHORT_FB                  3       /* Short count for fb rate */
 147 #define RETRY_LONG_FB                   2       /* Long count for fb rate */
 148
 149 #define APHY_CWMIN                      15
 150 #define PHY_CWMAX                       1023
 151
 152 #define EDCF_AIFSN_MIN                  1
 153
 154 #define FRAGNUM_MASK                    0xF
 155
 156 #define APHY_SLOT_TIME                  9
 157 #define BPHY_SLOT_TIME                  20
 158
 159 #define WL_SPURAVOID_OFF                0
 160 #define WL_SPURAVOID_ON1                1
 161 #define WL_SPURAVOID_ON2                2
 162
 163 /* invalid core flags, use the saved coreflags */
 164 #define BRCMS_USE_COREFLAGS             0xffffffff
 165
 166 /* values for PLCPHdr_override */
 167 #define BRCMS_PLCP_AUTO                 -1
 168 #define BRCMS_PLCP_SHORT                0
 169 #define BRCMS_PLCP_LONG                 1
 170
 171 /* values for g_protection_override and n_protection_override */
 172 #define BRCMS_PROTECTION_AUTO           -1
 173 #define BRCMS_PROTECTION_OFF            0
 174 #define BRCMS_PROTECTION_ON             1
 175 #define BRCMS_PROTECTION_MMHDR_ONLY     2
 176 #define BRCMS_PROTECTION_CTS_ONLY       3
 177
 178 /* values for g_protection_control and n_protection_control */
 179 #define BRCMS_PROTECTION_CTL_OFF        0
 180 #define BRCMS_PROTECTION_CTL_LOCAL      1
 181 #define BRCMS_PROTECTION_CTL_OVERLAP    2
 182
 183 /* values for n_protection */
 184 #define BRCMS_N_PROTECTION_OFF          0
 185 #define BRCMS_N_PROTECTION_OPTIONAL     1
 186 #define BRCMS_N_PROTECTION_20IN40       2
 187 #define BRCMS_N_PROTECTION_MIXEDMODE    3
 188
 189 /* values for band specific 40MHz capabilities */
 190 #define BRCMS_N_BW_20ALL                0
 191 #define BRCMS_N_BW_40ALL                1
 192 #define BRCMS_N_BW_20IN2G_40IN5G        2
 193
 194 /* bitflags for SGI support (sgi_rx iovar) */
 195 #define BRCMS_N_SGI_20                  0x01
 196 #define BRCMS_N_SGI_40                  0x02
 197
 198 /* defines used by the nrate iovar */
 199 /* MSC in use,indicates b0-6 holds an mcs */
 200 #define NRATE_MCS_INUSE                 0x00000080
 201 /* rate/mcs value */
 202 #define NRATE_RATE_MASK                 0x0000007f
 203 /* stf mode mask: siso, cdd, stbc, sdm */
 204 #define NRATE_STF_MASK                  0x0000ff00
 205 /* stf mode shift */
 206 #define NRATE_STF_SHIFT                 8
 207 /* bit indicate to override mcs only */
 208 #define NRATE_OVERRIDE_MCS_ONLY         0x40000000
 209 #define NRATE_SGI_MASK                  0x00800000      /* sgi mode */
 210 #define NRATE_SGI_SHIFT                 23              /* sgi mode */
 211 #define NRATE_LDPC_CODING               0x00400000      /* adv coding in use */
 212 #define NRATE_LDPC_SHIFT                22              /* ldpc shift */
 213
 214 #define NRATE_STF_SISO                  0               /* stf mode SISO */
 215 #define NRATE_STF_CDD                   1               /* stf mode CDD */
 216 #define NRATE_STF_STBC                  2               /* stf mode STBC */
 217 #define NRATE_STF_SDM                   3               /* stf mode SDM */
 218
 219 #define MAX_DMA_SEGS                    4
 220
 221 /* # of entries in Tx FIFO */
 222 #define NTXD                            64
 223 /* Max # of entries in Rx FIFO based on 4kb page size */
 224 #define NRXD                            256
 225
 226 /* Amount of headroom to leave in Tx FIFO */
 227 #define TX_HEADROOM                     4
 228
 229 /* try to keep this # rbufs posted to the chip */
 230 #define NRXBUFPOST                      32
 231
 232 /* max # frames to process in brcms_c_recv() */
 233 #define RXBND                           8
 234 /* max # tx status to process in wlc_txstatus() */
 235 #define TXSBND                          8
 236
 237 /* brcmu_format_flags() bit description structure */
 238 struct brcms_c_bit_desc {
 239         u32 bit;
 240         const char *name;
 241 };
 242
 243 /*
 244  * The following table lists the buffer memory allocated to xmt fifos in HW.
 245  * the size is in units of 256bytes(one block), total size is HW dependent
 246  * ucode has default fifo partition, sw can overwrite if necessary
 247  *
 248  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 249  * the twiki is updated before making changes.
 250  */
 251
 252 /* Starting corerev for the fifo size table */
 253 #define XMTFIFOTBL_STARTREV     17
 254
 255 struct d11init {
 256         __le16 addr;
 257         __le16 size;
 258         __le32 value;
 259 };
 260
 261 struct edcf_acparam {
 262         u8 ACI;
 263         u8 ECW;
 264         u16 TXOP;
 265 } __packed;
 266
 267 /* debug/trace */
 268 uint brcm_msg_level;
 269
 270 /* TX FIFO number to WME/802.1E Access Category */
 271 static const u8 wme_fifo2ac[] = {
 272         IEEE80211_AC_BK,
 273         IEEE80211_AC_BE,
 274         IEEE80211_AC_VI,
 275         IEEE80211_AC_VO,
 276         IEEE80211_AC_BE,
 277         IEEE80211_AC_BE
 278 };
 279
 280 /* ieee80211 Access Category to TX FIFO number */
 281 static const u8 wme_ac2fifo[] = {
 282         TX_AC_VO_FIFO,
 283         TX_AC_VI_FIFO,
 284         TX_AC_BE_FIFO,
 285         TX_AC_BK_FIFO
 286 };
 287
 288 static const u16 xmtfifo_sz[][NFIFO] = {
 289         /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
 290         {20, 192, 192, 21, 17, 5},
 291         /* corerev 18: */
 292         {0, 0, 0, 0, 0, 0},
 293         /* corerev 19: */
 294         {0, 0, 0, 0, 0, 0},
 295         /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 296         {20, 192, 192, 21, 17, 5},
 297         /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 298         {9, 58, 22, 14, 14, 5},
 299         /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 300         {20, 192, 192, 21, 17, 5},
 301         /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 302         {20, 192, 192, 21, 17, 5},
 303         /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 304         {9, 58, 22, 14, 14, 5},
 305         /* corerev 25: */
 306         {0, 0, 0, 0, 0, 0},
 307         /* corerev 26: */
 308         {0, 0, 0, 0, 0, 0},
 309         /* corerev 27: */
 310         {0, 0, 0, 0, 0, 0},
 311         /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
 312         {9, 58, 22, 14, 14, 5},
 313 };
 314
 315 #ifdef DEBUG
 316 static const char * const fifo_names[] = {
 317         "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
 318 #else
 319 static const char fifo_names[6][0];
 320 #endif
 321
 322 #ifdef DEBUG
 323 /* pointer to most recently allocated wl/wlc */
 324 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
 325 #endif
 326
 327 /* Mapping of ieee80211 AC numbers to tx fifos */
 328 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
 329         [IEEE80211_AC_VO]       = TX_AC_VO_FIFO,
 330         [IEEE80211_AC_VI]       = TX_AC_VI_FIFO,
 331         [IEEE80211_AC_BE]       = TX_AC_BE_FIFO,
 332         [IEEE80211_AC_BK]       = TX_AC_BK_FIFO,
 333 };
 334
 335 /* Mapping of tx fifos to ieee80211 AC numbers */
 336 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
 337         [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
 338         [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
 339         [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
 340         [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
 341 };
 342
 343 static u8 brcms_ac_to_fifo(u8 ac)
 344 {
 345         if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
 346                 return TX_AC_BE_FIFO;
 347         return ac_to_fifo_mapping[ac];
 348 }
 349
 350 static u8 brcms_fifo_to_ac(u8 fifo)
 351 {
 352         if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
 353                 return IEEE80211_AC_BE;
 354         return fifo_to_ac_mapping[fifo];
 355 }
 356
 357 /* Find basic rate for a given rate */
 358 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
 359 {
 360         if (is_mcs_rate(rspec))
 361                 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
 362                        .leg_ofdm];
 363         return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
 364 }
 365
 366 static u16 frametype(u32 rspec, u8 mimoframe)
 367 {
 368         if (is_mcs_rate(rspec))
 369                 return mimoframe;
 370         return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
 371 }
 372
 373 /* currently the best mechanism for determining SIFS is the band in use */
 374 static u16 get_sifs(struct brcms_band *band)
 375 {
 376         return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
 377                                  BPHY_SIFS_TIME;
 378 }
 379
 380 /*
 381  * Detect Card removed.
 382  * Even checking an sbconfig register read will not false trigger when the core
 383  * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
 384  * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
 385  * reg with fixed 0/1 pattern (some platforms return all 0).
 386  * If clocks are present, call the sb routine which will figure out if the
 387  * device is removed.
 388  */
 389 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
 390 {
 391         u32 macctrl;
 392
 393         if (!wlc->hw->clk)
 394                 return ai_deviceremoved(wlc->hw->sih);
 395         macctrl = bcma_read32(wlc->hw->d11core,
 396                               D11REGOFFS(maccontrol));
 397         return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
 398 }
 399
 400 /* sum the individual fifo tx pending packet counts */
 401 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
 402 {
 403         int i;
 404         int pending = 0;
 405
 406         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
 407                 if (wlc->hw->di[i])
 408                         pending += dma_txpending(wlc->hw->di[i]);
 409         return pending;
 410 }
 411
 412 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
 413 {
 414         return wlc->pub->_nbands > 1 && !wlc->bandlocked;
 415 }
 416
 417 static int brcms_chspec_bw(u16 chanspec)
 418 {
 419         if (CHSPEC_IS40(chanspec))
 420                 return BRCMS_40_MHZ;
 421         if (CHSPEC_IS20(chanspec))
 422                 return BRCMS_20_MHZ;
 423
 424         return BRCMS_10_MHZ;
 425 }
 426
 427 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
 428 {
 429         if (cfg == NULL)
 430                 return;
 431
 432         kfree(cfg->current_bss);
 433         kfree(cfg);
 434 }
 435
 436 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
 437 {
 438         if (wlc == NULL)
 439                 return;
 440
 441         brcms_c_bsscfg_mfree(wlc->bsscfg);
 442         kfree(wlc->pub);
 443         kfree(wlc->modulecb);
 444         kfree(wlc->default_bss);
 445         kfree(wlc->protection);
 446         kfree(wlc->stf);
 447         kfree(wlc->bandstate[0]);
 448         kfree(wlc->corestate->macstat_snapshot);
 449         kfree(wlc->corestate);
 450         kfree(wlc->hw->bandstate[0]);
 451         kfree(wlc->hw);
 452         if (wlc->beacon)
 453                 dev_kfree_skb_any(wlc->beacon);
 454         if (wlc->probe_resp)
 455                 dev_kfree_skb_any(wlc->probe_resp);
 456
 457         /* free the wlc */
 458         kfree(wlc);
 459         wlc = NULL;
 460 }
 461
 462 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
 463 {
 464         struct brcms_bss_cfg *cfg;
 465
 466         cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
 467         if (cfg == NULL)
 468                 goto fail;
 469
 470         cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
 471         if (cfg->current_bss == NULL)
 472                 goto fail;
 473
 474         return cfg;
 475
 476  fail:
 477         brcms_c_bsscfg_mfree(cfg);
 478         return NULL;
 479 }
 480
 481 static struct brcms_c_info *
 482 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
 483 {
 484         struct brcms_c_info *wlc;
 485
 486         wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
 487         if (wlc == NULL) {
 488                 *err = 1002;
 489                 goto fail;
 490         }
 491
 492         /* allocate struct brcms_c_pub state structure */
 493         wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
 494         if (wlc->pub == NULL) {
 495                 *err = 1003;
 496                 goto fail;
 497         }
 498         wlc->pub->wlc = wlc;
 499
 500         /* allocate struct brcms_hardware state structure */
 501
 502         wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
 503         if (wlc->hw == NULL) {
 504                 *err = 1005;
 505                 goto fail;
 506         }
 507         wlc->hw->wlc = wlc;
 508
 509         wlc->hw->bandstate[0] =
 510                 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
 511         if (wlc->hw->bandstate[0] == NULL) {
 512                 *err = 1006;
 513                 goto fail;
 514         } else {
 515                 int i;
 516
 517                 for (i = 1; i < MAXBANDS; i++)
 518                         wlc->hw->bandstate[i] = (struct brcms_hw_band *)
 519                             ((unsigned long)wlc->hw->bandstate[0] +
 520                              (sizeof(struct brcms_hw_band) * i));
 521         }
 522
 523         wlc->modulecb =
 524                 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
 525         if (wlc->modulecb == NULL) {
 526                 *err = 1009;
 527                 goto fail;
 528         }
 529
 530         wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
 531         if (wlc->default_bss == NULL) {
 532                 *err = 1010;
 533                 goto fail;
 534         }
 535
 536         wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
 537         if (wlc->bsscfg == NULL) {
 538                 *err = 1011;
 539                 goto fail;
 540         }
 541
 542         wlc->protection = kzalloc(sizeof(struct brcms_protection),
 543                                   GFP_ATOMIC);
 544         if (wlc->protection == NULL) {
 545                 *err = 1016;
 546                 goto fail;
 547         }
 548
 549         wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
 550         if (wlc->stf == NULL) {
 551                 *err = 1017;
 552                 goto fail;
 553         }
 554
 555         wlc->bandstate[0] =
 556                 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
 557         if (wlc->bandstate[0] == NULL) {
 558                 *err = 1025;
 559                 goto fail;
 560         } else {
 561                 int i;
 562
 563                 for (i = 1; i < MAXBANDS; i++)
 564                         wlc->bandstate[i] = (struct brcms_band *)
 565                                 ((unsigned long)wlc->bandstate[0]
 566                                 + (sizeof(struct brcms_band)*i));
 567         }
 568
 569         wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
 570         if (wlc->corestate == NULL) {
 571                 *err = 1026;
 572                 goto fail;
 573         }
 574
 575         wlc->corestate->macstat_snapshot =
 576                 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
 577         if (wlc->corestate->macstat_snapshot == NULL) {
 578                 *err = 1027;
 579                 goto fail;
 580         }
 581
 582         return wlc;
 583
 584  fail:
 585         brcms_c_detach_mfree(wlc);
 586         return NULL;
 587 }
 588
 589 /*
 590  * Update the slot timing for standard 11b/g (20us slots)
 591  * or shortslot 11g (9us slots)
 592  * The PSM needs to be suspended for this call.
 593  */
 594 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
 595                                         bool shortslot)
 596 {
 597         struct bcma_device *core = wlc_hw->d11core;
 598
 599         if (shortslot) {
 600                 /* 11g short slot: 11a timing */
 601                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
 602                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 603         } else {
 604                 /* 11g long slot: 11b timing */
 605                 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
 606                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 607         }
 608 }
 609
 610 /*
 611  * calculate frame duration of a given rate and length, return
 612  * time in usec unit
 613  */
 614 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
 615                                     u8 preamble_type, uint mac_len)
 616 {
 617         uint nsyms, dur = 0, Ndps, kNdps;
 618         uint rate = rspec2rate(ratespec);
 619
 620         if (rate == 0) {
 621                 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
 622                           wlc->pub->unit);
 623                 rate = BRCM_RATE_1M;
 624         }
 625
 626         if (is_mcs_rate(ratespec)) {
 627                 uint mcs = ratespec & RSPEC_RATE_MASK;
 628                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
 629
 630                 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
 631                 if (preamble_type == BRCMS_MM_PREAMBLE)
 632                         dur += PREN_MM_EXT;
 633                 /* 1000Ndbps = kbps * 4 */
 634                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
 635                                    rspec_issgi(ratespec)) * 4;
 636
 637                 if (rspec_stc(ratespec) == 0)
 638                         nsyms =
 639                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
 640                                   APHY_TAIL_NBITS) * 1000, kNdps);
 641                 else
 642                         /* STBC needs to have even number of symbols */
 643                         nsyms =
 644                             2 *
 645                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
 646                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
 647
 648                 dur += APHY_SYMBOL_TIME * nsyms;
 649                 if (wlc->band->bandtype == BRCM_BAND_2G)
 650                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
 651         } else if (is_ofdm_rate(rate)) {
 652                 dur = APHY_PREAMBLE_TIME;
 653                 dur += APHY_SIGNAL_TIME;
 654                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
 655                 Ndps = rate * 2;
 656                 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
 657                 nsyms =
 658                     CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
 659                          Ndps);
 660                 dur += APHY_SYMBOL_TIME * nsyms;
 661                 if (wlc->band->bandtype == BRCM_BAND_2G)
 662                         dur += DOT11_OFDM_SIGNAL_EXTENSION;
 663         } else {
 664                 /*
 665                  * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
 666                  * will divide out
 667                  */
 668                 mac_len = mac_len * 8 * 2;
 669                 /* calc ceiling of bits/rate = microseconds of air time */
 670                 dur = (mac_len + rate - 1) / rate;
 671                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
 672                         dur += BPHY_PLCP_SHORT_TIME;
 673                 else
 674                         dur += BPHY_PLCP_TIME;
 675         }
 676         return dur;
 677 }
 678
 679 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
 680                                 const struct d11init *inits)
 681 {
 682         struct bcma_device *core = wlc_hw->d11core;
 683         int i;
 684         uint offset;
 685         u16 size;
 686         u32 value;
 687
 688         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
 689
 690         for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
 691                 size = le16_to_cpu(inits[i].size);
 692                 offset = le16_to_cpu(inits[i].addr);
 693                 value = le32_to_cpu(inits[i].value);
 694                 if (size == 2)
 695                         bcma_write16(core, offset, value);
 696                 else if (size == 4)
 697                         bcma_write32(core, offset, value);
 698                 else
 699                         break;
 700         }
 701 }
 702
 703 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
 704 {
 705         u8 idx;
 706         u16 addr[] = {
 707                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
 708                 M_HOST_FLAGS5
 709         };
 710
 711         for (idx = 0; idx < MHFMAX; idx++)
 712                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
 713 }
 714
 715 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
 716 {
 717         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
 718
 719         /* init microcode host flags */
 720         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 721
 722         /* do band-specific ucode IHR, SHM, and SCR inits */
 723         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
 724                 if (BRCMS_ISNPHY(wlc_hw->band))
 725                         brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
 726                 else
 727                         brcms_err(wlc_hw->d11core,
 728                                   "%s: wl%d: unsupported phy in corerev %d\n",
 729                                   __func__, wlc_hw->unit,
 730                                   wlc_hw->corerev);
 731         } else {
 732                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 733                         if (BRCMS_ISLCNPHY(wlc_hw->band))
 734                                 brcms_c_write_inits(wlc_hw,
 735                                                     ucode->d11lcn0bsinitvals24);
 736                         else
 737                                 brcms_err(wlc_hw->d11core,
 738                                           "%s: wl%d: unsupported phy in core rev %d\n",
 739                                           __func__, wlc_hw->unit,
 740                                           wlc_hw->corerev);
 741                 } else {
 742                         brcms_err(wlc_hw->d11core,
 743                                   "%s: wl%d: unsupported corerev %d\n",
 744                                   __func__, wlc_hw->unit, wlc_hw->corerev);
 745                 }
 746         }
 747 }
 748
 749 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
 750 {
 751         struct bcma_device *core = wlc_hw->d11core;
 752         u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
 753
 754         bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
 755 }
 756
 757 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
 758 {
 759         brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
 760
 761         wlc_hw->phyclk = clk;
 762
 763         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
 764
 765                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
 766                                    (SICF_PRST | SICF_FGC));
 767                 udelay(1);
 768                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
 769                 udelay(1);
 770
 771         } else {                /* take phy out of reset */
 772
 773                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
 774                 udelay(1);
 775                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
 776                 udelay(1);
 777
 778         }
 779 }
 780
 781 /* low-level band switch utility routine */
 782 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
 783 {
 784         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
 785                            bandunit);
 786
 787         wlc_hw->band = wlc_hw->bandstate[bandunit];
 788
 789         /*
 790          * BMAC_NOTE:
 791          *   until we eliminate need for wlc->band refs in low level code
 792          */
 793         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
 794
 795         /* set gmode core flag */
 796         if (wlc_hw->sbclk && !wlc_hw->noreset) {
 797                 u32 gmode = 0;
 798
 799                 if (bandunit == 0)
 800                         gmode = SICF_GMODE;
 801
 802                 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
 803         }
 804 }
 805
 806 /* switch to new band but leave it inactive */
 807 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
 808 {
 809         struct brcms_hardware *wlc_hw = wlc->hw;
 810         u32 macintmask;
 811         u32 macctrl;
 812
 813         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
 814         macctrl = bcma_read32(wlc_hw->d11core,
 815                               D11REGOFFS(maccontrol));
 816         WARN_ON((macctrl & MCTL_EN_MAC) != 0);
 817
 818         /* disable interrupts */
 819         macintmask = brcms_intrsoff(wlc->wl);
 820
 821         /* radio off */
 822         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 823
 824         brcms_b_core_phy_clk(wlc_hw, OFF);
 825
 826         brcms_c_setxband(wlc_hw, bandunit);
 827
 828         return macintmask;
 829 }
 830
 831 /* process an individual struct tx_status */
 832 static bool
 833 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
 834 {
 835         struct sk_buff *p = NULL;
 836         uint queue = NFIFO;
 837         struct dma_pub *dma = NULL;
 838         struct d11txh *txh = NULL;
 839         struct scb *scb = NULL;
 840         bool free_pdu;
 841         int tx_rts, tx_frame_count, tx_rts_count;
 842         uint totlen, supr_status;
 843         bool lastframe;
 844         struct ieee80211_hdr *h;
 845         u16 mcl;
 846         struct ieee80211_tx_info *tx_info;
 847         struct ieee80211_tx_rate *txrate;
 848         int i;
 849         bool fatal = true;
 850
 851         trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
 852                              txs->frameid, txs->status, txs->lasttxtime,
 853                              txs->sequence, txs->phyerr, txs->ackphyrxsh);
 854
 855         /* discard intermediate indications for ucode with one legitimate case:
 856          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
 857          *   but the subsequent tx of DATA failed. so it will start rts/cts
 858          *   from the beginning (resetting the rts transmission count)
 859          */
 860         if (!(txs->status & TX_STATUS_AMPDU)
 861             && (txs->status & TX_STATUS_INTERMEDIATE)) {
 862                 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
 863                 fatal = false;
 864                 goto out;
 865         }
 866
 867         queue = txs->frameid & TXFID_QUEUE_MASK;
 868         if (queue >= NFIFO) {
 869                 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
 870                 goto out;
 871         }
 872
 873         dma = wlc->hw->di[queue];
 874
 875         p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
 876         if (p == NULL) {
 877                 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
 878                 goto out;
 879         }
 880
 881         txh = (struct d11txh *) (p->data);
 882         mcl = le16_to_cpu(txh->MacTxControlLow);
 883
 884         if (txs->phyerr)
 885                 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
 886                           txs->phyerr, txh->MainRates);
 887
 888         if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
 889                 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
 890                 goto out;
 891         }
 892         tx_info = IEEE80211_SKB_CB(p);
 893         h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
 894
 895         if (tx_info->rate_driver_data[0])
 896                 scb = &wlc->pri_scb;
 897
 898         if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
 899                 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
 900                 fatal = false;
 901                 goto out;
 902         }
 903
 904         /*
 905          * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
 906          * frames; this traces them for the rest.
 907          */
 908         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
 909
 910         supr_status = txs->status & TX_STATUS_SUPR_MASK;
 911         if (supr_status == TX_STATUS_SUPR_BADCH) {
 912                 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
 913                 brcms_dbg_tx(wlc->hw->d11core,
 914                              "Pkt tx suppressed, dest chan %u, current %d\n",
 915                              (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
 916                              CHSPEC_CHANNEL(wlc->default_bss->chanspec));
 917         }
 918
 919         tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
 920         tx_frame_count =
 921             (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
 922         tx_rts_count =
 923             (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
 924
 925         lastframe = !ieee80211_has_morefrags(h->frame_control);
 926
 927         if (!lastframe) {
 928                 brcms_err(wlc->hw->d11core, "Not last frame!\n");
 929         } else {
 930                 /*
 931                  * Set information to be consumed by Minstrel ht.
 932                  *
 933                  * The "fallback limit" is the number of tx attempts a given
 934                  * MPDU is sent at the "primary" rate. Tx attempts beyond that
 935                  * limit are sent at the "secondary" rate.
 936                  * A 'short frame' does not exceed RTS treshold.
 937                  */
 938                 u16 sfbl,       /* Short Frame Rate Fallback Limit */
 939                     lfbl,       /* Long Frame Rate Fallback Limit */
 940                     fbl;
 941
 942                 if (queue < IEEE80211_NUM_ACS) {
 943                         sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
 944                                       EDCF_SFB);
 945                         lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
 946                                       EDCF_LFB);
 947                 } else {
 948                         sfbl = wlc->SFBL;
 949                         lfbl = wlc->LFBL;
 950                 }
 951
 952                 txrate = tx_info->status.rates;
 953                 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
 954                         fbl = lfbl;
 955                 else
 956                         fbl = sfbl;
 957
 958                 ieee80211_tx_info_clear_status(tx_info);
 959
 960                 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
 961                         /*
 962                          * rate selection requested a fallback rate
 963                          * and we used it
 964                          */
 965                         txrate[0].count = fbl;
 966                         txrate[1].count = tx_frame_count - fbl;
 967                 } else {
 968                         /*
 969                          * rate selection did not request fallback rate, or
 970                          * we didn't need it
 971                          */
 972                         txrate[0].count = tx_frame_count;
 973                         /*
 974                          * rc80211_minstrel.c:minstrel_tx_status() expects
 975                          * unused rates to be marked with idx = -1
 976                          */
 977                         txrate[1].idx = -1;
 978                         txrate[1].count = 0;
 979                 }
 980
 981                 /* clear the rest of the rates */
 982                 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
 983                         txrate[i].idx = -1;
 984                         txrate[i].count = 0;
 985                 }
 986
 987                 if (txs->status & TX_STATUS_ACK_RCV)
 988                         tx_info->flags |= IEEE80211_TX_STAT_ACK;
 989         }
 990
 991         totlen = p->len;
 992         free_pdu = true;
 993
 994         if (lastframe) {
 995                 /* remove PLCP & Broadcom tx descriptor header */
 996                 skb_pull(p, D11_PHY_HDR_LEN);
 997                 skb_pull(p, D11_TXH_LEN);
 998                 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
 999         } else {
1000                 brcms_err(wlc->hw->d11core,
1001                           "%s: Not last frame => not calling tx_status\n",
1002                           __func__);
1003         }
1004
1005         fatal = false;
1006
1007  out:
1008         if (fatal) {
1009                 if (txh)
1010                         trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1011                                            sizeof(*txh));
1012                 if (p)
1013                         brcmu_pkt_buf_free_skb(p);
1014         }
1015
1016         if (dma && queue < NFIFO) {
1017                 u16 ac_queue = brcms_fifo_to_ac(queue);
1018                 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1019                     ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1020                         ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1021                 dma_kick_tx(dma);
1022         }
1023
1024         return fatal;
1025 }
1026
1027 /* process tx completion events in BMAC
1028  * Return true if more tx status need to be processed. false otherwise.
1029  */
1030 static bool
1031 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1032 {
1033         struct bcma_device *core;
1034         struct tx_status txstatus, *txs;
1035         u32 s1, s2;
1036         uint n = 0;
1037         /*
1038          * Param 'max_tx_num' indicates max. # tx status to process before
1039          * break out.
1040          */
1041         uint max_tx_num = bound ? TXSBND : -1;
1042
1043         txs = &txstatus;
1044         core = wlc_hw->d11core;
1045         *fatal = false;
1046
1047         while (n < max_tx_num) {
1048                 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1049                 if (s1 == 0xffffffff) {
1050                         brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1051                                   __func__);
1052                         *fatal = true;
1053                         return false;
1054                 }
1055                 /* only process when valid */
1056                 if (!(s1 & TXS_V))
1057                         break;
1058
1059                 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1060                 txs->status = s1 & TXS_STATUS_MASK;
1061                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1062                 txs->sequence = s2 & TXS_SEQ_MASK;
1063                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1064                 txs->lasttxtime = 0;
1065
1066                 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1067                 if (*fatal == true)
1068                         return false;
1069                 n++;
1070         }
1071
1072         return n >= max_tx_num;
1073 }
1074
1075 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1076 {
1077         if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
1078                 /*
1079                  * DirFrmQ is now valid...defer setting until end
1080                  * of ATIM window
1081                  */
1082                 wlc->qvalid |= MCMD_DIRFRMQVAL;
1083 }
1084
1085 /* set initial host flags value */
1086 static void
1087 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1088 {
1089         struct brcms_hardware *wlc_hw = wlc->hw;
1090
1091         memset(mhfs, 0, MHFMAX * sizeof(u16));
1092
1093         mhfs[MHF2] |= mhf2_init;
1094
1095         /* prohibit use of slowclock on multifunction boards */
1096         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1097                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1098
1099         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1100                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1101                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1102         }
1103 }
1104
1105 static uint
1106 dmareg(uint direction, uint fifonum)
1107 {
1108         if (direction == DMA_TX)
1109                 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1110         return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1111 }
1112
1113 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1114 {
1115         uint i;
1116         char name[8];
1117         /*
1118          * ucode host flag 2 needed for pio mode, independent of band and fifo
1119          */
1120         u16 pio_mhf2 = 0;
1121         struct brcms_hardware *wlc_hw = wlc->hw;
1122         uint unit = wlc_hw->unit;
1123
1124         /* name and offsets for dma_attach */
1125         snprintf(name, sizeof(name), "wl%d", unit);
1126
1127         if (wlc_hw->di[0] == NULL) {    /* Init FIFOs */
1128                 int dma_attach_err = 0;
1129
1130                 /*
1131                  * FIFO 0
1132                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1133                  * RX: RX_FIFO (RX data packets)
1134                  */
1135                 wlc_hw->di[0] = dma_attach(name, wlc,
1136                                            (wme ? dmareg(DMA_TX, 0) : 0),
1137                                            dmareg(DMA_RX, 0),
1138                                            (wme ? NTXD : 0), NRXD,
1139                                            RXBUFSZ, -1, NRXBUFPOST,
1140                                            BRCMS_HWRXOFF);
1141                 dma_attach_err |= (NULL == wlc_hw->di[0]);
1142
1143                 /*
1144                  * FIFO 1
1145                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1146                  *   (legacy) TX_DATA_FIFO (TX data packets)
1147                  * RX: UNUSED
1148                  */
1149                 wlc_hw->di[1] = dma_attach(name, wlc,
1150                                            dmareg(DMA_TX, 1), 0,
1151                                            NTXD, 0, 0, -1, 0, 0);
1152                 dma_attach_err |= (NULL == wlc_hw->di[1]);
1153
1154                 /*
1155                  * FIFO 2
1156                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1157                  * RX: UNUSED
1158                  */
1159                 wlc_hw->di[2] = dma_attach(name, wlc,
1160                                            dmareg(DMA_TX, 2), 0,
1161                                            NTXD, 0, 0, -1, 0, 0);
1162                 dma_attach_err |= (NULL == wlc_hw->di[2]);
1163                 /*
1164                  * FIFO 3
1165                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1166                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1167                  */
1168                 wlc_hw->di[3] = dma_attach(name, wlc,
1169                                            dmareg(DMA_TX, 3),
1170                                            0, NTXD, 0, 0, -1,
1171                                            0, 0);
1172                 dma_attach_err |= (NULL == wlc_hw->di[3]);
1173 /* Cleaner to leave this as if with AP defined */
1174
1175                 if (dma_attach_err) {
1176                         brcms_err(wlc_hw->d11core,
1177                                   "wl%d: wlc_attach: dma_attach failed\n",
1178                                   unit);
1179                         return false;
1180                 }
1181
1182                 /* get pointer to dma engine tx flow control variable */
1183                 for (i = 0; i < NFIFO; i++)
1184                         if (wlc_hw->di[i])
1185                                 wlc_hw->txavail[i] =
1186                                     (uint *) dma_getvar(wlc_hw->di[i],
1187                                                         "&txavail");
1188         }
1189
1190         /* initial ucode host flags */
1191         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1192
1193         return true;
1194 }
1195
1196 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1197 {
1198         uint j;
1199
1200         for (j = 0; j < NFIFO; j++) {
1201                 if (wlc_hw->di[j]) {
1202                         dma_detach(wlc_hw->di[j]);
1203                         wlc_hw->di[j] = NULL;
1204                 }
1205         }
1206 }
1207
1208 /*
1209  * Initialize brcms_c_info default values ...
1210  * may get overrides later in this function
1211  *  BMAC_NOTES, move low out and resolve the dangling ones
1212  */
1213 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1214 {
1215         struct brcms_c_info *wlc = wlc_hw->wlc;
1216
1217         /* set default sw macintmask value */
1218         wlc->defmacintmask = DEF_MACINTMASK;
1219
1220         /* various 802.11g modes */
1221         wlc_hw->shortslot = false;
1222
1223         wlc_hw->SFBL = RETRY_SHORT_FB;
1224         wlc_hw->LFBL = RETRY_LONG_FB;
1225
1226         /* default mac retry limits */
1227         wlc_hw->SRL = RETRY_SHORT_DEF;
1228         wlc_hw->LRL = RETRY_LONG_DEF;
1229         wlc_hw->chanspec = ch20mhz_chspec(1);
1230 }
1231
1232 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1233 {
1234         /* delay before first read of ucode state */
1235         udelay(40);
1236
1237         /* wait until ucode is no longer asleep */
1238         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1239                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1240 }
1241
1242 /* control chip clock to save power, enable dynamic clock or force fast clock */
1243 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1244 {
1245         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1246                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1247                  * on backplane, but mac core will still run on ALP(not HT) when
1248                  * it enters powersave mode, which means the FCA bit may not be
1249                  * set. Should wakeup mac if driver wants it to run on HT.
1250                  */
1251
1252                 if (wlc_hw->clk) {
1253                         if (mode == BCMA_CLKMODE_FAST) {
1254                                 bcma_set32(wlc_hw->d11core,
1255                                            D11REGOFFS(clk_ctl_st),
1256                                            CCS_FORCEHT);
1257
1258                                 udelay(64);
1259
1260                                 SPINWAIT(
1261                                     ((bcma_read32(wlc_hw->d11core,
1262                                       D11REGOFFS(clk_ctl_st)) &
1263                                       CCS_HTAVAIL) == 0),
1264                                       PMU_MAX_TRANSITION_DLY);
1265                                 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1266                                         D11REGOFFS(clk_ctl_st)) &
1267                                         CCS_HTAVAIL));
1268                         } else {
1269                                 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1270                                     (bcma_read32(wlc_hw->d11core,
1271                                         D11REGOFFS(clk_ctl_st)) &
1272                                         (CCS_FORCEHT | CCS_HTAREQ)))
1273                                         SPINWAIT(
1274                                             ((bcma_read32(wlc_hw->d11core,
1275                                               offsetof(struct d11regs,
1276                                                        clk_ctl_st)) &
1277                                               CCS_HTAVAIL) == 0),
1278                                               PMU_MAX_TRANSITION_DLY);
1279                                 bcma_mask32(wlc_hw->d11core,
1280                                         D11REGOFFS(clk_ctl_st),
1281                                         ~CCS_FORCEHT);
1282                         }
1283                 }
1284                 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1285         } else {
1286
1287                 /* old chips w/o PMU, force HT through cc,
1288                  * then use FCA to verify mac is running fast clock
1289                  */
1290
1291                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1292
1293                 /* check fast clock is available (if core is not in reset) */
1294                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1295                         WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1296                                   SISF_FCLKA));
1297
1298                 /*
1299                  * keep the ucode wake bit on if forcefastclk is on since we
1300                  * do not want ucode to put us back to slow clock when it dozes
1301                  * for PM mode. Code below matches the wake override bit with
1302                  * current forcefastclk state. Only setting bit in wake_override
1303                  * instead of waking ucode immediately since old code had this
1304                  * behavior. Older code set wlc->forcefastclk but only had the
1305                  * wake happen if the wakup_ucode work (protected by an up
1306                  * check) was executed just below.
1307                  */
1308                 if (wlc_hw->forcefastclk)
1309                         mboolset(wlc_hw->wake_override,
1310                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1311                 else
1312                         mboolclr(wlc_hw->wake_override,
1313                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1314         }
1315 }
1316
1317 /* set or clear ucode host flag bits
1318  * it has an optimization for no-change write
1319  * it only writes through shared memory when the core has clock;
1320  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1321  *
1322  *
1323  * bands values are: BRCM_BAND_AUTO <--- Current band only
1324  *                   BRCM_BAND_5G   <--- 5G band only
1325  *                   BRCM_BAND_2G   <--- 2G band only
1326  *                   BRCM_BAND_ALL  <--- All bands
1327  */
1328 void
1329 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1330              int bands)
1331 {
1332         u16 save;
1333         u16 addr[MHFMAX] = {
1334                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1335                 M_HOST_FLAGS5
1336         };
1337         struct brcms_hw_band *band;
1338
1339         if ((val & ~mask) || idx >= MHFMAX)
1340                 return; /* error condition */
1341
1342         switch (bands) {
1343                 /* Current band only or all bands,
1344                  * then set the band to current band
1345                  */
1346         case BRCM_BAND_AUTO:
1347         case BRCM_BAND_ALL:
1348                 band = wlc_hw->band;
1349                 break;
1350         case BRCM_BAND_5G:
1351                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1352                 break;
1353         case BRCM_BAND_2G:
1354                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1355                 break;
1356         default:
1357                 band = NULL;    /* error condition */
1358         }
1359
1360         if (band) {
1361                 save = band->mhfs[idx];
1362                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1363
1364                 /* optimization: only write through if changed, and
1365                  * changed band is the current band
1366                  */
1367                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1368                     && (band == wlc_hw->band))
1369                         brcms_b_write_shm(wlc_hw, addr[idx],
1370                                            (u16) band->mhfs[idx]);
1371         }
1372
1373         if (bands == BRCM_BAND_ALL) {
1374                 wlc_hw->bandstate[0]->mhfs[idx] =
1375                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1376                 wlc_hw->bandstate[1]->mhfs[idx] =
1377                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1378         }
1379 }
1380
1381 /* set the maccontrol register to desired reset state and
1382  * initialize the sw cache of the register
1383  */
1384 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1385 {
1386         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1387         wlc_hw->maccontrol = 0;
1388         wlc_hw->suspended_fifos = 0;
1389         wlc_hw->wake_override = 0;
1390         wlc_hw->mute_override = 0;
1391         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1392 }
1393
1394 /*
1395  * write the software state of maccontrol and
1396  * overrides to the maccontrol register
1397  */
1398 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1399 {
1400         u32 maccontrol = wlc_hw->maccontrol;
1401
1402         /* OR in the wake bit if overridden */
1403         if (wlc_hw->wake_override)
1404                 maccontrol |= MCTL_WAKE;
1405
1406         /* set AP and INFRA bits for mute if needed */
1407         if (wlc_hw->mute_override) {
1408                 maccontrol &= ~(MCTL_AP);
1409                 maccontrol |= MCTL_INFRA;
1410         }
1411
1412         bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1413                      maccontrol);
1414 }
1415
1416 /* set or clear maccontrol bits */
1417 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1418 {
1419         u32 maccontrol;
1420         u32 new_maccontrol;
1421
1422         if (val & ~mask)
1423                 return; /* error condition */
1424         maccontrol = wlc_hw->maccontrol;
1425         new_maccontrol = (maccontrol & ~mask) | val;
1426
1427         /* if the new maccontrol value is the same as the old, nothing to do */
1428         if (new_maccontrol == maccontrol)
1429                 return;
1430
1431         /* something changed, cache the new value */
1432         wlc_hw->maccontrol = new_maccontrol;
1433
1434         /* write the new values with overrides applied */
1435         brcms_c_mctrl_write(wlc_hw);
1436 }
1437
1438 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1439                                  u32 override_bit)
1440 {
1441         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1442                 mboolset(wlc_hw->wake_override, override_bit);
1443                 return;
1444         }
1445
1446         mboolset(wlc_hw->wake_override, override_bit);
1447
1448         brcms_c_mctrl_write(wlc_hw);
1449         brcms_b_wait_for_wake(wlc_hw);
1450 }
1451
1452 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1453                                    u32 override_bit)
1454 {
1455         mboolclr(wlc_hw->wake_override, override_bit);
1456
1457         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1458                 return;
1459
1460         brcms_c_mctrl_write(wlc_hw);
1461 }
1462
1463 /* When driver needs ucode to stop beaconing, it has to make sure that
1464  * MCTL_AP is clear and MCTL_INFRA is set
1465  * Mode           MCTL_AP        MCTL_INFRA
1466  * AP                1              1
1467  * STA               0              1 <--- This will ensure no beacons
1468  * IBSS              0              0
1469  */
1470 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1471 {
1472         wlc_hw->mute_override = 1;
1473
1474         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1475          * override, then there is no change to write
1476          */
1477         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1478                 return;
1479
1480         brcms_c_mctrl_write(wlc_hw);
1481 }
1482
1483 /* Clear the override on AP and INFRA bits */
1484 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1485 {
1486         if (wlc_hw->mute_override == 0)
1487                 return;
1488
1489         wlc_hw->mute_override = 0;
1490
1491         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1492          * override, then there is no change to write
1493          */
1494         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1495                 return;
1496
1497         brcms_c_mctrl_write(wlc_hw);
1498 }
1499
1500 /*
1501  * Write a MAC address to the given match reg offset in the RXE match engine.
1502  */
1503 static void
1504 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1505                        const u8 *addr)
1506 {
1507         struct bcma_device *core = wlc_hw->d11core;
1508         u16 mac_l;
1509         u16 mac_m;
1510         u16 mac_h;
1511
1512         brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1513
1514         mac_l = addr[0] | (addr[1] << 8);
1515         mac_m = addr[2] | (addr[3] << 8);
1516         mac_h = addr[4] | (addr[5] << 8);
1517
1518         /* enter the MAC addr into the RXE match registers */
1519         bcma_write16(core, D11REGOFFS(rcm_ctl),
1520                      RCM_INC_DATA | match_reg_offset);
1521         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1522         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1523         bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1524 }
1525
1526 void
1527 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1528                             void *buf)
1529 {
1530         struct bcma_device *core = wlc_hw->d11core;
1531         u32 word;
1532         __le32 word_le;
1533         __be32 word_be;
1534         bool be_bit;
1535         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1536
1537         bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1538
1539         /* if MCTL_BIGEND bit set in mac control register,
1540          * the chip swaps data in fifo, as well as data in
1541          * template ram
1542          */
1543         be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1544
1545         while (len > 0) {
1546                 memcpy(&word, buf, sizeof(u32));
1547
1548                 if (be_bit) {
1549                         word_be = cpu_to_be32(word);
1550                         word = *(u32 *)&word_be;
1551                 } else {
1552                         word_le = cpu_to_le32(word);
1553                         word = *(u32 *)&word_le;
1554                 }
1555
1556                 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1557
1558                 buf = (u8 *) buf + sizeof(u32);
1559                 len -= sizeof(u32);
1560         }
1561 }
1562
1563 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1564 {
1565         wlc_hw->band->CWmin = newmin;
1566
1567         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1568                      OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1569         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1570         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1571 }
1572
1573 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1574 {
1575         wlc_hw->band->CWmax = newmax;
1576
1577         bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1578                      OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1579         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1580         bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1581 }
1582
1583 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1584 {
1585         bool fastclk;
1586
1587         /* request FAST clock if not on */
1588         fastclk = wlc_hw->forcefastclk;
1589         if (!fastclk)
1590                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1591
1592         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1593
1594         brcms_b_phy_reset(wlc_hw);
1595         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1596
1597         /* restore the clk */
1598         if (!fastclk)
1599                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1600 }
1601
1602 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1603 {
1604         u16 v;
1605         struct brcms_c_info *wlc = wlc_hw->wlc;
1606         /* update SYNTHPU_DLY */
1607
1608         if (BRCMS_ISLCNPHY(wlc->band))
1609                 v = SYNTHPU_DLY_LPPHY_US;
1610         else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1611                 v = SYNTHPU_DLY_NPHY_US;
1612         else
1613                 v = SYNTHPU_DLY_BPHY_US;
1614
1615         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1616 }
1617
1618 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1619 {
1620         u16 phyctl;
1621         u16 phytxant = wlc_hw->bmac_phytxant;
1622         u16 mask = PHY_TXC_ANT_MASK;
1623
1624         /* set the Probe Response frame phy control word */
1625         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1626         phyctl = (phyctl & ~mask) | phytxant;
1627         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1628
1629         /* set the Response (ACK/CTS) frame phy control word */
1630         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1631         phyctl = (phyctl & ~mask) | phytxant;
1632         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1633 }
1634
1635 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1636                                          u8 rate)
1637 {
1638         uint i;
1639         u8 plcp_rate = 0;
1640         struct plcp_signal_rate_lookup {
1641                 u8 rate;
1642                 u8 signal_rate;
1643         };
1644         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1645         const struct plcp_signal_rate_lookup rate_lookup[] = {
1646                 {BRCM_RATE_6M, 0xB},
1647                 {BRCM_RATE_9M, 0xF},
1648                 {BRCM_RATE_12M, 0xA},
1649                 {BRCM_RATE_18M, 0xE},
1650                 {BRCM_RATE_24M, 0x9},
1651                 {BRCM_RATE_36M, 0xD},
1652                 {BRCM_RATE_48M, 0x8},
1653                 {BRCM_RATE_54M, 0xC}
1654         };
1655
1656         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1657                 if (rate == rate_lookup[i].rate) {
1658                         plcp_rate = rate_lookup[i].signal_rate;
1659                         break;
1660                 }
1661         }
1662
1663         /* Find the SHM pointer to the rate table entry by looking in the
1664          * Direct-map Table
1665          */
1666         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1667 }
1668
1669 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1670 {
1671         u8 rate;
1672         u8 rates[8] = {
1673                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1674                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1675         };
1676         u16 entry_ptr;
1677         u16 pctl1;
1678         uint i;
1679
1680         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1681                 return;
1682
1683         /* walk the phy rate table and update the entries */
1684         for (i = 0; i < ARRAY_SIZE(rates); i++) {
1685                 rate = rates[i];
1686
1687                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1688
1689                 /* read the SHM Rate Table entry OFDM PCTL1 values */
1690                 pctl1 =
1691                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1692
1693                 /* modify the value */
1694                 pctl1 &= ~PHY_TXC1_MODE_MASK;
1695                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1696
1697                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1698                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1699                                    pctl1);
1700         }
1701 }
1702
1703 /* band-specific init */
1704 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1705 {
1706         struct brcms_hardware *wlc_hw = wlc->hw;
1707
1708         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1709                            wlc_hw->band->bandunit);
1710
1711         brcms_c_ucode_bsinit(wlc_hw);
1712
1713         wlc_phy_init(wlc_hw->band->pi, chanspec);
1714
1715         brcms_c_ucode_txant_set(wlc_hw);
1716
1717         /*
1718          * cwmin is band-specific, update hardware
1719          * with value for current band
1720          */
1721         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1722         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1723
1724         brcms_b_update_slot_timing(wlc_hw,
1725                                    wlc_hw->band->bandtype == BRCM_BAND_5G ?
1726                                    true : wlc_hw->shortslot);
1727
1728         /* write phytype and phyvers */
1729         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1730         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1731
1732         /*
1733          * initialize the txphyctl1 rate table since
1734          * shmem is shared between bands
1735          */
1736         brcms_upd_ofdm_pctl1_table(wlc_hw);
1737
1738         brcms_b_upd_synthpu(wlc_hw);
1739 }
1740
1741 /* Perform a soft reset of the PHY PLL */
1742 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1743 {
1744         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1745                   ~0, 0);
1746         udelay(1);
1747         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1748                   0x4, 0);
1749         udelay(1);
1750         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1751                   0x4, 4);
1752         udelay(1);
1753         ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1754                   0x4, 0);
1755         udelay(1);
1756 }
1757
1758 /* light way to turn on phy clock without reset for NPHY only
1759  *  refer to brcms_b_core_phy_clk for full version
1760  */
1761 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1762 {
1763         /* support(necessary for NPHY and HYPHY) only */
1764         if (!BRCMS_ISNPHY(wlc_hw->band))
1765                 return;
1766
1767         if (ON == clk)
1768                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1769         else
1770                 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1771
1772 }
1773
1774 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1775 {
1776         if (ON == clk)
1777                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1778         else
1779                 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1780 }
1781
1782 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1783 {
1784         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1785         u32 phy_bw_clkbits;
1786         bool phy_in_reset = false;
1787
1788         brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1789
1790         if (pih == NULL)
1791                 return;
1792
1793         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1794
1795         /* Specific reset sequence required for NPHY rev 3 and 4 */
1796         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1797             NREV_LE(wlc_hw->band->phyrev, 4)) {
1798                 /* Set the PHY bandwidth */
1799                 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1800
1801                 udelay(1);
1802
1803                 /* Perform a soft reset of the PHY PLL */
1804                 brcms_b_core_phypll_reset(wlc_hw);
1805
1806                 /* reset the PHY */
1807                 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1808                                    (SICF_PRST | SICF_PCLKE));
1809                 phy_in_reset = true;
1810         } else {
1811                 brcms_b_core_ioctl(wlc_hw,
1812                                    (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1813                                    (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1814         }
1815
1816         udelay(2);
1817         brcms_b_core_phy_clk(wlc_hw, ON);
1818
1819         if (pih)
1820                 wlc_phy_anacore(pih, ON);
1821 }
1822
1823 /* switch to and initialize new band */
1824 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1825                             u16 chanspec) {
1826         struct brcms_c_info *wlc = wlc_hw->wlc;
1827         u32 macintmask;
1828
1829         /* Enable the d11 core before accessing it */
1830         if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1831                 bcma_core_enable(wlc_hw->d11core, 0);
1832                 brcms_c_mctrl_reset(wlc_hw);
1833         }
1834
1835         macintmask = brcms_c_setband_inact(wlc, bandunit);
1836
1837         if (!wlc_hw->up)
1838                 return;
1839
1840         brcms_b_core_phy_clk(wlc_hw, ON);
1841
1842         /* band-specific initializations */
1843         brcms_b_bsinit(wlc, chanspec);
1844
1845         /*
1846          * If there are any pending software interrupt bits,
1847          * then replace these with a harmless nonzero value
1848          * so brcms_c_dpc() will re-enable interrupts when done.
1849          */
1850         if (wlc->macintstatus)
1851                 wlc->macintstatus = MI_DMAINT;
1852
1853         /* restore macintmask */
1854         brcms_intrsrestore(wlc->wl, macintmask);
1855
1856         /* ucode should still be suspended.. */
1857         WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1858                  MCTL_EN_MAC) != 0);
1859 }
1860
1861 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1862 {
1863
1864         /* reject unsupported corerev */
1865         if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1866                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1867                           wlc_hw->corerev);
1868                 return false;
1869         }
1870
1871         return true;
1872 }
1873
1874 /* Validate some board info parameters */
1875 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1876 {
1877         uint boardrev = wlc_hw->boardrev;
1878
1879         /* 4 bits each for board type, major, minor, and tiny version */
1880         uint brt = (boardrev & 0xf000) >> 12;
1881         uint b0 = (boardrev & 0xf00) >> 8;
1882         uint b1 = (boardrev & 0xf0) >> 4;
1883         uint b2 = boardrev & 0xf;
1884
1885         /* voards from other vendors are always considered valid */
1886         if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1887                 return true;
1888
1889         /* do some boardrev sanity checks when boardvendor is Broadcom */
1890         if (boardrev == 0)
1891                 return false;
1892
1893         if (boardrev <= 0xff)
1894                 return true;
1895
1896         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1897                 || (b2 > 9))
1898                 return false;
1899
1900         return true;
1901 }
1902
1903 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1904 {
1905         struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1906
1907         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1908         if (!is_zero_ether_addr(sprom->il0mac)) {
1909                 memcpy(etheraddr, sprom->il0mac, 6);
1910                 return;
1911         }
1912
1913         if (wlc_hw->_nbands > 1)
1914                 memcpy(etheraddr, sprom->et1mac, 6);
1915         else
1916                 memcpy(etheraddr, sprom->il0mac, 6);
1917 }
1918
1919 /* power both the pll and external oscillator on/off */
1920 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1921 {
1922         brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1923
1924         /*
1925          * dont power down if plldown is false or
1926          * we must poll hw radio disable
1927          */
1928         if (!want && wlc_hw->pllreq)
1929                 return;
1930
1931         wlc_hw->sbclk = want;
1932         if (!wlc_hw->sbclk) {
1933                 wlc_hw->clk = false;
1934                 if (wlc_hw->band && wlc_hw->band->pi)
1935                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1936         }
1937 }
1938
1939 /*
1940  * Return true if radio is disabled, otherwise false.
1941  * hw radio disable signal is an external pin, users activate it asynchronously
1942  * this function could be called when driver is down and w/o clock
1943  * it operates on different registers depending on corerev and boardflag.
1944  */
1945 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1946 {
1947         bool v, clk, xtal;
1948         u32 flags = 0;
1949
1950         xtal = wlc_hw->sbclk;
1951         if (!xtal)
1952                 brcms_b_xtal(wlc_hw, ON);
1953
1954         /* may need to take core out of reset first */
1955         clk = wlc_hw->clk;
1956         if (!clk) {
1957                 /*
1958                  * mac no longer enables phyclk automatically when driver
1959                  * accesses phyreg throughput mac. This can be skipped since
1960                  * only mac reg is accessed below
1961                  */
1962                 if (D11REV_GE(wlc_hw->corerev, 18))
1963                         flags |= SICF_PCLKE;
1964
1965                 /*
1966                  * TODO: test suspend/resume
1967                  *
1968                  * AI chip doesn't restore bar0win2 on
1969                  * hibernation/resume, need sw fixup
1970                  */
1971
1972                 bcma_core_enable(wlc_hw->d11core, flags);
1973                 brcms_c_mctrl_reset(wlc_hw);
1974         }
1975
1976         v = ((bcma_read32(wlc_hw->d11core,
1977                           D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1978
1979         /* put core back into reset */
1980         if (!clk)
1981                 bcma_core_disable(wlc_hw->d11core, 0);
1982
1983         if (!xtal)
1984                 brcms_b_xtal(wlc_hw, OFF);
1985
1986         return v;
1987 }
1988
1989 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1990 {
1991         struct dma_pub *di = wlc_hw->di[fifo];
1992         return dma_rxreset(di);
1993 }
1994
1995 /* d11 core reset
1996  *   ensure fask clock during reset
1997  *   reset dma
1998  *   reset d11(out of reset)
1999  *   reset phy(out of reset)
2000  *   clear software macintstatus for fresh new start
2001  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2002  */
2003 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2004 {
2005         uint i;
2006         bool fastclk;
2007
2008         if (flags == BRCMS_USE_COREFLAGS)
2009                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2010
2011         brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2012
2013         /* request FAST clock if not on  */
2014         fastclk = wlc_hw->forcefastclk;
2015         if (!fastclk)
2016                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2017
2018         /* reset the dma engines except first time thru */
2019         if (bcma_core_is_enabled(wlc_hw->d11core)) {
2020                 for (i = 0; i < NFIFO; i++)
2021                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2022                                 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2023                                           "dma_txreset[%d]: cannot stop dma\n",
2024                                            wlc_hw->unit, __func__, i);
2025
2026                 if ((wlc_hw->di[RX_FIFO])
2027                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2028                         brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2029                                   "[%d]: cannot stop dma\n",
2030                                   wlc_hw->unit, __func__, RX_FIFO);
2031         }
2032         /* if noreset, just stop the psm and return */
2033         if (wlc_hw->noreset) {
2034                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2035                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2036                 return;
2037         }
2038
2039         /*
2040          * mac no longer enables phyclk automatically when driver accesses
2041          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2042          * band->pi is invalid. need to enable PHY CLK
2043          */
2044         if (D11REV_GE(wlc_hw->corerev, 18))
2045                 flags |= SICF_PCLKE;
2046
2047         /*
2048          * reset the core
2049          * In chips with PMU, the fastclk request goes through d11 core
2050          * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2051          *
2052          * This adds some delay and we can optimize it by also requesting
2053          * fastclk through chipcommon during this period if necessary. But
2054          * that has to work coordinate with other driver like mips/arm since
2055          * they may touch chipcommon as well.
2056          */
2057         wlc_hw->clk = false;
2058         bcma_core_enable(wlc_hw->d11core, flags);
2059         wlc_hw->clk = true;
2060         if (wlc_hw->band && wlc_hw->band->pi)
2061                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2062
2063         brcms_c_mctrl_reset(wlc_hw);
2064
2065         if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2066                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2067
2068         brcms_b_phy_reset(wlc_hw);
2069
2070         /* turn on PHY_PLL */
2071         brcms_b_core_phypll_ctl(wlc_hw, true);
2072
2073         /* clear sw intstatus */
2074         wlc_hw->wlc->macintstatus = 0;
2075
2076         /* restore the clk setting */
2077         if (!fastclk)
2078                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2079 }
2080
2081 /* txfifo sizes needs to be modified(increased) since the newer cores
2082  * have more memory.
2083  */
2084 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2085 {
2086         struct bcma_device *core = wlc_hw->d11core;
2087         u16 fifo_nu;
2088         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2089         u16 txfifo_def, txfifo_def1;
2090         u16 txfifo_cmd;
2091
2092         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2093         txfifo_startblk = TXFIFO_START_BLK;
2094
2095         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2096         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2097
2098                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2099                 txfifo_def = (txfifo_startblk & 0xff) |
2100                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2101                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2102                     ((((txfifo_endblk -
2103                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2104                 txfifo_cmd =
2105                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2106
2107                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2108                 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2109                 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2110
2111                 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2112
2113                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2114         }
2115         /*
2116          * need to propagate to shm location to be in sync since ucode/hw won't
2117          * do this
2118          */
2119         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2120                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2121         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2122                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2123         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2124                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2125                             xmtfifo_sz[TX_AC_BK_FIFO]));
2126         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2127                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2128                             xmtfifo_sz[TX_BCMC_FIFO]));
2129 }
2130
2131 /* This function is used for changing the tsf frac register
2132  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2133  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2134  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2135  * HTPHY Formula is 2^26/freq(MHz) e.g.
2136  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2137  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2138  * For spuron: 123MHz -> 2^26/123    = 545600.5
2139  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2140  * For spur off: 120MHz -> 2^26/120    = 559240.5
2141  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2142  */
2143
2144 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2145 {
2146         struct bcma_device *core = wlc_hw->d11core;
2147
2148         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2149             (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2150                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2151                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2152                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2153                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2154                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2155                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2156                 } else {        /* 120Mhz */
2157                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2158                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2159                 }
2160         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2161                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2162                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2163                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2164                 } else {        /* 80Mhz */
2165                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2166                         bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2167                 }
2168         }
2169 }
2170
2171 void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
2172 {
2173         memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2174         wlc->bsscfg->type = BRCMS_TYPE_STATION;
2175 }
2176
2177 void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr, const u8 *bssid,
2178                       u8 *ssid, size_t ssid_len)
2179 {
2180         brcms_c_set_ssid(wlc, ssid, ssid_len);
2181
2182         memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2183         memcpy(wlc->bsscfg->BSSID, bssid, sizeof(wlc->bsscfg->BSSID));
2184         wlc->bsscfg->type = BRCMS_TYPE_AP;
2185
2186         brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, MCTL_AP | MCTL_INFRA);
2187 }
2188
2189 void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr)
2190 {
2191         memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2192         wlc->bsscfg->type = BRCMS_TYPE_ADHOC;
2193
2194         brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, 0);
2195 }
2196
2197 /* Initialize GPIOs that are controlled by D11 core */
2198 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2199 {
2200         struct brcms_hardware *wlc_hw = wlc->hw;
2201         u32 gc, gm;
2202
2203         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2204         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2205
2206         /*
2207          * Common GPIO setup:
2208          *      G0 = LED 0 = WLAN Activity
2209          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2210          *      G2 = LED 2 = WLAN 5 GHz Radio State
2211          *      G4 = radio disable input (HI enabled, LO disabled)
2212          */
2213
2214         gc = gm = 0;
2215
2216         /* Allocate GPIOs for mimo antenna diversity feature */
2217         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2218                 /* Enable antenna diversity, use 2x3 mode */
2219                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2220                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2221                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2222                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2223
2224                 /* init superswitch control */
2225                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2226
2227         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2228                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2229                 /*
2230                  * The board itself is powered by these GPIOs
2231                  * (when not sending pattern) so set them high
2232                  */
2233                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2234                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2235                 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2236                            (BOARD_GPIO_12 | BOARD_GPIO_13));
2237
2238                 /* Enable antenna diversity, use 2x4 mode */
2239                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2240                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2241                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2242                              BRCM_BAND_ALL);
2243
2244                 /* Configure the desired clock to be 4Mhz */
2245                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2246                                    ANTSEL_CLKDIV_4MHZ);
2247         }
2248
2249         /*
2250          * gpio 9 controls the PA. ucode is responsible
2251          * for wiggling out and oe
2252          */
2253         if (wlc_hw->boardflags & BFL_PACTRL)
2254                 gm |= gc |= BOARD_GPIO_PACTRL;
2255
2256         /* apply to gpiocontrol register */
2257         bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2258 }
2259
2260 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2261                               const __le32 ucode[], const size_t nbytes)
2262 {
2263         struct bcma_device *core = wlc_hw->d11core;
2264         uint i;
2265         uint count;
2266
2267         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2268
2269         count = (nbytes / sizeof(u32));
2270
2271         bcma_write32(core, D11REGOFFS(objaddr),
2272                      OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2273         (void)bcma_read32(core, D11REGOFFS(objaddr));
2274         for (i = 0; i < count; i++)
2275                 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2276
2277 }
2278
2279 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2280 {
2281         struct brcms_c_info *wlc;
2282         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2283
2284         wlc = wlc_hw->wlc;
2285
2286         if (wlc_hw->ucode_loaded)
2287                 return;
2288
2289         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2290                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2291                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2292                                           ucode->bcm43xx_16_mimosz);
2293                         wlc_hw->ucode_loaded = true;
2294                 } else
2295                         brcms_err(wlc_hw->d11core,
2296                                   "%s: wl%d: unsupported phy in corerev %d\n",
2297                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2298         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2299                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2300                         brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2301                                           ucode->bcm43xx_24_lcnsz);
2302                         wlc_hw->ucode_loaded = true;
2303                 } else {
2304                         brcms_err(wlc_hw->d11core,
2305                                   "%s: wl%d: unsupported phy in corerev %d\n",
2306                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2307                 }
2308         }
2309 }
2310
2311 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2312 {
2313         /* update sw state */
2314         wlc_hw->bmac_phytxant = phytxant;
2315
2316         /* push to ucode if up */
2317         if (!wlc_hw->up)
2318                 return;
2319         brcms_c_ucode_txant_set(wlc_hw);
2320
2321 }
2322
2323 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2324 {
2325         return (u16) wlc_hw->wlc->stf->txant;
2326 }
2327
2328 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2329 {
2330         wlc_hw->antsel_type = antsel_type;
2331
2332         /* Update the antsel type for phy module to use */
2333         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2334 }
2335
2336 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2337 {
2338         bool fatal = false;
2339         uint unit;
2340         uint intstatus, idx;
2341         struct bcma_device *core = wlc_hw->d11core;
2342
2343         unit = wlc_hw->unit;
2344
2345         for (idx = 0; idx < NFIFO; idx++) {
2346                 /* read intstatus register and ignore any non-error bits */
2347                 intstatus =
2348                         bcma_read32(core,
2349                                     D11REGOFFS(intctrlregs[idx].intstatus)) &
2350                         I_ERRORS;
2351                 if (!intstatus)
2352                         continue;
2353
2354                 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2355                               unit, idx, intstatus);
2356
2357                 if (intstatus & I_RO) {
2358                         brcms_err(core, "wl%d: fifo %d: receive fifo "
2359                                   "overflow\n", unit, idx);
2360                         fatal = true;
2361                 }
2362
2363                 if (intstatus & I_PC) {
2364                         brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2365                                   unit, idx);
2366                         fatal = true;
2367                 }
2368
2369                 if (intstatus & I_PD) {
2370                         brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2371                                   idx);
2372                         fatal = true;
2373                 }
2374
2375                 if (intstatus & I_DE) {
2376                         brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2377                                   "error\n", unit, idx);
2378                         fatal = true;
2379                 }
2380
2381                 if (intstatus & I_RU)
2382                         brcms_err(core, "wl%d: fifo %d: receive descriptor "
2383                                   "underflow\n", idx, unit);
2384
2385                 if (intstatus & I_XU) {
2386                         brcms_err(core, "wl%d: fifo %d: transmit fifo "
2387                                   "underflow\n", idx, unit);
2388                         fatal = true;
2389                 }
2390
2391                 if (fatal) {
2392                         brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2393                         break;
2394                 } else
2395                         bcma_write32(core,
2396                                      D11REGOFFS(intctrlregs[idx].intstatus),
2397                                      intstatus);
2398         }
2399 }
2400
2401 void brcms_c_intrson(struct brcms_c_info *wlc)
2402 {
2403         struct brcms_hardware *wlc_hw = wlc->hw;
2404         wlc->macintmask = wlc->defmacintmask;
2405         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2406 }
2407
2408 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2409 {
2410         struct brcms_hardware *wlc_hw = wlc->hw;
2411         u32 macintmask;
2412
2413         if (!wlc_hw->clk)
2414                 return 0;
2415
2416         macintmask = wlc->macintmask;   /* isr can still happen */
2417
2418         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2419         (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2420         udelay(1);              /* ensure int line is no longer driven */
2421         wlc->macintmask = 0;
2422
2423         /* return previous macintmask; resolve race between us and our isr */
2424         return wlc->macintstatus ? 0 : macintmask;
2425 }
2426
2427 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2428 {
2429         struct brcms_hardware *wlc_hw = wlc->hw;
2430         if (!wlc_hw->clk)
2431                 return;
2432
2433         wlc->macintmask = macintmask;
2434         bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2435 }
2436
2437 /* assumes that the d11 MAC is enabled */
2438 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2439                                     uint tx_fifo)
2440 {
2441         u8 fifo = 1 << tx_fifo;
2442
2443         /* Two clients of this code, 11h Quiet period and scanning. */
2444
2445         /* only suspend if not already suspended */
2446         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2447                 return;
2448
2449         /* force the core awake only if not already */
2450         if (wlc_hw->suspended_fifos == 0)
2451                 brcms_c_ucode_wake_override_set(wlc_hw,
2452                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2453
2454         wlc_hw->suspended_fifos |= fifo;
2455
2456         if (wlc_hw->di[tx_fifo]) {
2457                 /*
2458                  * Suspending AMPDU transmissions in the middle can cause
2459                  * underflow which may result in mismatch between ucode and
2460                  * driver so suspend the mac before suspending the FIFO
2461                  */
2462                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2463                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2464
2465                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2466
2467                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2468                         brcms_c_enable_mac(wlc_hw->wlc);
2469         }
2470 }
2471
2472 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2473                                    uint tx_fifo)
2474 {
2475         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2476          * but need to be done here for PIO otherwise the watchdog will catch
2477          * the inconsistency and fire
2478          */
2479         /* Two clients of this code, 11h Quiet period and scanning. */
2480         if (wlc_hw->di[tx_fifo])
2481                 dma_txresume(wlc_hw->di[tx_fifo]);
2482
2483         /* allow core to sleep again */
2484         if (wlc_hw->suspended_fifos == 0)
2485                 return;
2486         else {
2487                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2488                 if (wlc_hw->suspended_fifos == 0)
2489                         brcms_c_ucode_wake_override_clear(wlc_hw,
2490                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2491         }
2492 }
2493
2494 /* precondition: requires the mac core to be enabled */
2495 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2496 {
2497         static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2498         u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2499
2500         if (mute_tx) {
2501                 /* suspend tx fifos */
2502                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2503                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2504                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2505                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2506
2507                 /* zero the address match register so we do not send ACKs */
2508                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2509         } else {
2510                 /* resume tx fifos */
2511                 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2512                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2513                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2514                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2515
2516                 /* Restore address */
2517                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2518         }
2519
2520         wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2521
2522         if (mute_tx)
2523                 brcms_c_ucode_mute_override_set(wlc_hw);
2524         else
2525                 brcms_c_ucode_mute_override_clear(wlc_hw);
2526 }
2527
2528 void
2529 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2530 {
2531         brcms_b_mute(wlc->hw, mute_tx);
2532 }
2533
2534 /*
2535  * Read and clear macintmask and macintstatus and intstatus registers.
2536  * This routine should be called with interrupts off
2537  * Return:
2538  *   -1 if brcms_deviceremoved(wlc) evaluates to true;
2539  *   0 if the interrupt is not for us, or we are in some special cases;
2540  *   device interrupt status bits otherwise.
2541  */
2542 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2543 {
2544         struct brcms_hardware *wlc_hw = wlc->hw;
2545         struct bcma_device *core = wlc_hw->d11core;
2546         u32 macintstatus, mask;
2547
2548         /* macintstatus includes a DMA interrupt summary bit */
2549         macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2550         mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2551
2552         trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2553
2554         /* detect cardbus removed, in power down(suspend) and in reset */
2555         if (brcms_deviceremoved(wlc))
2556                 return -1;
2557
2558         /* brcms_deviceremoved() succeeds even when the core is still resetting,
2559          * handle that case here.
2560          */
2561         if (macintstatus == 0xffffffff)
2562                 return 0;
2563
2564         /* defer unsolicited interrupts */
2565         macintstatus &= mask;
2566
2567         /* if not for us */
2568         if (macintstatus == 0)
2569                 return 0;
2570
2571         /* turn off the interrupts */
2572         bcma_write32(core, D11REGOFFS(macintmask), 0);
2573         (void)bcma_read32(core, D11REGOFFS(macintmask));
2574         wlc->macintmask = 0;
2575
2576         /* clear device interrupts */
2577         bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2578
2579         /* MI_DMAINT is indication of non-zero intstatus */
2580         if (macintstatus & MI_DMAINT)
2581                 /*
2582                  * only fifo interrupt enabled is I_RI in
2583                  * RX_FIFO. If MI_DMAINT is set, assume it
2584                  * is set and clear the interrupt.
2585                  */
2586                 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2587                              DEF_RXINTMASK);
2588
2589         return macintstatus;
2590 }
2591
2592 /* Update wlc->macintstatus and wlc->intstatus[]. */
2593 /* Return true if they are updated successfully. false otherwise */
2594 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2595 {
2596         u32 macintstatus;
2597
2598         /* read and clear macintstatus and intstatus registers */
2599         macintstatus = wlc_intstatus(wlc, false);
2600
2601         /* device is removed */
2602         if (macintstatus == 0xffffffff)
2603                 return false;
2604
2605         /* update interrupt status in software */
2606         wlc->macintstatus |= macintstatus;
2607
2608         return true;
2609 }
2610
2611 /*
2612  * First-level interrupt processing.
2613  * Return true if this was our interrupt
2614  * and if further brcms_c_dpc() processing is required,
2615  * false otherwise.
2616  */
2617 bool brcms_c_isr(struct brcms_c_info *wlc)
2618 {
2619         struct brcms_hardware *wlc_hw = wlc->hw;
2620         u32 macintstatus;
2621
2622         if (!wlc_hw->up || !wlc->macintmask)
2623                 return false;
2624
2625         /* read and clear macintstatus and intstatus registers */
2626         macintstatus = wlc_intstatus(wlc, true);
2627
2628         if (macintstatus == 0xffffffff) {
2629                 brcms_err(wlc_hw->d11core,
2630                           "DEVICEREMOVED detected in the ISR code path\n");
2631                 return false;
2632         }
2633
2634         /* it is not for us */
2635         if (macintstatus == 0)
2636                 return false;
2637
2638         /* save interrupt status bits */
2639         wlc->macintstatus = macintstatus;
2640
2641         return true;
2642
2643 }
2644
2645 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2646 {
2647         struct brcms_hardware *wlc_hw = wlc->hw;
2648         struct bcma_device *core = wlc_hw->d11core;
2649         u32 mc, mi;
2650
2651         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2652                            wlc_hw->band->bandunit);
2653
2654         /*
2655          * Track overlapping suspend requests
2656          */
2657         wlc_hw->mac_suspend_depth++;
2658         if (wlc_hw->mac_suspend_depth > 1)
2659                 return;
2660
2661         /* force the core awake */
2662         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2663
2664         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2665
2666         if (mc == 0xffffffff) {
2667                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2668                           __func__);
2669                 brcms_down(wlc->wl);
2670                 return;
2671         }
2672         WARN_ON(mc & MCTL_PSM_JMP_0);
2673         WARN_ON(!(mc & MCTL_PSM_RUN));
2674         WARN_ON(!(mc & MCTL_EN_MAC));
2675
2676         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2677         if (mi == 0xffffffff) {
2678                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2679                           __func__);
2680                 brcms_down(wlc->wl);
2681                 return;
2682         }
2683         WARN_ON(mi & MI_MACSSPNDD);
2684
2685         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2686
2687         SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2688                  BRCMS_MAX_MAC_SUSPEND);
2689
2690         if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2691                 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2692                           " and MI_MACSSPNDD is still not on.\n",
2693                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2694                 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2695                           "psm_brc 0x%04x\n", wlc_hw->unit,
2696                           bcma_read32(core, D11REGOFFS(psmdebug)),
2697                           bcma_read32(core, D11REGOFFS(phydebug)),
2698                           bcma_read16(core, D11REGOFFS(psm_brc)));
2699         }
2700
2701         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2702         if (mc == 0xffffffff) {
2703                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2704                           __func__);
2705                 brcms_down(wlc->wl);
2706                 return;
2707         }
2708         WARN_ON(mc & MCTL_PSM_JMP_0);
2709         WARN_ON(!(mc & MCTL_PSM_RUN));
2710         WARN_ON(mc & MCTL_EN_MAC);
2711 }
2712
2713 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2714 {
2715         struct brcms_hardware *wlc_hw = wlc->hw;
2716         struct bcma_device *core = wlc_hw->d11core;
2717         u32 mc, mi;
2718
2719         brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2720                            wlc->band->bandunit);
2721
2722         /*
2723          * Track overlapping suspend requests
2724          */
2725         wlc_hw->mac_suspend_depth--;
2726         if (wlc_hw->mac_suspend_depth > 0)
2727                 return;
2728
2729         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2730         WARN_ON(mc & MCTL_PSM_JMP_0);
2731         WARN_ON(mc & MCTL_EN_MAC);
2732         WARN_ON(!(mc & MCTL_PSM_RUN));
2733
2734         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2735         bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2736
2737         mc = bcma_read32(core, D11REGOFFS(maccontrol));
2738         WARN_ON(mc & MCTL_PSM_JMP_0);
2739         WARN_ON(!(mc & MCTL_EN_MAC));
2740         WARN_ON(!(mc & MCTL_PSM_RUN));
2741
2742         mi = bcma_read32(core, D11REGOFFS(macintstatus));
2743         WARN_ON(mi & MI_MACSSPNDD);
2744
2745         brcms_c_ucode_wake_override_clear(wlc_hw,
2746                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2747 }
2748
2749 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2750 {
2751         wlc_hw->hw_stf_ss_opmode = stf_mode;
2752
2753         if (wlc_hw->clk)
2754                 brcms_upd_ofdm_pctl1_table(wlc_hw);
2755 }
2756
2757 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2758 {
2759         struct bcma_device *core = wlc_hw->d11core;
2760         u32 w, val;
2761         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2762
2763         /* Validate dchip register access */
2764
2765         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2766         (void)bcma_read32(core, D11REGOFFS(objaddr));
2767         w = bcma_read32(core, D11REGOFFS(objdata));
2768
2769         /* Can we write and read back a 32bit register? */
2770         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2771         (void)bcma_read32(core, D11REGOFFS(objaddr));
2772         bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2773
2774         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2775         (void)bcma_read32(core, D11REGOFFS(objaddr));
2776         val = bcma_read32(core, D11REGOFFS(objdata));
2777         if (val != (u32) 0xaa5555aa) {
2778                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2779                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
2780                 return false;
2781         }
2782
2783         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2784         (void)bcma_read32(core, D11REGOFFS(objaddr));
2785         bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2786
2787         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2788         (void)bcma_read32(core, D11REGOFFS(objaddr));
2789         val = bcma_read32(core, D11REGOFFS(objdata));
2790         if (val != (u32) 0x55aaaa55) {
2791                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2792                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
2793                 return false;
2794         }
2795
2796         bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2797         (void)bcma_read32(core, D11REGOFFS(objaddr));
2798         bcma_write32(core, D11REGOFFS(objdata), w);
2799
2800         /* clear CFPStart */
2801         bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2802
2803         w = bcma_read32(core, D11REGOFFS(maccontrol));
2804         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2805             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2806                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2807                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2808                           (MCTL_IHR_EN | MCTL_WAKE),
2809                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2810                 return false;
2811         }
2812
2813         return true;
2814 }
2815
2816 #define PHYPLL_WAIT_US  100000
2817
2818 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2819 {
2820         struct bcma_device *core = wlc_hw->d11core;
2821         u32 tmp;
2822
2823         brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2824
2825         tmp = 0;
2826
2827         if (on) {
2828                 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2829                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2830                                    CCS_ERSRC_REQ_HT |
2831                                    CCS_ERSRC_REQ_D11PLL |
2832                                    CCS_ERSRC_REQ_PHYPLL);
2833                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2834                                   CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2835                                  PHYPLL_WAIT_US);
2836
2837                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2838                         if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2839                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2840                                           __func__);
2841                 } else {
2842                         bcma_set32(core, D11REGOFFS(clk_ctl_st),
2843                                    tmp | CCS_ERSRC_REQ_D11PLL |
2844                                    CCS_ERSRC_REQ_PHYPLL);
2845                         SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2846                                   (CCS_ERSRC_AVAIL_D11PLL |
2847                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
2848                                  (CCS_ERSRC_AVAIL_D11PLL |
2849                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2850
2851                         tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2852                         if ((tmp &
2853                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2854                             !=
2855                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2856                                 brcms_err(core, "%s: turn on PHY PLL failed\n",
2857                                           __func__);
2858                 }
2859         } else {
2860                 /*
2861                  * Since the PLL may be shared, other cores can still
2862                  * be requesting it; so we'll deassert the request but
2863                  * not wait for status to comply.
2864                  */
2865                 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2866                             ~CCS_ERSRC_REQ_PHYPLL);
2867                 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2868         }
2869 }
2870
2871 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2872 {
2873         bool dev_gone;
2874
2875         brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2876
2877         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2878
2879         if (dev_gone)
2880                 return;
2881
2882         if (wlc_hw->noreset)
2883                 return;
2884
2885         /* radio off */
2886         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2887
2888         /* turn off analog core */
2889         wlc_phy_anacore(wlc_hw->band->pi, OFF);
2890
2891         /* turn off PHYPLL to save power */
2892         brcms_b_core_phypll_ctl(wlc_hw, false);
2893
2894         wlc_hw->clk = false;
2895         bcma_core_disable(wlc_hw->d11core, 0);
2896         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2897 }
2898
2899 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2900 {
2901         struct brcms_hardware *wlc_hw = wlc->hw;
2902         uint i;
2903
2904         /* free any posted tx packets */
2905         for (i = 0; i < NFIFO; i++) {
2906                 if (wlc_hw->di[i]) {
2907                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2908                         if (i < TX_BCMC_FIFO)
2909                                 ieee80211_wake_queue(wlc->pub->ieee_hw,
2910                                                      brcms_fifo_to_ac(i));
2911                 }
2912         }
2913
2914         /* free any posted rx packets */
2915         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2916 }
2917
2918 static u16
2919 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2920 {
2921         struct bcma_device *core = wlc_hw->d11core;
2922         u16 objoff = D11REGOFFS(objdata);
2923
2924         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2925         (void)bcma_read32(core, D11REGOFFS(objaddr));
2926         if (offset & 2)
2927                 objoff += 2;
2928
2929         return bcma_read16(core, objoff);
2930 }
2931
2932 static void
2933 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2934                      u32 sel)
2935 {
2936         struct bcma_device *core = wlc_hw->d11core;
2937         u16 objoff = D11REGOFFS(objdata);
2938
2939         bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2940         (void)bcma_read32(core, D11REGOFFS(objaddr));
2941         if (offset & 2)
2942                 objoff += 2;
2943
2944         bcma_wflush16(core, objoff, v);
2945 }
2946
2947 /*
2948  * Read a single u16 from shared memory.
2949  * SHM 'offset' needs to be an even address
2950  */
2951 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2952 {
2953         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2954 }
2955
2956 /*
2957  * Write a single u16 to shared memory.
2958  * SHM 'offset' needs to be an even address
2959  */
2960 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2961 {
2962         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2963 }
2964
2965 /*
2966  * Copy a buffer to shared memory of specified type .
2967  * SHM 'offset' needs to be an even address and
2968  * Buffer length 'len' must be an even number of bytes
2969  * 'sel' selects the type of memory
2970  */
2971 void
2972 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2973                       const void *buf, int len, u32 sel)
2974 {
2975         u16 v;
2976         const u8 *p = (const u8 *)buf;
2977         int i;
2978
2979         if (len <= 0 || (offset & 1) || (len & 1))
2980                 return;
2981
2982         for (i = 0; i < len; i += 2) {
2983                 v = p[i] | (p[i + 1] << 8);
2984                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2985         }
2986 }
2987
2988 /*
2989  * Copy a piece of shared memory of specified type to a buffer .
2990  * SHM 'offset' needs to be an even address and
2991  * Buffer length 'len' must be an even number of bytes
2992  * 'sel' selects the type of memory
2993  */
2994 void
2995 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2996                          int len, u32 sel)
2997 {
2998         u16 v;
2999         u8 *p = (u8 *) buf;
3000         int i;
3001
3002         if (len <= 0 || (offset & 1) || (len & 1))
3003                 return;
3004
3005         for (i = 0; i < len; i += 2) {
3006                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3007                 p[i] = v & 0xFF;
3008                 p[i + 1] = (v >> 8) & 0xFF;
3009         }
3010 }
3011
3012 /* Copy a buffer to shared memory.
3013  * SHM 'offset' needs to be an even address and
3014  * Buffer length 'len' must be an even number of bytes
3015  */
3016 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
3017                         const void *buf, int len)
3018 {
3019         brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3020 }
3021
3022 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3023                                    u16 SRL, u16 LRL)
3024 {
3025         wlc_hw->SRL = SRL;
3026         wlc_hw->LRL = LRL;
3027
3028         /* write retry limit to SCR, shouldn't need to suspend */
3029         if (wlc_hw->up) {
3030                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3031                              OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3032                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3033                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3034                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3035                              OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3036                 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3037                 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3038         }
3039 }
3040
3041 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3042 {
3043         if (set) {
3044                 if (mboolisset(wlc_hw->pllreq, req_bit))
3045                         return;
3046
3047                 mboolset(wlc_hw->pllreq, req_bit);
3048
3049                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3050                         if (!wlc_hw->sbclk)
3051                                 brcms_b_xtal(wlc_hw, ON);
3052                 }
3053         } else {
3054                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3055                         return;
3056
3057                 mboolclr(wlc_hw->pllreq, req_bit);
3058
3059                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3060                         if (wlc_hw->sbclk)
3061                                 brcms_b_xtal(wlc_hw, OFF);
3062                 }
3063         }
3064 }
3065
3066 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3067 {
3068         wlc_hw->antsel_avail = antsel_avail;
3069 }
3070
3071 /*
3072  * conditions under which the PM bit should be set in outgoing frames
3073  * and STAY_AWAKE is meaningful
3074  */
3075 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3076 {
3077         /* disallow PS when one of the following global conditions meets */
3078         if (!wlc->pub->associated)
3079                 return false;
3080
3081         /* disallow PS when one of these meets when not scanning */
3082         if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3083                 return false;
3084
3085         if (wlc->bsscfg->type == BRCMS_TYPE_AP)
3086                 return false;
3087
3088         if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
3089                 return false;
3090
3091         return true;
3092 }
3093
3094 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3095 {
3096         int i;
3097         struct macstat macstats;
3098 #ifdef DEBUG
3099         u16 delta;
3100         u16 rxf0ovfl;
3101         u16 txfunfl[NFIFO];
3102 #endif                          /* DEBUG */
3103
3104         /* if driver down, make no sense to update stats */
3105         if (!wlc->pub->up)
3106                 return;
3107
3108 #ifdef DEBUG
3109         /* save last rx fifo 0 overflow count */
3110         rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3111
3112         /* save last tx fifo  underflow count */
3113         for (i = 0; i < NFIFO; i++)
3114                 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3115 #endif                          /* DEBUG */
3116
3117         /* Read mac stats from contiguous shared memory */
3118         brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3119                                 sizeof(struct macstat), OBJADDR_SHM_SEL);
3120
3121 #ifdef DEBUG
3122         /* check for rx fifo 0 overflow */
3123         delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3124         if (delta)
3125                 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3126                           wlc->pub->unit, delta);
3127
3128         /* check for tx fifo underflows */
3129         for (i = 0; i < NFIFO; i++) {
3130                 delta =
3131                     (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3132                               txfunfl[i]);
3133                 if (delta)
3134                         brcms_err(wlc->hw->d11core,
3135                                   "wl%d: %u tx fifo %d underflows!\n",
3136                                   wlc->pub->unit, delta, i);
3137         }
3138 #endif                          /* DEBUG */
3139
3140         /* merge counters from dma module */
3141         for (i = 0; i < NFIFO; i++) {
3142                 if (wlc->hw->di[i])
3143                         dma_counterreset(wlc->hw->di[i]);
3144         }
3145 }
3146
3147 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3148 {
3149         /* reset the core */
3150         if (!brcms_deviceremoved(wlc_hw->wlc))
3151                 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3152
3153         /* purge the dma rings */
3154         brcms_c_flushqueues(wlc_hw->wlc);
3155 }
3156
3157 void brcms_c_reset(struct brcms_c_info *wlc)
3158 {
3159         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3160
3161         /* slurp up hw mac counters before core reset */
3162         brcms_c_statsupd(wlc);
3163
3164         /* reset our snapshot of macstat counters */
3165         memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3166
3167         brcms_b_reset(wlc->hw);
3168 }
3169
3170 void brcms_c_init_scb(struct scb *scb)
3171 {
3172         int i;
3173
3174         memset(scb, 0, sizeof(struct scb));
3175         scb->flags = SCB_WMECAP | SCB_HTCAP;
3176         for (i = 0; i < NUMPRIO; i++) {
3177                 scb->seqnum[i] = 0;
3178                 scb->seqctl[i] = 0xFFFF;
3179         }
3180
3181         scb->seqctl_nonqos = 0xFFFF;
3182         scb->magic = SCB_MAGIC;
3183 }
3184
3185 /* d11 core init
3186  *   reset PSM
3187  *   download ucode/PCM
3188  *   let ucode run to suspended
3189  *   download ucode inits
3190  *   config other core registers
3191  *   init dma
3192  */
3193 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3194 {
3195         struct brcms_hardware *wlc_hw = wlc->hw;
3196         struct bcma_device *core = wlc_hw->d11core;
3197         u32 sflags;
3198         u32 bcnint_us;
3199         uint i = 0;
3200         bool fifosz_fixup = false;
3201         int err = 0;
3202         u16 buf[NFIFO];
3203         struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3204
3205         brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3206
3207         /* reset PSM */
3208         brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3209
3210         brcms_ucode_download(wlc_hw);
3211         /*
3212          * FIFOSZ fixup. driver wants to controls the fifo allocation.
3213          */
3214         fifosz_fixup = true;
3215
3216         /* let the PSM run to the suspended state, set mode to BSS STA */
3217         bcma_write32(core, D11REGOFFS(macintstatus), -1);
3218         brcms_b_mctrl(wlc_hw, ~0,
3219                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3220
3221         /* wait for ucode to self-suspend after auto-init */
3222         SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3223                    MI_MACSSPNDD) == 0), 1000 * 1000);
3224         if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3225                 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3226                           "suspend!\n", wlc_hw->unit);
3227
3228         brcms_c_gpio_init(wlc);
3229
3230         sflags = bcma_aread32(core, BCMA_IOST);
3231
3232         if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3233                 if (BRCMS_ISNPHY(wlc_hw->band))
3234                         brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3235                 else
3236                         brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3237                                   " %d\n", __func__, wlc_hw->unit,
3238                                   wlc_hw->corerev);
3239         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3240                 if (BRCMS_ISLCNPHY(wlc_hw->band))
3241                         brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3242                 else
3243                         brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3244                                   " %d\n", __func__, wlc_hw->unit,
3245                                   wlc_hw->corerev);
3246         } else {
3247                 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3248                           __func__, wlc_hw->unit, wlc_hw->corerev);
3249         }
3250
3251         /* For old ucode, txfifo sizes needs to be modified(increased) */
3252         if (fifosz_fixup)
3253                 brcms_b_corerev_fifofixup(wlc_hw);
3254
3255         /* check txfifo allocations match between ucode and driver */
3256         buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3257         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3258                 i = TX_AC_BE_FIFO;
3259                 err = -1;
3260         }
3261         buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3262         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3263                 i = TX_AC_VI_FIFO;
3264                 err = -1;
3265         }
3266         buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3267         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3268         buf[TX_AC_BK_FIFO] &= 0xff;
3269         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3270                 i = TX_AC_BK_FIFO;
3271                 err = -1;
3272         }
3273         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3274                 i = TX_AC_VO_FIFO;
3275                 err = -1;
3276         }
3277         buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3278         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3279         buf[TX_BCMC_FIFO] &= 0xff;
3280         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3281                 i = TX_BCMC_FIFO;
3282                 err = -1;
3283         }
3284         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3285                 i = TX_ATIM_FIFO;
3286                 err = -1;
3287         }
3288         if (err != 0)
3289                 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3290                           " driver size %d index %d\n", buf[i],
3291                           wlc_hw->xmtfifo_sz[i], i);
3292
3293         /* make sure we can still talk to the mac */
3294         WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3295
3296         /* band-specific inits done by wlc_bsinit() */
3297
3298         /* Set up frame burst size and antenna swap threshold init values */
3299         brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3300         brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3301
3302         /* enable one rx interrupt per received frame */
3303         bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3304
3305         /* set the station mode (BSS STA) */
3306         brcms_b_mctrl(wlc_hw,
3307                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3308                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
3309
3310         /* set up Beacon interval */
3311         bcnint_us = 0x8000 << 10;
3312         bcma_write32(core, D11REGOFFS(tsf_cfprep),
3313                      (bcnint_us << CFPREP_CBI_SHIFT));
3314         bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3315         bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3316
3317         /* write interrupt mask */
3318         bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3319                      DEF_RXINTMASK);
3320
3321         /* allow the MAC to control the PHY clock (dynamic on/off) */
3322         brcms_b_macphyclk_set(wlc_hw, ON);
3323
3324         /* program dynamic clock control fast powerup delay register */
3325         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3326         bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3327
3328         /* tell the ucode the corerev */
3329         brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3330
3331         /* tell the ucode MAC capabilities */
3332         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3333                            (u16) (wlc_hw->machwcap & 0xffff));
3334         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3335                            (u16) ((wlc_hw->
3336                                       machwcap >> 16) & 0xffff));
3337
3338         /* write retry limits to SCR, this done after PSM init */
3339         bcma_write32(core, D11REGOFFS(objaddr),
3340                      OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3341         (void)bcma_read32(core, D11REGOFFS(objaddr));
3342         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3343         bcma_write32(core, D11REGOFFS(objaddr),
3344                      OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3345         (void)bcma_read32(core, D11REGOFFS(objaddr));
3346         bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3347
3348         /* write rate fallback retry limits */
3349         brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3350         brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3351
3352         bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3353         bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3354
3355         /* init the tx dma engines */
3356         for (i = 0; i < NFIFO; i++) {
3357                 if (wlc_hw->di[i])
3358                         dma_txinit(wlc_hw->di[i]);
3359         }
3360
3361         /* init the rx dma engine(s) and post receive buffers */
3362         dma_rxinit(wlc_hw->di[RX_FIFO]);
3363         dma_rxfill(wlc_hw->di[RX_FIFO]);
3364 }
3365
3366 void
3367 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3368         u32 macintmask;
3369         bool fastclk;
3370         struct brcms_c_info *wlc = wlc_hw->wlc;
3371
3372         /* request FAST clock if not on */
3373         fastclk = wlc_hw->forcefastclk;
3374         if (!fastclk)
3375                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3376
3377         /* disable interrupts */
3378         macintmask = brcms_intrsoff(wlc->wl);
3379
3380         /* set up the specified band and chanspec */
3381         brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3382         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3383
3384         /* do one-time phy inits and calibration */
3385         wlc_phy_cal_init(wlc_hw->band->pi);
3386
3387         /* core-specific initialization */
3388         brcms_b_coreinit(wlc);
3389
3390         /* band-specific inits */
3391         brcms_b_bsinit(wlc, chanspec);
3392
3393         /* restore macintmask */
3394         brcms_intrsrestore(wlc->wl, macintmask);
3395
3396         /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3397          * is suspended and brcms_c_enable_mac() will clear this override bit.
3398          */
3399         mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3400
3401         /*
3402          * initialize mac_suspend_depth to 1 to match ucode
3403          * initial suspended state
3404          */
3405         wlc_hw->mac_suspend_depth = 1;
3406
3407         /* restore the clk */
3408         if (!fastclk)
3409                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3410 }
3411
3412 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3413                                      u16 chanspec)
3414 {
3415         /* Save our copy of the chanspec */
3416         wlc->chanspec = chanspec;
3417
3418         /* Set the chanspec and power limits for this locale */
3419         brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3420
3421         if (wlc->stf->ss_algosel_auto)
3422                 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3423                                             chanspec);
3424
3425         brcms_c_stf_ss_update(wlc, wlc->band);
3426 }
3427
3428 static void
3429 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3430 {
3431         brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3432                 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3433                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3434                 brcms_chspec_bw(wlc->default_bss->chanspec),
3435                 wlc->stf->txstreams);
3436 }
3437
3438 /* derive wlc->band->basic_rate[] table from 'rateset' */
3439 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3440                               struct brcms_c_rateset *rateset)
3441 {
3442         u8 rate;
3443         u8 mandatory;
3444         u8 cck_basic = 0;
3445         u8 ofdm_basic = 0;
3446         u8 *br = wlc->band->basic_rate;
3447         uint i;
3448
3449         /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3450         memset(br, 0, BRCM_MAXRATE + 1);
3451
3452         /* For each basic rate in the rates list, make an entry in the
3453          * best basic lookup.
3454          */
3455         for (i = 0; i < rateset->count; i++) {
3456                 /* only make an entry for a basic rate */
3457                 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3458                         continue;
3459
3460                 /* mask off basic bit */
3461                 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3462
3463                 if (rate > BRCM_MAXRATE) {
3464                         brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3465                                   "invalid rate 0x%X in rate set\n",
3466                                   rateset->rates[i]);
3467                         continue;
3468                 }
3469
3470                 br[rate] = rate;
3471         }
3472
3473         /* The rate lookup table now has non-zero entries for each
3474          * basic rate, equal to the basic rate: br[basicN] = basicN
3475          *
3476          * To look up the best basic rate corresponding to any
3477          * particular rate, code can use the basic_rate table
3478          * like this
3479          *
3480          * basic_rate = wlc->band->basic_rate[tx_rate]
3481          *
3482          * Make sure there is a best basic rate entry for
3483          * every rate by walking up the table from low rates
3484          * to high, filling in holes in the lookup table
3485          */
3486
3487         for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3488                 rate = wlc->band->hw_rateset.rates[i];
3489
3490                 if (br[rate] != 0) {
3491                         /* This rate is a basic rate.
3492                          * Keep track of the best basic rate so far by
3493                          * modulation type.
3494                          */
3495                         if (is_ofdm_rate(rate))
3496                                 ofdm_basic = rate;
3497                         else
3498                                 cck_basic = rate;
3499
3500                         continue;
3501                 }
3502
3503                 /* This rate is not a basic rate so figure out the
3504                  * best basic rate less than this rate and fill in
3505                  * the hole in the table
3506                  */
3507
3508                 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3509
3510                 if (br[rate] != 0)
3511                         continue;
3512
3513                 if (is_ofdm_rate(rate)) {
3514                         /*
3515                          * In 11g and 11a, the OFDM mandatory rates
3516                          * are 6, 12, and 24 Mbps
3517                          */
3518                         if (rate >= BRCM_RATE_24M)
3519                                 mandatory = BRCM_RATE_24M;
3520                         else if (rate >= BRCM_RATE_12M)
3521                                 mandatory = BRCM_RATE_12M;
3522                         else
3523                                 mandatory = BRCM_RATE_6M;
3524                 } else {
3525                         /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3526                         mandatory = rate;
3527                 }
3528
3529                 br[rate] = mandatory;
3530         }
3531 }
3532
3533 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3534                                      u16 chanspec)
3535 {
3536         struct brcms_c_rateset default_rateset;
3537         uint parkband;
3538         uint i, band_order[2];
3539
3540         /*
3541          * We might have been bandlocked during down and the chip
3542          * power-cycled (hibernate). Figure out the right band to park on
3543          */
3544         if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3545                 /* updated in brcms_c_bandlock() */
3546                 parkband = wlc->band->bandunit;
3547                 band_order[0] = band_order[1] = parkband;
3548         } else {
3549                 /* park on the band of the specified chanspec */
3550                 parkband = chspec_bandunit(chanspec);
3551
3552                 /* order so that parkband initialize last */
3553                 band_order[0] = parkband ^ 1;
3554                 band_order[1] = parkband;
3555         }
3556
3557         /* make each band operational, software state init */
3558         for (i = 0; i < wlc->pub->_nbands; i++) {
3559                 uint j = band_order[i];
3560
3561                 wlc->band = wlc->bandstate[j];
3562
3563                 brcms_default_rateset(wlc, &default_rateset);
3564
3565                 /* fill in hw_rate */
3566                 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3567                                    false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3568                                    (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3569
3570                 /* init basic rate lookup */
3571                 brcms_c_rate_lookup_init(wlc, &default_rateset);
3572         }
3573
3574         /* sync up phy/radio chanspec */
3575         brcms_c_set_phy_chanspec(wlc, chanspec);
3576 }
3577
3578 /*
3579  * Set or clear filtering related maccontrol bits based on
3580  * specified filter flags
3581  */
3582 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3583 {
3584         u32 promisc_bits = 0;
3585
3586         wlc->filter_flags = filter_flags;
3587
3588         if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3589                 promisc_bits |= MCTL_PROMISC;
3590
3591         if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3592                 promisc_bits |= MCTL_BCNS_PROMISC;
3593
3594         if (filter_flags & FIF_FCSFAIL)
3595                 promisc_bits |= MCTL_KEEPBADFCS;
3596
3597         if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3598                 promisc_bits |= MCTL_KEEPCONTROL;
3599
3600         brcms_b_mctrl(wlc->hw,
3601                 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3602                 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3603                 promisc_bits);
3604 }
3605
3606 /*
3607  * ucode, hwmac update
3608  *    Channel dependent updates for ucode and hw
3609  */
3610 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3611 {
3612         /* enable or disable any active IBSSs depending on whether or not
3613          * we are on the home channel
3614          */
3615         if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3616                 if (wlc->pub->associated) {
3617                         /*
3618                          * BMAC_NOTE: This is something that should be fixed
3619                          * in ucode inits. I think that the ucode inits set
3620                          * up the bcn templates and shm values with a bogus
3621                          * beacon. This should not be done in the inits. If
3622                          * ucode needs to set up a beacon for testing, the
3623                          * test routines should write it down, not expect the
3624                          * inits to populate a bogus beacon.
3625                          */
3626                         if (BRCMS_PHY_11N_CAP(wlc->band))
3627                                 brcms_b_write_shm(wlc->hw,
3628                                                 M_BCN_TXTSF_OFFSET, 0);
3629                 }
3630         } else {
3631                 /* disable an active IBSS if we are not on the home channel */
3632         }
3633 }
3634
3635 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3636                                    u8 basic_rate)
3637 {
3638         u8 phy_rate, index;
3639         u8 basic_phy_rate, basic_index;
3640         u16 dir_table, basic_table;
3641         u16 basic_ptr;
3642
3643         /* Shared memory address for the table we are reading */
3644         dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3645
3646         /* Shared memory address for the table we are writing */
3647         basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3648
3649         /*
3650          * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3651          * the index into the rate table.
3652          */
3653         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3654         basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3655         index = phy_rate & 0xf;
3656         basic_index = basic_phy_rate & 0xf;
3657
3658         /* Find the SHM pointer to the ACK rate entry by looking in the
3659          * Direct-map Table
3660          */
3661         basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3662
3663         /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3664          * to the correct basic rate for the given incoming rate
3665          */
3666         brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3667 }
3668
3669 static const struct brcms_c_rateset *
3670 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3671 {
3672         const struct brcms_c_rateset *rs_dflt;
3673
3674         if (BRCMS_PHY_11N_CAP(wlc->band)) {
3675                 if (wlc->band->bandtype == BRCM_BAND_5G)
3676                         rs_dflt = &ofdm_mimo_rates;
3677                 else
3678                         rs_dflt = &cck_ofdm_mimo_rates;
3679         } else if (wlc->band->gmode)
3680                 rs_dflt = &cck_ofdm_rates;
3681         else
3682                 rs_dflt = &cck_rates;
3683
3684         return rs_dflt;
3685 }
3686
3687 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3688 {
3689         const struct brcms_c_rateset *rs_dflt;
3690         struct brcms_c_rateset rs;
3691         u8 rate, basic_rate;
3692         uint i;
3693
3694         rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3695
3696         brcms_c_rateset_copy(rs_dflt, &rs);
3697         brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3698
3699         /* walk the phy rate table and update SHM basic rate lookup table */
3700         for (i = 0; i < rs.count; i++) {
3701                 rate = rs.rates[i] & BRCMS_RATE_MASK;
3702
3703                 /* for a given rate brcms_basic_rate returns the rate at
3704                  * which a response ACK/CTS should be sent.
3705                  */
3706                 basic_rate = brcms_basic_rate(wlc, rate);
3707                 if (basic_rate == 0)
3708                         /* This should only happen if we are using a
3709                          * restricted rateset.
3710                          */
3711                         basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3712
3713                 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3714         }
3715 }
3716
3717 /* band-specific init */
3718 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3719 {
3720         brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3721                        wlc->pub->unit, wlc->band->bandunit);
3722
3723         /* write ucode ACK/CTS rate table */
3724         brcms_c_set_ratetable(wlc);
3725
3726         /* update some band specific mac configuration */
3727         brcms_c_ucode_mac_upd(wlc);
3728
3729         /* init antenna selection */
3730         brcms_c_antsel_init(wlc->asi);
3731
3732 }
3733
3734 /* formula:  IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3735 static int
3736 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3737                    bool writeToShm)
3738 {
3739         int idle_busy_ratio_x_16 = 0;
3740         uint offset =
3741             isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3742             M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3743         if (duty_cycle > 100 || duty_cycle < 0) {
3744                 brcms_err(wlc->hw->d11core,
3745                           "wl%d:  duty cycle value off limit\n",
3746                           wlc->pub->unit);
3747                 return -EINVAL;
3748         }
3749         if (duty_cycle)
3750                 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3751         /* Only write to shared memory  when wl is up */
3752         if (writeToShm)
3753                 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3754
3755         if (isOFDM)
3756                 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3757         else
3758                 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3759
3760         return 0;
3761 }
3762
3763 /* push sw hps and wake state through hardware */
3764 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3765 {
3766         u32 v1, v2;
3767         bool hps;
3768         bool awake_before;
3769
3770         hps = brcms_c_ps_allowed(wlc);
3771
3772         brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3773                            hps);
3774
3775         v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3776         v2 = MCTL_WAKE;
3777         if (hps)
3778                 v2 |= MCTL_HPS;
3779
3780         brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3781
3782         awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3783
3784         if (!awake_before)
3785                 brcms_b_wait_for_wake(wlc->hw);
3786 }
3787
3788 /*
3789  * Write this BSS config's MAC address to core.
3790  * Updates RXE match engine.
3791  */
3792 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3793 {
3794         int err = 0;
3795         struct brcms_c_info *wlc = bsscfg->wlc;
3796
3797         /* enter the MAC addr into the RXE match registers */
3798         brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, wlc->pub->cur_etheraddr);
3799
3800         brcms_c_ampdu_macaddr_upd(wlc);
3801
3802         return err;
3803 }
3804
3805 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3806  * Updates RXE match engine.
3807  */
3808 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3809 {
3810         /* we need to update BSSID in RXE match registers */
3811         brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3812 }
3813
3814 void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len)
3815 {
3816         u8 len = min_t(u8, sizeof(wlc->bsscfg->SSID), ssid_len);
3817         memset(wlc->bsscfg->SSID, 0, sizeof(wlc->bsscfg->SSID));
3818
3819         memcpy(wlc->bsscfg->SSID, ssid, len);
3820         wlc->bsscfg->SSID_len = len;
3821 }
3822
3823 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3824 {
3825         wlc_hw->shortslot = shortslot;
3826
3827         if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3828                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3829                 brcms_b_update_slot_timing(wlc_hw, shortslot);
3830                 brcms_c_enable_mac(wlc_hw->wlc);
3831         }
3832 }
3833
3834 /*
3835  * Suspend the the MAC and update the slot timing
3836  * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3837  */
3838 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3839 {
3840         /* use the override if it is set */
3841         if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3842                 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3843
3844         if (wlc->shortslot == shortslot)
3845                 return;
3846
3847         wlc->shortslot = shortslot;
3848
3849         brcms_b_set_shortslot(wlc->hw, shortslot);
3850 }
3851
3852 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3853 {
3854         if (wlc->home_chanspec != chanspec) {
3855                 wlc->home_chanspec = chanspec;
3856
3857                 if (wlc->pub->associated)
3858                         wlc->bsscfg->current_bss->chanspec = chanspec;
3859         }
3860 }
3861
3862 void
3863 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3864                       bool mute_tx, struct txpwr_limits *txpwr)
3865 {
3866         uint bandunit;
3867
3868         brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3869                            chanspec);
3870
3871         wlc_hw->chanspec = chanspec;
3872
3873         /* Switch bands if necessary */
3874         if (wlc_hw->_nbands > 1) {
3875                 bandunit = chspec_bandunit(chanspec);
3876                 if (wlc_hw->band->bandunit != bandunit) {
3877                         /* brcms_b_setband disables other bandunit,
3878                          *  use light band switch if not up yet
3879                          */
3880                         if (wlc_hw->up) {
3881                                 wlc_phy_chanspec_radio_set(wlc_hw->
3882                                                            bandstate[bandunit]->
3883                                                            pi, chanspec);
3884                                 brcms_b_setband(wlc_hw, bandunit, chanspec);
3885                         } else {
3886                                 brcms_c_setxband(wlc_hw, bandunit);
3887                         }
3888                 }
3889         }
3890
3891         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3892
3893         if (!wlc_hw->up) {
3894                 if (wlc_hw->clk)
3895                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3896                                                   chanspec);
3897                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3898         } else {
3899                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3900                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3901
3902                 /* Update muting of the channel */
3903                 brcms_b_mute(wlc_hw, mute_tx);
3904         }
3905 }
3906
3907 /* switch to and initialize new band */
3908 static void brcms_c_setband(struct brcms_c_info *wlc,
3909                                            uint bandunit)
3910 {
3911         wlc->band = wlc->bandstate[bandunit];
3912
3913         if (!wlc->pub->up)
3914                 return;
3915
3916         /* wait for at least one beacon before entering sleeping state */
3917         brcms_c_set_ps_ctrl(wlc);
3918
3919         /* band-specific initializations */
3920         brcms_c_bsinit(wlc);
3921 }
3922
3923 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3924 {
3925         uint bandunit;
3926         bool switchband = false;
3927         u16 old_chanspec = wlc->chanspec;
3928
3929         if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3930                 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3931                           wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3932                 return;
3933         }
3934
3935         /* Switch bands if necessary */
3936         if (wlc->pub->_nbands > 1) {
3937                 bandunit = chspec_bandunit(chanspec);
3938                 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3939                         switchband = true;
3940                         if (wlc->bandlocked) {
3941                                 brcms_err(wlc->hw->d11core,
3942                                           "wl%d: %s: chspec %d band is locked!\n",
3943                                           wlc->pub->unit, __func__,
3944                                           CHSPEC_CHANNEL(chanspec));
3945                                 return;
3946                         }
3947                         /*
3948                          * should the setband call come after the
3949                          * brcms_b_chanspec() ? if the setband updates
3950                          * (brcms_c_bsinit) use low level calls to inspect and
3951                          * set state, the state inspected may be from the wrong
3952                          * band, or the following brcms_b_set_chanspec() may
3953                          * undo the work.
3954                          */
3955                         brcms_c_setband(wlc, bandunit);
3956                 }
3957         }
3958
3959         /* sync up phy/radio chanspec */
3960         brcms_c_set_phy_chanspec(wlc, chanspec);
3961
3962         /* init antenna selection */
3963         if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3964                 brcms_c_antsel_init(wlc->asi);
3965
3966                 /* Fix the hardware rateset based on bw.
3967                  * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3968                  */
3969                 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3970                         wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3971         }
3972
3973         /* update some mac configuration since chanspec changed */
3974         brcms_c_ucode_mac_upd(wlc);
3975 }
3976
3977 /*
3978  * This function changes the phytxctl for beacon based on current
3979  * beacon ratespec AND txant setting as per this table:
3980  *  ratespec     CCK            ant = wlc->stf->txant
3981  *              OFDM            ant = 3
3982  */
3983 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3984                                        u32 bcn_rspec)
3985 {
3986         u16 phyctl;
3987         u16 phytxant = wlc->stf->phytxant;
3988         u16 mask = PHY_TXC_ANT_MASK;
3989
3990         /* for non-siso rates or default setting, use the available chains */
3991         if (BRCMS_PHY_11N_CAP(wlc->band))
3992                 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3993
3994         phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3995         phyctl = (phyctl & ~mask) | phytxant;
3996         brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3997 }
3998
3999 /*
4000  * centralized protection config change function to simplify debugging, no
4001  * consistency checking this should be called only on changes to avoid overhead
4002  * in periodic function
4003  */
4004 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
4005 {
4006         /*
4007          * Cannot use brcms_dbg_* here because this function is called
4008          * before wlc is sufficiently initialized.
4009          */
4010         BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
4011
4012         switch (idx) {
4013         case BRCMS_PROT_G_SPEC:
4014                 wlc->protection->_g = (bool) val;
4015                 break;
4016         case BRCMS_PROT_G_OVR:
4017                 wlc->protection->g_override = (s8) val;
4018                 break;
4019         case BRCMS_PROT_G_USER:
4020                 wlc->protection->gmode_user = (u8) val;
4021                 break;
4022         case BRCMS_PROT_OVERLAP:
4023                 wlc->protection->overlap = (s8) val;
4024                 break;
4025         case BRCMS_PROT_N_USER:
4026                 wlc->protection->nmode_user = (s8) val;
4027                 break;
4028         case BRCMS_PROT_N_CFG:
4029                 wlc->protection->n_cfg = (s8) val;
4030                 break;
4031         case BRCMS_PROT_N_CFG_OVR:
4032                 wlc->protection->n_cfg_override = (s8) val;
4033                 break;
4034         case BRCMS_PROT_N_NONGF:
4035                 wlc->protection->nongf = (bool) val;
4036                 break;
4037         case BRCMS_PROT_N_NONGF_OVR:
4038                 wlc->protection->nongf_override = (s8) val;
4039                 break;
4040         case BRCMS_PROT_N_PAM_OVR:
4041                 wlc->protection->n_pam_override = (s8) val;
4042                 break;
4043         case BRCMS_PROT_N_OBSS:
4044                 wlc->protection->n_obss = (bool) val;
4045                 break;
4046
4047         default:
4048                 break;
4049         }
4050
4051 }
4052
4053 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4054 {
4055         if (wlc->pub->up) {
4056                 brcms_c_update_beacon(wlc);
4057                 brcms_c_update_probe_resp(wlc, true);
4058         }
4059 }
4060
4061 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4062 {
4063         wlc->stf->ldpc = val;
4064
4065         if (wlc->pub->up) {
4066                 brcms_c_update_beacon(wlc);
4067                 brcms_c_update_probe_resp(wlc, true);
4068                 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4069         }
4070 }
4071
4072 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4073                        const struct ieee80211_tx_queue_params *params,
4074                        bool suspend)
4075 {
4076         int i;
4077         struct shm_acparams acp_shm;
4078         u16 *shm_entry;
4079
4080         /* Only apply params if the core is out of reset and has clocks */
4081         if (!wlc->clk) {
4082                 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4083                           wlc->pub->unit, __func__);
4084                 return;
4085         }
4086
4087         memset(&acp_shm, 0, sizeof(struct shm_acparams));
4088         /* fill in shm ac params struct */
4089         acp_shm.txop = params->txop;
4090         /* convert from units of 32us to us for ucode */
4091         wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4092             EDCF_TXOP2USEC(acp_shm.txop);
4093         acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4094
4095         if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4096             && acp_shm.aifs < EDCF_AIFSN_MAX)
4097                 acp_shm.aifs++;
4098
4099         if (acp_shm.aifs < EDCF_AIFSN_MIN
4100             || acp_shm.aifs > EDCF_AIFSN_MAX) {
4101                 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4102                           "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4103         } else {
4104                 acp_shm.cwmin = params->cw_min;
4105                 acp_shm.cwmax = params->cw_max;
4106                 acp_shm.cwcur = acp_shm.cwmin;
4107                 acp_shm.bslots =
4108                         bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4109                         acp_shm.cwcur;
4110                 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4111                 /* Indicate the new params to the ucode */
4112                 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4113                                                   wme_ac2fifo[aci] *
4114                                                   M_EDCF_QLEN +
4115                                                   M_EDCF_STATUS_OFF));
4116                 acp_shm.status |= WME_STATUS_NEWAC;
4117
4118                 /* Fill in shm acparam table */
4119                 shm_entry = (u16 *) &acp_shm;
4120                 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4121                         brcms_b_write_shm(wlc->hw,
4122                                           M_EDCF_QINFO +
4123                                           wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4124                                           *shm_entry++);
4125         }
4126
4127         if (suspend)
4128                 brcms_c_suspend_mac_and_wait(wlc);
4129
4130         brcms_c_update_beacon(wlc);
4131         brcms_c_update_probe_resp(wlc, false);
4132
4133         if (suspend)
4134                 brcms_c_enable_mac(wlc);
4135 }
4136
4137 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4138 {
4139         u16 aci;
4140         int i_ac;
4141         struct ieee80211_tx_queue_params txq_pars;
4142         static const struct edcf_acparam default_edcf_acparams[] = {
4143                  {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4144                  {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4145                  {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4146                  {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4147         }; /* ucode needs these parameters during its initialization */
4148         const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4149
4150         for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4151                 /* find out which ac this set of params applies to */
4152                 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4153
4154                 /* fill in shm ac params struct */
4155                 txq_pars.txop = edcf_acp->TXOP;
4156                 txq_pars.aifs = edcf_acp->ACI;
4157
4158                 /* CWmin = 2^(ECWmin) - 1 */
4159                 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4160                 /* CWmax = 2^(ECWmax) - 1 */
4161                 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4162                                             >> EDCF_ECWMAX_SHIFT);
4163                 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4164         }
4165
4166         if (suspend) {
4167                 brcms_c_suspend_mac_and_wait(wlc);
4168                 brcms_c_enable_mac(wlc);
4169         }
4170 }
4171
4172 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4173 {
4174         /* Don't start the timer if HWRADIO feature is disabled */
4175         if (wlc->radio_monitor)
4176                 return;
4177
4178         wlc->radio_monitor = true;
4179         brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4180         brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4181 }
4182
4183 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4184 {
4185         if (!wlc->radio_monitor)
4186                 return true;
4187
4188         wlc->radio_monitor = false;
4189         brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4190         return brcms_del_timer(wlc->radio_timer);
4191 }
4192
4193 /* read hwdisable state and propagate to wlc flag */
4194 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4195 {
4196         if (wlc->pub->hw_off)
4197                 return;
4198
4199         if (brcms_b_radio_read_hwdisabled(wlc->hw))
4200                 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4201         else
4202                 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4203 }
4204
4205 /* update hwradio status and return it */
4206 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4207 {
4208         brcms_c_radio_hwdisable_upd(wlc);
4209
4210         return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4211                         true : false;
4212 }
4213
4214 /* periodical query hw radio button while driver is "down" */
4215 static void brcms_c_radio_timer(void *arg)
4216 {
4217         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4218
4219         if (brcms_deviceremoved(wlc)) {
4220                 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4221                           wlc->pub->unit, __func__);
4222                 brcms_down(wlc->wl);
4223                 return;
4224         }
4225
4226         brcms_c_radio_hwdisable_upd(wlc);
4227 }
4228
4229 /* common low-level watchdog code */
4230 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4231 {
4232         struct brcms_hardware *wlc_hw = wlc->hw;
4233
4234         if (!wlc_hw->up)
4235                 return;
4236
4237         /* increment second count */
4238         wlc_hw->now++;
4239
4240         /* Check for FIFO error interrupts */
4241         brcms_b_fifoerrors(wlc_hw);
4242
4243         /* make sure RX dma has buffers */
4244         dma_rxfill(wlc->hw->di[RX_FIFO]);
4245
4246         wlc_phy_watchdog(wlc_hw->band->pi);
4247 }
4248
4249 /* common watchdog code */
4250 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4251 {
4252         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4253
4254         if (!wlc->pub->up)
4255                 return;
4256
4257         if (brcms_deviceremoved(wlc)) {
4258                 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4259                           wlc->pub->unit, __func__);
4260                 brcms_down(wlc->wl);
4261                 return;
4262         }
4263
4264         /* increment second count */
4265         wlc->pub->now++;
4266
4267         brcms_c_radio_hwdisable_upd(wlc);
4268         /* if radio is disable, driver may be down, quit here */
4269         if (wlc->pub->radio_disabled)
4270                 return;
4271
4272         brcms_b_watchdog(wlc);
4273
4274         /*
4275          * occasionally sample mac stat counters to
4276          * detect 16-bit counter wrap
4277          */
4278         if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4279                 brcms_c_statsupd(wlc);
4280
4281         if (BRCMS_ISNPHY(wlc->band) &&
4282             ((wlc->pub->now - wlc->tempsense_lasttime) >=
4283              BRCMS_TEMPSENSE_PERIOD)) {
4284                 wlc->tempsense_lasttime = wlc->pub->now;
4285                 brcms_c_tempsense_upd(wlc);
4286         }
4287 }
4288
4289 static void brcms_c_watchdog_by_timer(void *arg)
4290 {
4291         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4292
4293         brcms_c_watchdog(wlc);
4294 }
4295
4296 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4297 {
4298         wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4299                 wlc, "watchdog");
4300         if (!wlc->wdtimer) {
4301                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for wdtimer "
4302                           "failed\n", unit);
4303                 goto fail;
4304         }
4305
4306         wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4307                 wlc, "radio");
4308         if (!wlc->radio_timer) {
4309                 wiphy_err(wlc->wiphy, "wl%d:  wl_init_timer for radio_timer "
4310                           "failed\n", unit);
4311                 goto fail;
4312         }
4313
4314         return true;
4315
4316  fail:
4317         return false;
4318 }
4319
4320 /*
4321  * Initialize brcms_c_info default values ...
4322  * may get overrides later in this function
4323  */
4324 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4325 {
4326         int i;
4327
4328         /* Save our copy of the chanspec */
4329         wlc->chanspec = ch20mhz_chspec(1);
4330
4331         /* various 802.11g modes */
4332         wlc->shortslot = false;
4333         wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4334
4335         brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4336         brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4337
4338         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4339                                BRCMS_PROTECTION_AUTO);
4340         brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4341         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4342                                BRCMS_PROTECTION_AUTO);
4343         brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4344         brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4345
4346         brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4347                                BRCMS_PROTECTION_CTL_OVERLAP);
4348
4349         /* 802.11g draft 4.0 NonERP elt advertisement */
4350         wlc->include_legacy_erp = true;
4351
4352         wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4353         wlc->stf->txant = ANT_TX_DEF;
4354
4355         wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4356
4357         wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4358         for (i = 0; i < NFIFO; i++)
4359                 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4360         wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4361
4362         /* default rate fallback retry limits */
4363         wlc->SFBL = RETRY_SHORT_FB;
4364         wlc->LFBL = RETRY_LONG_FB;
4365
4366         /* default mac retry limits */
4367         wlc->SRL = RETRY_SHORT_DEF;
4368         wlc->LRL = RETRY_LONG_DEF;
4369
4370         /* WME QoS mode is Auto by default */
4371         wlc->pub->_ampdu = AMPDU_AGG_HOST;
4372 }
4373
4374 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4375 {
4376         uint err = 0;
4377         uint unit;
4378         unit = wlc->pub->unit;
4379
4380         wlc->asi = brcms_c_antsel_attach(wlc);
4381         if (wlc->asi == NULL) {
4382                 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4383                           "failed\n", unit);
4384                 err = 44;
4385                 goto fail;
4386         }
4387
4388         wlc->ampdu = brcms_c_ampdu_attach(wlc);
4389         if (wlc->ampdu == NULL) {
4390                 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4391                           "failed\n", unit);
4392                 err = 50;
4393                 goto fail;
4394         }
4395
4396         if ((brcms_c_stf_attach(wlc) != 0)) {
4397                 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4398                           "failed\n", unit);
4399                 err = 68;
4400                 goto fail;
4401         }
4402  fail:
4403         return err;
4404 }
4405
4406 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4407 {
4408         return wlc->pub;
4409 }
4410
4411 /* low level attach
4412  *    run backplane attach, init nvram
4413  *    run phy attach
4414  *    initialize software state for each core and band
4415  *    put the whole chip in reset(driver down state), no clock
4416  */
4417 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4418                           uint unit, bool piomode)
4419 {
4420         struct brcms_hardware *wlc_hw;
4421         uint err = 0;
4422         uint j;
4423         bool wme = false;
4424         struct shared_phy_params sha_params;
4425         struct wiphy *wiphy = wlc->wiphy;
4426         struct pci_dev *pcidev = core->bus->host_pci;
4427         struct ssb_sprom *sprom = &core->bus->sprom;
4428
4429         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4430                 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4431                                pcidev->vendor,
4432                                pcidev->device);
4433         else
4434                 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4435                                core->bus->boardinfo.vendor,
4436                                core->bus->boardinfo.type);
4437
4438         wme = true;
4439
4440         wlc_hw = wlc->hw;
4441         wlc_hw->wlc = wlc;
4442         wlc_hw->unit = unit;
4443         wlc_hw->band = wlc_hw->bandstate[0];
4444         wlc_hw->_piomode = piomode;
4445
4446         /* populate struct brcms_hardware with default values  */
4447         brcms_b_info_init(wlc_hw);
4448
4449         /*
4450          * Do the hardware portion of the attach. Also initialize software
4451          * state that depends on the particular hardware we are running.
4452          */
4453         wlc_hw->sih = ai_attach(core->bus);
4454         if (wlc_hw->sih == NULL) {
4455                 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4456                           unit);
4457                 err = 11;
4458                 goto fail;
4459         }
4460
4461         /* verify again the device is supported */
4462         if (!brcms_c_chipmatch(core)) {
4463                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4464                          unit);
4465                 err = 12;
4466                 goto fail;
4467         }
4468
4469         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4470                 wlc_hw->vendorid = pcidev->vendor;
4471                 wlc_hw->deviceid = pcidev->device;
4472         } else {
4473                 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4474                 wlc_hw->deviceid = core->bus->boardinfo.type;
4475         }
4476
4477         wlc_hw->d11core = core;
4478         wlc_hw->corerev = core->id.rev;
4479
4480         /* validate chip, chiprev and corerev */
4481         if (!brcms_c_isgoodchip(wlc_hw)) {
4482                 err = 13;
4483                 goto fail;
4484         }
4485
4486         /* initialize power control registers */
4487         ai_clkctl_init(wlc_hw->sih);
4488
4489         /* request fastclock and force fastclock for the rest of attach
4490          * bring the d11 core out of reset.
4491          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4492          *   is still false; But it will be called again inside wlc_corereset,
4493          *   after d11 is out of reset.
4494          */
4495         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4496         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4497
4498         if (!brcms_b_validate_chip_access(wlc_hw)) {
4499                 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4500                         "failed\n", unit);
4501                 err = 14;
4502                 goto fail;
4503         }
4504
4505         /* get the board rev, used just below */
4506         j = sprom->board_rev;
4507         /* promote srom boardrev of 0xFF to 1 */
4508         if (j == BOARDREV_PROMOTABLE)
4509                 j = BOARDREV_PROMOTED;
4510         wlc_hw->boardrev = (u16) j;
4511         if (!brcms_c_validboardtype(wlc_hw)) {
4512                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4513                           "board type (0x%x)" " or revision level (0x%x)\n",
4514                           unit, ai_get_boardtype(wlc_hw->sih),
4515                           wlc_hw->boardrev);
4516                 err = 15;
4517                 goto fail;
4518         }
4519         wlc_hw->sromrev = sprom->revision;
4520         wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4521         wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4522
4523         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4524                 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4525
4526         /* check device id(srom, nvram etc.) to set bands */
4527         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4528             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4529             wlc_hw->deviceid == BCM43224_CHIP_ID)
4530                 /* Dualband boards */
4531                 wlc_hw->_nbands = 2;
4532         else
4533                 wlc_hw->_nbands = 1;
4534
4535         if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4536                 wlc_hw->_nbands = 1;
4537
4538         /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4539          * unconditionally does the init of these values
4540          */
4541         wlc->vendorid = wlc_hw->vendorid;
4542         wlc->deviceid = wlc_hw->deviceid;
4543         wlc->pub->sih = wlc_hw->sih;
4544         wlc->pub->corerev = wlc_hw->corerev;
4545         wlc->pub->sromrev = wlc_hw->sromrev;
4546         wlc->pub->boardrev = wlc_hw->boardrev;
4547         wlc->pub->boardflags = wlc_hw->boardflags;
4548         wlc->pub->boardflags2 = wlc_hw->boardflags2;
4549         wlc->pub->_nbands = wlc_hw->_nbands;
4550
4551         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4552
4553         if (wlc_hw->physhim == NULL) {
4554                 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4555                         "failed\n", unit);
4556                 err = 25;
4557                 goto fail;
4558         }
4559
4560         /* pass all the parameters to wlc_phy_shared_attach in one struct */
4561         sha_params.sih = wlc_hw->sih;
4562         sha_params.physhim = wlc_hw->physhim;
4563         sha_params.unit = unit;
4564         sha_params.corerev = wlc_hw->corerev;
4565         sha_params.vid = wlc_hw->vendorid;
4566         sha_params.did = wlc_hw->deviceid;
4567         sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4568         sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4569         sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4570         sha_params.sromrev = wlc_hw->sromrev;
4571         sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4572         sha_params.boardrev = wlc_hw->boardrev;
4573         sha_params.boardflags = wlc_hw->boardflags;
4574         sha_params.boardflags2 = wlc_hw->boardflags2;
4575
4576         /* alloc and save pointer to shared phy state area */
4577         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4578         if (!wlc_hw->phy_sh) {
4579                 err = 16;
4580                 goto fail;
4581         }
4582
4583         /* initialize software state for each core and band */
4584         for (j = 0; j < wlc_hw->_nbands; j++) {
4585                 /*
4586                  * band0 is always 2.4Ghz
4587                  * band1, if present, is 5Ghz
4588                  */
4589
4590                 brcms_c_setxband(wlc_hw, j);
4591
4592                 wlc_hw->band->bandunit = j;
4593                 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4594                 wlc->band->bandunit = j;
4595                 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4596                 wlc->core->coreidx = core->core_index;
4597
4598                 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4599                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4600
4601                 /* init tx fifo size */
4602                 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4603                         (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4604                                 ARRAY_SIZE(xmtfifo_sz));
4605                 wlc_hw->xmtfifo_sz =
4606                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4607                 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4608
4609                 /* Get a phy for this band */
4610                 wlc_hw->band->pi =
4611                         wlc_phy_attach(wlc_hw->phy_sh, core,
4612                                        wlc_hw->band->bandtype,
4613                                        wlc->wiphy);
4614                 if (wlc_hw->band->pi == NULL) {
4615                         wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4616                                   "attach failed\n", unit);
4617                         err = 17;
4618                         goto fail;
4619                 }
4620
4621                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4622
4623                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4624                                        &wlc_hw->band->phyrev,
4625                                        &wlc_hw->band->radioid,
4626                                        &wlc_hw->band->radiorev);
4627                 wlc_hw->band->abgphy_encore =
4628                     wlc_phy_get_encore(wlc_hw->band->pi);
4629                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4630                 wlc_hw->band->core_flags =
4631                     wlc_phy_get_coreflags(wlc_hw->band->pi);
4632
4633                 /* verify good phy_type & supported phy revision */
4634                 if (BRCMS_ISNPHY(wlc_hw->band)) {
4635                         if (NCONF_HAS(wlc_hw->band->phyrev))
4636                                 goto good_phy;
4637                         else
4638                                 goto bad_phy;
4639                 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4640                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
4641                                 goto good_phy;
4642                         else
4643                                 goto bad_phy;
4644                 } else {
4645  bad_phy:
4646                         wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4647                                   "phy type/rev (%d/%d)\n", unit,
4648                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
4649                         err = 18;
4650                         goto fail;
4651                 }
4652
4653  good_phy:
4654                 /*
4655                  * BMAC_NOTE: wlc->band->pi should not be set below and should
4656                  * be done in the high level attach. However we can not make
4657                  * that change until all low level access is changed to
4658                  * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4659                  * keeping wlc_hw->band->pi as well for incremental update of
4660                  * low level fns, and cut over low only init when all fns
4661                  * updated.
4662                  */
4663                 wlc->band->pi = wlc_hw->band->pi;
4664                 wlc->band->phytype = wlc_hw->band->phytype;
4665                 wlc->band->phyrev = wlc_hw->band->phyrev;
4666                 wlc->band->radioid = wlc_hw->band->radioid;
4667                 wlc->band->radiorev = wlc_hw->band->radiorev;
4668
4669                 /* default contention windows size limits */
4670                 wlc_hw->band->CWmin = APHY_CWMIN;
4671                 wlc_hw->band->CWmax = PHY_CWMAX;
4672
4673                 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4674                         err = 19;
4675                         goto fail;
4676                 }
4677         }
4678
4679         /* disable core to match driver "down" state */
4680         brcms_c_coredisable(wlc_hw);
4681
4682         /* Match driver "down" state */
4683         ai_pci_down(wlc_hw->sih);
4684
4685         /* turn off pll and xtal to match driver "down" state */
4686         brcms_b_xtal(wlc_hw, OFF);
4687
4688         /* *******************************************************************
4689          * The hardware is in the DOWN state at this point. D11 core
4690          * or cores are in reset with clocks off, and the board PLLs
4691          * are off if possible.
4692          *
4693          * Beyond this point, wlc->sbclk == false and chip registers
4694          * should not be touched.
4695          *********************************************************************
4696          */
4697
4698         /* init etheraddr state variables */
4699         brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4700
4701         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4702             is_zero_ether_addr(wlc_hw->etheraddr)) {
4703                 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4704                           unit);
4705                 err = 22;
4706                 goto fail;
4707         }
4708
4709         brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4710                        wlc_hw->deviceid, wlc_hw->_nbands,
4711                        ai_get_boardtype(wlc_hw->sih));
4712
4713         return err;
4714
4715  fail:
4716         wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4717                   err);
4718         return err;
4719 }
4720
4721 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4722 {
4723         uint unit;
4724         unit = wlc->pub->unit;
4725
4726         if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4727                 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4728                 wlc->band->antgain = 8;
4729         } else if (wlc->band->antgain == -1) {
4730                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4731                           " srom, using 2dB\n", unit, __func__);
4732                 wlc->band->antgain = 8;
4733         } else {
4734                 s8 gain, fract;
4735                 /* Older sroms specified gain in whole dbm only.  In order
4736                  * be able to specify qdbm granularity and remain backward
4737                  * compatible the whole dbms are now encoded in only
4738                  * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4739                  * 6 bit signed number ranges from -32 - 31.
4740                  *
4741                  * Examples:
4742                  * 0x1 = 1 db,
4743                  * 0xc1 = 1.75 db (1 + 3 quarters),
4744                  * 0x3f = -1 (-1 + 0 quarters),
4745                  * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4746                  * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4747                  */
4748                 gain = wlc->band->antgain & 0x3f;
4749                 gain <<= 2;     /* Sign extend */
4750                 gain >>= 2;
4751                 fract = (wlc->band->antgain & 0xc0) >> 6;
4752                 wlc->band->antgain = 4 * gain + fract;
4753         }
4754 }
4755
4756 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4757 {
4758         int aa;
4759         uint unit;
4760         int bandtype;
4761         struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4762
4763         unit = wlc->pub->unit;
4764         bandtype = wlc->band->bandtype;
4765
4766         /* get antennas available */
4767         if (bandtype == BRCM_BAND_5G)
4768                 aa = sprom->ant_available_a;
4769         else
4770                 aa = sprom->ant_available_bg;
4771
4772         if ((aa < 1) || (aa > 15)) {
4773                 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4774                           " srom (0x%x), using 3\n", unit, __func__, aa);
4775                 aa = 3;
4776         }
4777
4778         /* reset the defaults if we have a single antenna */
4779         if (aa == 1) {
4780                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4781                 wlc->stf->txant = ANT_TX_FORCE_0;
4782         } else if (aa == 2) {
4783                 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4784                 wlc->stf->txant = ANT_TX_FORCE_1;
4785         } else {
4786         }
4787
4788         /* Compute Antenna Gain */
4789         if (bandtype == BRCM_BAND_5G)
4790                 wlc->band->antgain = sprom->antenna_gain.a1;
4791         else
4792                 wlc->band->antgain = sprom->antenna_gain.a0;
4793
4794         brcms_c_attach_antgain_init(wlc);
4795
4796         return true;
4797 }
4798
4799 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4800 {
4801         u16 chanspec;
4802         struct brcms_band *band;
4803         struct brcms_bss_info *bi = wlc->default_bss;
4804
4805         /* init default and target BSS with some sane initial values */
4806         memset(bi, 0, sizeof(*bi));
4807         bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4808
4809         /* fill the default channel as the first valid channel
4810          * starting from the 2G channels
4811          */
4812         chanspec = ch20mhz_chspec(1);
4813         wlc->home_chanspec = bi->chanspec = chanspec;
4814
4815         /* find the band of our default channel */
4816         band = wlc->band;
4817         if (wlc->pub->_nbands > 1 &&
4818             band->bandunit != chspec_bandunit(chanspec))
4819                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4820
4821         /* init bss rates to the band specific default rate set */
4822         brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4823                 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4824                 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4825                 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4826
4827         if (wlc->pub->_n_enab & SUPPORT_11N)
4828                 bi->flags |= BRCMS_BSS_HT;
4829 }
4830
4831 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4832 {
4833         uint i;
4834         struct brcms_band *band;
4835
4836         for (i = 0; i < wlc->pub->_nbands; i++) {
4837                 band = wlc->bandstate[i];
4838                 if (band->bandtype == BRCM_BAND_5G) {
4839                         if ((bwcap == BRCMS_N_BW_40ALL)
4840                             || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4841                                 band->mimo_cap_40 = true;
4842                         else
4843                                 band->mimo_cap_40 = false;
4844                 } else {
4845                         if (bwcap == BRCMS_N_BW_40ALL)
4846                                 band->mimo_cap_40 = true;
4847                         else
4848                                 band->mimo_cap_40 = false;
4849                 }
4850         }
4851 }
4852
4853 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4854 {
4855         /* free timer state */
4856         if (wlc->wdtimer) {
4857                 brcms_free_timer(wlc->wdtimer);
4858                 wlc->wdtimer = NULL;
4859         }
4860         if (wlc->radio_timer) {
4861                 brcms_free_timer(wlc->radio_timer);
4862                 wlc->radio_timer = NULL;
4863         }
4864 }
4865
4866 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4867 {
4868         if (wlc->asi) {
4869                 brcms_c_antsel_detach(wlc->asi);
4870                 wlc->asi = NULL;
4871         }
4872
4873         if (wlc->ampdu) {
4874                 brcms_c_ampdu_detach(wlc->ampdu);
4875                 wlc->ampdu = NULL;
4876         }
4877
4878         brcms_c_stf_detach(wlc);
4879 }
4880
4881 /*
4882  * low level detach
4883  */
4884 static int brcms_b_detach(struct brcms_c_info *wlc)
4885 {
4886         uint i;
4887         struct brcms_hw_band *band;
4888         struct brcms_hardware *wlc_hw = wlc->hw;
4889         int callbacks;
4890
4891         callbacks = 0;
4892
4893         brcms_b_detach_dmapio(wlc_hw);
4894
4895         band = wlc_hw->band;
4896         for (i = 0; i < wlc_hw->_nbands; i++) {
4897                 if (band->pi) {
4898                         /* Detach this band's phy */
4899                         wlc_phy_detach(band->pi);
4900                         band->pi = NULL;
4901                 }
4902                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4903         }
4904
4905         /* Free shared phy state */
4906         kfree(wlc_hw->phy_sh);
4907
4908         wlc_phy_shim_detach(wlc_hw->physhim);
4909
4910         if (wlc_hw->sih) {
4911                 ai_detach(wlc_hw->sih);
4912                 wlc_hw->sih = NULL;
4913         }
4914
4915         return callbacks;
4916
4917 }
4918
4919 /*
4920  * Return a count of the number of driver callbacks still pending.
4921  *
4922  * General policy is that brcms_c_detach can only dealloc/free software states.
4923  * It can NOT touch hardware registers since the d11core may be in reset and
4924  * clock may not be available.
4925  * One exception is sb register access, which is possible if crystal is turned
4926  * on after "down" state, driver should avoid software timer with the exception
4927  * of radio_monitor.
4928  */
4929 uint brcms_c_detach(struct brcms_c_info *wlc)
4930 {
4931         uint callbacks = 0;
4932
4933         if (wlc == NULL)
4934                 return 0;
4935
4936         callbacks += brcms_b_detach(wlc);
4937
4938         /* delete software timers */
4939         if (!brcms_c_radio_monitor_stop(wlc))
4940                 callbacks++;
4941
4942         brcms_c_channel_mgr_detach(wlc->cmi);
4943
4944         brcms_c_timers_deinit(wlc);
4945
4946         brcms_c_detach_module(wlc);
4947
4948         brcms_c_detach_mfree(wlc);
4949         return callbacks;
4950 }
4951
4952 /* update state that depends on the current value of "ap" */
4953 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4954 {
4955         /* STA-BSS; short capable */
4956         wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4957 }
4958
4959 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4960 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4961 {
4962         if (wlc_hw->wlc->pub->hw_up)
4963                 return;
4964
4965         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4966
4967         /*
4968          * Enable pll and xtal, initialize the power control registers,
4969          * and force fastclock for the remainder of brcms_c_up().
4970          */
4971         brcms_b_xtal(wlc_hw, ON);
4972         ai_clkctl_init(wlc_hw->sih);
4973         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4974
4975         /*
4976          * TODO: test suspend/resume
4977          *
4978          * AI chip doesn't restore bar0win2 on
4979          * hibernation/resume, need sw fixup
4980          */
4981
4982         /*
4983          * Inform phy that a POR reset has occurred so
4984          * it does a complete phy init
4985          */
4986         wlc_phy_por_inform(wlc_hw->band->pi);
4987
4988         wlc_hw->ucode_loaded = false;
4989         wlc_hw->wlc->pub->hw_up = true;
4990
4991         if ((wlc_hw->boardflags & BFL_FEM)
4992             && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4993                 if (!
4994                     (wlc_hw->boardrev >= 0x1250
4995                      && (wlc_hw->boardflags & BFL_FEM_BT)))
4996                         ai_epa_4313war(wlc_hw->sih);
4997         }
4998 }
4999
5000 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5001 {
5002         brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
5003
5004         /*
5005          * Enable pll and xtal, initialize the power control registers,
5006          * and force fastclock for the remainder of brcms_c_up().
5007          */
5008         brcms_b_xtal(wlc_hw, ON);
5009         ai_clkctl_init(wlc_hw->sih);
5010         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5011
5012         /*
5013          * Configure pci/pcmcia here instead of in brcms_c_attach()
5014          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
5015          */
5016         bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
5017                               true);
5018
5019         /*
5020          * Need to read the hwradio status here to cover the case where the
5021          * system is loaded with the hw radio disabled. We do not want to
5022          * bring the driver up in this case.
5023          */
5024         if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5025                 /* put SB PCI in down state again */
5026                 ai_pci_down(wlc_hw->sih);
5027                 brcms_b_xtal(wlc_hw, OFF);
5028                 return -ENOMEDIUM;
5029         }
5030
5031         ai_pci_up(wlc_hw->sih);
5032
5033         /* reset the d11 core */
5034         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5035
5036         return 0;
5037 }
5038
5039 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5040 {
5041         wlc_hw->up = true;
5042         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5043
5044         /* FULLY enable dynamic power control and d11 core interrupt */
5045         brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5046         brcms_intrson(wlc_hw->wlc->wl);
5047         return 0;
5048 }
5049
5050 /*
5051  * Write WME tunable parameters for retransmit/max rate
5052  * from wlc struct to ucode
5053  */
5054 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5055 {
5056         int ac;
5057
5058         /* Need clock to do this */
5059         if (!wlc->clk)
5060                 return;
5061
5062         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5063                 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5064                                   wlc->wme_retries[ac]);
5065 }
5066
5067 /* make interface operational */
5068 int brcms_c_up(struct brcms_c_info *wlc)
5069 {
5070         struct ieee80211_channel *ch;
5071
5072         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5073
5074         /* HW is turned off so don't try to access it */
5075         if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5076                 return -ENOMEDIUM;
5077
5078         if (!wlc->pub->hw_up) {
5079                 brcms_b_hw_up(wlc->hw);
5080                 wlc->pub->hw_up = true;
5081         }
5082
5083         if ((wlc->pub->boardflags & BFL_FEM)
5084             && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5085                 if (wlc->pub->boardrev >= 0x1250
5086                     && (wlc->pub->boardflags & BFL_FEM_BT))
5087                         brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5088                                 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5089                 else
5090                         brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5091                                     MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5092         }
5093
5094         /*
5095          * Need to read the hwradio status here to cover the case where the
5096          * system is loaded with the hw radio disabled. We do not want to bring
5097          * the driver up in this case. If radio is disabled, abort up, lower
5098          * power, start radio timer and return 0(for NDIS) don't call
5099          * radio_update to avoid looping brcms_c_up.
5100          *
5101          * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5102          */
5103         if (!wlc->pub->radio_disabled) {
5104                 int status = brcms_b_up_prep(wlc->hw);
5105                 if (status == -ENOMEDIUM) {
5106                         if (!mboolisset
5107                             (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5108                                 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5109                                 mboolset(wlc->pub->radio_disabled,
5110                                          WL_RADIO_HW_DISABLE);
5111                                 if (bsscfg->type == BRCMS_TYPE_STATION ||
5112                                     bsscfg->type == BRCMS_TYPE_ADHOC)
5113                                         brcms_err(wlc->hw->d11core,
5114                                                   "wl%d: up: rfdisable -> "
5115                                                   "bsscfg_disable()\n",
5116                                                    wlc->pub->unit);
5117                         }
5118                 }
5119         }
5120
5121         if (wlc->pub->radio_disabled) {
5122                 brcms_c_radio_monitor_start(wlc);
5123                 return 0;
5124         }
5125
5126         /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5127         wlc->clk = true;
5128
5129         brcms_c_radio_monitor_stop(wlc);
5130
5131         /* Set EDCF hostflags */
5132         brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5133
5134         brcms_init(wlc->wl);
5135         wlc->pub->up = true;
5136
5137         if (wlc->bandinit_pending) {
5138                 ch = wlc->pub->ieee_hw->conf.channel;
5139                 brcms_c_suspend_mac_and_wait(wlc);
5140                 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5141                 wlc->bandinit_pending = false;
5142                 brcms_c_enable_mac(wlc);
5143         }
5144
5145         brcms_b_up_finish(wlc->hw);
5146
5147         /* Program the TX wme params with the current settings */
5148         brcms_c_wme_retries_write(wlc);
5149
5150         /* start one second watchdog timer */
5151         brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5152         wlc->WDarmed = true;
5153
5154         /* ensure antenna config is up to date */
5155         brcms_c_stf_phy_txant_upd(wlc);
5156         /* ensure LDPC config is in sync */
5157         brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5158
5159         return 0;
5160 }
5161
5162 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5163 {
5164         uint callbacks = 0;
5165
5166         return callbacks;
5167 }
5168
5169 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5170 {
5171         bool dev_gone;
5172         uint callbacks = 0;
5173
5174         if (!wlc_hw->up)
5175                 return callbacks;
5176
5177         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5178
5179         /* disable interrupts */
5180         if (dev_gone)
5181                 wlc_hw->wlc->macintmask = 0;
5182         else {
5183                 /* now disable interrupts */
5184                 brcms_intrsoff(wlc_hw->wlc->wl);
5185
5186                 /* ensure we're running on the pll clock again */
5187                 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5188         }
5189         /* down phy at the last of this stage */
5190         callbacks += wlc_phy_down(wlc_hw->band->pi);
5191
5192         return callbacks;
5193 }
5194
5195 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5196 {
5197         uint callbacks = 0;
5198         bool dev_gone;
5199
5200         if (!wlc_hw->up)
5201                 return callbacks;
5202
5203         wlc_hw->up = false;
5204         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5205
5206         dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5207
5208         if (dev_gone) {
5209                 wlc_hw->sbclk = false;
5210                 wlc_hw->clk = false;
5211                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5212
5213                 /* reclaim any posted packets */
5214                 brcms_c_flushqueues(wlc_hw->wlc);
5215         } else {
5216
5217                 /* Reset and disable the core */
5218                 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5219                         if (bcma_read32(wlc_hw->d11core,
5220                                         D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5221                                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5222                         callbacks += brcms_reset(wlc_hw->wlc->wl);
5223                         brcms_c_coredisable(wlc_hw);
5224                 }
5225
5226                 /* turn off primary xtal and pll */
5227                 if (!wlc_hw->noreset) {
5228                         ai_pci_down(wlc_hw->sih);
5229                         brcms_b_xtal(wlc_hw, OFF);
5230                 }
5231         }
5232
5233         return callbacks;
5234 }
5235
5236 /*
5237  * Mark the interface nonoperational, stop the software mechanisms,
5238  * disable the hardware, free any transient buffer state.
5239  * Return a count of the number of driver callbacks still pending.
5240  */
5241 uint brcms_c_down(struct brcms_c_info *wlc)
5242 {
5243
5244         uint callbacks = 0;
5245         int i;
5246         bool dev_gone = false;
5247
5248         brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5249
5250         /* check if we are already in the going down path */
5251         if (wlc->going_down) {
5252                 brcms_err(wlc->hw->d11core,
5253                           "wl%d: %s: Driver going down so return\n",
5254                           wlc->pub->unit, __func__);
5255                 return 0;
5256         }
5257         if (!wlc->pub->up)
5258                 return callbacks;
5259
5260         wlc->going_down = true;
5261
5262         callbacks += brcms_b_bmac_down_prep(wlc->hw);
5263
5264         dev_gone = brcms_deviceremoved(wlc);
5265
5266         /* Call any registered down handlers */
5267         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5268                 if (wlc->modulecb[i].down_fn)
5269                         callbacks +=
5270                             wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5271         }
5272
5273         /* cancel the watchdog timer */
5274         if (wlc->WDarmed) {
5275                 if (!brcms_del_timer(wlc->wdtimer))
5276                         callbacks++;
5277                 wlc->WDarmed = false;
5278         }
5279         /* cancel all other timers */
5280         callbacks += brcms_c_down_del_timer(wlc);
5281
5282         wlc->pub->up = false;
5283
5284         wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5285
5286         callbacks += brcms_b_down_finish(wlc->hw);
5287
5288         /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5289         wlc->clk = false;
5290
5291         wlc->going_down = false;
5292         return callbacks;
5293 }
5294
5295 /* Set the current gmode configuration */
5296 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5297 {
5298         int ret = 0;
5299         uint i;
5300         struct brcms_c_rateset rs;
5301         /* Default to 54g Auto */
5302         /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5303         s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5304         bool shortslot_restrict = false; /* Restrict association to stations
5305                                           * that support shortslot
5306                                           */
5307         bool ofdm_basic = false;        /* Make 6, 12, and 24 basic rates */
5308         /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5309         int preamble = BRCMS_PLCP_LONG;
5310         bool preamble_restrict = false; /* Restrict association to stations
5311                                          * that support short preambles
5312                                          */
5313         struct brcms_band *band;
5314
5315         /* if N-support is enabled, allow Gmode set as long as requested
5316          * Gmode is not GMODE_LEGACY_B
5317          */
5318         if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5319                 return -ENOTSUPP;
5320
5321         /* verify that we are dealing with 2G band and grab the band pointer */
5322         if (wlc->band->bandtype == BRCM_BAND_2G)
5323                 band = wlc->band;
5324         else if ((wlc->pub->_nbands > 1) &&
5325                  (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5326                 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5327         else
5328                 return -EINVAL;
5329
5330         /* update configuration value */
5331         if (config)
5332                 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5333
5334         /* Clear rateset override */
5335         memset(&rs, 0, sizeof(rs));
5336
5337         switch (gmode) {
5338         case GMODE_LEGACY_B:
5339                 shortslot = BRCMS_SHORTSLOT_OFF;
5340                 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5341
5342                 break;
5343
5344         case GMODE_LRS:
5345                 break;
5346
5347         case GMODE_AUTO:
5348                 /* Accept defaults */
5349                 break;
5350
5351         case GMODE_ONLY:
5352                 ofdm_basic = true;
5353                 preamble = BRCMS_PLCP_SHORT;
5354                 preamble_restrict = true;
5355                 break;
5356
5357         case GMODE_PERFORMANCE:
5358                 shortslot = BRCMS_SHORTSLOT_ON;
5359                 shortslot_restrict = true;
5360                 ofdm_basic = true;
5361                 preamble = BRCMS_PLCP_SHORT;
5362                 preamble_restrict = true;
5363                 break;
5364
5365         default:
5366                 /* Error */
5367                 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5368                           wlc->pub->unit, __func__, gmode);
5369                 return -ENOTSUPP;
5370         }
5371
5372         band->gmode = gmode;
5373
5374         wlc->shortslot_override = shortslot;
5375
5376         /* Use the default 11g rateset */
5377         if (!rs.count)
5378                 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5379
5380         if (ofdm_basic) {
5381                 for (i = 0; i < rs.count; i++) {
5382                         if (rs.rates[i] == BRCM_RATE_6M
5383                             || rs.rates[i] == BRCM_RATE_12M
5384                             || rs.rates[i] == BRCM_RATE_24M)
5385                                 rs.rates[i] |= BRCMS_RATE_FLAG;
5386                 }
5387         }
5388
5389         /* Set default bss rateset */
5390         wlc->default_bss->rateset.count = rs.count;
5391         memcpy(wlc->default_bss->rateset.rates, rs.rates,
5392                sizeof(wlc->default_bss->rateset.rates));
5393
5394         return ret;
5395 }
5396
5397 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5398 {
5399         uint i;
5400         s32 nmode = AUTO;
5401
5402         if (wlc->stf->txstreams == WL_11N_3x3)
5403                 nmode = WL_11N_3x3;
5404         else
5405                 nmode = WL_11N_2x2;
5406
5407         /* force GMODE_AUTO if NMODE is ON */
5408         brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5409         if (nmode == WL_11N_3x3)
5410                 wlc->pub->_n_enab = SUPPORT_HT;
5411         else
5412                 wlc->pub->_n_enab = SUPPORT_11N;
5413         wlc->default_bss->flags |= BRCMS_BSS_HT;
5414         /* add the mcs rates to the default and hw ratesets */
5415         brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5416                               wlc->stf->txstreams);
5417         for (i = 0; i < wlc->pub->_nbands; i++)
5418                 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5419                        wlc->default_bss->rateset.mcs, MCSSET_LEN);
5420
5421         return 0;
5422 }
5423
5424 static int
5425 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5426                              struct brcms_c_rateset *rs_arg)
5427 {
5428         struct brcms_c_rateset rs, new;
5429         uint bandunit;
5430
5431         memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5432
5433         /* check for bad count value */
5434         if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5435                 return -EINVAL;
5436
5437         /* try the current band */
5438         bandunit = wlc->band->bandunit;
5439         memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5440         if (brcms_c_rate_hwrs_filter_sort_validate
5441             (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5442              wlc->stf->txstreams))
5443                 goto good;
5444
5445         /* try the other band */
5446         if (brcms_is_mband_unlocked(wlc)) {
5447                 bandunit = OTHERBANDUNIT(wlc);
5448                 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5449                 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5450                                                        &wlc->
5451                                                        bandstate[bandunit]->
5452                                                        hw_rateset, true,
5453                                                        wlc->stf->txstreams))
5454                         goto good;
5455         }
5456
5457         return -EBADE;
5458
5459  good:
5460         /* apply new rateset */
5461         memcpy(&wlc->default_bss->rateset, &new,
5462                sizeof(struct brcms_c_rateset));
5463         memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5464                sizeof(struct brcms_c_rateset));
5465         return 0;
5466 }
5467
5468 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5469 {
5470         u8 r;
5471         bool war = false;
5472
5473         if (wlc->pub->associated)
5474                 r = wlc->bsscfg->current_bss->rateset.rates[0];
5475         else
5476                 r = wlc->default_bss->rateset.rates[0];
5477
5478         wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5479 }
5480
5481 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5482 {
5483         u16 chspec = ch20mhz_chspec(channel);
5484
5485         if (channel < 0 || channel > MAXCHANNEL)
5486                 return -EINVAL;
5487
5488         if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5489                 return -EINVAL;
5490
5491
5492         if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5493                 if (wlc->band->bandunit != chspec_bandunit(chspec))
5494                         wlc->bandinit_pending = true;
5495                 else
5496                         wlc->bandinit_pending = false;
5497         }
5498
5499         wlc->default_bss->chanspec = chspec;
5500         /* brcms_c_BSSinit() will sanitize the rateset before
5501          * using it.. */
5502         if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5503                 brcms_c_set_home_chanspec(wlc, chspec);
5504                 brcms_c_suspend_mac_and_wait(wlc);
5505                 brcms_c_set_chanspec(wlc, chspec);
5506                 brcms_c_enable_mac(wlc);
5507         }
5508         return 0;
5509 }
5510
5511 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5512 {
5513         int ac;
5514
5515         if (srl < 1 || srl > RETRY_SHORT_MAX ||
5516             lrl < 1 || lrl > RETRY_SHORT_MAX)
5517                 return -EINVAL;
5518
5519         wlc->SRL = srl;
5520         wlc->LRL = lrl;
5521
5522         brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5523
5524         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5525                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5526                                                EDCF_SHORT,  wlc->SRL);
5527                 wlc->wme_retries[ac] =  SFIELD(wlc->wme_retries[ac],
5528                                                EDCF_LONG, wlc->LRL);
5529         }
5530         brcms_c_wme_retries_write(wlc);
5531
5532         return 0;
5533 }
5534
5535 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5536                                  struct brcm_rateset *currs)
5537 {
5538         struct brcms_c_rateset *rs;
5539
5540         if (wlc->pub->associated)
5541                 rs = &wlc->bsscfg->current_bss->rateset;
5542         else
5543                 rs = &wlc->default_bss->rateset;
5544
5545         /* Copy only legacy rateset section */
5546         currs->count = rs->count;
5547         memcpy(&currs->rates, &rs->rates, rs->count);
5548 }
5549
5550 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5551 {
5552         struct brcms_c_rateset internal_rs;
5553         int bcmerror;
5554
5555         if (rs->count > BRCMS_NUMRATES)
5556                 return -ENOBUFS;
5557
5558         memset(&internal_rs, 0, sizeof(internal_rs));
5559
5560         /* Copy only legacy rateset section */
5561         internal_rs.count = rs->count;
5562         memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5563
5564         /* merge rateset coming in with the current mcsset */
5565         if (wlc->pub->_n_enab & SUPPORT_11N) {
5566                 struct brcms_bss_info *mcsset_bss;
5567                 if (wlc->pub->associated)
5568                         mcsset_bss = wlc->bsscfg->current_bss;
5569                 else
5570                         mcsset_bss = wlc->default_bss;
5571                 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5572                        MCSSET_LEN);
5573         }
5574
5575         bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5576         if (!bcmerror)
5577                 brcms_c_ofdm_rateset_war(wlc);
5578
5579         return bcmerror;
5580 }
5581
5582 static void brcms_c_time_lock(struct brcms_c_info *wlc)
5583 {
5584         bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
5585         /* Commit the write */
5586         bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5587 }
5588
5589 static void brcms_c_time_unlock(struct brcms_c_info *wlc)
5590 {
5591         bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
5592         /* Commit the write */
5593         bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
5594 }
5595
5596 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5597 {
5598         u32 bcnint_us;
5599
5600         if (period == 0)
5601                 return -EINVAL;
5602
5603         wlc->default_bss->beacon_period = period;
5604
5605         bcnint_us = period << 10;
5606         brcms_c_time_lock(wlc);
5607         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfprep),
5608                      (bcnint_us << CFPREP_CBI_SHIFT));
5609         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_cfpstart), bcnint_us);
5610         brcms_c_time_unlock(wlc);
5611
5612         return 0;
5613 }
5614
5615 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5616 {
5617         return wlc->band->phytype;
5618 }
5619
5620 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5621 {
5622         wlc->shortslot_override = sslot_override;
5623
5624         /*
5625          * shortslot is an 11g feature, so no more work if we are
5626          * currently on the 5G band
5627          */
5628         if (wlc->band->bandtype == BRCM_BAND_5G)
5629                 return;
5630
5631         if (wlc->pub->up && wlc->pub->associated) {
5632                 /* let watchdog or beacon processing update shortslot */
5633         } else if (wlc->pub->up) {
5634                 /* unassociated shortslot is off */
5635                 brcms_c_switch_shortslot(wlc, false);
5636         } else {
5637                 /* driver is down, so just update the brcms_c_info
5638                  * value */
5639                 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5640                         wlc->shortslot = false;
5641                 else
5642                         wlc->shortslot =
5643                             (wlc->shortslot_override ==
5644                              BRCMS_SHORTSLOT_ON);
5645         }
5646 }
5647
5648 /*
5649  * register watchdog and down handlers.
5650  */
5651 int brcms_c_module_register(struct brcms_pub *pub,
5652                             const char *name, struct brcms_info *hdl,
5653                             int (*d_fn)(void *handle))
5654 {
5655         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5656         int i;
5657
5658         /* find an empty entry and just add, no duplication check! */
5659         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5660                 if (wlc->modulecb[i].name[0] == '\0') {
5661                         strncpy(wlc->modulecb[i].name, name,
5662                                 sizeof(wlc->modulecb[i].name) - 1);
5663                         wlc->modulecb[i].hdl = hdl;
5664                         wlc->modulecb[i].down_fn = d_fn;
5665                         return 0;
5666                 }
5667         }
5668
5669         return -ENOSR;
5670 }
5671
5672 /* unregister module callbacks */
5673 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5674                               struct brcms_info *hdl)
5675 {
5676         struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5677         int i;
5678
5679         if (wlc == NULL)
5680                 return -ENODATA;
5681
5682         for (i = 0; i < BRCMS_MAXMODULES; i++) {
5683                 if (!strcmp(wlc->modulecb[i].name, name) &&
5684                     (wlc->modulecb[i].hdl == hdl)) {
5685                         memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
5686                         return 0;
5687                 }
5688         }
5689
5690         /* table not found! */
5691         return -ENODATA;
5692 }
5693
5694 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5695 {
5696         struct pci_dev *pcidev = core->bus->host_pci;
5697         u16 vendor = pcidev->vendor;
5698         u16 device = pcidev->device;
5699
5700         if (vendor != PCI_VENDOR_ID_BROADCOM) {
5701                 pr_err("unknown vendor id %04x\n", vendor);
5702                 return false;
5703         }
5704
5705         if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5706                 return true;
5707         if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5708                 return true;
5709         if (device == BCM4313_D11N2G_ID)
5710                 return true;
5711         if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5712                 return true;
5713
5714         pr_err("unknown device id %04x\n", device);
5715         return false;
5716 }
5717
5718 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5719 {
5720         struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5721
5722         if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5723                 return true;
5724
5725         pr_err("unknown chip id %04x\n", chipinfo->id);
5726         return false;
5727 }
5728
5729 bool brcms_c_chipmatch(struct bcma_device *core)
5730 {
5731         switch (core->bus->hosttype) {
5732         case BCMA_HOSTTYPE_PCI:
5733                 return brcms_c_chipmatch_pci(core);
5734         case BCMA_HOSTTYPE_SOC:
5735                 return brcms_c_chipmatch_soc(core);
5736         default:
5737                 pr_err("unknown host type: %i\n", core->bus->hosttype);
5738                 return false;
5739         }
5740 }
5741
5742 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5743 {
5744         u16 table_ptr;
5745         u8 phy_rate, index;
5746
5747         /* get the phy specific rate encoding for the PLCP SIGNAL field */
5748         if (is_ofdm_rate(rate))
5749                 table_ptr = M_RT_DIRMAP_A;
5750         else
5751                 table_ptr = M_RT_DIRMAP_B;
5752
5753         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5754          * the index into the rate table.
5755          */
5756         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5757         index = phy_rate & 0xf;
5758
5759         /* Find the SHM pointer to the rate table entry by looking in the
5760          * Direct-map Table
5761          */
5762         return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5763 }
5764
5765 /*
5766  * bcmc_fid_generate:
5767  * Generate frame ID for a BCMC packet.  The frag field is not used
5768  * for MC frames so is used as part of the sequence number.
5769  */
5770 static inline u16
5771 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5772                   struct d11txh *txh)
5773 {
5774         u16 frameid;
5775
5776         frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5777                                                   TXFID_QUEUE_MASK);
5778         frameid |=
5779             (((wlc->
5780                mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5781             TX_BCMC_FIFO;
5782
5783         return frameid;
5784 }
5785
5786 static uint
5787 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5788                       u8 preamble_type)
5789 {
5790         uint dur = 0;
5791
5792         /*
5793          * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5794          * is less than or equal to the rate of the immediately previous
5795          * frame in the FES
5796          */
5797         rspec = brcms_basic_rate(wlc, rspec);
5798         /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5799         dur =
5800             brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5801                                 (DOT11_ACK_LEN + FCS_LEN));
5802         return dur;
5803 }
5804
5805 static uint
5806 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5807                       u8 preamble_type)
5808 {
5809         return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5810 }
5811
5812 static uint
5813 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5814                      u8 preamble_type)
5815 {
5816         /*
5817          * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5818          * is less than or equal to the rate of the immediately previous
5819          * frame in the FES
5820          */
5821         rspec = brcms_basic_rate(wlc, rspec);
5822         /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5823         return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5824                                    (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5825                                     FCS_LEN));
5826 }
5827
5828 /* brcms_c_compute_frame_dur()
5829  *
5830  * Calculate the 802.11 MAC header DUR field for MPDU
5831  * DUR for a single frame = 1 SIFS + 1 ACK
5832  * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5833  *
5834  * rate                 MPDU rate in unit of 500kbps
5835  * next_frag_len        next MPDU length in bytes
5836  * preamble_type        use short/GF or long/MM PLCP header
5837  */
5838 static u16
5839 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5840                       u8 preamble_type, uint next_frag_len)
5841 {
5842         u16 dur, sifs;
5843
5844         sifs = get_sifs(wlc->band);
5845
5846         dur = sifs;
5847         dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5848
5849         if (next_frag_len) {
5850                 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5851                 dur *= 2;
5852                 /* add another SIFS and the frag time */
5853                 dur += sifs;
5854                 dur +=
5855                     (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5856                                                  next_frag_len);
5857         }
5858         return dur;
5859 }
5860
5861 /* The opposite of brcms_c_calc_frame_time */
5862 static uint
5863 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5864                    u8 preamble_type, uint dur)
5865 {
5866         uint nsyms, mac_len, Ndps, kNdps;
5867         uint rate = rspec2rate(ratespec);
5868
5869         if (is_mcs_rate(ratespec)) {
5870                 uint mcs = ratespec & RSPEC_RATE_MASK;
5871                 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5872                 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5873                 /* payload calculation matches that of regular ofdm */
5874                 if (wlc->band->bandtype == BRCM_BAND_2G)
5875                         dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5876                 /* kNdbps = kbps * 4 */
5877                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5878                                    rspec_issgi(ratespec)) * 4;
5879                 nsyms = dur / APHY_SYMBOL_TIME;
5880                 mac_len =
5881                     ((nsyms * kNdps) -
5882                      ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5883         } else if (is_ofdm_rate(ratespec)) {
5884                 dur -= APHY_PREAMBLE_TIME;
5885                 dur -= APHY_SIGNAL_TIME;
5886                 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5887                 Ndps = rate * 2;
5888                 nsyms = dur / APHY_SYMBOL_TIME;
5889                 mac_len =
5890                     ((nsyms * Ndps) -
5891                      (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5892         } else {
5893                 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5894                         dur -= BPHY_PLCP_SHORT_TIME;
5895                 else
5896                         dur -= BPHY_PLCP_TIME;
5897                 mac_len = dur * rate;
5898                 /* divide out factor of 2 in rate (1/2 mbps) */
5899                 mac_len = mac_len / 8 / 2;
5900         }
5901         return mac_len;
5902 }
5903
5904 /*
5905  * Return true if the specified rate is supported by the specified band.
5906  * BRCM_BAND_AUTO indicates the current band.
5907  */
5908 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5909                     bool verbose)
5910 {
5911         struct brcms_c_rateset *hw_rateset;
5912         uint i;
5913
5914         if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5915                 hw_rateset = &wlc->band->hw_rateset;
5916         else if (wlc->pub->_nbands > 1)
5917                 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5918         else
5919                 /* other band specified and we are a single band device */
5920                 return false;
5921
5922         /* check if this is a mimo rate */
5923         if (is_mcs_rate(rspec)) {
5924                 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5925                         goto error;
5926
5927                 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5928         }
5929
5930         for (i = 0; i < hw_rateset->count; i++)
5931                 if (hw_rateset->rates[i] == rspec2rate(rspec))
5932                         return true;
5933  error:
5934         if (verbose)
5935                 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5936                           "not in hw_rateset\n", wlc->pub->unit, rspec);
5937
5938         return false;
5939 }
5940
5941 static u32
5942 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5943                        u32 int_val)
5944 {
5945         struct bcma_device *core = wlc->hw->d11core;
5946         u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5947         u8 rate = int_val & NRATE_RATE_MASK;
5948         u32 rspec;
5949         bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5950         bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5951         bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5952                                   == NRATE_OVERRIDE_MCS_ONLY);
5953         int bcmerror = 0;
5954
5955         if (!ismcs)
5956                 return (u32) rate;
5957
5958         /* validate the combination of rate/mcs/stf is allowed */
5959         if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5960                 /* mcs only allowed when nmode */
5961                 if (stf > PHY_TXC1_MODE_SDM) {
5962                         brcms_err(core, "wl%d: %s: Invalid stf\n",
5963                                   wlc->pub->unit, __func__);
5964                         bcmerror = -EINVAL;
5965                         goto done;
5966                 }
5967
5968                 /* mcs 32 is a special case, DUP mode 40 only */
5969                 if (rate == 32) {
5970                         if (!CHSPEC_IS40(wlc->home_chanspec) ||
5971                             ((stf != PHY_TXC1_MODE_SISO)
5972                              && (stf != PHY_TXC1_MODE_CDD))) {
5973                                 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5974                                           wlc->pub->unit, __func__);
5975                                 bcmerror = -EINVAL;
5976                                 goto done;
5977                         }
5978                         /* mcs > 7 must use stf SDM */
5979                 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5980                         /* mcs > 7 must use stf SDM */
5981                         if (stf != PHY_TXC1_MODE_SDM) {
5982                                 brcms_dbg_mac80211(core, "wl%d: enabling "
5983                                                    "SDM mode for mcs %d\n",
5984                                                    wlc->pub->unit, rate);
5985                                 stf = PHY_TXC1_MODE_SDM;
5986                         }
5987                 } else {
5988                         /*
5989                          * MCS 0-7 may use SISO, CDD, and for
5990                          * phy_rev >= 3 STBC
5991                          */
5992                         if ((stf > PHY_TXC1_MODE_STBC) ||
5993                             (!BRCMS_STBC_CAP_PHY(wlc)
5994                              && (stf == PHY_TXC1_MODE_STBC))) {
5995                                 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5996                                           wlc->pub->unit, __func__);
5997                                 bcmerror = -EINVAL;
5998                                 goto done;
5999                         }
6000                 }
6001         } else if (is_ofdm_rate(rate)) {
6002                 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
6003                         brcms_err(core, "wl%d: %s: Invalid OFDM\n",
6004                                   wlc->pub->unit, __func__);
6005                         bcmerror = -EINVAL;
6006                         goto done;
6007                 }
6008         } else if (is_cck_rate(rate)) {
6009                 if ((cur_band->bandtype != BRCM_BAND_2G)
6010                     || (stf != PHY_TXC1_MODE_SISO)) {
6011                         brcms_err(core, "wl%d: %s: Invalid CCK\n",
6012                                   wlc->pub->unit, __func__);
6013                         bcmerror = -EINVAL;
6014                         goto done;
6015                 }
6016         } else {
6017                 brcms_err(core, "wl%d: %s: Unknown rate type\n",
6018                           wlc->pub->unit, __func__);
6019                 bcmerror = -EINVAL;
6020                 goto done;
6021         }
6022         /* make sure multiple antennae are available for non-siso rates */
6023         if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
6024                 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
6025                           "request\n", wlc->pub->unit, __func__);
6026                 bcmerror = -EINVAL;
6027                 goto done;
6028         }
6029
6030         rspec = rate;
6031         if (ismcs) {
6032                 rspec |= RSPEC_MIMORATE;
6033                 /* For STBC populate the STC field of the ratespec */
6034                 if (stf == PHY_TXC1_MODE_STBC) {
6035                         u8 stc;
6036                         stc = 1;        /* Nss for single stream is always 1 */
6037                         rspec |= (stc << RSPEC_STC_SHIFT);
6038                 }
6039         }
6040
6041         rspec |= (stf << RSPEC_STF_SHIFT);
6042
6043         if (override_mcs_only)
6044                 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6045
6046         if (issgi)
6047                 rspec |= RSPEC_SHORT_GI;
6048
6049         if ((rate != 0)
6050             && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6051                 return rate;
6052
6053         return rspec;
6054 done:
6055         return rate;
6056 }
6057
6058 /*
6059  * Compute PLCP, but only requires actual rate and length of pkt.
6060  * Rate is given in the driver standard multiple of 500 kbps.
6061  * le is set for 11 Mbps rate if necessary.
6062  * Broken out for PRQ.
6063  */
6064
6065 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6066                              uint length, u8 *plcp)
6067 {
6068         u16 usec = 0;
6069         u8 le = 0;
6070
6071         switch (rate_500) {
6072         case BRCM_RATE_1M:
6073                 usec = length << 3;
6074                 break;
6075         case BRCM_RATE_2M:
6076                 usec = length << 2;
6077                 break;
6078         case BRCM_RATE_5M5:
6079                 usec = (length << 4) / 11;
6080                 if ((length << 4) - (usec * 11) > 0)
6081                         usec++;
6082                 break;
6083         case BRCM_RATE_11M:
6084                 usec = (length << 3) / 11;
6085                 if ((length << 3) - (usec * 11) > 0) {
6086                         usec++;
6087                         if ((usec * 11) - (length << 3) >= 8)
6088                                 le = D11B_PLCP_SIGNAL_LE;
6089                 }
6090                 break;
6091
6092         default:
6093                 brcms_err(wlc->hw->d11core,
6094                           "brcms_c_cck_plcp_set: unsupported rate %d\n",
6095                           rate_500);
6096                 rate_500 = BRCM_RATE_1M;
6097                 usec = length << 3;
6098                 break;
6099         }
6100         /* PLCP signal byte */
6101         plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6102         /* PLCP service byte */
6103         plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6104         /* PLCP length u16, little endian */
6105         plcp[2] = usec & 0xff;
6106         plcp[3] = (usec >> 8) & 0xff;
6107         /* PLCP CRC16 */
6108         plcp[4] = 0;
6109         plcp[5] = 0;
6110 }
6111
6112 /* Rate: 802.11 rate code, length: PSDU length in octets */
6113 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6114 {
6115         u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6116         plcp[0] = mcs;
6117         if (rspec_is40mhz(rspec) || (mcs == 32))
6118                 plcp[0] |= MIMO_PLCP_40MHZ;
6119         BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6120         plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6121         plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6122         plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6123         plcp[5] = 0;
6124 }
6125
6126 /* Rate: 802.11 rate code, length: PSDU length in octets */
6127 static void
6128 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6129 {
6130         u8 rate_signal;
6131         u32 tmp = 0;
6132         int rate = rspec2rate(rspec);
6133
6134         /*
6135          * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6136          * transmitted first
6137          */
6138         rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6139         memset(plcp, 0, D11_PHY_HDR_LEN);
6140         D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6141
6142         tmp = (length & 0xfff) << 5;
6143         plcp[2] |= (tmp >> 16) & 0xff;
6144         plcp[1] |= (tmp >> 8) & 0xff;
6145         plcp[0] |= tmp & 0xff;
6146 }
6147
6148 /* Rate: 802.11 rate code, length: PSDU length in octets */
6149 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6150                                  uint length, u8 *plcp)
6151 {
6152         int rate = rspec2rate(rspec);
6153
6154         brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6155 }
6156
6157 static void
6158 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6159                      uint length, u8 *plcp)
6160 {
6161         if (is_mcs_rate(rspec))
6162                 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6163         else if (is_ofdm_rate(rspec))
6164                 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6165         else
6166                 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6167 }
6168
6169 /* brcms_c_compute_rtscts_dur()
6170  *
6171  * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6172  * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6173  * DUR for CTS-TO-SELF w/ frame    = 2 SIFS         + next frame time + 1 ACK
6174  *
6175  * cts                  cts-to-self or rts/cts
6176  * rts_rate             rts or cts rate in unit of 500kbps
6177  * rate                 next MPDU rate in unit of 500kbps
6178  * frame_len            next MPDU frame length in bytes
6179  */
6180 u16
6181 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6182                            u32 rts_rate,
6183                            u32 frame_rate, u8 rts_preamble_type,
6184                            u8 frame_preamble_type, uint frame_len, bool ba)
6185 {
6186         u16 dur, sifs;
6187
6188         sifs = get_sifs(wlc->band);
6189
6190         if (!cts_only) {
6191                 /* RTS/CTS */
6192                 dur = 3 * sifs;
6193                 dur +=
6194                     (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6195                                                rts_preamble_type);
6196         } else {
6197                 /* CTS-TO-SELF */
6198                 dur = 2 * sifs;
6199         }
6200
6201         dur +=
6202             (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6203                                          frame_len);
6204         if (ba)
6205                 dur +=
6206                     (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6207                                               BRCMS_SHORT_PREAMBLE);
6208         else
6209                 dur +=
6210                     (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6211                                                frame_preamble_type);
6212         return dur;
6213 }
6214
6215 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6216 {
6217         u16 phyctl1 = 0;
6218         u16 bw;
6219
6220         if (BRCMS_ISLCNPHY(wlc->band)) {
6221                 bw = PHY_TXC1_BW_20MHZ;
6222         } else {
6223                 bw = rspec_get_bw(rspec);
6224                 /* 10Mhz is not supported yet */
6225                 if (bw < PHY_TXC1_BW_20MHZ) {
6226                         brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6227                                   "not supported yet, set to 20L\n", bw);
6228                         bw = PHY_TXC1_BW_20MHZ;
6229                 }
6230         }
6231
6232         if (is_mcs_rate(rspec)) {
6233                 uint mcs = rspec & RSPEC_RATE_MASK;
6234
6235                 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6236                 phyctl1 = rspec_phytxbyte2(rspec);
6237                 /* set the upper byte of phyctl1 */
6238                 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6239         } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6240                    && !BRCMS_ISSSLPNPHY(wlc->band)) {
6241                 /*
6242                  * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6243                  * Data Rate. Eventually MIMOPHY would also be converted to
6244                  * this format
6245                  */
6246                 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6247                 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6248         } else {                /* legacy OFDM/CCK */
6249                 s16 phycfg;
6250                 /* get the phyctl byte from rate phycfg table */
6251                 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6252                 if (phycfg == -1) {
6253                         brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6254                                   "legacy OFDM/CCK rate\n");
6255                         phycfg = 0;
6256                 }
6257                 /* set the upper byte of phyctl1 */
6258                 phyctl1 =
6259                     (bw | (phycfg << 8) |
6260                      (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6261         }
6262         return phyctl1;
6263 }
6264
6265 /*
6266  * Add struct d11txh, struct cck_phy_hdr.
6267  *
6268  * 'p' data must start with 802.11 MAC header
6269  * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6270  *
6271  * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6272  *
6273  */
6274 static u16
6275 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6276                      struct sk_buff *p, struct scb *scb, uint frag,
6277                      uint nfrags, uint queue, uint next_frag_len)
6278 {
6279         struct ieee80211_hdr *h;
6280         struct d11txh *txh;
6281         u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6282         int len, phylen, rts_phylen;
6283         u16 mch, phyctl, xfts, mainrates;
6284         u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6285         u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6286         u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6287         bool use_rts = false;
6288         bool use_cts = false;
6289         bool use_rifs = false;
6290         bool short_preamble[2] = { false, false };
6291         u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6292         u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6293         u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6294         struct ieee80211_rts *rts = NULL;
6295         bool qos;
6296         uint ac;
6297         bool hwtkmic = false;
6298         u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6299 #define ANTCFG_NONE 0xFF
6300         u8 antcfg = ANTCFG_NONE;
6301         u8 fbantcfg = ANTCFG_NONE;
6302         uint phyctl1_stf = 0;
6303         u16 durid = 0;
6304         struct ieee80211_tx_rate *txrate[2];
6305         int k;
6306         struct ieee80211_tx_info *tx_info;
6307         bool is_mcs;
6308         u16 mimo_txbw;
6309         u8 mimo_preamble_type;
6310
6311         /* locate 802.11 MAC header */
6312         h = (struct ieee80211_hdr *)(p->data);
6313         qos = ieee80211_is_data_qos(h->frame_control);
6314
6315         /* compute length of frame in bytes for use in PLCP computations */
6316         len = p->len;
6317         phylen = len + FCS_LEN;
6318
6319         /* Get tx_info */
6320         tx_info = IEEE80211_SKB_CB(p);
6321
6322         /* add PLCP */
6323         plcp = skb_push(p, D11_PHY_HDR_LEN);
6324
6325         /* add Broadcom tx descriptor header */
6326         txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6327         memset(txh, 0, D11_TXH_LEN);
6328
6329         /* setup frameid */
6330         if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6331                 /* non-AP STA should never use BCMC queue */
6332                 if (queue == TX_BCMC_FIFO) {
6333                         brcms_err(wlc->hw->d11core,
6334                                   "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6335                                   wlc->pub->unit, __func__);
6336                         frameid = bcmc_fid_generate(wlc, NULL, txh);
6337                 } else {
6338                         /* Increment the counter for first fragment */
6339                         if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6340                                 scb->seqnum[p->priority]++;
6341
6342                         /* extract fragment number from frame first */
6343                         seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6344                         seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6345                         h->seq_ctrl = cpu_to_le16(seq);
6346
6347                         frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6348                             (queue & TXFID_QUEUE_MASK);
6349                 }
6350         }
6351         frameid |= queue & TXFID_QUEUE_MASK;
6352
6353         /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6354         if (ieee80211_is_beacon(h->frame_control))
6355                 mcl |= TXC_IGNOREPMQ;
6356
6357         txrate[0] = tx_info->control.rates;
6358         txrate[1] = txrate[0] + 1;
6359
6360         /*
6361          * if rate control algorithm didn't give us a fallback
6362          * rate, use the primary rate
6363          */
6364         if (txrate[1]->idx < 0)
6365                 txrate[1] = txrate[0];
6366
6367         for (k = 0; k < hw->max_rates; k++) {
6368                 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6369                 if (!is_mcs) {
6370                         if ((txrate[k]->idx >= 0)
6371                             && (txrate[k]->idx <
6372                                 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6373                                 rspec[k] =
6374                                     hw->wiphy->bands[tx_info->band]->
6375                                     bitrates[txrate[k]->idx].hw_value;
6376                                 short_preamble[k] =
6377                                     txrate[k]->
6378                                     flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6379                                     true : false;
6380                         } else {
6381                                 rspec[k] = BRCM_RATE_1M;
6382                         }
6383                 } else {
6384                         rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6385                                         NRATE_MCS_INUSE | txrate[k]->idx);
6386                 }
6387
6388                 /*
6389                  * Currently only support same setting for primay and
6390                  * fallback rates. Unify flags for each rate into a
6391                  * single value for the frame
6392                  */
6393                 use_rts |=
6394                     txrate[k]->
6395                     flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6396                 use_cts |=
6397                     txrate[k]->
6398                     flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6399
6400
6401                 /*
6402                  * (1) RATE:
6403                  *   determine and validate primary rate
6404                  *   and fallback rates
6405                  */
6406                 if (!rspec_active(rspec[k])) {
6407                         rspec[k] = BRCM_RATE_1M;
6408                 } else {
6409                         if (!is_multicast_ether_addr(h->addr1)) {
6410                                 /* set tx antenna config */
6411                                 brcms_c_antsel_antcfg_get(wlc->asi, false,
6412                                         false, 0, 0, &antcfg, &fbantcfg);
6413                         }
6414                 }
6415         }
6416
6417         phyctl1_stf = wlc->stf->ss_opmode;
6418
6419         if (wlc->pub->_n_enab & SUPPORT_11N) {
6420                 for (k = 0; k < hw->max_rates; k++) {
6421                         /*
6422                          * apply siso/cdd to single stream mcs's or ofdm
6423                          * if rspec is auto selected
6424                          */
6425                         if (((is_mcs_rate(rspec[k]) &&
6426                               is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6427                              is_ofdm_rate(rspec[k]))
6428                             && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6429                                 || !(rspec[k] & RSPEC_OVERRIDE))) {
6430                                 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6431
6432                                 /* For SISO MCS use STBC if possible */
6433                                 if (is_mcs_rate(rspec[k])
6434                                     && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6435                                         u8 stc;
6436
6437                                         /* Nss for single stream is always 1 */
6438                                         stc = 1;
6439                                         rspec[k] |= (PHY_TXC1_MODE_STBC <<
6440                                                         RSPEC_STF_SHIFT) |
6441                                                     (stc << RSPEC_STC_SHIFT);
6442                                 } else
6443                                         rspec[k] |=
6444                                             (phyctl1_stf << RSPEC_STF_SHIFT);
6445                         }
6446
6447                         /*
6448                          * Is the phy configured to use 40MHZ frames? If
6449                          * so then pick the desired txbw
6450                          */
6451                         if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6452                                 /* default txbw is 20in40 SB */
6453                                 mimo_ctlchbw = mimo_txbw =
6454                                    CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6455                                                                  wlc->band->pi))
6456                                    ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6457
6458                                 if (is_mcs_rate(rspec[k])) {
6459                                         /* mcs 32 must be 40b/w DUP */
6460                                         if ((rspec[k] & RSPEC_RATE_MASK)
6461                                             == 32) {
6462                                                 mimo_txbw =
6463                                                     PHY_TXC1_BW_40MHZ_DUP;
6464                                                 /* use override */
6465                                         } else if (wlc->mimo_40txbw != AUTO)
6466                                                 mimo_txbw = wlc->mimo_40txbw;
6467                                         /* else check if dst is using 40 Mhz */
6468                                         else if (scb->flags & SCB_IS40)
6469                                                 mimo_txbw = PHY_TXC1_BW_40MHZ;
6470                                 } else if (is_ofdm_rate(rspec[k])) {
6471                                         if (wlc->ofdm_40txbw != AUTO)
6472                                                 mimo_txbw = wlc->ofdm_40txbw;
6473                                 } else if (wlc->cck_40txbw != AUTO) {
6474                                         mimo_txbw = wlc->cck_40txbw;
6475                                 }
6476                         } else {
6477                                 /*
6478                                  * mcs32 is 40 b/w only.
6479                                  * This is possible for probe packets on
6480                                  * a STA during SCAN
6481                                  */
6482                                 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6483                                         /* mcs 0 */
6484                                         rspec[k] = RSPEC_MIMORATE;
6485
6486                                 mimo_txbw = PHY_TXC1_BW_20MHZ;
6487                         }
6488
6489                         /* Set channel width */
6490                         rspec[k] &= ~RSPEC_BW_MASK;
6491                         if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6492                                 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6493                         else
6494                                 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6495
6496                         /* Disable short GI, not supported yet */
6497                         rspec[k] &= ~RSPEC_SHORT_GI;
6498
6499                         mimo_preamble_type = BRCMS_MM_PREAMBLE;
6500                         if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6501                                 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6502
6503                         if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6504                             && (!is_mcs_rate(rspec[k]))) {
6505                                 brcms_warn(wlc->hw->d11core,
6506                                            "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
6507                                            wlc->pub->unit, __func__);
6508                         }
6509
6510                         if (is_mcs_rate(rspec[k])) {
6511                                 preamble_type[k] = mimo_preamble_type;
6512
6513                                 /*
6514                                  * if SGI is selected, then forced mm
6515                                  * for single stream
6516                                  */
6517                                 if ((rspec[k] & RSPEC_SHORT_GI)
6518                                     && is_single_stream(rspec[k] &
6519                                                         RSPEC_RATE_MASK))
6520                                         preamble_type[k] = BRCMS_MM_PREAMBLE;
6521                         }
6522
6523                         /* should be better conditionalized */
6524                         if (!is_mcs_rate(rspec[0])
6525                             && (tx_info->control.rates[0].
6526                                 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6527                                 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6528                 }
6529         } else {
6530                 for (k = 0; k < hw->max_rates; k++) {
6531                         /* Set ctrlchbw as 20Mhz */
6532                         rspec[k] &= ~RSPEC_BW_MASK;
6533                         rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6534
6535                         /* for nphy, stf of ofdm frames must follow policies */
6536                         if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6537                                 rspec[k] &= ~RSPEC_STF_MASK;
6538                                 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6539                         }
6540                 }
6541         }
6542
6543         /* Reset these for use with AMPDU's */
6544         txrate[0]->count = 0;
6545         txrate[1]->count = 0;
6546
6547         /* (2) PROTECTION, may change rspec */
6548         if ((ieee80211_is_data(h->frame_control) ||
6549             ieee80211_is_mgmt(h->frame_control)) &&
6550             (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6551                 use_rts = true;
6552
6553         /* (3) PLCP: determine PLCP header and MAC duration,
6554          * fill struct d11txh */
6555         brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6556         brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6557         memcpy(&txh->FragPLCPFallback,
6558                plcp_fallback, sizeof(txh->FragPLCPFallback));
6559
6560         /* Length field now put in CCK FBR CRC field */
6561         if (is_cck_rate(rspec[1])) {
6562                 txh->FragPLCPFallback[4] = phylen & 0xff;
6563                 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6564         }
6565
6566         /* MIMO-RATE: need validation ?? */
6567         mainrates = is_ofdm_rate(rspec[0]) ?
6568                         D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6569                         plcp[0];
6570
6571         /* DUR field for main rate */
6572         if (!ieee80211_is_pspoll(h->frame_control) &&
6573             !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6574                 durid =
6575                     brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6576                                           next_frag_len);
6577                 h->duration_id = cpu_to_le16(durid);
6578         } else if (use_rifs) {
6579                 /* NAV protect to end of next max packet size */
6580                 durid =
6581                     (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6582                                                  preamble_type[0],
6583                                                  DOT11_MAX_FRAG_LEN);
6584                 durid += RIFS_11N_TIME;
6585                 h->duration_id = cpu_to_le16(durid);
6586         }
6587
6588         /* DUR field for fallback rate */
6589         if (ieee80211_is_pspoll(h->frame_control))
6590                 txh->FragDurFallback = h->duration_id;
6591         else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6592                 txh->FragDurFallback = 0;
6593         else {
6594                 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6595                                               preamble_type[1], next_frag_len);
6596                 txh->FragDurFallback = cpu_to_le16(durid);
6597         }
6598
6599         /* (4) MAC-HDR: MacTxControlLow */
6600         if (frag == 0)
6601                 mcl |= TXC_STARTMSDU;
6602
6603         if (!is_multicast_ether_addr(h->addr1))
6604                 mcl |= TXC_IMMEDACK;
6605
6606         if (wlc->band->bandtype == BRCM_BAND_5G)
6607                 mcl |= TXC_FREQBAND_5G;
6608
6609         if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6610                 mcl |= TXC_BW_40;
6611
6612         /* set AMIC bit if using hardware TKIP MIC */
6613         if (hwtkmic)
6614                 mcl |= TXC_AMIC;
6615
6616         txh->MacTxControlLow = cpu_to_le16(mcl);
6617
6618         /* MacTxControlHigh */
6619         mch = 0;
6620
6621         /* Set fallback rate preamble type */
6622         if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6623             (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6624                 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6625                         mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6626         }
6627
6628         /* MacFrameControl */
6629         memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6630         txh->TxFesTimeNormal = cpu_to_le16(0);
6631
6632         txh->TxFesTimeFallback = cpu_to_le16(0);
6633
6634         /* TxFrameRA */
6635         memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6636
6637         /* TxFrameID */
6638         txh->TxFrameID = cpu_to_le16(frameid);
6639
6640         /*
6641          * TxStatus, Note the case of recreating the first frag of a suppressed
6642          * frame then we may need to reset the retry cnt's via the status reg
6643          */
6644         txh->TxStatus = cpu_to_le16(status);
6645
6646         /*
6647          * extra fields for ucode AMPDU aggregation, the new fields are added to
6648          * the END of previous structure so that it's compatible in driver.
6649          */
6650         txh->MaxNMpdus = cpu_to_le16(0);
6651         txh->MaxABytes_MRT = cpu_to_le16(0);
6652         txh->MaxABytes_FBR = cpu_to_le16(0);
6653         txh->MinMBytes = cpu_to_le16(0);
6654
6655         /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6656          * furnish struct d11txh */
6657         /* RTS PLCP header and RTS frame */
6658         if (use_rts || use_cts) {
6659                 if (use_rts && use_cts)
6660                         use_cts = false;
6661
6662                 for (k = 0; k < 2; k++) {
6663                         rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6664                                                               false,
6665                                                               mimo_ctlchbw);
6666                 }
6667
6668                 if (!is_ofdm_rate(rts_rspec[0]) &&
6669                     !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6670                       (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6671                         rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6672                         mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6673                 }
6674
6675                 if (!is_ofdm_rate(rts_rspec[1]) &&
6676                     !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6677                       (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6678                         rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6679                         mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6680                 }
6681
6682                 /* RTS/CTS additions to MacTxControlLow */
6683                 if (use_cts) {
6684                         txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6685                 } else {
6686                         txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6687                         txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6688                 }
6689
6690                 /* RTS PLCP header */
6691                 rts_plcp = txh->RTSPhyHeader;
6692                 if (use_cts)
6693                         rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6694                 else
6695                         rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6696
6697                 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6698
6699                 /* fallback rate version of RTS PLCP header */
6700                 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6701                                  rts_plcp_fallback);
6702                 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6703                        sizeof(txh->RTSPLCPFallback));
6704
6705                 /* RTS frame fields... */
6706                 rts = (struct ieee80211_rts *)&txh->rts_frame;
6707
6708                 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6709                                                rspec[0], rts_preamble_type[0],
6710                                                preamble_type[0], phylen, false);
6711                 rts->duration = cpu_to_le16(durid);
6712                 /* fallback rate version of RTS DUR field */
6713                 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6714                                                rts_rspec[1], rspec[1],
6715                                                rts_preamble_type[1],
6716                                                preamble_type[1], phylen, false);
6717                 txh->RTSDurFallback = cpu_to_le16(durid);
6718
6719                 if (use_cts) {
6720                         rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6721                                                          IEEE80211_STYPE_CTS);
6722
6723                         memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6724                 } else {
6725                         rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6726                                                          IEEE80211_STYPE_RTS);
6727
6728                         memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6729                 }
6730
6731                 /* mainrate
6732                  *    low 8 bits: main frag rate/mcs,
6733                  *    high 8 bits: rts/cts rate/mcs
6734                  */
6735                 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6736                                 D11A_PHY_HDR_GRATE(
6737                                         (struct ofdm_phy_hdr *) rts_plcp) :
6738                                 rts_plcp[0]) << 8;
6739         } else {
6740                 memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6741                 memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
6742                 memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
6743                 txh->RTSDurFallback = 0;
6744         }
6745
6746 #ifdef SUPPORT_40MHZ
6747         /* add null delimiter count */
6748         if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6749                 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6750                    brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6751
6752 #endif
6753
6754         /*
6755          * Now that RTS/RTS FB preamble types are updated, write
6756          * the final value
6757          */
6758         txh->MacTxControlHigh = cpu_to_le16(mch);
6759
6760         /*
6761          * MainRates (both the rts and frag plcp rates have
6762          * been calculated now)
6763          */
6764         txh->MainRates = cpu_to_le16(mainrates);
6765
6766         /* XtraFrameTypes */
6767         xfts = frametype(rspec[1], wlc->mimoft);
6768         xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6769         xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6770         xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6771                                                              XFTS_CHANNEL_SHIFT;
6772         txh->XtraFrameTypes = cpu_to_le16(xfts);
6773
6774         /* PhyTxControlWord */
6775         phyctl = frametype(rspec[0], wlc->mimoft);
6776         if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6777             (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6778                 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6779                         phyctl |= PHY_TXC_SHORT_HDR;
6780         }
6781
6782         /* phytxant is properly bit shifted */
6783         phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6784         txh->PhyTxControlWord = cpu_to_le16(phyctl);
6785
6786         /* PhyTxControlWord_1 */
6787         if (BRCMS_PHY_11N_CAP(wlc->band)) {
6788                 u16 phyctl1 = 0;
6789
6790                 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6791                 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6792                 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6793                 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6794
6795                 if (use_rts || use_cts) {
6796                         phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6797                         txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6798                         phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6799                         txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6800                 }
6801
6802                 /*
6803                  * For mcs frames, if mixedmode(overloaded with long preamble)
6804                  * is going to be set, fill in non-zero MModeLen and/or
6805                  * MModeFbrLen it will be unnecessary if they are separated
6806                  */
6807                 if (is_mcs_rate(rspec[0]) &&
6808                     (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6809                         u16 mmodelen =
6810                             brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6811                         txh->MModeLen = cpu_to_le16(mmodelen);
6812                 }
6813
6814                 if (is_mcs_rate(rspec[1]) &&
6815                     (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6816                         u16 mmodefbrlen =
6817                             brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6818                         txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6819                 }
6820         }
6821
6822         ac = skb_get_queue_mapping(p);
6823         if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6824                 uint frag_dur, dur, dur_fallback;
6825
6826                 /* WME: Update TXOP threshold */
6827                 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6828                         frag_dur =
6829                             brcms_c_calc_frame_time(wlc, rspec[0],
6830                                         preamble_type[0], phylen);
6831
6832                         if (rts) {
6833                                 /* 1 RTS or CTS-to-self frame */
6834                                 dur =
6835                                     brcms_c_calc_cts_time(wlc, rts_rspec[0],
6836                                                       rts_preamble_type[0]);
6837                                 dur_fallback =
6838                                     brcms_c_calc_cts_time(wlc, rts_rspec[1],
6839                                                       rts_preamble_type[1]);
6840                                 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6841                                 dur += le16_to_cpu(rts->duration);
6842                                 dur_fallback +=
6843                                         le16_to_cpu(txh->RTSDurFallback);
6844                         } else if (use_rifs) {
6845                                 dur = frag_dur;
6846                                 dur_fallback = 0;
6847                         } else {
6848                                 /* frame + SIFS + ACK */
6849                                 dur = frag_dur;
6850                                 dur +=
6851                                     brcms_c_compute_frame_dur(wlc, rspec[0],
6852                                                           preamble_type[0], 0);
6853
6854                                 dur_fallback =
6855                                     brcms_c_calc_frame_time(wlc, rspec[1],
6856                                                         preamble_type[1],
6857                                                         phylen);
6858                                 dur_fallback +=
6859                                     brcms_c_compute_frame_dur(wlc, rspec[1],
6860                                                           preamble_type[1], 0);
6861                         }
6862                         /* NEED to set TxFesTimeNormal (hard) */
6863                         txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6864                         /*
6865                          * NEED to set fallback rate version of
6866                          * TxFesTimeNormal (hard)
6867                          */
6868                         txh->TxFesTimeFallback =
6869                                 cpu_to_le16((u16) dur_fallback);
6870
6871                         /*
6872                          * update txop byte threshold (txop minus intraframe
6873                          * overhead)
6874                          */
6875                         if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6876                                 uint newfragthresh;
6877
6878                                 newfragthresh =
6879                                     brcms_c_calc_frame_len(wlc,
6880                                         rspec[0], preamble_type[0],
6881                                         (wlc->edcf_txop[ac] -
6882                                                 (dur - frag_dur)));
6883                                 /* range bound the fragthreshold */
6884                                 if (newfragthresh < DOT11_MIN_FRAG_LEN)
6885                                         newfragthresh =
6886                                             DOT11_MIN_FRAG_LEN;
6887                                 else if (newfragthresh >
6888                                          wlc->usr_fragthresh)
6889                                         newfragthresh =
6890                                             wlc->usr_fragthresh;
6891                                 /* update the fragthresh and do txc update */
6892                                 if (wlc->fragthresh[queue] !=
6893                                     (u16) newfragthresh)
6894                                         wlc->fragthresh[queue] =
6895                                             (u16) newfragthresh;
6896                         } else {
6897                                 brcms_warn(wlc->hw->d11core,
6898                                            "wl%d: %s txop invalid for rate %d\n",
6899                                            wlc->pub->unit, fifo_names[queue],
6900                                            rspec2rate(rspec[0]));
6901                         }
6902
6903                         if (dur > wlc->edcf_txop[ac])
6904                                 brcms_warn(wlc->hw->d11core,
6905                                            "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
6906                                            wlc->pub->unit, __func__,
6907                                            fifo_names[queue],
6908                                            phylen, wlc->fragthresh[queue],
6909                                            dur, wlc->edcf_txop[ac]);
6910                 }
6911         }
6912
6913         return 0;
6914 }
6915
6916 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6917 {
6918         struct dma_pub *dma;
6919         int fifo, ret = -ENOSPC;
6920         struct d11txh *txh;
6921         u16 frameid = INVALIDFID;
6922
6923         fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6924         dma = wlc->hw->di[fifo];
6925         txh = (struct d11txh *)(skb->data);
6926
6927         if (dma->txavail == 0) {
6928                 /*
6929                  * We sometimes get a frame from mac80211 after stopping
6930                  * the queues. This only ever seems to be a single frame
6931                  * and is seems likely to be a race. TX_HEADROOM should
6932                  * ensure that we have enough space to handle these stray
6933                  * packets, so warn if there isn't. If we're out of space
6934                  * in the tx ring and the tx queue isn't stopped then
6935                  * we've really got a bug; warn loudly if that happens.
6936                  */
6937                 brcms_warn(wlc->hw->d11core,
6938                            "Received frame for tx with no space in DMA ring\n");
6939                 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6940                                                  skb_get_queue_mapping(skb)));
6941                 return -ENOSPC;
6942         }
6943
6944         /* When a BC/MC frame is being committed to the BCMC fifo
6945          * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6946          */
6947         if (fifo == TX_BCMC_FIFO)
6948                 frameid = le16_to_cpu(txh->TxFrameID);
6949
6950         /* Commit BCMC sequence number in the SHM frame ID location */
6951         if (frameid != INVALIDFID) {
6952                 /*
6953                  * To inform the ucode of the last mcast frame posted
6954                  * so that it can clear moredata bit
6955                  */
6956                 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6957         }
6958
6959         ret = brcms_c_txfifo(wlc, fifo, skb);
6960         /*
6961          * The only reason for brcms_c_txfifo to fail is because
6962          * there weren't any DMA descriptors, but we've already
6963          * checked for that. So if it does fail yell loudly.
6964          */
6965         WARN_ON_ONCE(ret);
6966
6967         return ret;
6968 }
6969
6970 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6971                               struct ieee80211_hw *hw)
6972 {
6973         uint fifo;
6974         struct scb *scb = &wlc->pri_scb;
6975
6976         fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6977         brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6978         if (!brcms_c_tx(wlc, sdu))
6979                 return true;
6980
6981         /* packet discarded */
6982         dev_kfree_skb_any(sdu);
6983         return false;
6984 }
6985
6986 int
6987 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6988 {
6989         struct dma_pub *dma = wlc->hw->di[fifo];
6990         int ret;
6991         u16 queue;
6992
6993         ret = dma_txfast(wlc, dma, p);
6994         if (ret < 0)
6995                 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6996
6997         /*
6998          * Stop queue if DMA ring is full. Reserve some free descriptors,
6999          * as we sometimes receive a frame from mac80211 after the queues
7000          * are stopped.
7001          */
7002         queue = skb_get_queue_mapping(p);
7003         if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
7004             !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
7005                 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
7006
7007         return ret;
7008 }
7009
7010 u32
7011 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
7012                            bool use_rspec, u16 mimo_ctlchbw)
7013 {
7014         u32 rts_rspec = 0;
7015
7016         if (use_rspec)
7017                 /* use frame rate as rts rate */
7018                 rts_rspec = rspec;
7019         else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
7020                 /* Use 11Mbps as the g protection RTS target rate and fallback.
7021                  * Use the brcms_basic_rate() lookup to find the best basic rate
7022                  * under the target in case 11 Mbps is not Basic.
7023                  * 6 and 9 Mbps are not usually selected by rate selection, but
7024                  * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7025                  * is more robust.
7026                  */
7027                 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7028         else
7029                 /* calculate RTS rate and fallback rate based on the frame rate
7030                  * RTS must be sent at a basic rate since it is a
7031                  * control frame, sec 9.6 of 802.11 spec
7032                  */
7033                 rts_rspec = brcms_basic_rate(wlc, rspec);
7034
7035         if (BRCMS_PHY_11N_CAP(wlc->band)) {
7036                 /* set rts txbw to correct side band */
7037                 rts_rspec &= ~RSPEC_BW_MASK;
7038
7039                 /*
7040                  * if rspec/rspec_fallback is 40MHz, then send RTS on both
7041                  * 20MHz channel (DUP), otherwise send RTS on control channel
7042                  */
7043                 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7044                         rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7045                 else
7046                         rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7047
7048                 /* pick siso/cdd as default for ofdm */
7049                 if (is_ofdm_rate(rts_rspec)) {
7050                         rts_rspec &= ~RSPEC_STF_MASK;
7051                         rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7052                 }
7053         }
7054         return rts_rspec;
7055 }
7056
7057 /* Update beacon listen interval in shared memory */
7058 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7059 {
7060         /* wake up every DTIM is the default */
7061         if (wlc->bcn_li_dtim == 1)
7062                 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7063         else
7064                 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7065                               (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7066 }
7067
7068 static void
7069 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7070                   u32 *tsf_h_ptr)
7071 {
7072         struct bcma_device *core = wlc_hw->d11core;
7073
7074         /* read the tsf timer low, then high to get an atomic read */
7075         *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7076         *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7077 }
7078
7079 /*
7080  * recover 64bit TSF value from the 16bit TSF value in the rx header
7081  * given the assumption that the TSF passed in header is within 65ms
7082  * of the current tsf.
7083  *
7084  * 6       5       4       4       3       2       1
7085  * 3.......6.......8.......0.......2.......4.......6.......8......0
7086  * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7087  *
7088  * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7089  * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7090  * receive call sequence after rx interrupt. Only the higher 16 bits
7091  * are used. Finally, the tsf_h is read from the tsf register.
7092  */
7093 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7094                                  struct d11rxhdr *rxh)
7095 {
7096         u32 tsf_h, tsf_l;
7097         u16 rx_tsf_0_15, rx_tsf_16_31;
7098
7099         brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7100
7101         rx_tsf_16_31 = (u16)(tsf_l >> 16);
7102         rx_tsf_0_15 = rxh->RxTSFTime;
7103
7104         /*
7105          * a greater tsf time indicates the low 16 bits of
7106          * tsf_l wrapped, so decrement the high 16 bits.
7107          */
7108         if ((u16)tsf_l < rx_tsf_0_15) {
7109                 rx_tsf_16_31 -= 1;
7110                 if (rx_tsf_16_31 == 0xffff)
7111                         tsf_h -= 1;
7112         }
7113
7114         return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7115 }
7116
7117 static void
7118 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7119                      struct sk_buff *p,
7120                      struct ieee80211_rx_status *rx_status)
7121 {
7122         int preamble;
7123         int channel;
7124         u32 rspec;
7125         unsigned char *plcp;
7126
7127         /* fill in TSF and flag its presence */
7128         rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7129         rx_status->flag |= RX_FLAG_MACTIME_START;
7130
7131         channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7132
7133         rx_status->band =
7134                 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7135         rx_status->freq =
7136                 ieee80211_channel_to_frequency(channel, rx_status->band);
7137
7138         rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7139
7140         /* noise */
7141         /* qual */
7142         rx_status->antenna =
7143                 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7144
7145         plcp = p->data;
7146
7147         rspec = brcms_c_compute_rspec(rxh, plcp);
7148         if (is_mcs_rate(rspec)) {
7149                 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7150                 rx_status->flag |= RX_FLAG_HT;
7151                 if (rspec_is40mhz(rspec))
7152                         rx_status->flag |= RX_FLAG_40MHZ;
7153         } else {
7154                 switch (rspec2rate(rspec)) {
7155                 case BRCM_RATE_1M:
7156                         rx_status->rate_idx = 0;
7157                         break;
7158                 case BRCM_RATE_2M:
7159                         rx_status->rate_idx = 1;
7160                         break;
7161                 case BRCM_RATE_5M5:
7162                         rx_status->rate_idx = 2;
7163                         break;
7164                 case BRCM_RATE_11M:
7165                         rx_status->rate_idx = 3;
7166                         break;
7167                 case BRCM_RATE_6M:
7168                         rx_status->rate_idx = 4;
7169                         break;
7170                 case BRCM_RATE_9M:
7171                         rx_status->rate_idx = 5;
7172                         break;
7173                 case BRCM_RATE_12M:
7174                         rx_status->rate_idx = 6;
7175                         break;
7176                 case BRCM_RATE_18M:
7177                         rx_status->rate_idx = 7;
7178                         break;
7179                 case BRCM_RATE_24M:
7180                         rx_status->rate_idx = 8;
7181                         break;
7182                 case BRCM_RATE_36M:
7183                         rx_status->rate_idx = 9;
7184                         break;
7185                 case BRCM_RATE_48M:
7186                         rx_status->rate_idx = 10;
7187                         break;
7188                 case BRCM_RATE_54M:
7189                         rx_status->rate_idx = 11;
7190                         break;
7191                 default:
7192                         brcms_err(wlc->hw->d11core,
7193                                   "%s: Unknown rate\n", __func__);
7194                 }
7195
7196                 /*
7197                  * For 5GHz, we should decrease the index as it is
7198                  * a subset of the 2.4G rates. See bitrates field
7199                  * of brcms_band_5GHz_nphy (in mac80211_if.c).
7200                  */
7201                 if (rx_status->band == IEEE80211_BAND_5GHZ)
7202                         rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7203
7204                 /* Determine short preamble and rate_idx */
7205                 preamble = 0;
7206                 if (is_cck_rate(rspec)) {
7207                         if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7208                                 rx_status->flag |= RX_FLAG_SHORTPRE;
7209                 } else if (is_ofdm_rate(rspec)) {
7210                         rx_status->flag |= RX_FLAG_SHORTPRE;
7211                 } else {
7212                         brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7213                                   __func__);
7214                 }
7215         }
7216
7217         if (plcp3_issgi(plcp[3]))
7218                 rx_status->flag |= RX_FLAG_SHORT_GI;
7219
7220         if (rxh->RxStatus1 & RXS_DECERR) {
7221                 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7222                 brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_PLCP_CRC\n",
7223                           __func__);
7224         }
7225         if (rxh->RxStatus1 & RXS_FCSERR) {
7226                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7227                 brcms_err(wlc->hw->d11core, "%s:  RX_FLAG_FAILED_FCS_CRC\n",
7228                           __func__);
7229         }
7230 }
7231
7232 static void
7233 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7234                 struct sk_buff *p)
7235 {
7236         int len_mpdu;
7237         struct ieee80211_rx_status rx_status;
7238         struct ieee80211_hdr *hdr;
7239
7240         memset(&rx_status, 0, sizeof(rx_status));
7241         prep_mac80211_status(wlc, rxh, p, &rx_status);
7242
7243         /* mac header+body length, exclude CRC and plcp header */
7244         len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7245         skb_pull(p, D11_PHY_HDR_LEN);
7246         __skb_trim(p, len_mpdu);
7247
7248         /* unmute transmit */
7249         if (wlc->hw->suspended_fifos) {
7250                 hdr = (struct ieee80211_hdr *)p->data;
7251                 if (ieee80211_is_beacon(hdr->frame_control))
7252                         brcms_b_mute(wlc->hw, false);
7253         }
7254
7255         memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7256         ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7257 }
7258
7259 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7260  * number of bytes goes in the length field
7261  *
7262  * Formula given by HT PHY Spec v 1.13
7263  *   len = 3(nsyms + nstream + 3) - 3
7264  */
7265 u16
7266 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7267                       uint mac_len)
7268 {
7269         uint nsyms, len = 0, kNdps;
7270
7271         if (is_mcs_rate(ratespec)) {
7272                 uint mcs = ratespec & RSPEC_RATE_MASK;
7273                 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7274                                   rspec_stc(ratespec);
7275
7276                 /*
7277                  * the payload duration calculation matches that
7278                  * of regular ofdm
7279                  */
7280                 /* 1000Ndbps = kbps * 4 */
7281                 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7282                                    rspec_issgi(ratespec)) * 4;
7283
7284                 if (rspec_stc(ratespec) == 0)
7285                         nsyms =
7286                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7287                                   APHY_TAIL_NBITS) * 1000, kNdps);
7288                 else
7289                         /* STBC needs to have even number of symbols */
7290                         nsyms =
7291                             2 *
7292                             CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7293                                   APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7294
7295                 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7296                 nsyms += (tot_streams + 3);
7297                 /*
7298                  * 3 bytes/symbol @ legacy 6Mbps rate
7299                  * (-3) excluding service bits and tail bits
7300                  */
7301                 len = (3 * nsyms) - 3;
7302         }
7303
7304         return (u16) len;
7305 }
7306
7307 static void
7308 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7309 {
7310         const struct brcms_c_rateset *rs_dflt;
7311         struct brcms_c_rateset rs;
7312         u8 rate;
7313         u16 entry_ptr;
7314         u8 plcp[D11_PHY_HDR_LEN];
7315         u16 dur, sifs;
7316         uint i;
7317
7318         sifs = get_sifs(wlc->band);
7319
7320         rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7321
7322         brcms_c_rateset_copy(rs_dflt, &rs);
7323         brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7324
7325         /*
7326          * walk the phy rate table and update MAC core SHM
7327          * basic rate table entries
7328          */
7329         for (i = 0; i < rs.count; i++) {
7330                 rate = rs.rates[i] & BRCMS_RATE_MASK;
7331
7332                 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7333
7334                 /* Calculate the Probe Response PLCP for the given rate */
7335                 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7336
7337                 /*
7338                  * Calculate the duration of the Probe Response
7339                  * frame plus SIFS for the MAC
7340                  */
7341                 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7342                                                 BRCMS_LONG_PREAMBLE, frame_len);
7343                 dur += sifs;
7344
7345                 /* Update the SHM Rate Table entry Probe Response values */
7346                 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7347                               (u16) (plcp[0] + (plcp[1] << 8)));
7348                 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7349                               (u16) (plcp[2] + (plcp[3] << 8)));
7350                 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7351         }
7352 }
7353
7354 int brcms_c_get_header_len(void)
7355 {
7356         return TXOFF;
7357 }
7358
7359 static void brcms_c_beacon_write(struct brcms_c_info *wlc,
7360                                  struct sk_buff *beacon, u16 tim_offset,
7361                                  u16 dtim_period, bool bcn0, bool bcn1)
7362 {
7363         size_t len;
7364         struct ieee80211_tx_info *tx_info;
7365         struct brcms_hardware *wlc_hw = wlc->hw;
7366         struct ieee80211_hw *ieee_hw = brcms_c_pub(wlc)->ieee_hw;
7367
7368         /* Get tx_info */
7369         tx_info = IEEE80211_SKB_CB(beacon);
7370
7371         len = min_t(size_t, beacon->len, BCN_TMPL_LEN);
7372         wlc->bcn_rspec = ieee80211_get_tx_rate(ieee_hw, tx_info)->hw_value;
7373
7374         brcms_c_compute_plcp(wlc, wlc->bcn_rspec,
7375                              len + FCS_LEN - D11_PHY_HDR_LEN, beacon->data);
7376
7377         /* "Regular" and 16 MBSS but not for 4 MBSS */
7378         /* Update the phytxctl for the beacon based on the rspec */
7379         brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
7380
7381         if (bcn0) {
7382                 /* write the probe response into the template region */
7383                 brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE,
7384                                             (len + 3) & ~3, beacon->data);
7385
7386                 /* write beacon length to SCR */
7387                 brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
7388         }
7389         if (bcn1) {
7390                 /* write the probe response into the template region */
7391                 brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE,
7392                                             (len + 3) & ~3, beacon->data);
7393
7394                 /* write beacon length to SCR */
7395                 brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
7396         }
7397
7398         if (tim_offset != 0) {
7399                 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7400                                   tim_offset + D11B_PHY_HDR_LEN);
7401                 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, dtim_period);
7402         } else {
7403                 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7404                                   len + D11B_PHY_HDR_LEN);
7405                 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, 0);
7406         }
7407 }
7408
7409 static void brcms_c_update_beacon_hw(struct brcms_c_info *wlc,
7410                                      struct sk_buff *beacon, u16 tim_offset,
7411                                      u16 dtim_period)
7412 {
7413         struct brcms_hardware *wlc_hw = wlc->hw;
7414         struct bcma_device *core = wlc_hw->d11core;
7415
7416         /* Hardware beaconing for this config */
7417         u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
7418
7419         /* Check if both templates are in use, if so sched. an interrupt
7420          *      that will call back into this routine
7421          */
7422         if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid)
7423                 /* clear any previous status */
7424                 bcma_write32(core, D11REGOFFS(macintstatus), MI_BCNTPL);
7425
7426         if (wlc->beacon_template_virgin) {
7427                 wlc->beacon_template_virgin = false;
7428                 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7429                                      true);
7430                 /* mark beacon0 valid */
7431                 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7432                 return;
7433         }
7434
7435         /* Check that after scheduling the interrupt both of the
7436          *      templates are still busy. if not clear the int. & remask
7437          */
7438         if ((bcma_read32(core, D11REGOFFS(maccommand)) & both_valid) == both_valid) {
7439                 wlc->defmacintmask |= MI_BCNTPL;
7440                 return;
7441         }
7442
7443         if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN0VLD)) {
7444                 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period, true,
7445                                      false);
7446                 /* mark beacon0 valid */
7447                 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN0VLD);
7448                 return;
7449         }
7450         if (!(bcma_read32(core, D11REGOFFS(maccommand)) & MCMD_BCN1VLD)) {
7451                 brcms_c_beacon_write(wlc, beacon, tim_offset, dtim_period,
7452                                      false, true);
7453                 /* mark beacon0 valid */
7454                 bcma_set32(core, D11REGOFFS(maccommand), MCMD_BCN1VLD);
7455                 return;
7456         }
7457         return;
7458 }
7459
7460 /*
7461  * Update all beacons for the system.
7462  */
7463 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7464 {
7465         struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7466
7467         if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7468                              bsscfg->type == BRCMS_TYPE_ADHOC)) {
7469                 /* Clear the soft intmask */
7470                 wlc->defmacintmask &= ~MI_BCNTPL;
7471                 if (!wlc->beacon)
7472                         return;
7473                 brcms_c_update_beacon_hw(wlc, wlc->beacon,
7474                                          wlc->beacon_tim_offset,
7475                                          wlc->beacon_dtim_period);
7476         }
7477 }
7478
7479 void brcms_c_set_new_beacon(struct brcms_c_info *wlc, struct sk_buff *beacon,
7480                             u16 tim_offset, u16 dtim_period)
7481 {
7482         if (!beacon)
7483                 return;
7484         if (wlc->beacon)
7485                 dev_kfree_skb_any(wlc->beacon);
7486         wlc->beacon = beacon;
7487
7488         /* add PLCP */
7489         skb_push(wlc->beacon, D11_PHY_HDR_LEN);
7490         wlc->beacon_tim_offset = tim_offset;
7491         wlc->beacon_dtim_period = dtim_period;
7492         brcms_c_update_beacon(wlc);
7493 }
7494
7495 void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc,
7496                                 struct sk_buff *probe_resp)
7497 {
7498         if (!probe_resp)
7499                 return;
7500         if (wlc->probe_resp)
7501                 dev_kfree_skb_any(wlc->probe_resp);
7502         wlc->probe_resp = probe_resp;
7503
7504         /* add PLCP */
7505         skb_push(wlc->probe_resp, D11_PHY_HDR_LEN);
7506         brcms_c_update_probe_resp(wlc, false);
7507 }
7508
7509 void brcms_c_enable_probe_resp(struct brcms_c_info *wlc, bool enable)
7510 {
7511         /*
7512          * prevent ucode from sending probe responses by setting the timeout
7513          * to 1, it can not send it in that time frame.
7514          */
7515         wlc->prb_resp_timeout = enable ? BRCMS_PRB_RESP_TIMEOUT : 1;
7516         brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7517         /* TODO: if (enable) => also deactivate receiving of probe request */
7518 }
7519
7520 /* Write ssid into shared memory */
7521 static void
7522 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7523 {
7524         u8 *ssidptr = cfg->SSID;
7525         u16 base = M_SSID;
7526         u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7527
7528         /* padding the ssid with zero and copy it into shm */
7529         memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7530         memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7531
7532         brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7533         brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7534 }
7535
7536 static void
7537 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7538                               struct brcms_bss_cfg *cfg,
7539                               struct sk_buff *probe_resp,
7540                               bool suspend)
7541 {
7542         int len;
7543
7544         len = min_t(size_t, probe_resp->len, BCN_TMPL_LEN);
7545
7546         if (suspend)
7547                 brcms_c_suspend_mac_and_wait(wlc);
7548
7549         /* write the probe response into the template region */
7550         brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7551                                     (len + 3) & ~3, probe_resp->data);
7552
7553         /* write the length of the probe response frame (+PLCP/-FCS) */
7554         brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7555
7556         /* write the SSID and SSID length */
7557         brcms_c_shm_ssid_upd(wlc, cfg);
7558
7559         /*
7560          * Write PLCP headers and durations for probe response frames
7561          * at all rates. Use the actual frame length covered by the
7562          * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7563          * by subtracting the PLCP len and adding the FCS.
7564          */
7565         brcms_c_mod_prb_rsp_rate_table(wlc,
7566                                       (u16)len + FCS_LEN - D11_PHY_HDR_LEN);
7567
7568         if (suspend)
7569                 brcms_c_enable_mac(wlc);
7570 }
7571
7572 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7573 {
7574         struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7575
7576         /* update AP or IBSS probe responses */
7577         if (wlc->pub->up && (bsscfg->type == BRCMS_TYPE_AP ||
7578                              bsscfg->type == BRCMS_TYPE_ADHOC)) {
7579                 if (!wlc->probe_resp)
7580                         return;
7581                 brcms_c_bss_update_probe_resp(wlc, bsscfg, wlc->probe_resp,
7582                                               suspend);
7583         }
7584 }
7585
7586 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7587                            uint *blocks)
7588 {
7589         if (fifo >= NFIFO)
7590                 return -EINVAL;
7591
7592         *blocks = wlc_hw->xmtfifo_sz[fifo];
7593
7594         return 0;
7595 }
7596
7597 void
7598 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7599                   const u8 *addr)
7600 {
7601         brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7602         if (match_reg_offset == RCM_BSSID_OFFSET)
7603                 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7604 }
7605
7606 /*
7607  * Flag 'scan in progress' to withhold dynamic phy calibration
7608  */
7609 void brcms_c_scan_start(struct brcms_c_info *wlc)
7610 {
7611         wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7612 }
7613
7614 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7615 {
7616         wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7617 }
7618
7619 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7620 {
7621         wlc->pub->associated = state;
7622 }
7623
7624 /*
7625  * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7626  * AMPDU traffic, packets pending in hardware have to be invalidated so that
7627  * when later on hardware releases them, they can be handled appropriately.
7628  */
7629 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7630                                struct ieee80211_sta *sta,
7631                                void (*dma_callback_fn))
7632 {
7633         struct dma_pub *dmah;
7634         int i;
7635         for (i = 0; i < NFIFO; i++) {
7636                 dmah = hw->di[i];
7637                 if (dmah != NULL)
7638                         dma_walk_packets(dmah, dma_callback_fn, sta);
7639         }
7640 }
7641
7642 int brcms_c_get_curband(struct brcms_c_info *wlc)
7643 {
7644         return wlc->band->bandunit;
7645 }
7646
7647 bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
7648 {
7649         int i;
7650
7651         /* Kick DMA to send any pending AMPDU */
7652         for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7653                 if (wlc->hw->di[i])
7654                         dma_kick_tx(wlc->hw->di[i]);
7655
7656         return !brcms_txpktpendtot(wlc);
7657 }
7658
7659 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7660 {
7661         wlc->bcn_li_bcn = interval;
7662         if (wlc->pub->up)
7663                 brcms_c_bcn_li_upd(wlc);
7664 }
7665
7666 u64 brcms_c_tsf_get(struct brcms_c_info *wlc)
7667 {
7668         u32 tsf_h, tsf_l;
7669         u64 tsf;
7670
7671         brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7672
7673         tsf = tsf_h;
7674         tsf <<= 32;
7675         tsf |= tsf_l;
7676
7677         return tsf;
7678 }
7679
7680 void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf)
7681 {
7682         u32 tsf_h, tsf_l;
7683
7684         brcms_c_time_lock(wlc);
7685
7686         tsf_l = tsf;
7687         tsf_h = (tsf >> 32);
7688
7689         /* read the tsf timer low, then high to get an atomic read */
7690         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l);
7691         bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h);
7692
7693         brcms_c_time_unlock(wlc);
7694 }
7695
7696 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7697 {
7698         uint qdbm;
7699
7700         /* Remove override bit and clip to max qdbm value */
7701         qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7702         return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7703 }
7704
7705 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7706 {
7707         uint qdbm;
7708         bool override;
7709
7710         wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7711
7712         /* Return qdbm units */
7713         return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7714 }
7715
7716 /* Process received frames */
7717 /*
7718  * Return true if more frames need to be processed. false otherwise.
7719  * Param 'bound' indicates max. # frames to process before break out.
7720  */
7721 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7722 {
7723         struct d11rxhdr *rxh;
7724         struct ieee80211_hdr *h;
7725         uint len;
7726         bool is_amsdu;
7727
7728         /* frame starts with rxhdr */
7729         rxh = (struct d11rxhdr *) (p->data);
7730
7731         /* strip off rxhdr */
7732         skb_pull(p, BRCMS_HWRXOFF);
7733
7734         /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7735         if (rxh->RxStatus1 & RXS_PBPRES) {
7736                 if (p->len < 2) {
7737                         brcms_err(wlc->hw->d11core,
7738                                   "wl%d: recv: rcvd runt of len %d\n",
7739                                   wlc->pub->unit, p->len);
7740                         goto toss;
7741                 }
7742                 skb_pull(p, 2);
7743         }
7744
7745         h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7746         len = p->len;
7747
7748         if (rxh->RxStatus1 & RXS_FCSERR) {
7749                 if (!(wlc->filter_flags & FIF_FCSFAIL))
7750                         goto toss;
7751         }
7752
7753         /* check received pkt has at least frame control field */
7754         if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7755                 goto toss;
7756
7757         /* not supporting A-MSDU */
7758         is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7759         if (is_amsdu)
7760                 goto toss;
7761
7762         brcms_c_recvctl(wlc, rxh, p);
7763         return;
7764
7765  toss:
7766         brcmu_pkt_buf_free_skb(p);
7767 }
7768
7769 /* Process received frames */
7770 /*
7771  * Return true if more frames need to be processed. false otherwise.
7772  * Param 'bound' indicates max. # frames to process before break out.
7773  */
7774 static bool
7775 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7776 {
7777         struct sk_buff *p;
7778         struct sk_buff *next = NULL;
7779         struct sk_buff_head recv_frames;
7780
7781         uint n = 0;
7782         uint bound_limit = bound ? RXBND : -1;
7783         bool morepending = false;
7784
7785         skb_queue_head_init(&recv_frames);
7786
7787         /* gather received frames */
7788         do {
7789                 /* !give others some time to run! */
7790                 if (n >= bound_limit)
7791                         break;
7792
7793                 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7794                 n++;
7795         } while (morepending);
7796
7797         /* post more rbufs */
7798         dma_rxfill(wlc_hw->di[fifo]);
7799
7800         /* process each frame */
7801         skb_queue_walk_safe(&recv_frames, p, next) {
7802                 struct d11rxhdr_le *rxh_le;
7803                 struct d11rxhdr *rxh;
7804
7805                 skb_unlink(p, &recv_frames);
7806                 rxh_le = (struct d11rxhdr_le *)p->data;
7807                 rxh = (struct d11rxhdr *)p->data;
7808
7809                 /* fixup rx header endianness */
7810                 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7811                 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7812                 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7813                 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7814                 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7815                 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7816                 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7817                 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7818                 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7819                 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7820                 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7821
7822                 brcms_c_recv(wlc_hw->wlc, p);
7823         }
7824
7825         return morepending;
7826 }
7827
7828 /* second-level interrupt processing
7829  *   Return true if another dpc needs to be re-scheduled. false otherwise.
7830  *   Param 'bounded' indicates if applicable loops should be bounded.
7831  */
7832 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7833 {
7834         u32 macintstatus;
7835         struct brcms_hardware *wlc_hw = wlc->hw;
7836         struct bcma_device *core = wlc_hw->d11core;
7837
7838         if (brcms_deviceremoved(wlc)) {
7839                 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7840                           __func__);
7841                 brcms_down(wlc->wl);
7842                 return false;
7843         }
7844
7845         /* grab and clear the saved software intstatus bits */
7846         macintstatus = wlc->macintstatus;
7847         wlc->macintstatus = 0;
7848
7849         brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7850                       wlc_hw->unit, macintstatus);
7851
7852         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7853
7854         /* tx status */
7855         if (macintstatus & MI_TFS) {
7856                 bool fatal;
7857                 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7858                         wlc->macintstatus |= MI_TFS;
7859                 if (fatal) {
7860                         brcms_err(core, "MI_TFS: fatal\n");
7861                         goto fatal;
7862                 }
7863         }
7864
7865         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7866                 brcms_c_tbtt(wlc);
7867
7868         /* ATIM window end */
7869         if (macintstatus & MI_ATIMWINEND) {
7870                 brcms_dbg_info(core, "end of ATIM window\n");
7871                 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7872                 wlc->qvalid = 0;
7873         }
7874
7875         /*
7876          * received data or control frame, MI_DMAINT is
7877          * indication of RX_FIFO interrupt
7878          */
7879         if (macintstatus & MI_DMAINT)
7880                 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7881                         wlc->macintstatus |= MI_DMAINT;
7882
7883         /* noise sample collected */
7884         if (macintstatus & MI_BG_NOISE)
7885                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7886
7887         if (macintstatus & MI_GP0) {
7888                 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7889                           "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7890
7891                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7892                             __func__, ai_get_chip_id(wlc_hw->sih),
7893                             ai_get_chiprev(wlc_hw->sih));
7894                 brcms_fatal_error(wlc_hw->wlc->wl);
7895         }
7896
7897         /* gptimer timeout */
7898         if (macintstatus & MI_TO)
7899                 bcma_write32(core, D11REGOFFS(gptimer), 0);
7900
7901         if (macintstatus & MI_RFDISABLE) {
7902                 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7903                                " RF Disable Input\n", wlc_hw->unit);
7904                 brcms_rfkill_set_hw_state(wlc->wl);
7905         }
7906
7907         /* BCN template is available */
7908         if (macintstatus & MI_BCNTPL)
7909                 brcms_c_update_beacon(wlc);
7910
7911         /* it isn't done and needs to be resched if macintstatus is non-zero */
7912         return wlc->macintstatus != 0;
7913
7914  fatal:
7915         brcms_fatal_error(wlc_hw->wlc->wl);
7916         return wlc->macintstatus != 0;
7917 }
7918
7919 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7920 {
7921         struct bcma_device *core = wlc->hw->d11core;
7922         struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
7923         u16 chanspec;
7924
7925         brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7926
7927         chanspec = ch20mhz_chspec(ch->hw_value);
7928
7929         brcms_b_init(wlc->hw, chanspec);
7930
7931         /* update beacon listen interval */
7932         brcms_c_bcn_li_upd(wlc);
7933
7934         /* write ethernet address to core */
7935         brcms_c_set_mac(wlc->bsscfg);
7936         brcms_c_set_bssid(wlc->bsscfg);
7937
7938         /* Update tsf_cfprep if associated and up */
7939         if (wlc->pub->associated && wlc->pub->up) {
7940                 u32 bi;
7941
7942                 /* get beacon period and convert to uS */
7943                 bi = wlc->bsscfg->current_bss->beacon_period << 10;
7944                 /*
7945                  * update since init path would reset
7946                  * to default value
7947                  */
7948                 bcma_write32(core, D11REGOFFS(tsf_cfprep),
7949                              bi << CFPREP_CBI_SHIFT);
7950
7951                 /* Update maccontrol PM related bits */
7952                 brcms_c_set_ps_ctrl(wlc);
7953         }
7954
7955         brcms_c_bandinit_ordered(wlc, chanspec);
7956
7957         /* init probe response timeout */
7958         brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7959
7960         /* init max burst txop (framebursting) */
7961         brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7962                       (wlc->
7963                        _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7964
7965         /* initialize maximum allowed duty cycle */
7966         brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7967         brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7968
7969         /*
7970          * Update some shared memory locations related to
7971          * max AMPDU size allowed to received
7972          */
7973         brcms_c_ampdu_shm_upd(wlc->ampdu);
7974
7975         /* band-specific inits */
7976         brcms_c_bsinit(wlc);
7977
7978         /* Enable EDCF mode (while the MAC is suspended) */
7979         bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7980         brcms_c_edcf_setparams(wlc, false);
7981
7982         /* read the ucode version if we have not yet done so */
7983         if (wlc->ucode_rev == 0) {
7984                 u16 rev;
7985                 u16 patch;
7986
7987                 rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR);
7988                 patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7989                 wlc->ucode_rev = (rev << NBITS(u16)) | patch;
7990                 snprintf(wlc->wiphy->fw_version,
7991                          sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch);
7992         }
7993
7994         /* ..now really unleash hell (allow the MAC out of suspend) */
7995         brcms_c_enable_mac(wlc);
7996
7997         /* suspend the tx fifos and mute the phy for preism cac time */
7998         if (mute_tx)
7999                 brcms_b_mute(wlc->hw, true);
8000
8001         /* enable the RF Disable Delay timer */
8002         bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8003
8004         /*
8005          * Initialize WME parameters; if they haven't been set by some other
8006          * mechanism (IOVar, etc) then read them from the hardware.
8007          */
8008         if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
8009                 /* Uninitialized; read from HW */
8010                 int ac;
8011
8012                 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8013                         wlc->wme_retries[ac] =
8014                             brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8015         }
8016 }
8017
8018 /*
8019  * The common driver entry routine. Error codes should be unique
8020  */
8021 struct brcms_c_info *
8022 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
8023                bool piomode, uint *perr)
8024 {
8025         struct brcms_c_info *wlc;
8026         uint err = 0;
8027         uint i, j;
8028         struct brcms_pub *pub;
8029
8030         /* allocate struct brcms_c_info state and its substructures */
8031         wlc = brcms_c_attach_malloc(unit, &err, 0);
8032         if (wlc == NULL)
8033                 goto fail;
8034         wlc->wiphy = wl->wiphy;
8035         pub = wlc->pub;
8036
8037 #if defined(DEBUG)
8038         wlc_info_dbg = wlc;
8039 #endif
8040
8041         wlc->band = wlc->bandstate[0];
8042         wlc->core = wlc->corestate;
8043         wlc->wl = wl;
8044         pub->unit = unit;
8045         pub->_piomode = piomode;
8046         wlc->bandinit_pending = false;
8047         wlc->beacon_template_virgin = true;
8048
8049         /* populate struct brcms_c_info with default values  */
8050         brcms_c_info_init(wlc, unit);
8051
8052         /* update sta/ap related parameters */
8053         brcms_c_ap_upd(wlc);
8054
8055         /*
8056          * low level attach steps(all hw accesses go
8057          * inside, no more in rest of the attach)
8058          */
8059         err = brcms_b_attach(wlc, core, unit, piomode);
8060         if (err)
8061                 goto fail;
8062
8063         brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
8064
8065         pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
8066
8067         /* disable allowed duty cycle */
8068         wlc->tx_duty_cycle_ofdm = 0;
8069         wlc->tx_duty_cycle_cck = 0;
8070
8071         brcms_c_stf_phy_chain_calc(wlc);
8072
8073         /* txchain 1: txant 0, txchain 2: txant 1 */
8074         if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
8075                 wlc->stf->txant = wlc->stf->hw_txchain - 1;
8076
8077         /* push to BMAC driver */
8078         wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
8079                                wlc->stf->hw_rxchain);
8080
8081         /* pull up some info resulting from the low attach */
8082         for (i = 0; i < NFIFO; i++)
8083                 wlc->core->txavail[i] = wlc->hw->txavail[i];
8084
8085         memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8086         memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8087
8088         for (j = 0; j < wlc->pub->_nbands; j++) {
8089                 wlc->band = wlc->bandstate[j];
8090
8091                 if (!brcms_c_attach_stf_ant_init(wlc)) {
8092                         err = 24;
8093                         goto fail;
8094                 }
8095
8096                 /* default contention windows size limits */
8097                 wlc->band->CWmin = APHY_CWMIN;
8098                 wlc->band->CWmax = PHY_CWMAX;
8099
8100                 /* init gmode value */
8101                 if (wlc->band->bandtype == BRCM_BAND_2G) {
8102                         wlc->band->gmode = GMODE_AUTO;
8103                         brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
8104                                            wlc->band->gmode);
8105                 }
8106
8107                 /* init _n_enab supported mode */
8108                 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8109                         pub->_n_enab = SUPPORT_11N;
8110                         brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
8111                                                    ((pub->_n_enab ==
8112                                                      SUPPORT_11N) ? WL_11N_2x2 :
8113                                                     WL_11N_3x3));
8114                 }
8115
8116                 /* init per-band default rateset, depend on band->gmode */
8117                 brcms_default_rateset(wlc, &wlc->band->defrateset);
8118
8119                 /* fill in hw_rateset */
8120                 brcms_c_rateset_filter(&wlc->band->defrateset,
8121                                    &wlc->band->hw_rateset, false,
8122                                    BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8123                                    (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8124         }
8125
8126         /*
8127          * update antenna config due to
8128          * wlc->stf->txant/txchain/ant_rx_ovr change
8129          */
8130         brcms_c_stf_phy_txant_upd(wlc);
8131
8132         /* attach each modules */
8133         err = brcms_c_attach_module(wlc);
8134         if (err != 0)
8135                 goto fail;
8136
8137         if (!brcms_c_timers_init(wlc, unit)) {
8138                 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8139                           __func__);
8140                 err = 32;
8141                 goto fail;
8142         }
8143
8144         /* depend on rateset, gmode */
8145         wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8146         if (!wlc->cmi) {
8147                 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8148                           "\n", unit, __func__);
8149                 err = 33;
8150                 goto fail;
8151         }
8152
8153         /* init default when all parameters are ready, i.e. ->rateset */
8154         brcms_c_bss_default_init(wlc);
8155
8156         /*
8157          * Complete the wlc default state initializations..
8158          */
8159
8160         wlc->bsscfg->wlc = wlc;
8161
8162         wlc->mimoft = FT_HT;
8163         wlc->mimo_40txbw = AUTO;
8164         wlc->ofdm_40txbw = AUTO;
8165         wlc->cck_40txbw = AUTO;
8166         brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8167
8168         /* Set default values of SGI */
8169         if (BRCMS_SGI_CAP_PHY(wlc)) {
8170                 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8171                                                BRCMS_N_SGI_40));
8172         } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8173                 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8174                                                BRCMS_N_SGI_40));
8175         } else {
8176                 brcms_c_ht_update_sgi_rx(wlc, 0);
8177         }
8178
8179         brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8180
8181         if (perr)
8182                 *perr = 0;
8183
8184         return wlc;
8185
8186  fail:
8187         wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8188                   unit, __func__, err);
8189         if (wlc)
8190                 brcms_c_detach(wlc);
8191
8192         if (perr)
8193                 *perr = err;
8194         return NULL;
8195 }