2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
18 #include <linux/string.h>
20 #include <linux/etherdevice.h>
21 #include <linux/crc8.h>
24 #include <chipcommon.h>
25 #include <brcmu_utils.h>
33 * SROM CRC8 polynomial value:
35 * x^8 + x^7 +x^6 + x^4 + x^2 + 1
37 #define SROM_CRC8_POLY 0xAB
39 /* Maximum srom: 6 Kilobits == 768 bytes */
43 #define PCI_F0DEVID 48
49 #define SROM_WL1LHMAXP 29
51 #define SROM_WL1LPAB0 30
52 #define SROM_WL1LPAB1 31
53 #define SROM_WL1LPAB2 32
55 #define SROM_WL1HPAB0 33
56 #define SROM_WL1HPAB1 34
57 #define SROM_WL1HPAB2 35
59 #define SROM_MACHI_IL0 36
60 #define SROM_MACMID_IL0 37
61 #define SROM_MACLO_IL0 38
62 #define SROM_MACHI_ET1 42
63 #define SROM_MACMID_ET1 43
64 #define SROM_MACLO_ET1 44
65 #define SROM3_MACHI 37
66 #define SROM3_MACMID 38
67 #define SROM3_MACLO 39
69 #define SROM_BXARSSI2G 40
70 #define SROM_BXARSSI5G 41
72 #define SROM_TRI52G 42
73 #define SROM_TRI5GHL 43
75 #define SROM_RXPO52G 45
77 #define SROM_AABREV 46
78 /* Fields in AABREV */
79 #define SROM_BR_MASK 0x00ff
80 #define SROM_CC_MASK 0x0f00
81 #define SROM_CC_SHIFT 8
82 #define SROM_AA0_MASK 0x3000
83 #define SROM_AA0_SHIFT 12
84 #define SROM_AA1_MASK 0xc000
85 #define SROM_AA1_SHIFT 14
87 #define SROM_WL0PAB0 47
88 #define SROM_WL0PAB1 48
89 #define SROM_WL0PAB2 49
91 #define SROM_LEDBH10 50
92 #define SROM_LEDBH32 51
94 #define SROM_WL10MAXP 52
96 #define SROM_WL1PAB0 53
97 #define SROM_WL1PAB1 54
98 #define SROM_WL1PAB2 55
104 #define SROM3_BFL2 61
108 #define SROM_CCODE 59
112 #define SROM3_LEDDC 62
114 #define SROM_CRCREV 63
116 /* SROM Rev 4: Reallocate the software part of the srom to accommodate
117 * MIMO features. It assumes up to two PCIE functions and 440 bytes
118 * of usable srom i.e. the usable storage in chips with OTP that
119 * implements hardware redundancy.
122 #define SROM4_WORDS 220
124 #define SROM4_SIGN 32
125 #define SROM4_SIGNATURE 0x5372
127 #define SROM4_BREV 33
129 #define SROM4_BFL0 34
130 #define SROM4_BFL1 35
131 #define SROM4_BFL2 36
132 #define SROM4_BFL3 37
133 #define SROM5_BFL0 37
134 #define SROM5_BFL1 38
135 #define SROM5_BFL2 39
136 #define SROM5_BFL3 40
138 #define SROM4_MACHI 38
139 #define SROM4_MACMID 39
140 #define SROM4_MACLO 40
141 #define SROM5_MACHI 41
142 #define SROM5_MACMID 42
143 #define SROM5_MACLO 43
145 #define SROM4_CCODE 41
146 #define SROM4_REGREV 42
147 #define SROM5_CCODE 34
148 #define SROM5_REGREV 35
150 #define SROM4_LEDBH10 43
151 #define SROM4_LEDBH32 44
152 #define SROM5_LEDBH10 59
153 #define SROM5_LEDBH32 60
155 #define SROM4_LEDDC 45
156 #define SROM5_LEDDC 45
160 #define SROM4_AG10 47
161 #define SROM4_AG32 48
163 #define SROM4_TXPID2G 49
164 #define SROM4_TXPID5G 51
165 #define SROM4_TXPID5GL 53
166 #define SROM4_TXPID5GH 55
168 #define SROM4_TXRXC 61
169 #define SROM4_TXCHAIN_MASK 0x000f
170 #define SROM4_TXCHAIN_SHIFT 0
171 #define SROM4_RXCHAIN_MASK 0x00f0
172 #define SROM4_RXCHAIN_SHIFT 4
173 #define SROM4_SWITCH_MASK 0xff00
174 #define SROM4_SWITCH_SHIFT 8
176 /* Per-path fields */
177 #define MAX_PATH_SROM 4
178 #define SROM4_PATH0 64
179 #define SROM4_PATH1 87
180 #define SROM4_PATH2 110
181 #define SROM4_PATH3 133
183 #define SROM4_2G_ITT_MAXP 0
184 #define SROM4_2G_PA 1
185 #define SROM4_5G_ITT_MAXP 5
186 #define SROM4_5GLH_MAXP 6
187 #define SROM4_5G_PA 7
188 #define SROM4_5GL_PA 11
189 #define SROM4_5GH_PA 15
191 /* All the miriad power offsets */
192 #define SROM4_2G_CCKPO 156
193 #define SROM4_2G_OFDMPO 157
194 #define SROM4_5G_OFDMPO 159
195 #define SROM4_5GL_OFDMPO 161
196 #define SROM4_5GH_OFDMPO 163
197 #define SROM4_2G_MCSPO 165
198 #define SROM4_5G_MCSPO 173
199 #define SROM4_5GL_MCSPO 181
200 #define SROM4_5GH_MCSPO 189
201 #define SROM4_CDDPO 197
202 #define SROM4_STBCPO 198
203 #define SROM4_BW40PO 199
204 #define SROM4_BWDUPPO 200
206 #define SROM4_CRCREV 219
208 /* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
209 * This is acombined srom for both MIMO and SISO boards, usable in
210 * the .130 4Kilobit OTP with hardware redundancy.
212 #define SROM8_BREV 65
214 #define SROM8_BFL0 66
215 #define SROM8_BFL1 67
216 #define SROM8_BFL2 68
217 #define SROM8_BFL3 69
219 #define SROM8_MACHI 70
220 #define SROM8_MACMID 71
221 #define SROM8_MACLO 72
223 #define SROM8_CCODE 73
224 #define SROM8_REGREV 74
226 #define SROM8_LEDBH10 75
227 #define SROM8_LEDBH32 76
229 #define SROM8_LEDDC 77
233 #define SROM8_AG10 79
234 #define SROM8_AG32 80
236 #define SROM8_TXRXC 81
238 #define SROM8_BXARSSI2G 82
239 #define SROM8_BXARSSI5G 83
240 #define SROM8_TRI52G 84
241 #define SROM8_TRI5GHL 85
242 #define SROM8_RXPO52G 86
244 #define SROM8_FEM2G 87
245 #define SROM8_FEM5G 88
246 #define SROM8_FEM_ANTSWLUT_MASK 0xf800
247 #define SROM8_FEM_ANTSWLUT_SHIFT 11
248 #define SROM8_FEM_TR_ISO_MASK 0x0700
249 #define SROM8_FEM_TR_ISO_SHIFT 8
250 #define SROM8_FEM_PDET_RANGE_MASK 0x00f8
251 #define SROM8_FEM_PDET_RANGE_SHIFT 3
252 #define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
253 #define SROM8_FEM_EXTPA_GAIN_SHIFT 1
254 #define SROM8_FEM_TSSIPOS_MASK 0x0001
255 #define SROM8_FEM_TSSIPOS_SHIFT 0
257 #define SROM8_THERMAL 89
259 /* Temp sense related entries */
260 #define SROM8_MPWR_RAWTS 90
261 #define SROM8_TS_SLP_OPT_CORRX 91
262 /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
263 * IQSWP: IQ CAL swap disable */
264 #define SROM8_FOC_HWIQ_IQSWP 92
266 /* Temperature delta for PHY calibration */
267 #define SROM8_PHYCAL_TEMPDELTA 93
269 /* Per-path offsets & fields */
270 #define SROM8_PATH0 96
271 #define SROM8_PATH1 112
272 #define SROM8_PATH2 128
273 #define SROM8_PATH3 144
275 #define SROM8_2G_ITT_MAXP 0
276 #define SROM8_2G_PA 1
277 #define SROM8_5G_ITT_MAXP 4
278 #define SROM8_5GLH_MAXP 5
279 #define SROM8_5G_PA 6
280 #define SROM8_5GL_PA 9
281 #define SROM8_5GH_PA 12
283 /* All the miriad power offsets */
284 #define SROM8_2G_CCKPO 160
286 #define SROM8_2G_OFDMPO 161
287 #define SROM8_5G_OFDMPO 163
288 #define SROM8_5GL_OFDMPO 165
289 #define SROM8_5GH_OFDMPO 167
291 #define SROM8_2G_MCSPO 169
292 #define SROM8_5G_MCSPO 177
293 #define SROM8_5GL_MCSPO 185
294 #define SROM8_5GH_MCSPO 193
296 #define SROM8_CDDPO 201
297 #define SROM8_STBCPO 202
298 #define SROM8_BW40PO 203
299 #define SROM8_BWDUPPO 204
301 /* SISO PA parameters are in the path0 spaces */
302 #define SROM8_SISO 96
304 /* Legacy names for SISO PA paramters */
305 #define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
306 #define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
307 #define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
308 #define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
309 #define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
310 #define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
311 #define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
312 #define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
313 #define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
314 #define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
315 #define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
316 #define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
317 #define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
318 #define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
319 #define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
322 #define SROM9_2GPO_CCKBW20 160
323 #define SROM9_2GPO_CCKBW20UL 161
324 #define SROM9_2GPO_LOFDMBW20 162
325 #define SROM9_2GPO_LOFDMBW20UL 164
327 #define SROM9_5GLPO_LOFDMBW20 166
328 #define SROM9_5GLPO_LOFDMBW20UL 168
329 #define SROM9_5GMPO_LOFDMBW20 170
330 #define SROM9_5GMPO_LOFDMBW20UL 172
331 #define SROM9_5GHPO_LOFDMBW20 174
332 #define SROM9_5GHPO_LOFDMBW20UL 176
334 #define SROM9_2GPO_MCSBW20 178
335 #define SROM9_2GPO_MCSBW20UL 180
336 #define SROM9_2GPO_MCSBW40 182
338 #define SROM9_5GLPO_MCSBW20 184
339 #define SROM9_5GLPO_MCSBW20UL 186
340 #define SROM9_5GLPO_MCSBW40 188
341 #define SROM9_5GMPO_MCSBW20 190
342 #define SROM9_5GMPO_MCSBW20UL 192
343 #define SROM9_5GMPO_MCSBW40 194
344 #define SROM9_5GHPO_MCSBW20 196
345 #define SROM9_5GHPO_MCSBW20UL 198
346 #define SROM9_5GHPO_MCSBW40 200
348 #define SROM9_PO_MCS32 202
349 #define SROM9_PO_LOFDM40DUP 203
351 /* SROM flags (see sromvar_t) */
353 /* value continues as described by the next entry */
355 #define SRFL_NOFFS 2 /* value bits can't be all one's */
356 #define SRFL_PRHEX 4 /* value is in hexdecimal format */
357 #define SRFL_PRSIGN 8 /* value is in signed decimal format */
358 #define SRFL_CCODE 0x10 /* value is in country code format */
359 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
360 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
361 /* do not generate a nvram param, entry is for mfgc */
362 #define SRFL_NOVAR 0x80
364 /* Max. nvram variable table size */
365 #define MAXSZ_NVRAM_VARS 4096
368 * indicates type of value.
370 enum brcms_srom_var_type {
377 * storage type for srom variable.
379 * var_list: for linked list operations.
380 * varid: identifier of the variable.
381 * var_type: type of variable.
382 * buf: variable value when var_type == BRCMS_SROM_STRING.
383 * uval: unsigned variable value when var_type == BRCMS_SROM_UNUMBER.
384 * sval: signed variable value when var_type == BRCMS_SROM_SNUMBER.
386 struct brcms_srom_list_head {
387 struct list_head var_list;
388 enum brcms_srom_id varid;
389 enum brcms_srom_var_type var_type;
397 struct brcms_sromvar {
398 enum brcms_srom_id varid;
405 struct brcms_varbuf {
406 char *base; /* pointer to buffer base */
407 char *buf; /* pointer to current position */
408 unsigned int size; /* current (residual) size in bytes */
413 * - Ethernet address spans across 3 consecutive words
416 * - Add multiple entries next to each other if a value spans across multiple
417 * words (even multiple fields in the same word) with each entry except the
418 * last having it's SRFL_MORE bit set.
419 * - Ethernet address entry does not follow above rule and must not have
420 * SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
421 * - The last entry's name field must be NULL to indicate the end of the table.
422 * Other entries must have non-NULL name.
424 static const struct brcms_sromvar pci_sromvars[] = {
425 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
427 {BRCMS_SROM_BOARDREV, 0x0000000e, SRFL_PRHEX, SROM_AABREV,
429 {BRCMS_SROM_BOARDREV, 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
430 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
431 {BRCMS_SROM_BOARDFLAGS, 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
432 {BRCMS_SROM_BOARDFLAGS, 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
434 {BRCMS_SROM_CONT, 0, 0, SROM_BFL2, 0xffff},
435 {BRCMS_SROM_BOARDFLAGS, 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL,
437 {BRCMS_SROM_CONT, 0, 0, SROM3_BFL2, 0xffff},
438 {BRCMS_SROM_BOARDFLAGS, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0,
440 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL1, 0xffff},
441 {BRCMS_SROM_BOARDFLAGS, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0,
443 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL1, 0xffff},
444 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
446 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
447 {BRCMS_SROM_BOARDFLAGS2, 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2,
449 {BRCMS_SROM_CONT, 0, 0, SROM4_BFL3, 0xffff},
450 {BRCMS_SROM_BOARDFLAGS2, 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2,
452 {BRCMS_SROM_CONT, 0, 0, SROM5_BFL3, 0xffff},
453 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
455 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
456 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
457 {BRCMS_SROM_BOARDNUM, 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
458 {BRCMS_SROM_BOARDNUM, 0x00000008, 0, SROM3_MACLO, 0xffff},
459 {BRCMS_SROM_BOARDNUM, 0x00000010, 0, SROM4_MACLO, 0xffff},
460 {BRCMS_SROM_BOARDNUM, 0x000000e0, 0, SROM5_MACLO, 0xffff},
461 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
462 {BRCMS_SROM_CC, 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
463 {BRCMS_SROM_REGREV, 0x00000008, 0, SROM_OPO, 0xff00},
464 {BRCMS_SROM_REGREV, 0x00000010, 0, SROM4_REGREV, 0x00ff},
465 {BRCMS_SROM_REGREV, 0x000000e0, 0, SROM5_REGREV, 0x00ff},
466 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
467 {BRCMS_SROM_LEDBH0, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
468 {BRCMS_SROM_LEDBH1, 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
469 {BRCMS_SROM_LEDBH2, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
470 {BRCMS_SROM_LEDBH3, 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
471 {BRCMS_SROM_LEDBH0, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
472 {BRCMS_SROM_LEDBH1, 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
473 {BRCMS_SROM_LEDBH2, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
474 {BRCMS_SROM_LEDBH3, 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
475 {BRCMS_SROM_LEDBH0, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
476 {BRCMS_SROM_LEDBH1, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
477 {BRCMS_SROM_LEDBH2, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
478 {BRCMS_SROM_LEDBH3, 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
479 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
480 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
481 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
482 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
483 {BRCMS_SROM_PA0B0, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
484 {BRCMS_SROM_PA0B1, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
485 {BRCMS_SROM_PA0B2, 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
486 {BRCMS_SROM_PA0ITSSIT, 0x0000000e, 0, SROM_ITT, 0x00ff},
487 {BRCMS_SROM_PA0MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
488 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
489 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
490 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
491 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
492 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
493 {BRCMS_SROM_OPO, 0x0000000c, 0, SROM_OPO, 0x00ff},
494 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
495 {BRCMS_SROM_AA2G, 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
496 {BRCMS_SROM_AA2G, 0x000000f0, 0, SROM4_AA, 0x00ff},
497 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
498 {BRCMS_SROM_AA5G, 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
499 {BRCMS_SROM_AA5G, 0x000000f0, 0, SROM4_AA, 0xff00},
500 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
501 {BRCMS_SROM_AG0, 0x0000000e, 0, SROM_AG10, 0x00ff},
502 {BRCMS_SROM_AG1, 0x0000000e, 0, SROM_AG10, 0xff00},
503 {BRCMS_SROM_AG0, 0x000000f0, 0, SROM4_AG10, 0x00ff},
504 {BRCMS_SROM_AG1, 0x000000f0, 0, SROM4_AG10, 0xff00},
505 {BRCMS_SROM_AG2, 0x000000f0, 0, SROM4_AG32, 0x00ff},
506 {BRCMS_SROM_AG3, 0x000000f0, 0, SROM4_AG32, 0xff00},
507 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
508 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
509 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
510 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
511 {BRCMS_SROM_PA1B0, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
512 {BRCMS_SROM_PA1B1, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
513 {BRCMS_SROM_PA1B2, 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
514 {BRCMS_SROM_PA1LOB0, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
515 {BRCMS_SROM_PA1LOB1, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
516 {BRCMS_SROM_PA1LOB2, 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
517 {BRCMS_SROM_PA1HIB0, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
518 {BRCMS_SROM_PA1HIB1, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
519 {BRCMS_SROM_PA1HIB2, 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
520 {BRCMS_SROM_PA1ITSSIT, 0x0000000e, 0, SROM_ITT, 0xff00},
521 {BRCMS_SROM_PA1MAXPWR, 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
522 {BRCMS_SROM_PA1LOMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
523 {BRCMS_SROM_PA1HIMAXPWR, 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
524 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
525 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
526 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
527 {BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
528 {BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
529 {BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
530 {BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
531 {BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
532 {BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
533 {BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
534 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
535 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
536 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
537 {BRCMS_SROM_BXA2G, 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
538 {BRCMS_SROM_RSSISAV2G, 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
539 {BRCMS_SROM_RSSISMC2G, 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
540 {BRCMS_SROM_RSSISMF2G, 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
541 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
542 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
543 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
544 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
545 {BRCMS_SROM_BXA5G, 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
546 {BRCMS_SROM_RSSISAV5G, 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
547 {BRCMS_SROM_RSSISMC5G, 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
548 {BRCMS_SROM_RSSISMF5G, 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
549 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
550 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
551 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
552 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
553 {BRCMS_SROM_TRI2G, 0x00000008, 0, SROM_TRI52G, 0x00ff},
554 {BRCMS_SROM_TRI5G, 0x00000008, 0, SROM_TRI52G, 0xff00},
555 {BRCMS_SROM_TRI5GL, 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
556 {BRCMS_SROM_TRI5GH, 0x00000008, 0, SROM_TRI5GHL, 0xff00},
557 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
558 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
559 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
560 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
561 {BRCMS_SROM_RXPO2G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
562 {BRCMS_SROM_RXPO5G, 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
563 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
564 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
565 {BRCMS_SROM_TXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
567 {BRCMS_SROM_RXCHAIN, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
569 {BRCMS_SROM_ANTSWITCH, 0x000000f0, SRFL_NOFFS, SROM4_TXRXC,
571 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
573 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
575 {BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
577 {BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
578 SROM8_FEM_TSSIPOS_MASK},
579 {BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
580 SROM8_FEM_EXTPA_GAIN_MASK},
581 {BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
582 SROM8_FEM_PDET_RANGE_MASK},
583 {BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
584 {BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
585 SROM8_FEM_ANTSWLUT_MASK},
586 {BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
587 SROM8_FEM_TSSIPOS_MASK},
588 {BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
589 SROM8_FEM_EXTPA_GAIN_MASK},
590 {BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
591 SROM8_FEM_PDET_RANGE_MASK},
592 {BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
593 {BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
594 SROM8_FEM_ANTSWLUT_MASK},
595 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
596 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
597 {BRCMS_SROM_TXPID2GA0, 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
598 {BRCMS_SROM_TXPID2GA1, 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
599 {BRCMS_SROM_TXPID2GA2, 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
600 {BRCMS_SROM_TXPID2GA3, 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
601 {BRCMS_SROM_TXPID5GA0, 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
602 {BRCMS_SROM_TXPID5GA1, 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
603 {BRCMS_SROM_TXPID5GA2, 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
604 {BRCMS_SROM_TXPID5GA3, 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
605 {BRCMS_SROM_TXPID5GLA0, 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
606 {BRCMS_SROM_TXPID5GLA1, 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
607 {BRCMS_SROM_TXPID5GLA2, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
608 {BRCMS_SROM_TXPID5GLA3, 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
609 {BRCMS_SROM_TXPID5GHA0, 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
610 {BRCMS_SROM_TXPID5GHA1, 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
611 {BRCMS_SROM_TXPID5GHA2, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
612 {BRCMS_SROM_TXPID5GHA3, 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
614 {BRCMS_SROM_CCODE, 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
615 {BRCMS_SROM_CCODE, 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
616 {BRCMS_SROM_CCODE, 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
617 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
618 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
619 {BRCMS_SROM_MACADDR, 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
620 {BRCMS_SROM_MACADDR, 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
621 {BRCMS_SROM_MACADDR, 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
622 {BRCMS_SROM_IL0MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0,
624 {BRCMS_SROM_ET1MACADDR, 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1,
626 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
628 {BRCMS_SROM_LEDDC, 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC,
630 {BRCMS_SROM_LEDDC, 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC,
632 {BRCMS_SROM_LEDDC, 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC,
634 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
636 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
638 {BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
639 SROM8_TS_SLP_OPT_CORRX, 0x00ff},
640 {BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
642 {BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
643 SROM8_TS_SLP_OPT_CORRX, 0x0300},
644 {BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
645 SROM8_FOC_HWIQ_IQSWP, 0x000f},
646 {BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
648 {BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
650 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
653 {BRCMS_SROM_CCK2GPO, 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
654 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
655 {BRCMS_SROM_OFDM2GPO, 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
656 {BRCMS_SROM_CONT, 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
657 {BRCMS_SROM_OFDM5GPO, 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
658 {BRCMS_SROM_CONT, 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
659 {BRCMS_SROM_OFDM5GLPO, 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
660 {BRCMS_SROM_CONT, 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
661 {BRCMS_SROM_OFDM5GHPO, 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
662 {BRCMS_SROM_CONT, 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
663 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
664 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
665 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
666 {BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
667 {BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
668 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
669 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
670 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
671 {BRCMS_SROM_MCS2GPO0, 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
672 {BRCMS_SROM_MCS2GPO1, 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
673 {BRCMS_SROM_MCS2GPO2, 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
674 {BRCMS_SROM_MCS2GPO3, 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
675 {BRCMS_SROM_MCS2GPO4, 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
676 {BRCMS_SROM_MCS2GPO5, 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
677 {BRCMS_SROM_MCS2GPO6, 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
678 {BRCMS_SROM_MCS2GPO7, 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
679 {BRCMS_SROM_MCS5GPO0, 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
680 {BRCMS_SROM_MCS5GPO1, 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
681 {BRCMS_SROM_MCS5GPO2, 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
682 {BRCMS_SROM_MCS5GPO3, 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
683 {BRCMS_SROM_MCS5GPO4, 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
684 {BRCMS_SROM_MCS5GPO5, 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
685 {BRCMS_SROM_MCS5GPO6, 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
686 {BRCMS_SROM_MCS5GPO7, 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
687 {BRCMS_SROM_MCS5GLPO0, 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
688 {BRCMS_SROM_MCS5GLPO1, 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
689 {BRCMS_SROM_MCS5GLPO2, 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
690 {BRCMS_SROM_MCS5GLPO3, 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
691 {BRCMS_SROM_MCS5GLPO4, 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
692 {BRCMS_SROM_MCS5GLPO5, 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
693 {BRCMS_SROM_MCS5GLPO6, 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
694 {BRCMS_SROM_MCS5GLPO7, 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
695 {BRCMS_SROM_MCS5GHPO0, 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
696 {BRCMS_SROM_MCS5GHPO1, 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
697 {BRCMS_SROM_MCS5GHPO2, 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
698 {BRCMS_SROM_MCS5GHPO3, 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
699 {BRCMS_SROM_MCS5GHPO4, 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
700 {BRCMS_SROM_MCS5GHPO5, 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
701 {BRCMS_SROM_MCS5GHPO6, 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
702 {BRCMS_SROM_MCS5GHPO7, 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
703 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
704 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
705 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
706 {BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
707 {BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
708 {BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
709 {BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
710 {BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
711 {BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
712 {BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
713 {BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
714 {BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
715 {BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
716 {BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
717 {BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
718 {BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
719 {BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
720 {BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
721 {BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
722 {BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
723 {BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
724 {BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
725 {BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
726 {BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
727 {BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
728 {BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
729 {BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
730 {BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
731 {BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
732 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
733 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
734 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
735 {BRCMS_SROM_CDDPO, 0x000000f0, 0, SROM4_CDDPO, 0xffff},
736 {BRCMS_SROM_STBCPO, 0x000000f0, 0, SROM4_STBCPO, 0xffff},
737 {BRCMS_SROM_BW40PO, 0x000000f0, 0, SROM4_BW40PO, 0xffff},
738 {BRCMS_SROM_BWDUPPO, 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
739 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
740 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
741 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
742 {BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
744 /* power per rate from sromrev 9 */
745 {BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
746 {BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
747 {BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
748 SROM9_2GPO_LOFDMBW20, 0xffff},
749 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
750 {BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
751 SROM9_2GPO_LOFDMBW20UL, 0xffff},
752 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
753 {BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
754 SROM9_5GLPO_LOFDMBW20, 0xffff},
755 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
756 {BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
757 SROM9_5GLPO_LOFDMBW20UL, 0xffff},
758 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
759 {BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
760 SROM9_5GMPO_LOFDMBW20, 0xffff},
761 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
762 {BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
763 SROM9_5GMPO_LOFDMBW20UL, 0xffff},
764 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
765 {BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
766 SROM9_5GHPO_LOFDMBW20, 0xffff},
767 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
768 {BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
769 SROM9_5GHPO_LOFDMBW20UL, 0xffff},
770 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
771 {BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
773 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
774 {BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
776 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
777 {BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
779 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
780 {BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
782 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
783 {BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
784 SROM9_5GLPO_MCSBW20UL, 0xffff},
785 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
786 {BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
788 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
789 {BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
791 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
792 {BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
793 SROM9_5GMPO_MCSBW20UL, 0xffff},
794 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
795 {BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
797 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
798 {BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
800 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
801 {BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
802 SROM9_5GHPO_MCSBW20UL, 0xffff},
803 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
804 {BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
806 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
807 {BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
808 {BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
810 {BRCMS_SROM_NULL, 0, 0, 0, 0}
813 static const struct brcms_sromvar perpath_pci_sromvars[] = {
814 {BRCMS_SROM_MAXP2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
815 {BRCMS_SROM_ITT2GA0, 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
816 {BRCMS_SROM_ITT5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
817 {BRCMS_SROM_PA2GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
818 {BRCMS_SROM_PA2GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
819 {BRCMS_SROM_PA2GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
820 {BRCMS_SROM_PA2GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
821 {BRCMS_SROM_MAXP5GA0, 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
822 {BRCMS_SROM_MAXP5GHA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
823 {BRCMS_SROM_MAXP5GLA0, 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
824 {BRCMS_SROM_PA5GW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
825 {BRCMS_SROM_PA5GW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
826 {BRCMS_SROM_PA5GW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
827 {BRCMS_SROM_PA5GW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
828 {BRCMS_SROM_PA5GLW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
829 {BRCMS_SROM_PA5GLW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1,
831 {BRCMS_SROM_PA5GLW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2,
833 {BRCMS_SROM_PA5GLW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3,
835 {BRCMS_SROM_PA5GHW0A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
836 {BRCMS_SROM_PA5GHW1A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1,
838 {BRCMS_SROM_PA5GHW2A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2,
840 {BRCMS_SROM_PA5GHW3A0, 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3,
842 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
843 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
844 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
845 {BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
846 {BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
847 {BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
848 {BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
849 {BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
850 {BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
851 {BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
852 {BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
853 {BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
854 {BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
855 {BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
857 {BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
859 {BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
860 {BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
862 {BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
864 {BRCMS_SROM_NULL, 0, 0, 0, 0}
867 /* crc table has the same contents for every device instance, so it can be
868 * shared between devices. */
869 static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
872 srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
875 return (u16 __iomem *)(curmap + PCI_BAR0_SPROM_OFFSET);
876 if (sih->cccaps & CC_CAP_SROM)
877 return (u16 __iomem *)
878 (curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP);
883 /* Parse SROM and create name=value pairs. 'srom' points to
884 * the SROM word array. 'off' specifies the offset of the
885 * first word 'srom' points to, which should be either 0 or
886 * SROM3_SWRG_OFF (full SROM or software region).
889 static uint mask_shift(u16 mask)
892 for (i = 0; i < (sizeof(mask) << 3); i++) {
899 static uint mask_width(u16 mask)
902 for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
904 return (uint) (i - mask_shift(mask) + 1);
909 static inline void ltoh16_buf(u16 *buf, unsigned int size)
913 *(buf + size) = le16_to_cpu(*(__le16 *)(buf + size));
916 static inline void htol16_buf(u16 *buf, unsigned int size)
920 *(__le16 *)(buf + size) = cpu_to_le16(*(buf + size));
924 * convert binary srom data into linked list of srom variable items.
927 _initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
929 struct brcms_srom_list_head *entry;
930 enum brcms_srom_id id;
933 const struct brcms_sromvar *srv;
936 u32 sr = (1 << sromrev);
938 /* first store the srom revision */
939 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
940 entry->varid = BRCMS_SROM_REV;
941 entry->var_type = BRCMS_SROM_UNUMBER;
942 entry->uval = sromrev;
943 list_add(&entry->var_list, var_list);
945 for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
946 enum brcms_srom_var_type type;
950 if ((srv->revmask & sr) == 0)
956 /* This entry is for mfgc only. Don't generate param for it, */
957 if (flags & SRFL_NOVAR)
960 if (flags & SRFL_ETHADDR) {
962 * stored in string format XX:XX:XX:XX:XX:XX (17 chars)
964 ea[0] = (srom[srv->off] >> 8) & 0xff;
965 ea[1] = srom[srv->off] & 0xff;
966 ea[2] = (srom[srv->off + 1] >> 8) & 0xff;
967 ea[3] = srom[srv->off + 1] & 0xff;
968 ea[4] = (srom[srv->off + 2] >> 8) & 0xff;
969 ea[5] = srom[srv->off + 2] & 0xff;
970 /* 17 characters + string terminator - union size */
971 extra_space = 18 - sizeof(s32);
972 type = BRCMS_SROM_STRING;
975 val = (w & srv->mask) >> mask_shift(srv->mask);
976 width = mask_width(srv->mask);
978 while (srv->flags & SRFL_MORE) {
985 ((w & srv->mask) >> mask_shift(srv->
988 width += mask_width(srv->mask);
991 if ((flags & SRFL_NOFFS)
992 && ((int)val == (1 << width) - 1))
995 if (flags & SRFL_CCODE) {
996 type = BRCMS_SROM_STRING;
997 } else if (flags & SRFL_LEDDC) {
998 /* LED Powersave duty cycle has to be scaled:
999 *(oncount >> 24) (offcount >> 8)
1001 u32 w32 = /* oncount */
1002 (((val >> 8) & 0xff) << 24) |
1004 (((val & 0xff)) << 8);
1005 type = BRCMS_SROM_UNUMBER;
1007 } else if ((flags & SRFL_PRSIGN)
1008 && (val & (1 << (width - 1)))) {
1009 type = BRCMS_SROM_SNUMBER;
1012 type = BRCMS_SROM_UNUMBER;
1015 entry = kzalloc(sizeof(struct brcms_srom_list_head) +
1016 extra_space, GFP_KERNEL);
1018 entry->var_type = type;
1019 if (flags & SRFL_ETHADDR) {
1020 snprintf(entry->buf, 18, "%pM", ea);
1021 } else if (flags & SRFL_CCODE) {
1023 entry->buf[0] = '\0';
1025 snprintf(entry->buf, 3, "%c%c",
1026 (val >> 8), (val & 0xff));
1031 list_add(&entry->var_list, var_list);
1035 /* Do per-path variables */
1040 psz = SROM8_PATH1 - SROM8_PATH0;
1043 psz = SROM4_PATH1 - SROM4_PATH0;
1046 for (p = 0; p < MAX_PATH_SROM; p++) {
1047 for (srv = perpath_pci_sromvars;
1048 srv->varid != BRCMS_SROM_NULL; srv++) {
1049 if ((srv->revmask & sr) == 0)
1052 if (srv->flags & SRFL_NOVAR)
1055 w = srom[pb + srv->off];
1056 val = (w & srv->mask) >> mask_shift(srv->mask);
1057 width = mask_width(srv->mask);
1059 /* Cheating: no per-path var is more than
1061 if ((srv->flags & SRFL_NOFFS)
1062 && ((int)val == (1 << width) - 1))
1066 kzalloc(sizeof(struct brcms_srom_list_head),
1068 entry->varid = srv->varid+p;
1069 entry->var_type = BRCMS_SROM_UNUMBER;
1071 list_add(&entry->var_list, var_list);
1079 * Read in and validate sprom.
1080 * Return 0 on success, nonzero on error.
1083 sprom_read_pci(struct si_pub *sih, u16 __iomem *sprom, uint wordoff,
1084 u16 *buf, uint nwords, bool check_crc)
1089 /* read the sprom */
1090 for (i = 0; i < nwords; i++)
1091 buf[i] = R_REG(&sprom[wordoff + i]);
1095 if (buf[0] == 0xffff)
1097 * The hardware thinks that an srom that starts with
1098 * 0xffff is blank, regardless of the rest of the
1099 * content, so declare it bad.
1103 /* fixup the endianness so crc8 will pass */
1104 htol16_buf(buf, nwords * 2);
1105 if (crc8(brcms_srom_crc8_table, (u8 *) buf, nwords * 2,
1107 CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1108 /* DBG only pci always read srom4 first, then srom8/9 */
1111 /* now correct the endianness of the byte array */
1112 ltoh16_buf(buf, nwords * 2);
1117 static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
1120 uint sz = OTP_SZ_MAX / 2; /* size in words */
1123 otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
1127 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
1129 memcpy(buf, otp, bufsz);
1134 if (buf[0] == 0xffff)
1135 /* The hardware thinks that an srom that starts with 0xffff
1136 * is blank, regardless of the rest of the content, so declare
1141 /* fixup the endianness so crc8 will pass */
1142 htol16_buf(buf, bufsz);
1143 if (crc8(brcms_srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2,
1144 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
1147 /* now correct the endianness of the byte array */
1148 ltoh16_buf(buf, bufsz);
1154 * Initialize nonvolatile variable table from sprom.
1155 * Return 0 on success, nonzero on error.
1157 static int initvars_srom_pci(struct si_pub *sih, void __iomem *curmap)
1160 u16 __iomem *sromwindow;
1166 * Apply CRC over SROM content regardless SROM is present or not.
1168 srom = kmalloc(SROM_MAX, GFP_ATOMIC);
1172 sromwindow = srom_window_address(sih, curmap);
1174 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
1175 if (ai_is_sprom_available(sih)) {
1176 err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
1179 if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
1180 (((sih->buscoretype == PCIE_CORE_ID)
1181 && (sih->buscorerev >= 6))
1182 || ((sih->buscoretype == PCI_CORE_ID)
1183 && (sih->buscorerev >= 0xe)))) {
1184 /* sromrev >= 4, read more */
1185 err = sprom_read_pci(sih, sromwindow, 0, srom,
1187 sromrev = srom[SROM4_CRCREV] & 0xff;
1188 } else if (err == 0) {
1189 /* srom is good and is rev < 4 */
1190 /* top word of sprom contains version and crc8 */
1191 sromrev = srom[SROM_CRCREV] & 0xff;
1192 /* bcm4401 sroms misprogrammed */
1193 if (sromrev == 0x10)
1197 /* Use OTP if SPROM not available */
1198 err = otp_read_pci(sih, srom, SROM_MAX);
1200 /* OTP only contain SROM rev8/rev9 for now */
1201 sromrev = srom[SROM4_CRCREV] & 0xff;
1205 struct si_info *sii = (struct si_info *)sih;
1207 /* Bitmask for the sromrev */
1211 * srom version check: Current valid versions: 1, 2, 3, 4, 5, 8,
1214 if ((sr & 0x33e) == 0) {
1219 INIT_LIST_HEAD(&sii->var_list);
1221 /* parse SROM into name=value pairs. */
1222 _initvars_srom_pci(sromrev, srom, &sii->var_list);
1230 void srom_free_vars(struct si_pub *sih)
1232 struct si_info *sii;
1233 struct brcms_srom_list_head *entry, *next;
1235 sii = (struct si_info *)sih;
1236 list_for_each_entry_safe(entry, next, &sii->var_list, var_list) {
1237 list_del(&entry->var_list);
1242 * Initialize local vars from the right source for this platform.
1243 * Return 0 on success, nonzero on error.
1245 int srom_var_init(struct si_pub *sih, void __iomem *curmap)
1252 return initvars_srom_pci(sih, curmap);
1258 * Search the name=value vars for a specific one and return its value.
1259 * Returns NULL if not found.
1261 char *getvar(struct si_pub *sih, enum brcms_srom_id id)
1263 struct si_info *sii;
1264 struct brcms_srom_list_head *entry;
1266 sii = (struct si_info *)sih;
1268 list_for_each_entry(entry, &sii->var_list, var_list)
1269 if (entry->varid == id)
1270 return &entry->buf[0];
1277 * Search the vars for a specific one and return its value as
1278 * an integer. Returns 0 if not found.-
1280 int getintvar(struct si_pub *sih, enum brcms_srom_id id)
1282 struct si_info *sii;
1283 struct brcms_srom_list_head *entry;
1286 sii = (struct si_info *)sih;
1288 list_for_each_entry(entry, &sii->var_list, var_list)
1289 if (entry->varid == id) {
1290 if (entry->var_type == BRCMS_SROM_SNUMBER ||
1291 entry->var_type == BRCMS_SROM_UNUMBER)
1292 return (int)entry->sval;
1293 else if (!kstrtoul(&entry->buf[0], 0, &res))