drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47 BRCMF_FW_NVRAM_DEF(43602, "brcmfmac43602-pcie.bin", "brcmfmac43602-pcie.txt");
  48 BRCMF_FW_NVRAM_DEF(4350, "brcmfmac4350-pcie.bin", "brcmfmac4350-pcie.txt");
  49 BRCMF_FW_NVRAM_DEF(4350C, "brcmfmac4350c2-pcie.bin", "brcmfmac4350c2-pcie.txt");
  50 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-pcie.bin", "brcmfmac4356-pcie.txt");
  51 BRCMF_FW_NVRAM_DEF(43570, "brcmfmac43570-pcie.bin", "brcmfmac43570-pcie.txt");
  52 BRCMF_FW_NVRAM_DEF(4358, "brcmfmac4358-pcie.bin", "brcmfmac4358-pcie.txt");
  53 BRCMF_FW_NVRAM_DEF(4359, "brcmfmac4359-pcie.bin", "brcmfmac4359-pcie.txt");
  54 BRCMF_FW_NVRAM_DEF(4365B, "brcmfmac4365b-pcie.bin", "brcmfmac4365b-pcie.txt");
  55 BRCMF_FW_NVRAM_DEF(4366B, "brcmfmac4366b-pcie.bin", "brcmfmac4366b-pcie.txt");
  56 BRCMF_FW_NVRAM_DEF(4371, "brcmfmac4371-pcie.bin", "brcmfmac4371-pcie.txt");
  57
  58 static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
  59         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
  60         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
  61         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
  62         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  63         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
  64         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
  65         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
  66         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
  67         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
  68         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFFF, 4365B),
  69         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFFF, 4366B),
  70         BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
  71 };
  72
  73 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  74
  75 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  76 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  77
  78 /* backplane addres space accessed by BAR0 */
  79 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  80 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  81 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  82
  83 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  84 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  85
  86 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  87 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  88
  89 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  90 #define BRCMF_PCIE_REG_INTMASK                  0x94
  91 #define BRCMF_PCIE_REG_SBMBX                    0x98
  92
  93 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
  94
  95 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  96 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  97 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  98 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  99 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
 100 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
 101
 102 #define BRCMF_PCIE_GENREV1                      1
 103 #define BRCMF_PCIE_GENREV2                      2
 104
 105 #define BRCMF_PCIE2_INTA                        0x01
 106 #define BRCMF_PCIE2_INTB                        0x02
 107
 108 #define BRCMF_PCIE_INT_0                        0x01
 109 #define BRCMF_PCIE_INT_1                        0x02
 110 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 111                                                  BRCMF_PCIE_INT_1)
 112
 113 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 114 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 115 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 116 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 117 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 118 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 119 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 120 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 121 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 122 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 123
 124 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 125                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 126                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 127                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 128                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 129                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 130                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 131                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 132
 133 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 134 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 135 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 136 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 137 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 138
 139 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 140 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 141
 142 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 143 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 144 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 145 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 146 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 147 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 148 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 149 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 150 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 151 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 152 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 153
 154 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 155 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 156 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 157 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 158
 159 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 160 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 161 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 162 #define BRCMF_RING_MEM_SZ                       16
 163 #define BRCMF_RING_STATE_SZ                     8
 164
 165 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 166 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 167 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 168 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 169 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 170 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 171 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 172 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 173 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 174 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 175
 176 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 177
 178 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 179 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 180 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 181
 182 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 183 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 184
 185 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 186 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 187 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 188
 189 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 190 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 191 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 192 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 193
 194 #define BRCMF_PCIE_MBDATA_TIMEOUT               msecs_to_jiffies(2000)
 195
 196 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 197 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 198 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 199 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 200 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 201 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 202 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 203 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 204 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 205 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 206 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 207 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 208 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 209
 210
 211 struct brcmf_pcie_console {
 212         u32 base_addr;
 213         u32 buf_addr;
 214         u32 bufsize;
 215         u32 read_idx;
 216         u8 log_str[256];
 217         u8 log_idx;
 218 };
 219
 220 struct brcmf_pcie_shared_info {
 221         u32 tcm_base_address;
 222         u32 flags;
 223         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 224         struct brcmf_pcie_ringbuf *flowrings;
 225         u16 max_rxbufpost;
 226         u32 nrof_flowrings;
 227         u32 rx_dataoffset;
 228         u32 htod_mb_data_addr;
 229         u32 dtoh_mb_data_addr;
 230         u32 ring_info_addr;
 231         struct brcmf_pcie_console console;
 232         void *scratch;
 233         dma_addr_t scratch_dmahandle;
 234         void *ringupd;
 235         dma_addr_t ringupd_dmahandle;
 236 };
 237
 238 struct brcmf_pcie_core_info {
 239         u32 base;
 240         u32 wrapbase;
 241 };
 242
 243 struct brcmf_pciedev_info {
 244         enum brcmf_pcie_state state;
 245         bool in_irq;
 246         struct pci_dev *pdev;
 247         char fw_name[BRCMF_FW_NAME_LEN];
 248         char nvram_name[BRCMF_FW_NAME_LEN];
 249         void __iomem *regs;
 250         void __iomem *tcm;
 251         u32 tcm_size;
 252         u32 ram_base;
 253         u32 ram_size;
 254         struct brcmf_chip *ci;
 255         u32 coreid;
 256         u32 generic_corerev;
 257         struct brcmf_pcie_shared_info shared;
 258         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 259         wait_queue_head_t mbdata_resp_wait;
 260         bool mbdata_completed;
 261         bool irq_allocated;
 262         bool wowl_enabled;
 263         u8 dma_idx_sz;
 264         void *idxbuf;
 265         u32 idxbuf_sz;
 266         dma_addr_t idxbuf_dmahandle;
 267         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 268         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 269                           u16 value);
 270 };
 271
 272 struct brcmf_pcie_ringbuf {
 273         struct brcmf_commonring commonring;
 274         dma_addr_t dma_handle;
 275         u32 w_idx_addr;
 276         u32 r_idx_addr;
 277         struct brcmf_pciedev_info *devinfo;
 278         u8 id;
 279 };
 280
 281
 282 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 283         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 284         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 285         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 286         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 287         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 288 };
 289
 290 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 291         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 292         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 293         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 294         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 295         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 296 };
 297
 298
 299 static u32
 300 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 301 {
 302         void __iomem *address = devinfo->regs + reg_offset;
 303
 304         return (ioread32(address));
 305 }
 306
 307
 308 static void
 309 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 310                        u32 value)
 311 {
 312         void __iomem *address = devinfo->regs + reg_offset;
 313
 314         iowrite32(value, address);
 315 }
 316
 317
 318 static u8
 319 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 320 {
 321         void __iomem *address = devinfo->tcm + mem_offset;
 322
 323         return (ioread8(address));
 324 }
 325
 326
 327 static u16
 328 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 329 {
 330         void __iomem *address = devinfo->tcm + mem_offset;
 331
 332         return (ioread16(address));
 333 }
 334
 335
 336 static void
 337 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 338                        u16 value)
 339 {
 340         void __iomem *address = devinfo->tcm + mem_offset;
 341
 342         iowrite16(value, address);
 343 }
 344
 345
 346 static u16
 347 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 348 {
 349         u16 *address = devinfo->idxbuf + mem_offset;
 350
 351         return (*(address));
 352 }
 353
 354
 355 static void
 356 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 357                      u16 value)
 358 {
 359         u16 *address = devinfo->idxbuf + mem_offset;
 360
 361         *(address) = value;
 362 }
 363
 364
 365 static u32
 366 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 367 {
 368         void __iomem *address = devinfo->tcm + mem_offset;
 369
 370         return (ioread32(address));
 371 }
 372
 373
 374 static void
 375 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 376                        u32 value)
 377 {
 378         void __iomem *address = devinfo->tcm + mem_offset;
 379
 380         iowrite32(value, address);
 381 }
 382
 383
 384 static u32
 385 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 386 {
 387         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 388
 389         return (ioread32(addr));
 390 }
 391
 392
 393 static void
 394 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 395                        u32 value)
 396 {
 397         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 398
 399         iowrite32(value, addr);
 400 }
 401
 402
 403 static void
 404 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 405                           void *srcaddr, u32 len)
 406 {
 407         void __iomem *address = devinfo->tcm + mem_offset;
 408         __le32 *src32;
 409         __le16 *src16;
 410         u8 *src8;
 411
 412         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 413                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 414                         src8 = (u8 *)srcaddr;
 415                         while (len) {
 416                                 iowrite8(*src8, address);
 417                                 address++;
 418                                 src8++;
 419                                 len--;
 420                         }
 421                 } else {
 422                         len = len / 2;
 423                         src16 = (__le16 *)srcaddr;
 424                         while (len) {
 425                                 iowrite16(le16_to_cpu(*src16), address);
 426                                 address += 2;
 427                                 src16++;
 428                                 len--;
 429                         }
 430                 }
 431         } else {
 432                 len = len / 4;
 433                 src32 = (__le32 *)srcaddr;
 434                 while (len) {
 435                         iowrite32(le32_to_cpu(*src32), address);
 436                         address += 4;
 437                         src32++;
 438                         len--;
 439                 }
 440         }
 441 }
 442
 443
 444 static void
 445 brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 446                           void *dstaddr, u32 len)
 447 {
 448         void __iomem *address = devinfo->tcm + mem_offset;
 449         __le32 *dst32;
 450         __le16 *dst16;
 451         u8 *dst8;
 452
 453         if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 454                 if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 455                         dst8 = (u8 *)dstaddr;
 456                         while (len) {
 457                                 *dst8 = ioread8(address);
 458                                 address++;
 459                                 dst8++;
 460                                 len--;
 461                         }
 462                 } else {
 463                         len = len / 2;
 464                         dst16 = (__le16 *)dstaddr;
 465                         while (len) {
 466                                 *dst16 = cpu_to_le16(ioread16(address));
 467                                 address += 2;
 468                                 dst16++;
 469                                 len--;
 470                         }
 471                 }
 472         } else {
 473                 len = len / 4;
 474                 dst32 = (__le32 *)dstaddr;
 475                 while (len) {
 476                         *dst32 = cpu_to_le32(ioread32(address));
 477                         address += 4;
 478                         dst32++;
 479                         len--;
 480                 }
 481         }
 482 }
 483
 484
 485 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 486                 CHIPCREGOFFS(reg), value)
 487
 488
 489 static void
 490 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 491 {
 492         const struct pci_dev *pdev = devinfo->pdev;
 493         struct brcmf_core *core;
 494         u32 bar0_win;
 495
 496         core = brcmf_chip_get_core(devinfo->ci, coreid);
 497         if (core) {
 498                 bar0_win = core->base;
 499                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 500                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 501                                           &bar0_win) == 0) {
 502                         if (bar0_win != core->base) {
 503                                 bar0_win = core->base;
 504                                 pci_write_config_dword(pdev,
 505                                                        BRCMF_PCIE_BAR0_WINDOW,
 506                                                        bar0_win);
 507                         }
 508                 }
 509         } else {
 510                 brcmf_err("Unsupported core selected %x\n", coreid);
 511         }
 512 }
 513
 514
 515 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 516 {
 517         struct brcmf_core *core;
 518         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 519                              BRCMF_PCIE_CFGREG_PM_CSR,
 520                              BRCMF_PCIE_CFGREG_MSI_CAP,
 521                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 522                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 523                              BRCMF_PCIE_CFGREG_MSI_DATA,
 524                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 525                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 526                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 527                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 528                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 529         u32 i;
 530         u32 val;
 531         u32 lsc;
 532
 533         if (!devinfo->ci)
 534                 return;
 535
 536         /* Disable ASPM */
 537         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 538         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 539                               &lsc);
 540         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 541         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 542                                val);
 543
 544         /* Watchdog reset */
 545         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 546         WRITECC32(devinfo, watchdog, 4);
 547         msleep(100);
 548
 549         /* Restore ASPM */
 550         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 551         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 552                                lsc);
 553
 554         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 555         if (core->rev <= 13) {
 556                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 557                         brcmf_pcie_write_reg32(devinfo,
 558                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 559                                                cfg_offset[i]);
 560                         val = brcmf_pcie_read_reg32(devinfo,
 561                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 562                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 563                                   cfg_offset[i], val);
 564                         brcmf_pcie_write_reg32(devinfo,
 565                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 566                                                val);
 567                 }
 568         }
 569 }
 570
 571
 572 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 573 {
 574         u32 config;
 575
 576         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 577         /* BAR1 window may not be sized properly */
 578         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 579         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 580         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 581         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 582
 583         device_wakeup_enable(&devinfo->pdev->dev);
 584 }
 585
 586
 587 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 588 {
 589         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 590                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 591                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 592                                        5);
 593                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 594                                        0);
 595                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 596                                        7);
 597                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 598                                        0);
 599         }
 600         return 0;
 601 }
 602
 603
 604 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 605                                           u32 resetintr)
 606 {
 607         struct brcmf_core *core;
 608
 609         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 610                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 611                 brcmf_chip_resetcore(core, 0, 0, 0);
 612         }
 613
 614         if (!brcmf_chip_set_active(devinfo->ci, resetintr))
 615                 return -EINVAL;
 616         return 0;
 617 }
 618
 619
 620 static int
 621 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 622 {
 623         struct brcmf_pcie_shared_info *shared;
 624         u32 addr;
 625         u32 cur_htod_mb_data;
 626         u32 i;
 627
 628         shared = &devinfo->shared;
 629         addr = shared->htod_mb_data_addr;
 630         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 631
 632         if (cur_htod_mb_data != 0)
 633                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 634                           cur_htod_mb_data);
 635
 636         i = 0;
 637         while (cur_htod_mb_data != 0) {
 638                 msleep(10);
 639                 i++;
 640                 if (i > 100)
 641                         return -EIO;
 642                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 643         }
 644
 645         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 646         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 647         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 648
 649         return 0;
 650 }
 651
 652
 653 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 654 {
 655         struct brcmf_pcie_shared_info *shared;
 656         u32 addr;
 657         u32 dtoh_mb_data;
 658
 659         shared = &devinfo->shared;
 660         addr = shared->dtoh_mb_data_addr;
 661         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 662
 663         if (!dtoh_mb_data)
 664                 return;
 665
 666         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 667
 668         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 669         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 670                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 671                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 672                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 673         }
 674         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 675                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 676         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 677                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 678                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 679                         devinfo->mbdata_completed = true;
 680                         wake_up(&devinfo->mbdata_resp_wait);
 681                 }
 682         }
 683 }
 684
 685
 686 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 687 {
 688         struct brcmf_pcie_shared_info *shared;
 689         struct brcmf_pcie_console *console;
 690         u32 addr;
 691
 692         shared = &devinfo->shared;
 693         console = &shared->console;
 694         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 695         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 696
 697         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 698         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 699         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 700         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 701
 702         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 703                   console->base_addr, console->buf_addr, console->bufsize);
 704 }
 705
 706
 707 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 708 {
 709         struct brcmf_pcie_console *console;
 710         u32 addr;
 711         u8 ch;
 712         u32 newidx;
 713
 714         if (!BRCMF_FWCON_ON())
 715                 return;
 716
 717         console = &devinfo->shared.console;
 718         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 719         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 720         while (newidx != console->read_idx) {
 721                 addr = console->buf_addr + console->read_idx;
 722                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 723                 console->read_idx++;
 724                 if (console->read_idx == console->bufsize)
 725                         console->read_idx = 0;
 726                 if (ch == '\r')
 727                         continue;
 728                 console->log_str[console->log_idx] = ch;
 729                 console->log_idx++;
 730                 if ((ch != '\n') &&
 731                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 732                         ch = '\n';
 733                         console->log_str[console->log_idx] = ch;
 734                         console->log_idx++;
 735                 }
 736                 if (ch == '\n') {
 737                         console->log_str[console->log_idx] = 0;
 738                         pr_debug("CONSOLE: %s", console->log_str);
 739                         console->log_idx = 0;
 740                 }
 741         }
 742 }
 743
 744
 745 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 746 {
 747         u32 reg_value;
 748
 749         brcmf_dbg(PCIE, "RING !\n");
 750         reg_value = brcmf_pcie_read_reg32(devinfo,
 751                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 752         reg_value |= BRCMF_PCIE2_INTB;
 753         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 754                                reg_value);
 755 }
 756
 757
 758 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 759 {
 760         brcmf_dbg(PCIE, "RING !\n");
 761         /* Any arbitrary value will do, lets use 1 */
 762         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 763 }
 764
 765
 766 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 767 {
 768         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 769                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 770                                        0);
 771         else
 772                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 773                                        0);
 774 }
 775
 776
 777 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 778 {
 779         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 780                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 781                                        BRCMF_PCIE_INT_DEF);
 782         else
 783                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 784                                        BRCMF_PCIE_MB_INT_D2H_DB |
 785                                        BRCMF_PCIE_MB_INT_FN0_0 |
 786                                        BRCMF_PCIE_MB_INT_FN0_1);
 787 }
 788
 789
 790 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 791 {
 792         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 793         u32 status;
 794
 795         status = 0;
 796         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 797         if (status) {
 798                 brcmf_pcie_intr_disable(devinfo);
 799                 brcmf_dbg(PCIE, "Enter\n");
 800                 return IRQ_WAKE_THREAD;
 801         }
 802         return IRQ_NONE;
 803 }
 804
 805
 806 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 807 {
 808         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 809
 810         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 811                 brcmf_pcie_intr_disable(devinfo);
 812                 brcmf_dbg(PCIE, "Enter\n");
 813                 return IRQ_WAKE_THREAD;
 814         }
 815         return IRQ_NONE;
 816 }
 817
 818
 819 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 820 {
 821         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 822         const struct pci_dev *pdev = devinfo->pdev;
 823         u32 status;
 824
 825         devinfo->in_irq = true;
 826         status = 0;
 827         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 828         brcmf_dbg(PCIE, "Enter %x\n", status);
 829         if (status) {
 830                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 831                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 832                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 833         }
 834         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 835                 brcmf_pcie_intr_enable(devinfo);
 836         devinfo->in_irq = false;
 837         return IRQ_HANDLED;
 838 }
 839
 840
 841 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 842 {
 843         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 844         u32 status;
 845
 846         devinfo->in_irq = true;
 847         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 848         brcmf_dbg(PCIE, "Enter %x\n", status);
 849         if (status) {
 850                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 851                                        status);
 852                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 853                               BRCMF_PCIE_MB_INT_FN0_1))
 854                         brcmf_pcie_handle_mb_data(devinfo);
 855                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 856                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 857                                 brcmf_proto_msgbuf_rx_trigger(
 858                                                         &devinfo->pdev->dev);
 859                 }
 860         }
 861         brcmf_pcie_bus_console_read(devinfo);
 862         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 863                 brcmf_pcie_intr_enable(devinfo);
 864         devinfo->in_irq = false;
 865         return IRQ_HANDLED;
 866 }
 867
 868
 869 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 870 {
 871         struct pci_dev *pdev;
 872
 873         pdev = devinfo->pdev;
 874
 875         brcmf_pcie_intr_disable(devinfo);
 876
 877         brcmf_dbg(PCIE, "Enter\n");
 878         /* is it a v1 or v2 implementation */
 879         pci_enable_msi(pdev);
 880         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 881                 if (request_threaded_irq(pdev->irq,
 882                                          brcmf_pcie_quick_check_isr_v1,
 883                                          brcmf_pcie_isr_thread_v1,
 884                                          IRQF_SHARED, "brcmf_pcie_intr",
 885                                          devinfo)) {
 886                         pci_disable_msi(pdev);
 887                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 888                         return -EIO;
 889                 }
 890         } else {
 891                 if (request_threaded_irq(pdev->irq,
 892                                          brcmf_pcie_quick_check_isr_v2,
 893                                          brcmf_pcie_isr_thread_v2,
 894                                          IRQF_SHARED, "brcmf_pcie_intr",
 895                                          devinfo)) {
 896                         pci_disable_msi(pdev);
 897                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 898                         return -EIO;
 899                 }
 900         }
 901         devinfo->irq_allocated = true;
 902         return 0;
 903 }
 904
 905
 906 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 907 {
 908         struct pci_dev *pdev;
 909         u32 status;
 910         u32 count;
 911
 912         if (!devinfo->irq_allocated)
 913                 return;
 914
 915         pdev = devinfo->pdev;
 916
 917         brcmf_pcie_intr_disable(devinfo);
 918         free_irq(pdev->irq, devinfo);
 919         pci_disable_msi(pdev);
 920
 921         msleep(50);
 922         count = 0;
 923         while ((devinfo->in_irq) && (count < 20)) {
 924                 msleep(50);
 925                 count++;
 926         }
 927         if (devinfo->in_irq)
 928                 brcmf_err("Still in IRQ (processing) !!!\n");
 929
 930         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 931                 status = 0;
 932                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 933                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 934         } else {
 935                 status = brcmf_pcie_read_reg32(devinfo,
 936                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 937                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 938                                        status);
 939         }
 940         devinfo->irq_allocated = false;
 941 }
 942
 943
 944 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 945 {
 946         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 947         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 948         struct brcmf_commonring *commonring = &ring->commonring;
 949
 950         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 951                 return -EIO;
 952
 953         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 954                   commonring->w_ptr, ring->id);
 955
 956         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 957
 958         return 0;
 959 }
 960
 961
 962 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 963 {
 964         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 965         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 966         struct brcmf_commonring *commonring = &ring->commonring;
 967
 968         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 969                 return -EIO;
 970
 971         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 972                   commonring->r_ptr, ring->id);
 973
 974         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 975
 976         return 0;
 977 }
 978
 979
 980 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 981 {
 982         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 983         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 984
 985         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 986                 return -EIO;
 987
 988         devinfo->ringbell(devinfo);
 989
 990         return 0;
 991 }
 992
 993
 994 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 995 {
 996         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 997         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 998         struct brcmf_commonring *commonring = &ring->commonring;
 999
1000         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1001                 return -EIO;
1002
1003         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1004
1005         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1006                   commonring->w_ptr, ring->id);
1007
1008         return 0;
1009 }
1010
1011
1012 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1013 {
1014         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1015         struct brcmf_pciedev_info *devinfo = ring->devinfo;
1016         struct brcmf_commonring *commonring = &ring->commonring;
1017
1018         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1019                 return -EIO;
1020
1021         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1022
1023         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1024                   commonring->r_ptr, ring->id);
1025
1026         return 0;
1027 }
1028
1029
1030 static void *
1031 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1032                                      u32 size, u32 tcm_dma_phys_addr,
1033                                      dma_addr_t *dma_handle)
1034 {
1035         void *ring;
1036         u64 address;
1037
1038         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1039                                   GFP_KERNEL);
1040         if (!ring)
1041                 return NULL;
1042
1043         address = (u64)*dma_handle;
1044         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1045                                address & 0xffffffff);
1046         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1047
1048         memset(ring, 0, size);
1049
1050         return (ring);
1051 }
1052
1053
1054 static struct brcmf_pcie_ringbuf *
1055 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1056                               u32 tcm_ring_phys_addr)
1057 {
1058         void *dma_buf;
1059         dma_addr_t dma_handle;
1060         struct brcmf_pcie_ringbuf *ring;
1061         u32 size;
1062         u32 addr;
1063
1064         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1065         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1066                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1067                         &dma_handle);
1068         if (!dma_buf)
1069                 return NULL;
1070
1071         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1072         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1073         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1074         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1075
1076         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1077         if (!ring) {
1078                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1079                                   dma_handle);
1080                 return NULL;
1081         }
1082         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1083                                 brcmf_ring_itemsize[ring_id], dma_buf);
1084         ring->dma_handle = dma_handle;
1085         ring->devinfo = devinfo;
1086         brcmf_commonring_register_cb(&ring->commonring,
1087                                      brcmf_pcie_ring_mb_ring_bell,
1088                                      brcmf_pcie_ring_mb_update_rptr,
1089                                      brcmf_pcie_ring_mb_update_wptr,
1090                                      brcmf_pcie_ring_mb_write_rptr,
1091                                      brcmf_pcie_ring_mb_write_wptr, ring);
1092
1093         return (ring);
1094 }
1095
1096
1097 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1098                                           struct brcmf_pcie_ringbuf *ring)
1099 {
1100         void *dma_buf;
1101         u32 size;
1102
1103         if (!ring)
1104                 return;
1105
1106         dma_buf = ring->commonring.buf_addr;
1107         if (dma_buf) {
1108                 size = ring->commonring.depth * ring->commonring.item_len;
1109                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1110         }
1111         kfree(ring);
1112 }
1113
1114
1115 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1116 {
1117         u32 i;
1118
1119         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1120                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1121                                               devinfo->shared.commonrings[i]);
1122                 devinfo->shared.commonrings[i] = NULL;
1123         }
1124         kfree(devinfo->shared.flowrings);
1125         devinfo->shared.flowrings = NULL;
1126         if (devinfo->idxbuf) {
1127                 dma_free_coherent(&devinfo->pdev->dev,
1128                                   devinfo->idxbuf_sz,
1129                                   devinfo->idxbuf,
1130                                   devinfo->idxbuf_dmahandle);
1131                 devinfo->idxbuf = NULL;
1132         }
1133 }
1134
1135
1136 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1137 {
1138         struct brcmf_pcie_ringbuf *ring;
1139         struct brcmf_pcie_ringbuf *rings;
1140         u32 ring_addr;
1141         u32 d2h_w_idx_ptr;
1142         u32 d2h_r_idx_ptr;
1143         u32 h2d_w_idx_ptr;
1144         u32 h2d_r_idx_ptr;
1145         u32 addr;
1146         u32 ring_mem_ptr;
1147         u32 i;
1148         u64 address;
1149         u32 bufsz;
1150         u16 max_sub_queues;
1151         u8 idx_offset;
1152
1153         ring_addr = devinfo->shared.ring_info_addr;
1154         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1155         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1156         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1157
1158         if (devinfo->dma_idx_sz != 0) {
1159                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1160                         devinfo->dma_idx_sz * 2;
1161                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1162                                                      &devinfo->idxbuf_dmahandle,
1163                                                      GFP_KERNEL);
1164                 if (!devinfo->idxbuf)
1165                         devinfo->dma_idx_sz = 0;
1166         }
1167
1168         if (devinfo->dma_idx_sz == 0) {
1169                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1170                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1171                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1172                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1173                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1174                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1175                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1176                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1177                 idx_offset = sizeof(u32);
1178                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1179                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1180                 brcmf_dbg(PCIE, "Using TCM indices\n");
1181         } else {
1182                 memset(devinfo->idxbuf, 0, bufsz);
1183                 devinfo->idxbuf_sz = bufsz;
1184                 idx_offset = devinfo->dma_idx_sz;
1185                 devinfo->write_ptr = brcmf_pcie_write_idx;
1186                 devinfo->read_ptr = brcmf_pcie_read_idx;
1187
1188                 h2d_w_idx_ptr = 0;
1189                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1190                 address = (u64)devinfo->idxbuf_dmahandle;
1191                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1192                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1193
1194                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1195                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1196                 address += max_sub_queues * idx_offset;
1197                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1198                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1199
1200                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1201                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1202                 address += max_sub_queues * idx_offset;
1203                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1204                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1205
1206                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1207                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1208                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1209                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1210                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1211                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1212                 brcmf_dbg(PCIE, "Using host memory indices\n");
1213         }
1214
1215         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1216         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1217
1218         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1219                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1220                 if (!ring)
1221                         goto fail;
1222                 ring->w_idx_addr = h2d_w_idx_ptr;
1223                 ring->r_idx_addr = h2d_r_idx_ptr;
1224                 ring->id = i;
1225                 devinfo->shared.commonrings[i] = ring;
1226
1227                 h2d_w_idx_ptr += idx_offset;
1228                 h2d_r_idx_ptr += idx_offset;
1229                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1230         }
1231
1232         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1233              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1234                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1235                 if (!ring)
1236                         goto fail;
1237                 ring->w_idx_addr = d2h_w_idx_ptr;
1238                 ring->r_idx_addr = d2h_r_idx_ptr;
1239                 ring->id = i;
1240                 devinfo->shared.commonrings[i] = ring;
1241
1242                 d2h_w_idx_ptr += idx_offset;
1243                 d2h_r_idx_ptr += idx_offset;
1244                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1245         }
1246
1247         devinfo->shared.nrof_flowrings =
1248                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1249         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1250                         GFP_KERNEL);
1251         if (!rings)
1252                 goto fail;
1253
1254         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1255                   devinfo->shared.nrof_flowrings);
1256
1257         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1258                 ring = &rings[i];
1259                 ring->devinfo = devinfo;
1260                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1261                 brcmf_commonring_register_cb(&ring->commonring,
1262                                              brcmf_pcie_ring_mb_ring_bell,
1263                                              brcmf_pcie_ring_mb_update_rptr,
1264                                              brcmf_pcie_ring_mb_update_wptr,
1265                                              brcmf_pcie_ring_mb_write_rptr,
1266                                              brcmf_pcie_ring_mb_write_wptr,
1267                                              ring);
1268                 ring->w_idx_addr = h2d_w_idx_ptr;
1269                 ring->r_idx_addr = h2d_r_idx_ptr;
1270                 h2d_w_idx_ptr += idx_offset;
1271                 h2d_r_idx_ptr += idx_offset;
1272         }
1273         devinfo->shared.flowrings = rings;
1274
1275         return 0;
1276
1277 fail:
1278         brcmf_err("Allocating ring buffers failed\n");
1279         brcmf_pcie_release_ringbuffers(devinfo);
1280         return -ENOMEM;
1281 }
1282
1283
1284 static void
1285 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1286 {
1287         if (devinfo->shared.scratch)
1288                 dma_free_coherent(&devinfo->pdev->dev,
1289                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1290                                   devinfo->shared.scratch,
1291                                   devinfo->shared.scratch_dmahandle);
1292         if (devinfo->shared.ringupd)
1293                 dma_free_coherent(&devinfo->pdev->dev,
1294                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1295                                   devinfo->shared.ringupd,
1296                                   devinfo->shared.ringupd_dmahandle);
1297 }
1298
1299 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1300 {
1301         u64 address;
1302         u32 addr;
1303
1304         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1305                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1306                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1307         if (!devinfo->shared.scratch)
1308                 goto fail;
1309
1310         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1311
1312         addr = devinfo->shared.tcm_base_address +
1313                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1314         address = (u64)devinfo->shared.scratch_dmahandle;
1315         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1316         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1317         addr = devinfo->shared.tcm_base_address +
1318                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1319         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1320
1321         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1322                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1323                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1324         if (!devinfo->shared.ringupd)
1325                 goto fail;
1326
1327         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1328
1329         addr = devinfo->shared.tcm_base_address +
1330                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1331         address = (u64)devinfo->shared.ringupd_dmahandle;
1332         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1333         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1334         addr = devinfo->shared.tcm_base_address +
1335                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1336         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1337         return 0;
1338
1339 fail:
1340         brcmf_err("Allocating scratch buffers failed\n");
1341         brcmf_pcie_release_scratchbuffers(devinfo);
1342         return -ENOMEM;
1343 }
1344
1345
1346 static void brcmf_pcie_down(struct device *dev)
1347 {
1348 }
1349
1350
1351 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1352 {
1353         return 0;
1354 }
1355
1356
1357 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1358                                 uint len)
1359 {
1360         return 0;
1361 }
1362
1363
1364 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1365                                 uint len)
1366 {
1367         return 0;
1368 }
1369
1370
1371 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1372 {
1373         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1374         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1375         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1376
1377         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1378         devinfo->wowl_enabled = enabled;
1379 }
1380
1381
1382 static size_t brcmf_pcie_get_ramsize(struct device *dev)
1383 {
1384         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1385         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1386         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1387
1388         return devinfo->ci->ramsize - devinfo->ci->srsize;
1389 }
1390
1391
1392 static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1393 {
1394         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1395         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1396         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1397
1398         brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1399         brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1400         return 0;
1401 }
1402
1403
1404 static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1405         .txdata = brcmf_pcie_tx,
1406         .stop = brcmf_pcie_down,
1407         .txctl = brcmf_pcie_tx_ctlpkt,
1408         .rxctl = brcmf_pcie_rx_ctlpkt,
1409         .wowl_config = brcmf_pcie_wowl_config,
1410         .get_ramsize = brcmf_pcie_get_ramsize,
1411         .get_memdump = brcmf_pcie_get_memdump,
1412 };
1413
1414
1415 static int
1416 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1417                                u32 sharedram_addr)
1418 {
1419         struct brcmf_pcie_shared_info *shared;
1420         u32 addr;
1421         u32 version;
1422
1423         shared = &devinfo->shared;
1424         shared->tcm_base_address = sharedram_addr;
1425
1426         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1427         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1428         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1429         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1430             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1431                 brcmf_err("Unsupported PCIE version %d\n", version);
1432                 return -EINVAL;
1433         }
1434
1435         /* check firmware support dma indicies */
1436         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1437                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1438                         devinfo->dma_idx_sz = sizeof(u16);
1439                 else
1440                         devinfo->dma_idx_sz = sizeof(u32);
1441         }
1442
1443         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1444         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1445         if (shared->max_rxbufpost == 0)
1446                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1447
1448         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1449         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1450
1451         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1452         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1453
1454         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1455         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1456
1457         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1458         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1459
1460         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1461                   shared->max_rxbufpost, shared->rx_dataoffset);
1462
1463         brcmf_pcie_bus_console_init(devinfo);
1464
1465         return 0;
1466 }
1467
1468
1469 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1470                                         const struct firmware *fw, void *nvram,
1471                                         u32 nvram_len)
1472 {
1473         u32 sharedram_addr;
1474         u32 sharedram_addr_written;
1475         u32 loop_counter;
1476         int err;
1477         u32 address;
1478         u32 resetintr;
1479
1480         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1481         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1482
1483         brcmf_dbg(PCIE, "Halt ARM.\n");
1484         err = brcmf_pcie_enter_download_state(devinfo);
1485         if (err)
1486                 return err;
1487
1488         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1489         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1490                                   (void *)fw->data, fw->size);
1491
1492         resetintr = get_unaligned_le32(fw->data);
1493         release_firmware(fw);
1494
1495         /* reset last 4 bytes of RAM address. to be used for shared
1496          * area. This identifies when FW is running
1497          */
1498         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1499
1500         if (nvram) {
1501                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1502                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1503                           nvram_len;
1504                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1505                 brcmf_fw_nvram_free(nvram);
1506         } else {
1507                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1508                           devinfo->nvram_name);
1509         }
1510
1511         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1512                                                        devinfo->ci->ramsize -
1513                                                        4);
1514         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1515         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1516         if (err)
1517                 return err;
1518
1519         brcmf_dbg(PCIE, "Wait for FW init\n");
1520         sharedram_addr = sharedram_addr_written;
1521         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1522         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1523                 msleep(50);
1524                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1525                                                        devinfo->ci->ramsize -
1526                                                        4);
1527                 loop_counter--;
1528         }
1529         if (sharedram_addr == sharedram_addr_written) {
1530                 brcmf_err("FW failed to initialize\n");
1531                 return -ENODEV;
1532         }
1533         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1534
1535         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1536 }
1537
1538
1539 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1540 {
1541         struct pci_dev *pdev;
1542         int err;
1543         phys_addr_t  bar0_addr, bar1_addr;
1544         ulong bar1_size;
1545
1546         pdev = devinfo->pdev;
1547
1548         err = pci_enable_device(pdev);
1549         if (err) {
1550                 brcmf_err("pci_enable_device failed err=%d\n", err);
1551                 return err;
1552         }
1553
1554         pci_set_master(pdev);
1555
1556         /* Bar-0 mapped address */
1557         bar0_addr = pci_resource_start(pdev, 0);
1558         /* Bar-1 mapped address */
1559         bar1_addr = pci_resource_start(pdev, 2);
1560         /* read Bar-1 mapped memory range */
1561         bar1_size = pci_resource_len(pdev, 2);
1562         if ((bar1_size == 0) || (bar1_addr == 0)) {
1563                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1564                           bar1_size, (unsigned long long)bar1_addr);
1565                 return -EINVAL;
1566         }
1567
1568         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1569         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1570         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1571
1572         if (!devinfo->regs || !devinfo->tcm) {
1573                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1574                           devinfo->tcm);
1575                 return -EINVAL;
1576         }
1577         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1578                   devinfo->regs, (unsigned long long)bar0_addr);
1579         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1580                   devinfo->tcm, (unsigned long long)bar1_addr);
1581
1582         return 0;
1583 }
1584
1585
1586 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1587 {
1588         if (devinfo->tcm)
1589                 iounmap(devinfo->tcm);
1590         if (devinfo->regs)
1591                 iounmap(devinfo->regs);
1592
1593         pci_disable_device(devinfo->pdev);
1594 }
1595
1596
1597 static int brcmf_pcie_attach_bus(struct device *dev)
1598 {
1599         int ret;
1600
1601         /* Attach to the common driver interface */
1602         ret = brcmf_attach(dev);
1603         if (ret) {
1604                 brcmf_err("brcmf_attach failed\n");
1605         } else {
1606                 ret = brcmf_bus_start(dev);
1607                 if (ret)
1608                         brcmf_err("dongle is not responding\n");
1609         }
1610
1611         return ret;
1612 }
1613
1614
1615 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1616 {
1617         u32 ret_addr;
1618
1619         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1620         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1621         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1622
1623         return ret_addr;
1624 }
1625
1626
1627 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1628 {
1629         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1630
1631         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1632         return brcmf_pcie_read_reg32(devinfo, addr);
1633 }
1634
1635
1636 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1637 {
1638         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1639
1640         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1641         brcmf_pcie_write_reg32(devinfo, addr, value);
1642 }
1643
1644
1645 static int brcmf_pcie_buscoreprep(void *ctx)
1646 {
1647         return brcmf_pcie_get_resource(ctx);
1648 }
1649
1650
1651 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1652 {
1653         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1654         u32 val;
1655
1656         devinfo->ci = chip;
1657         brcmf_pcie_reset_device(devinfo);
1658
1659         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1660         if (val != 0xffffffff)
1661                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1662                                        val);
1663
1664         return 0;
1665 }
1666
1667
1668 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1669                                         u32 rstvec)
1670 {
1671         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1672
1673         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1674 }
1675
1676
1677 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1678         .prepare = brcmf_pcie_buscoreprep,
1679         .reset = brcmf_pcie_buscore_reset,
1680         .activate = brcmf_pcie_buscore_activate,
1681         .read32 = brcmf_pcie_buscore_read32,
1682         .write32 = brcmf_pcie_buscore_write32,
1683 };
1684
1685 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1686                              void *nvram, u32 nvram_len)
1687 {
1688         struct brcmf_bus *bus = dev_get_drvdata(dev);
1689         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1690         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1691         struct brcmf_commonring **flowrings;
1692         int ret;
1693         u32 i;
1694
1695         brcmf_pcie_attach(devinfo);
1696
1697         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1698         if (ret)
1699                 goto fail;
1700
1701         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1702
1703         ret = brcmf_pcie_init_ringbuffers(devinfo);
1704         if (ret)
1705                 goto fail;
1706
1707         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1708         if (ret)
1709                 goto fail;
1710
1711         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1712         ret = brcmf_pcie_request_irq(devinfo);
1713         if (ret)
1714                 goto fail;
1715
1716         /* hook the commonrings in the bus structure. */
1717         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1718                 bus->msgbuf->commonrings[i] =
1719                                 &devinfo->shared.commonrings[i]->commonring;
1720
1721         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1722                             GFP_KERNEL);
1723         if (!flowrings)
1724                 goto fail;
1725
1726         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1727                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1728         bus->msgbuf->flowrings = flowrings;
1729
1730         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1731         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1732         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1733
1734         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1735
1736         brcmf_pcie_intr_enable(devinfo);
1737         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1738                 return;
1739
1740         brcmf_pcie_bus_console_read(devinfo);
1741
1742 fail:
1743         device_release_driver(dev);
1744 }
1745
1746 static int
1747 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1748 {
1749         int ret;
1750         struct brcmf_pciedev_info *devinfo;
1751         struct brcmf_pciedev *pcie_bus_dev;
1752         struct brcmf_bus *bus;
1753         u16 domain_nr;
1754         u16 bus_nr;
1755
1756         domain_nr = pci_domain_nr(pdev->bus) + 1;
1757         bus_nr = pdev->bus->number;
1758         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1759                   domain_nr, bus_nr);
1760
1761         ret = -ENOMEM;
1762         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1763         if (devinfo == NULL)
1764                 return ret;
1765
1766         devinfo->pdev = pdev;
1767         pcie_bus_dev = NULL;
1768         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1769         if (IS_ERR(devinfo->ci)) {
1770                 ret = PTR_ERR(devinfo->ci);
1771                 devinfo->ci = NULL;
1772                 goto fail;
1773         }
1774
1775         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1776         if (pcie_bus_dev == NULL) {
1777                 ret = -ENOMEM;
1778                 goto fail;
1779         }
1780
1781         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1782         if (!bus) {
1783                 ret = -ENOMEM;
1784                 goto fail;
1785         }
1786         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1787         if (!bus->msgbuf) {
1788                 ret = -ENOMEM;
1789                 kfree(bus);
1790                 goto fail;
1791         }
1792
1793         /* hook it all together. */
1794         pcie_bus_dev->devinfo = devinfo;
1795         pcie_bus_dev->bus = bus;
1796         bus->dev = &pdev->dev;
1797         bus->bus_priv.pcie = pcie_bus_dev;
1798         bus->ops = &brcmf_pcie_bus_ops;
1799         bus->proto_type = BRCMF_PROTO_MSGBUF;
1800         bus->chip = devinfo->coreid;
1801         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1802         dev_set_drvdata(&pdev->dev, bus);
1803
1804         ret = brcmf_fw_map_chip_to_name(devinfo->ci->chip, devinfo->ci->chiprev,
1805                                         brcmf_pcie_fwnames,
1806                                         ARRAY_SIZE(brcmf_pcie_fwnames),
1807                                         devinfo->fw_name, devinfo->nvram_name);
1808         if (ret)
1809                 goto fail_bus;
1810
1811         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1812                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1813                                           devinfo->fw_name, devinfo->nvram_name,
1814                                           brcmf_pcie_setup, domain_nr, bus_nr);
1815         if (ret == 0)
1816                 return 0;
1817 fail_bus:
1818         kfree(bus->msgbuf);
1819         kfree(bus);
1820 fail:
1821         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1822         brcmf_pcie_release_resource(devinfo);
1823         if (devinfo->ci)
1824                 brcmf_chip_detach(devinfo->ci);
1825         kfree(pcie_bus_dev);
1826         kfree(devinfo);
1827         return ret;
1828 }
1829
1830
1831 static void
1832 brcmf_pcie_remove(struct pci_dev *pdev)
1833 {
1834         struct brcmf_pciedev_info *devinfo;
1835         struct brcmf_bus *bus;
1836
1837         brcmf_dbg(PCIE, "Enter\n");
1838
1839         bus = dev_get_drvdata(&pdev->dev);
1840         if (bus == NULL)
1841                 return;
1842
1843         devinfo = bus->bus_priv.pcie->devinfo;
1844
1845         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1846         if (devinfo->ci)
1847                 brcmf_pcie_intr_disable(devinfo);
1848
1849         brcmf_detach(&pdev->dev);
1850
1851         kfree(bus->bus_priv.pcie);
1852         kfree(bus->msgbuf->flowrings);
1853         kfree(bus->msgbuf);
1854         kfree(bus);
1855
1856         brcmf_pcie_release_irq(devinfo);
1857         brcmf_pcie_release_scratchbuffers(devinfo);
1858         brcmf_pcie_release_ringbuffers(devinfo);
1859         brcmf_pcie_reset_device(devinfo);
1860         brcmf_pcie_release_resource(devinfo);
1861
1862         if (devinfo->ci)
1863                 brcmf_chip_detach(devinfo->ci);
1864
1865         kfree(devinfo);
1866         dev_set_drvdata(&pdev->dev, NULL);
1867 }
1868
1869
1870 #ifdef CONFIG_PM
1871
1872
1873 static int brcmf_pcie_pm_enter_D3(struct device *dev)
1874 {
1875         struct brcmf_pciedev_info *devinfo;
1876         struct brcmf_bus *bus;
1877
1878         brcmf_dbg(PCIE, "Enter\n");
1879
1880         bus = dev_get_drvdata(dev);
1881         devinfo = bus->bus_priv.pcie->devinfo;
1882
1883         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1884
1885         devinfo->mbdata_completed = false;
1886         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1887
1888         wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
1889                            BRCMF_PCIE_MBDATA_TIMEOUT);
1890         if (!devinfo->mbdata_completed) {
1891                 brcmf_err("Timeout on response for entering D3 substate\n");
1892                 return -EIO;
1893         }
1894
1895         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1896
1897         return 0;
1898 }
1899
1900
1901 static int brcmf_pcie_pm_leave_D3(struct device *dev)
1902 {
1903         struct brcmf_pciedev_info *devinfo;
1904         struct brcmf_bus *bus;
1905         struct pci_dev *pdev;
1906         int err;
1907
1908         brcmf_dbg(PCIE, "Enter\n");
1909
1910         bus = dev_get_drvdata(dev);
1911         devinfo = bus->bus_priv.pcie->devinfo;
1912         brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
1913
1914         /* Check if device is still up and running, if so we are ready */
1915         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1916                 brcmf_dbg(PCIE, "Try to wakeup device....\n");
1917                 if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
1918                         goto cleanup;
1919                 brcmf_dbg(PCIE, "Hot resume, continue....\n");
1920                 devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1921                 brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1922                 brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1923                 brcmf_pcie_intr_enable(devinfo);
1924                 return 0;
1925         }
1926
1927 cleanup:
1928         brcmf_chip_detach(devinfo->ci);
1929         devinfo->ci = NULL;
1930         pdev = devinfo->pdev;
1931         brcmf_pcie_remove(pdev);
1932
1933         err = brcmf_pcie_probe(pdev, NULL);
1934         if (err)
1935                 brcmf_err("probe after resume failed, err=%d\n", err);
1936
1937         return err;
1938 }
1939
1940
1941 static const struct dev_pm_ops brcmf_pciedrvr_pm = {
1942         .suspend = brcmf_pcie_pm_enter_D3,
1943         .resume = brcmf_pcie_pm_leave_D3,
1944         .freeze = brcmf_pcie_pm_enter_D3,
1945         .restore = brcmf_pcie_pm_leave_D3,
1946 };
1947
1948
1949 #endif /* CONFIG_PM */
1950
1951
1952 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1953         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1954
1955 static struct pci_device_id brcmf_pcie_devid_table[] = {
1956         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
1957         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1958         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1959         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1960         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1961         BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID),
1962         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1963         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1964         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1965         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1966         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
1967         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
1968         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
1969         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
1970         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
1971         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
1972         BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID),
1973         { /* end: all zeroes */ }
1974 };
1975
1976
1977 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
1978
1979
1980 static struct pci_driver brcmf_pciedrvr = {
1981         .node = {},
1982         .name = KBUILD_MODNAME,
1983         .id_table = brcmf_pcie_devid_table,
1984         .probe = brcmf_pcie_probe,
1985         .remove = brcmf_pcie_remove,
1986 #ifdef CONFIG_PM
1987         .driver.pm = &brcmf_pciedrvr_pm,
1988 #endif
1989 };
1990
1991
1992 void brcmf_pcie_register(void)
1993 {
1994         int err;
1995
1996         brcmf_dbg(PCIE, "Enter\n");
1997         err = pci_register_driver(&brcmf_pciedrvr);
1998         if (err)
1999                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2000 }
2001
2002
2003 void brcmf_pcie_exit(void)
2004 {
2005         brcmf_dbg(PCIE, "Enter\n");
2006         pci_unregister_driver(&brcmf_pciedrvr);
2007 }