2 * Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers
4 * Copyright (c) 2010, ST-Ericsson
5 * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
8 * ST-Ericsson UMAC CW1200 driver which is
9 * Copyright (c) 2010, ST-Ericsson
10 * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched.h>
20 #include <linux/firmware.h>
28 static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
31 u32 silicon_type = (config_reg_val >> 24) & 0x7;
32 u32 silicon_vers = (config_reg_val >> 31) & 0x1;
34 switch (silicon_type) {
37 hw_type = HIF_9000_SILICON_VERSATILE;
40 case 0x02: /* CW1x00 */
41 case 0x04: /* CW1x60 */
42 *major_revision = silicon_type;
44 hw_type = HIF_8601_VERSATILE;
46 hw_type = HIF_8601_SILICON;
55 static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
57 int ret, block, num_blocks;
63 const struct firmware *firmware = NULL;
65 /* Macroses are local. */
66 #define APB_WRITE(reg, val) \
68 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
72 #define APB_READ(reg, val) \
74 ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
78 #define REG_WRITE(reg, val) \
80 ret = cw1200_reg_write_32(priv, (reg), (val)); \
84 #define REG_READ(reg, val) \
86 ret = cw1200_reg_read_32(priv, (reg), &(val)); \
91 switch (priv->hw_revision) {
92 case CW1200_HW_REV_CUT10:
93 fw_path = FIRMWARE_CUT10;
95 priv->sdd_path = SDD_FILE_10;
97 case CW1200_HW_REV_CUT11:
98 fw_path = FIRMWARE_CUT11;
100 priv->sdd_path = SDD_FILE_11;
102 case CW1200_HW_REV_CUT20:
103 fw_path = FIRMWARE_CUT20;
105 priv->sdd_path = SDD_FILE_20;
107 case CW1200_HW_REV_CUT22:
108 fw_path = FIRMWARE_CUT22;
110 priv->sdd_path = SDD_FILE_22;
113 fw_path = FIRMWARE_CW1X60;
115 priv->sdd_path = SDD_FILE_CW1X60;
118 pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
122 /* Initialize common registers */
123 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
124 APB_WRITE(DOWNLOAD_PUT_REG, 0);
125 APB_WRITE(DOWNLOAD_GET_REG, 0);
126 APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
127 APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
129 /* Write the NOP Instruction */
130 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
131 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
133 /* Release CPU from RESET */
134 REG_READ(ST90TDS_CONFIG_REG_ID, val32);
135 val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
136 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
139 val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
140 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
142 /* Load a firmware file */
143 ret = request_firmware(&firmware, fw_path, priv->pdev);
145 pr_err("Can't load firmware file %s.\n", fw_path);
149 buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
151 pr_err("Can't allocate firmware load buffer.\n");
156 /* Check if the bootloader is ready */
157 for (i = 0; i < 100; i += 1 + i / 2) {
158 APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
159 if (val32 == DOWNLOAD_I_AM_HERE)
162 } /* End of for loop */
164 if (val32 != DOWNLOAD_I_AM_HERE) {
165 pr_err("Bootloader is not ready.\n");
170 /* Calculcate number of download blocks */
171 num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
173 /* Updating the length in Download Ctrl Area */
174 val32 = firmware->size; /* Explicit cast from size_t to u32 */
175 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, val32);
177 /* Firmware downloading loop */
178 for (block = 0; block < num_blocks; block++) {
182 /* check the download status */
183 APB_READ(DOWNLOAD_STATUS_REG, val32);
184 if (val32 != DOWNLOAD_PENDING) {
185 pr_err("Bootloader reported error %d.\n", val32);
190 /* loop until put - get <= 24K */
191 for (i = 0; i < 100; i++) {
192 APB_READ(DOWNLOAD_GET_REG, get);
194 (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
199 if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
200 pr_err("Timeout waiting for FIFO.\n");
205 /* calculate the block size */
206 tx_size = block_size = min((size_t)(firmware->size - put),
207 (size_t)DOWNLOAD_BLOCK_SIZE);
209 memcpy(buf, &firmware->data[put], block_size);
210 if (block_size < DOWNLOAD_BLOCK_SIZE) {
211 memset(&buf[block_size], 0,
212 DOWNLOAD_BLOCK_SIZE - block_size);
213 tx_size = DOWNLOAD_BLOCK_SIZE;
216 /* send the block to sram */
217 ret = cw1200_apb_write(priv,
218 CW1200_APB(DOWNLOAD_FIFO_OFFSET +
219 (put & (DOWNLOAD_FIFO_SIZE - 1))),
222 pr_err("Can't write firmware block @ %d!\n",
223 put & (DOWNLOAD_FIFO_SIZE - 1));
227 /* update the put register */
229 APB_WRITE(DOWNLOAD_PUT_REG, put);
230 } /* End of firmware download loop */
232 /* Wait for the download completion */
233 for (i = 0; i < 300; i += 1 + i / 2) {
234 APB_READ(DOWNLOAD_STATUS_REG, val32);
235 if (val32 != DOWNLOAD_PENDING)
239 if (val32 != DOWNLOAD_SUCCESS) {
240 pr_err("Wait for download completion failed: 0x%.8X\n", val32);
244 pr_info("Firmware download completed.\n");
251 release_firmware(firmware);
261 static int config_reg_read(struct cw1200_common *priv, u32 *val)
263 switch (priv->hw_type) {
264 case HIF_9000_SILICON_VERSATILE: {
266 int ret = cw1200_reg_read_16(priv,
267 ST90TDS_CONFIG_REG_ID,
274 case HIF_8601_VERSATILE:
275 case HIF_8601_SILICON:
277 cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
283 static int config_reg_write(struct cw1200_common *priv, u32 val)
285 switch (priv->hw_type) {
286 case HIF_9000_SILICON_VERSATILE:
287 return cw1200_reg_write_16(priv,
288 ST90TDS_CONFIG_REG_ID,
290 case HIF_8601_VERSATILE:
291 case HIF_8601_SILICON:
293 return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
299 int cw1200_load_firmware(struct cw1200_common *priv)
305 int major_revision = -1;
307 /* Read CONFIG Register */
308 ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
310 pr_err("Can't read config register.\n");
314 if (val32 == 0 || val32 == 0xffffffff) {
315 pr_err("Bad config register value (0x%08x)\n", val32);
320 priv->hw_type = cw1200_get_hw_type(val32, &major_revision);
321 if (priv->hw_type < 0) {
322 pr_err("Can't deduce hardware type.\n");
327 /* Set DPLL Reg value, and read back to confirm writes work */
328 ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
329 cw1200_dpll_from_clk(priv->hw_refclk));
331 pr_err("Can't write DPLL register.\n");
337 ret = cw1200_reg_read_32(priv,
338 ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
340 pr_err("Can't read DPLL register.\n");
344 if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
345 pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
346 cw1200_dpll_from_clk(priv->hw_refclk), val32);
351 /* Set wakeup bit in device */
352 ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
354 pr_err("set_wakeup: can't read control register.\n");
358 ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
359 val16 | ST90TDS_CONT_WUP_BIT);
361 pr_err("set_wakeup: can't write control register.\n");
365 /* Wait for wakeup */
366 for (i = 0; i < 300; i += (1 + i / 2)) {
367 ret = cw1200_reg_read_16(priv,
368 ST90TDS_CONTROL_REG_ID, &val16);
370 pr_err("wait_for_wakeup: can't read control register.\n");
374 if (val16 & ST90TDS_CONT_RDY_BIT)
380 if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
381 pr_err("wait_for_wakeup: device is not responding.\n");
386 switch (major_revision) {
388 /* CW1200 Hardware detection logic : Check for CUT1.1 */
389 ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
391 pr_err("HW detection: can't read CUT ID.\n");
396 case CW1200_CUT_11_ID_STR:
397 pr_info("CW1x00 Cut 1.1 silicon detected.\n");
398 priv->hw_revision = CW1200_HW_REV_CUT11;
401 pr_info("CW1x00 Cut 1.0 silicon detected.\n");
402 priv->hw_revision = CW1200_HW_REV_CUT10;
406 /* According to ST-E, CUT<2.0 has busted BA TID0-3.
407 Just disable it entirely...
409 priv->ba_rx_tid_mask = 0;
410 priv->ba_tx_tid_mask = 0;
414 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
416 pr_err("(1) HW detection: can't read CUT ID\n");
419 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
421 pr_err("(2) HW detection: can't read CUT ID.\n");
425 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
427 pr_err("(3) HW detection: can't read CUT ID.\n");
431 if (ar1 == CW1200_CUT_22_ID_STR1 &&
432 ar2 == CW1200_CUT_22_ID_STR2 &&
433 ar3 == CW1200_CUT_22_ID_STR3) {
434 pr_info("CW1x00 Cut 2.2 silicon detected.\n");
435 priv->hw_revision = CW1200_HW_REV_CUT22;
437 pr_info("CW1x00 Cut 2.0 silicon detected.\n");
438 priv->hw_revision = CW1200_HW_REV_CUT20;
443 pr_info("CW1x60 silicon detected.\n");
444 priv->hw_revision = CW1X60_HW_REV;
447 pr_err("Unsupported silicon major revision %d.\n",
453 /* Checking for access mode */
454 ret = config_reg_read(priv, &val32);
456 pr_err("Can't read config register.\n");
460 if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
461 pr_err("Device is already in QUEUE mode!\n");
466 switch (priv->hw_type) {
467 case HIF_8601_SILICON:
468 if (priv->hw_revision == CW1X60_HW_REV) {
469 pr_err("Can't handle CW1160/1260 firmware load yet.\n");
473 ret = cw1200_load_firmware_cw1200(priv);
476 pr_err("Can't perform firmware load for hw type %d.\n",
482 pr_err("Firmware load error.\n");
486 /* Enable interrupt signalling */
487 priv->hwbus_ops->lock(priv->hwbus_priv);
488 ret = __cw1200_irq_enable(priv, 1);
489 priv->hwbus_ops->unlock(priv->hwbus_priv);
493 /* Configure device for MESSSAGE MODE */
494 ret = config_reg_read(priv, &val32);
496 pr_err("Can't read config register.\n");
499 ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
501 pr_err("Can't write config register.\n");
505 /* Unless we read the CONFIG Register we are
506 * not able to get an interrupt
509 config_reg_read(priv, &val32);
515 /* Disable interrupt signalling */
516 priv->hwbus_ops->lock(priv->hwbus_priv);
517 ret = __cw1200_irq_enable(priv, 0);
518 priv->hwbus_ops->unlock(priv->hwbus_priv);