1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 Intel Deutschland GmbH
38 * All rights reserved.
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
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54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
78 #include "iwl-trans.h"
82 #include "iwl-agn-hw.h"
83 #include "iwl-fw-error-dump.h"
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
95 if (!trans_pcie->fw_mon_page)
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
110 struct page *page = NULL;
116 /* default max_power is maximum */
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
135 for (power = max_power; power >= 11; power--) {
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
158 if (WARN_ON_ONCE(!page))
161 if (power != max_power)
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
188 if (trans->cfg->apmg_not_supported)
191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
247 /* Disable L0S exit timer (platform NMI Work/Around) */
248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
269 iwl_pcie_apm_config(trans);
271 /* Configure analog phase-lock-loop before activating to D0A */
272 if (trans->cfg->base_params->pll_cfg_val)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
274 trans->cfg->base_params->pll_cfg_val);
277 * Set "initialization complete" bit to move adapter from
278 * D0U* --> D0A* (powered-up active) state.
280 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
283 * Wait for clock stabilization; once stabilized, access to
284 * device-internal resources is supported, e.g. iwl_write_prph()
285 * and accesses to uCode SRAM.
287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
291 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
295 if (trans->cfg->host_interrupt_operation_mode) {
297 * This is a bit of an abuse - This is needed for 7260 / 3160
298 * only check host_interrupt_operation_mode even if this is
299 * not related to host_interrupt_operation_mode.
301 * Enable the oscillator to count wake up time for L1 exit. This
302 * consumes slightly more power (100uA) - but allows to be sure
303 * that we wake up from L1 on time.
305 * This looks weird: read twice the same register, discard the
306 * value, set a bit, and yet again, read that same register
307 * just to discard the value. But that's the way the hardware
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_read_prph(trans, OSC_CLK);
312 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
313 iwl_read_prph(trans, OSC_CLK);
314 iwl_read_prph(trans, OSC_CLK);
318 * Enable DMA clock and wait for it to stabilize.
320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
321 * bits do not disable clocks. This preserves any hardware
322 * bits already set by default in "CLK_CTRL_REG" after reset.
324 if (!trans->cfg->apmg_not_supported) {
325 iwl_write_prph(trans, APMG_CLK_EN_REG,
326 APMG_CLK_VAL_DMA_CLK_RQT);
329 /* Disable L1-Active */
330 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
333 /* Clear the interrupt in APMG if the NIC is in RFKILL */
334 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
335 APMG_RTC_INT_STT_RFKILL);
338 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
345 * Enable LP XTAL to avoid HW bug where device may consume much power if
346 * FW is not loaded after device reset. LP XTAL is disabled by default
347 * after device HW reset. Do it only if XTAL is fed by internal source.
348 * Configure device's "persistence" mode to avoid resetting XTAL again when
349 * SHRD_HW_RST occurs in S3.
351 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
355 u32 apmg_xtal_cfg_reg;
359 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
360 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
362 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
363 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
368 * Set "initialization complete" bit to move adapter from
369 * D0U* --> D0A* (powered-up active) state.
371 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
374 * Wait for clock stabilization; once stabilized, access to
375 * device-internal resources is possible.
377 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
379 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
381 if (WARN_ON(ret < 0)) {
382 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
383 /* Release XTAL ON request */
384 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
385 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
390 * Clear "disable persistence" to avoid LP XTAL resetting when
391 * SHRD_HW_RST is applied in S3.
393 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
394 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
397 * Force APMG XTAL to be active to prevent its disabling by HW
398 * caused by APMG idle state.
400 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
401 SHR_APMG_XTAL_CFG_REG);
402 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
404 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
407 * Reset entire device again - do controller reset (results in
408 * SHRD_HW_RST). Turn MAC off before proceeding.
410 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
414 /* Enable LP XTAL by indirect access through CSR */
415 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
416 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
417 SHR_APMG_GP1_WF_XTAL_LP_EN |
418 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
420 /* Clear delay line clock power up */
421 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
422 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
423 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
426 * Enable persistence mode to avoid LP XTAL resetting when
427 * SHRD_HW_RST is applied in S3.
429 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
430 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
433 * Clear "initialization complete" bit to move adapter from
434 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
436 iwl_clear_bit(trans, CSR_GP_CNTRL,
437 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
439 /* Activates XTAL resources monitor */
440 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
441 CSR_MONITOR_XTAL_RESOURCES);
443 /* Release XTAL ON request */
444 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
445 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
448 /* Release APMG XTAL */
449 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
451 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
454 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
458 /* stop device's busmaster DMA activity */
459 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
461 ret = iwl_poll_bit(trans, CSR_RESET,
462 CSR_RESET_REG_FLAG_MASTER_DISABLED,
463 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
465 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
467 IWL_DEBUG_INFO(trans, "stop master\n");
472 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
474 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
477 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
478 iwl_pcie_apm_init(trans);
480 /* inform ME that we are leaving */
481 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
482 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
483 APMG_PCIDEV_STT_VAL_WAKE_ME);
484 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
485 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
486 CSR_RESET_LINK_PWR_MGMT_DISABLED);
487 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
488 CSR_HW_IF_CONFIG_REG_PREPARE |
489 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
491 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
492 CSR_RESET_LINK_PWR_MGMT_DISABLED);
497 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
499 /* Stop device's DMA activity */
500 iwl_pcie_apm_stop_master(trans);
502 if (trans->cfg->lp_xtal_workaround) {
503 iwl_pcie_apm_lp_xtal_enable(trans);
507 /* Reset the entire device */
508 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
513 * Clear "initialization complete" bit to move adapter from
514 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
516 iwl_clear_bit(trans, CSR_GP_CNTRL,
517 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
520 static int iwl_pcie_nic_init(struct iwl_trans *trans)
522 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
525 spin_lock(&trans_pcie->irq_lock);
526 iwl_pcie_apm_init(trans);
528 spin_unlock(&trans_pcie->irq_lock);
530 iwl_pcie_set_pwr(trans, false);
532 iwl_op_mode_nic_config(trans->op_mode);
534 /* Allocate the RX queue, or reset if it is already allocated */
535 iwl_pcie_rx_init(trans);
537 /* Allocate or reset and init all Tx and Command queues */
538 if (iwl_pcie_tx_init(trans))
541 if (trans->cfg->base_params->shadow_reg_enable) {
542 /* enable shadow regs in HW */
543 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
544 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
550 #define HW_READY_TIMEOUT (50)
552 /* Note: returns poll_bit return value, which is >= 0 if success */
553 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
557 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
560 /* See if we got it */
561 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
562 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
563 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
567 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
569 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
573 /* Note: returns standard 0/-ERROR code */
574 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
580 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
582 ret = iwl_pcie_set_hw_ready(trans);
583 /* If the card is ready, exit 0 */
587 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
588 CSR_RESET_LINK_PWR_MGMT_DISABLED);
591 for (iter = 0; iter < 10; iter++) {
592 /* If HW is not ready, prepare the conditions to check again */
593 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
594 CSR_HW_IF_CONFIG_REG_PREPARE);
597 ret = iwl_pcie_set_hw_ready(trans);
601 usleep_range(200, 1000);
603 } while (t < 150000);
607 IWL_ERR(trans, "Couldn't prepare the card\n");
615 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
616 dma_addr_t phy_addr, u32 byte_cnt)
618 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
621 trans_pcie->ucode_write_complete = false;
623 iwl_write_direct32(trans,
624 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
625 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
627 iwl_write_direct32(trans,
628 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
631 iwl_write_direct32(trans,
632 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
633 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
635 iwl_write_direct32(trans,
636 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
637 (iwl_get_dma_hi_addr(phy_addr)
638 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
640 iwl_write_direct32(trans,
641 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
642 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
643 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
644 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
646 iwl_write_direct32(trans,
647 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
648 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
649 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
650 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
652 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
653 trans_pcie->ucode_write_complete, 5 * HZ);
655 IWL_ERR(trans, "Failed to load firmware chunk!\n");
662 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
663 const struct fw_desc *section)
667 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
670 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
673 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
674 GFP_KERNEL | __GFP_NOWARN);
676 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
677 chunk_sz = PAGE_SIZE;
678 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
679 &p_addr, GFP_KERNEL);
684 for (offset = 0; offset < section->len; offset += chunk_sz) {
685 u32 copy_size, dst_addr;
686 bool extended_addr = false;
688 copy_size = min_t(u32, chunk_sz, section->len - offset);
689 dst_addr = section->offset + offset;
691 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
692 dst_addr <= IWL_FW_MEM_EXTENDED_END)
693 extended_addr = true;
696 iwl_set_bits_prph(trans, LMPM_CHICK,
697 LMPM_CHICK_EXTENDED_ADDR_SPACE);
699 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
700 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
704 iwl_clear_bits_prph(trans, LMPM_CHICK,
705 LMPM_CHICK_EXTENDED_ADDR_SPACE);
709 "Could not load the [%d] uCode section\n",
715 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
720 * Driver Takes the ownership on secure machine before FW load
721 * and prevent race with the BT load.
722 * W/A for ROM bug. (should be remove in the next Si step)
724 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
726 u32 val, loop = 1000;
729 * Check the RSA semaphore is accessible.
730 * If the HW isn't locked and the rsa semaphore isn't accessible,
733 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
734 if (val & (BIT(1) | BIT(17))) {
736 "can't access the RSA semaphore it is write protected\n");
740 /* take ownership on the AUX IF */
741 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
742 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
745 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
746 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
748 iwl_write_prph(trans, RSA_ENABLE, 0);
756 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
760 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
761 const struct fw_img *image,
763 int *first_ucode_section)
766 int i, ret = 0, sec_num = 0x1;
767 u32 val, last_read_idx = 0;
771 *first_ucode_section = 0;
774 (*first_ucode_section)++;
777 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
781 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
783 * PAGING_SEPARATOR_SECTION delimiter - separate between
784 * CPU2 non paged to CPU2 paging sec.
786 if (!image->sec[i].data ||
787 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
788 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
790 "Break since Data not valid or Empty section, sec = %d\n",
795 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
799 /* Notify the ucode of the loaded section number and status */
800 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
801 val = val | (sec_num << shift_param);
802 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
803 sec_num = (sec_num << 1) | 0x1;
806 *first_ucode_section = last_read_idx;
809 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
811 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
816 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
817 const struct fw_img *image,
819 int *first_ucode_section)
823 u32 last_read_idx = 0;
827 *first_ucode_section = 0;
830 (*first_ucode_section)++;
833 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
837 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
839 * PAGING_SEPARATOR_SECTION delimiter - separate between
840 * CPU2 non paged to CPU2 paging sec.
842 if (!image->sec[i].data ||
843 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
844 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
846 "Break since Data not valid or Empty section, sec = %d\n",
851 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
856 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
857 iwl_set_bits_prph(trans,
858 CSR_UCODE_LOAD_STATUS_ADDR,
859 (LMPM_CPU_UCODE_LOADING_COMPLETED |
860 LMPM_CPU_HDRS_LOADING_COMPLETED |
861 LMPM_CPU_UCODE_LOADING_STARTED) <<
864 *first_ucode_section = last_read_idx;
869 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
871 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
872 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
877 "DBG DEST version is %d - expect issues\n",
880 IWL_INFO(trans, "Applying debug destination %s\n",
881 get_fw_dbg_mode_string(dest->monitor_mode));
883 if (dest->monitor_mode == EXTERNAL_MODE)
884 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
886 IWL_WARN(trans, "PCI should have external buffer debug\n");
888 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
889 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
890 u32 val = le32_to_cpu(dest->reg_ops[i].val);
892 switch (dest->reg_ops[i].op) {
894 iwl_write32(trans, addr, val);
897 iwl_set_bit(trans, addr, BIT(val));
900 iwl_clear_bit(trans, addr, BIT(val));
903 iwl_write_prph(trans, addr, val);
906 iwl_set_bits_prph(trans, addr, BIT(val));
909 iwl_clear_bits_prph(trans, addr, BIT(val));
912 if (iwl_read_prph(trans, addr) & BIT(val)) {
914 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
920 IWL_ERR(trans, "FW debug - unknown OP %d\n",
921 dest->reg_ops[i].op);
927 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
928 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
929 trans_pcie->fw_mon_phys >> dest->base_shift);
930 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
931 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
932 (trans_pcie->fw_mon_phys +
933 trans_pcie->fw_mon_size - 256) >>
936 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
937 (trans_pcie->fw_mon_phys +
938 trans_pcie->fw_mon_size) >>
943 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
944 const struct fw_img *image)
946 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
948 int first_ucode_section;
950 IWL_DEBUG_FW(trans, "working with %s CPU\n",
951 image->is_dual_cpus ? "Dual" : "Single");
953 /* load to FW the binary non secured sections of CPU1 */
954 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
958 if (image->is_dual_cpus) {
959 /* set CPU2 header address */
960 iwl_write_prph(trans,
961 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
962 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
964 /* load to FW the binary sections of CPU2 */
965 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
966 &first_ucode_section);
971 /* supported for 7000 only for the moment */
972 if (iwlwifi_mod_params.fw_monitor &&
973 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
974 iwl_pcie_alloc_fw_monitor(trans, 0);
976 if (trans_pcie->fw_mon_size) {
977 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
978 trans_pcie->fw_mon_phys >> 4);
979 iwl_write_prph(trans, MON_BUFF_END_ADDR,
980 (trans_pcie->fw_mon_phys +
981 trans_pcie->fw_mon_size) >> 4);
983 } else if (trans->dbg_dest_tlv) {
984 iwl_pcie_apply_destination(trans);
987 /* release CPU reset */
988 iwl_write32(trans, CSR_RESET, 0);
993 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
994 const struct fw_img *image)
997 int first_ucode_section;
999 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000 image->is_dual_cpus ? "Dual" : "Single");
1002 if (trans->dbg_dest_tlv)
1003 iwl_pcie_apply_destination(trans);
1005 /* TODO: remove in the next Si step */
1006 ret = iwl_pcie_rsa_race_bug_wa(trans);
1010 /* configure the ucode to be ready to get the secured image */
1011 /* release CPU reset */
1012 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1014 /* load to FW the binary Secured sections of CPU1 */
1015 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1016 &first_ucode_section);
1020 /* load to FW the binary sections of CPU2 */
1021 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1022 &first_ucode_section);
1025 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1026 const struct fw_img *fw, bool run_in_rfkill)
1028 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1032 mutex_lock(&trans_pcie->mutex);
1034 /* Someone called stop_device, don't try to start_fw */
1035 if (trans_pcie->is_down) {
1037 "Can't start_fw since the HW hasn't been started\n");
1042 /* This may fail if AMT took ownership of the device */
1043 if (iwl_pcie_prepare_card_hw(trans)) {
1044 IWL_WARN(trans, "Exit HW not ready\n");
1049 iwl_enable_rfkill_int(trans);
1051 /* If platform's RF_KILL switch is NOT set to KILL */
1052 hw_rfkill = iwl_is_rfkill_set(trans);
1054 set_bit(STATUS_RFKILL, &trans->status);
1056 clear_bit(STATUS_RFKILL, &trans->status);
1057 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1058 if (hw_rfkill && !run_in_rfkill) {
1063 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1065 ret = iwl_pcie_nic_init(trans);
1067 IWL_ERR(trans, "Unable to init nic\n");
1071 /* make sure rfkill handshake bits are cleared */
1072 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1073 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1074 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1076 /* clear (again), then enable host interrupts */
1077 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1078 iwl_enable_interrupts(trans);
1080 /* really make sure rfkill handshake bits are cleared */
1081 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1082 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1084 /* Load the given image to the HW */
1085 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1086 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1088 ret = iwl_pcie_load_given_ucode(trans, fw);
1091 mutex_unlock(&trans_pcie->mutex);
1095 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1097 iwl_pcie_reset_ict(trans);
1098 iwl_pcie_tx_start(trans, scd_addr);
1101 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1104 bool hw_rfkill, was_hw_rfkill;
1106 lockdep_assert_held(&trans_pcie->mutex);
1108 if (trans_pcie->is_down)
1111 trans_pcie->is_down = true;
1113 was_hw_rfkill = iwl_is_rfkill_set(trans);
1115 /* tell the device to stop sending interrupts */
1116 spin_lock(&trans_pcie->irq_lock);
1117 iwl_disable_interrupts(trans);
1118 spin_unlock(&trans_pcie->irq_lock);
1120 /* device going down, Stop using ICT table */
1121 iwl_pcie_disable_ict(trans);
1124 * If a HW restart happens during firmware loading,
1125 * then the firmware loading might call this function
1126 * and later it might be called again due to the
1127 * restart. So don't process again if the device is
1130 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1131 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1132 iwl_pcie_tx_stop(trans);
1133 iwl_pcie_rx_stop(trans);
1135 /* Power-down device's busmaster DMA clocks */
1136 if (!trans->cfg->apmg_not_supported) {
1137 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1138 APMG_CLK_VAL_DMA_CLK_RQT);
1143 /* Make sure (redundant) we've released our request to stay awake */
1144 iwl_clear_bit(trans, CSR_GP_CNTRL,
1145 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1147 /* Stop the device, and put it in low power state */
1148 iwl_pcie_apm_stop(trans, false);
1150 /* stop and reset the on-board processor */
1151 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1155 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1156 * This is a bug in certain verions of the hardware.
1157 * Certain devices also keep sending HW RF kill interrupt all
1158 * the time, unless the interrupt is ACKed even if the interrupt
1159 * should be masked. Re-ACK all the interrupts here.
1161 spin_lock(&trans_pcie->irq_lock);
1162 iwl_disable_interrupts(trans);
1163 spin_unlock(&trans_pcie->irq_lock);
1166 /* clear all status bits */
1167 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1168 clear_bit(STATUS_INT_ENABLED, &trans->status);
1169 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1170 clear_bit(STATUS_RFKILL, &trans->status);
1173 * Even if we stop the HW, we still want the RF kill
1176 iwl_enable_rfkill_int(trans);
1179 * Check again since the RF kill state may have changed while
1180 * all the interrupts were disabled, in this case we couldn't
1181 * receive the RF kill interrupt and update the state in the
1183 * Don't call the op_mode if the rkfill state hasn't changed.
1184 * This allows the op_mode to call stop_device from the rfkill
1185 * notification without endless recursion. Under very rare
1186 * circumstances, we might have a small recursion if the rfkill
1187 * state changed exactly now while we were called from stop_device.
1188 * This is very unlikely but can happen and is supported.
1190 hw_rfkill = iwl_is_rfkill_set(trans);
1192 set_bit(STATUS_RFKILL, &trans->status);
1194 clear_bit(STATUS_RFKILL, &trans->status);
1195 if (hw_rfkill != was_hw_rfkill)
1196 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1198 /* re-take ownership to prevent other users from stealing the deivce */
1199 iwl_pcie_prepare_card_hw(trans);
1202 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1204 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1206 mutex_lock(&trans_pcie->mutex);
1207 _iwl_trans_pcie_stop_device(trans, low_power);
1208 mutex_unlock(&trans_pcie->mutex);
1211 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1213 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1214 IWL_TRANS_GET_PCIE_TRANS(trans);
1216 lockdep_assert_held(&trans_pcie->mutex);
1218 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1219 _iwl_trans_pcie_stop_device(trans, true);
1222 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1225 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1228 /* Enable persistence mode to avoid reset */
1229 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1230 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1233 iwl_disable_interrupts(trans);
1236 * in testing mode, the host stays awake and the
1237 * hardware won't be reset (not even partially)
1242 iwl_pcie_disable_ict(trans);
1244 synchronize_irq(trans_pcie->pci_dev->irq);
1246 iwl_clear_bit(trans, CSR_GP_CNTRL,
1247 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1248 iwl_clear_bit(trans, CSR_GP_CNTRL,
1249 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1253 * reset TX queues -- some of their registers reset during S3
1254 * so if we don't reset everything here the D3 image would try
1255 * to execute some invalid memory upon resume
1257 iwl_trans_pcie_tx_reset(trans);
1260 iwl_pcie_set_pwr(trans, true);
1263 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1264 enum iwl_d3_status *status,
1265 bool test, bool reset)
1271 iwl_enable_interrupts(trans);
1272 *status = IWL_D3_STATUS_ALIVE;
1277 * Also enables interrupts - none will happen as the device doesn't
1278 * know we're waking it up, only when the opmode actually tells it
1281 iwl_pcie_reset_ict(trans);
1283 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1284 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1286 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1289 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1290 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1291 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1294 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1298 iwl_pcie_set_pwr(trans, false);
1301 iwl_clear_bit(trans, CSR_GP_CNTRL,
1302 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1304 iwl_trans_pcie_tx_reset(trans);
1306 ret = iwl_pcie_rx_init(trans);
1309 "Failed to resume the device (RX reset)\n");
1314 val = iwl_read32(trans, CSR_RESET);
1315 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1316 *status = IWL_D3_STATUS_RESET;
1318 *status = IWL_D3_STATUS_ALIVE;
1323 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1329 lockdep_assert_held(&trans_pcie->mutex);
1331 err = iwl_pcie_prepare_card_hw(trans);
1333 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1337 /* Reset the entire device */
1338 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1340 usleep_range(10, 15);
1342 iwl_pcie_apm_init(trans);
1344 /* From now on, the op_mode will be kept updated about RF kill state */
1345 iwl_enable_rfkill_int(trans);
1347 /* Set is_down to false here so that...*/
1348 trans_pcie->is_down = false;
1350 hw_rfkill = iwl_is_rfkill_set(trans);
1352 set_bit(STATUS_RFKILL, &trans->status);
1354 clear_bit(STATUS_RFKILL, &trans->status);
1355 /* ... rfkill can call stop_device and set it false if needed */
1356 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1358 /* Make sure we sync here, because we'll need full access later */
1360 pm_runtime_resume(trans->dev);
1365 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1367 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1370 mutex_lock(&trans_pcie->mutex);
1371 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1372 mutex_unlock(&trans_pcie->mutex);
1377 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1379 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1381 mutex_lock(&trans_pcie->mutex);
1383 /* disable interrupts - don't enable HW RF kill interrupt */
1384 spin_lock(&trans_pcie->irq_lock);
1385 iwl_disable_interrupts(trans);
1386 spin_unlock(&trans_pcie->irq_lock);
1388 iwl_pcie_apm_stop(trans, true);
1390 spin_lock(&trans_pcie->irq_lock);
1391 iwl_disable_interrupts(trans);
1392 spin_unlock(&trans_pcie->irq_lock);
1394 iwl_pcie_disable_ict(trans);
1396 mutex_unlock(&trans_pcie->mutex);
1398 synchronize_irq(trans_pcie->pci_dev->irq);
1401 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1403 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1406 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1408 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1411 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1413 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1416 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1418 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1419 ((reg & 0x000FFFFF) | (3 << 24)));
1420 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1423 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1426 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1427 ((addr & 0x000FFFFF) | (3 << 24)));
1428 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1431 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1432 const struct iwl_trans_config *trans_cfg)
1434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1436 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1437 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1438 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1439 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1440 trans_pcie->n_no_reclaim_cmds = 0;
1442 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1443 if (trans_pcie->n_no_reclaim_cmds)
1444 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1445 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1447 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1448 trans_pcie->rx_page_order =
1449 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1451 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header;
1452 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1453 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1454 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1456 trans->command_groups = trans_cfg->command_groups;
1457 trans->command_groups_size = trans_cfg->command_groups_size;
1459 /* init ref_count to 1 (should be cleared when ucode is loaded) */
1460 trans_pcie->ref_count = 1;
1462 /* Initialize NAPI here - it should be before registering to mac80211
1463 * in the opmode but after the HW struct is allocated.
1464 * As this function may be called again in some corner cases don't
1465 * do anything if NAPI was already initialized.
1467 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1468 init_dummy_netdev(&trans_pcie->napi_dev);
1471 void iwl_trans_pcie_free(struct iwl_trans *trans)
1473 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476 /* TODO: check if this is really needed */
1477 pm_runtime_disable(trans->dev);
1479 synchronize_irq(trans_pcie->pci_dev->irq);
1481 iwl_pcie_tx_free(trans);
1482 iwl_pcie_rx_free(trans);
1484 free_irq(trans_pcie->pci_dev->irq, trans);
1485 iwl_pcie_free_ict(trans);
1487 pci_disable_msi(trans_pcie->pci_dev);
1488 iounmap(trans_pcie->hw_base);
1489 pci_release_regions(trans_pcie->pci_dev);
1490 pci_disable_device(trans_pcie->pci_dev);
1492 iwl_pcie_free_fw_monitor(trans);
1494 for_each_possible_cpu(i) {
1495 struct iwl_tso_hdr_page *p =
1496 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1499 __free_page(p->page);
1502 free_percpu(trans_pcie->tso_hdr_page);
1503 iwl_trans_free(trans);
1506 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1509 set_bit(STATUS_TPOWER_PMI, &trans->status);
1511 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1514 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1515 unsigned long *flags)
1518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1520 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1522 if (trans_pcie->cmd_hold_nic_awake)
1525 /* this bit wakes up the NIC */
1526 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1527 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1528 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1532 * These bits say the device is running, and should keep running for
1533 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1534 * but they do not indicate that embedded SRAM is restored yet;
1535 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1536 * to/from host DRAM when sleeping/waking for power-saving.
1537 * Each direction takes approximately 1/4 millisecond; with this
1538 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1539 * series of register accesses are expected (e.g. reading Event Log),
1540 * to keep device from sleeping.
1542 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1543 * SRAM is okay/restored. We don't check that here because this call
1544 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1545 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1547 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1548 * and do not save/restore SRAM when power cycling.
1550 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1551 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1552 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1553 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1554 if (unlikely(ret < 0)) {
1555 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1557 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1558 iwl_read32(trans, CSR_GP_CNTRL));
1559 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1565 * Fool sparse by faking we release the lock - sparse will
1566 * track nic_access anyway.
1568 __release(&trans_pcie->reg_lock);
1572 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1573 unsigned long *flags)
1575 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1577 lockdep_assert_held(&trans_pcie->reg_lock);
1580 * Fool sparse by faking we acquiring the lock - sparse will
1581 * track nic_access anyway.
1583 __acquire(&trans_pcie->reg_lock);
1585 if (trans_pcie->cmd_hold_nic_awake)
1588 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1589 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1591 * Above we read the CSR_GP_CNTRL register, which will flush
1592 * any previous writes, but we need the write that clears the
1593 * MAC_ACCESS_REQ bit to be performed before any other writes
1594 * scheduled on different CPUs (after we drop reg_lock).
1598 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1601 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1602 void *buf, int dwords)
1604 unsigned long flags;
1608 if (iwl_trans_grab_nic_access(trans, &flags)) {
1609 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1610 for (offs = 0; offs < dwords; offs++)
1611 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1612 iwl_trans_release_nic_access(trans, &flags);
1619 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1620 const void *buf, int dwords)
1622 unsigned long flags;
1624 const u32 *vals = buf;
1626 if (iwl_trans_grab_nic_access(trans, &flags)) {
1627 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1628 for (offs = 0; offs < dwords; offs++)
1629 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1630 vals ? vals[offs] : 0);
1631 iwl_trans_release_nic_access(trans, &flags);
1638 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1642 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1645 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1646 struct iwl_txq *txq = &trans_pcie->txq[queue];
1649 spin_lock_bh(&txq->lock);
1653 if (txq->frozen == freeze)
1656 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1657 freeze ? "Freezing" : "Waking", queue);
1659 txq->frozen = freeze;
1661 if (txq->q.read_ptr == txq->q.write_ptr)
1665 if (unlikely(time_after(now,
1666 txq->stuck_timer.expires))) {
1668 * The timer should have fired, maybe it is
1669 * spinning right now on the lock.
1673 /* remember how long until the timer fires */
1674 txq->frozen_expiry_remainder =
1675 txq->stuck_timer.expires - now;
1676 del_timer(&txq->stuck_timer);
1681 * Wake a non-empty queue -> arm timer with the
1682 * remainder before it froze
1684 mod_timer(&txq->stuck_timer,
1685 now + txq->frozen_expiry_remainder);
1688 spin_unlock_bh(&txq->lock);
1692 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1697 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1698 struct iwl_txq *txq = &trans_pcie->txq[i];
1700 if (i == trans_pcie->cmd_queue)
1703 spin_lock_bh(&txq->lock);
1705 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1708 iwl_write32(trans, HBUS_TARG_WRPTR,
1709 txq->q.write_ptr | (i << 8));
1715 spin_unlock_bh(&txq->lock);
1719 #define IWL_FLUSH_WAIT_MS 2000
1721 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1723 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1724 struct iwl_txq *txq;
1725 struct iwl_queue *q;
1727 unsigned long now = jiffies;
1732 /* waiting for all the tx frames complete might take a while */
1733 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1736 if (cnt == trans_pcie->cmd_queue)
1738 if (!test_bit(cnt, trans_pcie->queue_used))
1740 if (!(BIT(cnt) & txq_bm))
1743 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1744 txq = &trans_pcie->txq[cnt];
1746 wr_ptr = ACCESS_ONCE(q->write_ptr);
1748 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1749 !time_after(jiffies,
1750 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1751 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1753 if (WARN_ONCE(wr_ptr != write_ptr,
1754 "WR pointer moved while flushing %d -> %d\n",
1760 if (q->read_ptr != q->write_ptr) {
1762 "fail to flush all tx fifo queues Q %d\n", cnt);
1766 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1772 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1773 txq->q.read_ptr, txq->q.write_ptr);
1775 scd_sram_addr = trans_pcie->scd_base_addr +
1776 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1777 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1779 iwl_print_hex_error(trans, buf, sizeof(buf));
1781 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1782 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1783 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1785 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1786 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1787 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1788 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1790 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1791 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1794 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1796 tbl_dw = tbl_dw & 0x0000FFFF;
1799 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1800 cnt, active ? "" : "in", fifo, tbl_dw,
1801 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1802 (TFD_QUEUE_SIZE_MAX - 1),
1803 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1809 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1810 u32 mask, u32 value)
1812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813 unsigned long flags;
1815 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1816 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1817 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1820 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1822 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1823 unsigned long flags;
1825 if (iwlwifi_mod_params.d0i3_disable)
1828 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1829 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1830 trans_pcie->ref_count++;
1831 pm_runtime_get(&trans_pcie->pci_dev->dev);
1832 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1835 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1837 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1838 unsigned long flags;
1840 if (iwlwifi_mod_params.d0i3_disable)
1843 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1844 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1845 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1846 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1849 trans_pcie->ref_count--;
1851 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
1852 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
1854 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1857 static const char *get_csr_string(int cmd)
1859 #define IWL_CMD(x) case x: return #x
1861 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1862 IWL_CMD(CSR_INT_COALESCING);
1864 IWL_CMD(CSR_INT_MASK);
1865 IWL_CMD(CSR_FH_INT_STATUS);
1866 IWL_CMD(CSR_GPIO_IN);
1868 IWL_CMD(CSR_GP_CNTRL);
1869 IWL_CMD(CSR_HW_REV);
1870 IWL_CMD(CSR_EEPROM_REG);
1871 IWL_CMD(CSR_EEPROM_GP);
1872 IWL_CMD(CSR_OTP_GP_REG);
1873 IWL_CMD(CSR_GIO_REG);
1874 IWL_CMD(CSR_GP_UCODE_REG);
1875 IWL_CMD(CSR_GP_DRIVER_REG);
1876 IWL_CMD(CSR_UCODE_DRV_GP1);
1877 IWL_CMD(CSR_UCODE_DRV_GP2);
1878 IWL_CMD(CSR_LED_REG);
1879 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1880 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1881 IWL_CMD(CSR_ANA_PLL_CFG);
1882 IWL_CMD(CSR_HW_REV_WA_REG);
1883 IWL_CMD(CSR_MONITOR_STATUS_REG);
1884 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1891 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1894 static const u32 csr_tbl[] = {
1895 CSR_HW_IF_CONFIG_REG,
1913 CSR_DRAM_INT_TBL_REG,
1914 CSR_GIO_CHICKEN_BITS,
1916 CSR_MONITOR_STATUS_REG,
1918 CSR_DBG_HPET_MEM_REG
1920 IWL_ERR(trans, "CSR values:\n");
1921 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1922 "CSR_INT_PERIODIC_REG)\n");
1923 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1924 IWL_ERR(trans, " %25s: 0X%08x\n",
1925 get_csr_string(csr_tbl[i]),
1926 iwl_read32(trans, csr_tbl[i]));
1930 #ifdef CONFIG_IWLWIFI_DEBUGFS
1931 /* create and remove of files */
1932 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1933 if (!debugfs_create_file(#name, mode, parent, trans, \
1934 &iwl_dbgfs_##name##_ops)) \
1938 /* file operation */
1939 #define DEBUGFS_READ_FILE_OPS(name) \
1940 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1941 .read = iwl_dbgfs_##name##_read, \
1942 .open = simple_open, \
1943 .llseek = generic_file_llseek, \
1946 #define DEBUGFS_WRITE_FILE_OPS(name) \
1947 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1948 .write = iwl_dbgfs_##name##_write, \
1949 .open = simple_open, \
1950 .llseek = generic_file_llseek, \
1953 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1954 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1955 .write = iwl_dbgfs_##name##_write, \
1956 .read = iwl_dbgfs_##name##_read, \
1957 .open = simple_open, \
1958 .llseek = generic_file_llseek, \
1961 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1962 char __user *user_buf,
1963 size_t count, loff_t *ppos)
1965 struct iwl_trans *trans = file->private_data;
1966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1967 struct iwl_txq *txq;
1968 struct iwl_queue *q;
1975 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1977 if (!trans_pcie->txq)
1980 buf = kzalloc(bufsz, GFP_KERNEL);
1984 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1985 txq = &trans_pcie->txq[cnt];
1987 pos += scnprintf(buf + pos, bufsz - pos,
1988 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1989 cnt, q->read_ptr, q->write_ptr,
1990 !!test_bit(cnt, trans_pcie->queue_used),
1991 !!test_bit(cnt, trans_pcie->queue_stopped),
1992 txq->need_update, txq->frozen,
1993 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1995 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2000 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2001 char __user *user_buf,
2002 size_t count, loff_t *ppos)
2004 struct iwl_trans *trans = file->private_data;
2005 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2007 int pos = 0, i, ret;
2008 size_t bufsz = sizeof(buf);
2010 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2012 if (!trans_pcie->rxq)
2015 buf = kzalloc(bufsz, GFP_KERNEL);
2019 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2020 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2022 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2024 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2026 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2028 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2030 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2032 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2035 pos += scnprintf(buf + pos, bufsz - pos,
2036 "\tclosed_rb_num: %u\n",
2037 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2040 pos += scnprintf(buf + pos, bufsz - pos,
2041 "\tclosed_rb_num: Not Allocated\n");
2044 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2050 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2051 char __user *user_buf,
2052 size_t count, loff_t *ppos)
2054 struct iwl_trans *trans = file->private_data;
2055 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2056 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2060 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2063 buf = kzalloc(bufsz, GFP_KERNEL);
2067 pos += scnprintf(buf + pos, bufsz - pos,
2068 "Interrupt Statistics Report:\n");
2070 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2072 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2074 if (isr_stats->sw || isr_stats->hw) {
2075 pos += scnprintf(buf + pos, bufsz - pos,
2076 "\tLast Restarting Code: 0x%X\n",
2077 isr_stats->err_code);
2079 #ifdef CONFIG_IWLWIFI_DEBUG
2080 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2082 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2085 pos += scnprintf(buf + pos, bufsz - pos,
2086 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2088 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2091 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2094 pos += scnprintf(buf + pos, bufsz - pos,
2095 "Rx command responses:\t\t %u\n", isr_stats->rx);
2097 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2100 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2101 isr_stats->unhandled);
2103 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2108 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2109 const char __user *user_buf,
2110 size_t count, loff_t *ppos)
2112 struct iwl_trans *trans = file->private_data;
2113 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2114 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2120 memset(buf, 0, sizeof(buf));
2121 buf_size = min(count, sizeof(buf) - 1);
2122 if (copy_from_user(buf, user_buf, buf_size))
2124 if (sscanf(buf, "%x", &reset_flag) != 1)
2126 if (reset_flag == 0)
2127 memset(isr_stats, 0, sizeof(*isr_stats));
2132 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2133 const char __user *user_buf,
2134 size_t count, loff_t *ppos)
2136 struct iwl_trans *trans = file->private_data;
2141 memset(buf, 0, sizeof(buf));
2142 buf_size = min(count, sizeof(buf) - 1);
2143 if (copy_from_user(buf, user_buf, buf_size))
2145 if (sscanf(buf, "%d", &csr) != 1)
2148 iwl_pcie_dump_csr(trans);
2153 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2154 char __user *user_buf,
2155 size_t count, loff_t *ppos)
2157 struct iwl_trans *trans = file->private_data;
2161 ret = iwl_dump_fh(trans, &buf);
2166 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2171 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2172 DEBUGFS_READ_FILE_OPS(fh_reg);
2173 DEBUGFS_READ_FILE_OPS(rx_queue);
2174 DEBUGFS_READ_FILE_OPS(tx_queue);
2175 DEBUGFS_WRITE_FILE_OPS(csr);
2177 /* Create the debugfs files and directories */
2178 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2180 struct dentry *dir = trans->dbgfs_dir;
2182 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2183 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2184 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2185 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2186 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2190 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2193 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2195 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2200 for (i = 0; i < IWL_NUM_OF_TBS; i++)
2201 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2206 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2207 struct iwl_fw_error_dump_data **data,
2208 int allocated_rb_nums)
2210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2211 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2212 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2213 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2214 u32 i, r, j, rb_len = 0;
2216 spin_lock(&rxq->lock);
2218 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2220 for (i = rxq->read, j = 0;
2221 i != r && j < allocated_rb_nums;
2222 i = (i + 1) & RX_QUEUE_MASK, j++) {
2223 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2224 struct iwl_fw_error_dump_rb *rb;
2226 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2229 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2231 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2232 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2233 rb = (void *)(*data)->data;
2234 rb->index = cpu_to_le32(i);
2235 memcpy(rb->data, page_address(rxb->page), max_len);
2236 /* remap the page for the free benefit */
2237 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2241 *data = iwl_fw_error_next_data(*data);
2244 spin_unlock(&rxq->lock);
2248 #define IWL_CSR_TO_DUMP (0x250)
2250 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2251 struct iwl_fw_error_dump_data **data)
2253 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2257 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2258 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2259 val = (void *)(*data)->data;
2261 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2262 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2264 *data = iwl_fw_error_next_data(*data);
2269 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2270 struct iwl_fw_error_dump_data **data)
2272 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2273 unsigned long flags;
2277 if (!iwl_trans_grab_nic_access(trans, &flags))
2280 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2281 (*data)->len = cpu_to_le32(fh_regs_len);
2282 val = (void *)(*data)->data;
2284 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2285 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2287 iwl_trans_release_nic_access(trans, &flags);
2289 *data = iwl_fw_error_next_data(*data);
2291 return sizeof(**data) + fh_regs_len;
2295 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2296 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2299 u32 buf_size_in_dwords = (monitor_len >> 2);
2300 u32 *buffer = (u32 *)fw_mon_data->data;
2301 unsigned long flags;
2304 if (!iwl_trans_grab_nic_access(trans, &flags))
2307 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2308 for (i = 0; i < buf_size_in_dwords; i++)
2309 buffer[i] = iwl_read_prph_no_grab(trans,
2310 MON_DMARB_RD_DATA_ADDR);
2311 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2313 iwl_trans_release_nic_access(trans, &flags);
2319 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2320 struct iwl_fw_error_dump_data **data,
2323 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2326 if ((trans_pcie->fw_mon_page &&
2327 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2328 trans->dbg_dest_tlv) {
2329 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2330 u32 base, write_ptr, wrap_cnt;
2332 /* If there was a dest TLV - use the values from there */
2333 if (trans->dbg_dest_tlv) {
2335 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2336 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2337 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2339 base = MON_BUFF_BASE_ADDR;
2340 write_ptr = MON_BUFF_WRPTR;
2341 wrap_cnt = MON_BUFF_CYCLE_CNT;
2344 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2345 fw_mon_data = (void *)(*data)->data;
2346 fw_mon_data->fw_mon_wr_ptr =
2347 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2348 fw_mon_data->fw_mon_cycle_cnt =
2349 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2350 fw_mon_data->fw_mon_base_ptr =
2351 cpu_to_le32(iwl_read_prph(trans, base));
2353 len += sizeof(**data) + sizeof(*fw_mon_data);
2354 if (trans_pcie->fw_mon_page) {
2356 * The firmware is now asserted, it won't write anything
2357 * to the buffer. CPU can take ownership to fetch the
2358 * data. The buffer will be handed back to the device
2359 * before the firmware will be restarted.
2361 dma_sync_single_for_cpu(trans->dev,
2362 trans_pcie->fw_mon_phys,
2363 trans_pcie->fw_mon_size,
2365 memcpy(fw_mon_data->data,
2366 page_address(trans_pcie->fw_mon_page),
2367 trans_pcie->fw_mon_size);
2369 monitor_len = trans_pcie->fw_mon_size;
2370 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2372 * Update pointers to reflect actual values after
2375 base = iwl_read_prph(trans, base) <<
2376 trans->dbg_dest_tlv->base_shift;
2377 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2378 monitor_len / sizeof(u32));
2379 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2381 iwl_trans_pci_dump_marbh_monitor(trans,
2385 /* Didn't match anything - output no monitor data */
2390 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2396 static struct iwl_trans_dump_data
2397 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2398 const struct iwl_fw_dbg_trigger_tlv *trigger)
2400 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2401 struct iwl_fw_error_dump_data *data;
2402 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2403 struct iwl_fw_error_dump_txcmd *txcmd;
2404 struct iwl_trans_dump_data *dump_data;
2408 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2409 !trans->cfg->mq_rx_supported;
2411 /* transport dump header */
2412 len = sizeof(*dump_data);
2415 len += sizeof(*data) +
2416 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2419 if (trans_pcie->fw_mon_page) {
2420 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2421 trans_pcie->fw_mon_size;
2422 monitor_len = trans_pcie->fw_mon_size;
2423 } else if (trans->dbg_dest_tlv) {
2426 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2427 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2429 base = iwl_read_prph(trans, base) <<
2430 trans->dbg_dest_tlv->base_shift;
2431 end = iwl_read_prph(trans, end) <<
2432 trans->dbg_dest_tlv->end_shift;
2434 /* Make "end" point to the actual end */
2435 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2436 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2437 end += (1 << trans->dbg_dest_tlv->end_shift);
2438 monitor_len = end - base;
2439 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2445 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2446 dump_data = vzalloc(len);
2450 data = (void *)dump_data->data;
2451 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2452 dump_data->len = len;
2458 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2461 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2464 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2465 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2467 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2469 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2470 len += num_rbs * (sizeof(*data) +
2471 sizeof(struct iwl_fw_error_dump_rb) +
2472 (PAGE_SIZE << trans_pcie->rx_page_order));
2475 dump_data = vzalloc(len);
2480 data = (void *)dump_data->data;
2481 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2482 txcmd = (void *)data->data;
2483 spin_lock_bh(&cmdq->lock);
2484 ptr = cmdq->q.write_ptr;
2485 for (i = 0; i < cmdq->q.n_window; i++) {
2486 u8 idx = get_cmd_index(&cmdq->q, ptr);
2489 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2490 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2493 len += sizeof(*txcmd) + caplen;
2494 txcmd->cmdlen = cpu_to_le32(cmdlen);
2495 txcmd->caplen = cpu_to_le32(caplen);
2496 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2497 txcmd = (void *)((u8 *)txcmd->data + caplen);
2500 ptr = iwl_queue_dec_wrap(ptr);
2502 spin_unlock_bh(&cmdq->lock);
2504 data->len = cpu_to_le32(len);
2505 len += sizeof(*data);
2506 data = iwl_fw_error_next_data(data);
2508 len += iwl_trans_pcie_dump_csr(trans, &data);
2509 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2511 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2513 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2515 dump_data->len = len;
2520 #ifdef CONFIG_PM_SLEEP
2521 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2523 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2524 return iwl_pci_fw_enter_d0i3(trans);
2529 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2531 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2532 iwl_pci_fw_exit_d0i3(trans);
2534 #endif /* CONFIG_PM_SLEEP */
2536 static const struct iwl_trans_ops trans_ops_pcie = {
2537 .start_hw = iwl_trans_pcie_start_hw,
2538 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2539 .fw_alive = iwl_trans_pcie_fw_alive,
2540 .start_fw = iwl_trans_pcie_start_fw,
2541 .stop_device = iwl_trans_pcie_stop_device,
2543 .d3_suspend = iwl_trans_pcie_d3_suspend,
2544 .d3_resume = iwl_trans_pcie_d3_resume,
2546 #ifdef CONFIG_PM_SLEEP
2547 .suspend = iwl_trans_pcie_suspend,
2548 .resume = iwl_trans_pcie_resume,
2549 #endif /* CONFIG_PM_SLEEP */
2551 .send_cmd = iwl_trans_pcie_send_hcmd,
2553 .tx = iwl_trans_pcie_tx,
2554 .reclaim = iwl_trans_pcie_reclaim,
2556 .txq_disable = iwl_trans_pcie_txq_disable,
2557 .txq_enable = iwl_trans_pcie_txq_enable,
2559 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2560 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2561 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2563 .write8 = iwl_trans_pcie_write8,
2564 .write32 = iwl_trans_pcie_write32,
2565 .read32 = iwl_trans_pcie_read32,
2566 .read_prph = iwl_trans_pcie_read_prph,
2567 .write_prph = iwl_trans_pcie_write_prph,
2568 .read_mem = iwl_trans_pcie_read_mem,
2569 .write_mem = iwl_trans_pcie_write_mem,
2570 .configure = iwl_trans_pcie_configure,
2571 .set_pmi = iwl_trans_pcie_set_pmi,
2572 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2573 .release_nic_access = iwl_trans_pcie_release_nic_access,
2574 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2576 .ref = iwl_trans_pcie_ref,
2577 .unref = iwl_trans_pcie_unref,
2579 .dump_data = iwl_trans_pcie_dump_data,
2582 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2583 const struct pci_device_id *ent,
2584 const struct iwl_cfg *cfg)
2586 struct iwl_trans_pcie *trans_pcie;
2587 struct iwl_trans *trans;
2591 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2592 &pdev->dev, cfg, &trans_ops_pcie, 0);
2594 return ERR_PTR(-ENOMEM);
2596 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS;
2598 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2600 trans_pcie->trans = trans;
2601 spin_lock_init(&trans_pcie->irq_lock);
2602 spin_lock_init(&trans_pcie->reg_lock);
2603 spin_lock_init(&trans_pcie->ref_lock);
2604 mutex_init(&trans_pcie->mutex);
2605 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2606 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2607 if (!trans_pcie->tso_hdr_page) {
2612 ret = pci_enable_device(pdev);
2616 if (!cfg->base_params->pcie_l1_allowed) {
2618 * W/A - seems to solve weird behavior. We need to remove this
2619 * if we don't want to stay in L1 all the time. This wastes a
2622 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2623 PCIE_LINK_STATE_L1 |
2624 PCIE_LINK_STATE_CLKPM);
2627 if (cfg->mq_rx_supported)
2632 pci_set_master(pdev);
2634 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2636 ret = pci_set_consistent_dma_mask(pdev,
2637 DMA_BIT_MASK(addr_size));
2639 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2641 ret = pci_set_consistent_dma_mask(pdev,
2643 /* both attempts failed: */
2645 dev_err(&pdev->dev, "No suitable DMA available\n");
2646 goto out_pci_disable_device;
2650 ret = pci_request_regions(pdev, DRV_NAME);
2652 dev_err(&pdev->dev, "pci_request_regions failed\n");
2653 goto out_pci_disable_device;
2656 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2657 if (!trans_pcie->hw_base) {
2658 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2660 goto out_pci_release_regions;
2663 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2664 * PCI Tx retries from interfering with C3 CPU state */
2665 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2667 trans->dev = &pdev->dev;
2668 trans_pcie->pci_dev = pdev;
2669 iwl_disable_interrupts(trans);
2671 ret = pci_enable_msi(pdev);
2673 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret);
2674 /* enable rfkill interrupt: hw bug w/a */
2675 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2676 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2677 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2678 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2682 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2684 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2685 * changed, and now the revision step also includes bit 0-1 (no more
2686 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2687 * in the old format.
2689 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2690 unsigned long flags;
2692 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2693 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2695 ret = iwl_pcie_prepare_card_hw(trans);
2697 IWL_WARN(trans, "Exit HW not ready\n");
2698 goto out_pci_disable_msi;
2702 * in-order to recognize C step driver should read chip version
2703 * id located at the AUX bus MISC address space.
2705 iwl_set_bit(trans, CSR_GP_CNTRL,
2706 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2709 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2710 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2711 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2714 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2715 goto out_pci_disable_msi;
2718 if (iwl_trans_grab_nic_access(trans, &flags)) {
2721 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
2722 hw_step |= ENABLE_WFPM;
2723 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
2724 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
2725 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2727 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2728 (SILICON_C_STEP << 2);
2729 iwl_trans_release_nic_access(trans, &flags);
2733 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2734 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2735 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2737 /* Initialize the wait queue for commands */
2738 init_waitqueue_head(&trans_pcie->wait_command_queue);
2740 init_waitqueue_head(&trans_pcie->d0i3_waitq);
2742 ret = iwl_pcie_alloc_ict(trans);
2744 goto out_pci_disable_msi;
2746 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2747 iwl_pcie_irq_handler,
2748 IRQF_SHARED, DRV_NAME, trans);
2750 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2754 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2756 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
2757 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
2759 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
2760 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
2765 iwl_pcie_free_ict(trans);
2766 out_pci_disable_msi:
2767 pci_disable_msi(pdev);
2768 out_pci_release_regions:
2769 pci_release_regions(pdev);
2770 out_pci_disable_device:
2771 pci_disable_device(pdev);
2773 free_percpu(trans_pcie->tso_hdr_page);
2774 iwl_trans_free(trans);
2775 return ERR_PTR(ret);