drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
   5  *
   6  * Portions of this file are derived from the ipw3945 project, as well
   7  * as portions of the ieee80211 subsystem header files.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  21  *
  22  * The full GNU General Public License is included in this distribution in the
  23  * file called LICENSE.
  24  *
  25  * Contact Information:
  26  *  Intel Linux Wireless <linuxwifi@intel.com>
  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
  29  *****************************************************************************/
  30 #include <linux/etherdevice.h>
  31 #include <linux/ieee80211.h>
  32 #include <linux/slab.h>
  33 #include <linux/sched.h>
  34 #include <net/ip6_checksum.h>
  35 #include <net/tso.h>
  36 #include <net/ip6_checksum.h>
  37
  38 #include "iwl-debug.h"
  39 #include "iwl-csr.h"
  40 #include "iwl-prph.h"
  41 #include "iwl-io.h"
  42 #include "iwl-scd.h"
  43 #include "iwl-op-mode.h"
  44 #include "internal.h"
  45 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  46 #include "dvm/commands.h"
  47
  48 #define IWL_TX_CRC_SIZE 4
  49 #define IWL_TX_DELIMITER_SIZE 4
  50
  51 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  52  * DMA services
  53  *
  54  * Theory of operation
  55  *
  56  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  57  * of buffer descriptors, each of which points to one or more data buffers for
  58  * the device to read from or fill.  Driver and device exchange status of each
  59  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  60  * entries in each circular buffer, to protect against confusing empty and full
  61  * queue states.
  62  *
  63  * The device reads or writes the data in the queues via the device's several
  64  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  65  *
  66  * For Tx queue, there are low mark and high mark limits. If, after queuing
  67  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  68  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  69  * Tx queue resumed.
  70  *
  71  ***************************************************/
  72 static int iwl_queue_space(const struct iwl_queue *q)
  73 {
  74         unsigned int max;
  75         unsigned int used;
  76
  77         /*
  78          * To avoid ambiguity between empty and completely full queues, there
  79          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
  80          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
  81          * to reserve any queue entries for this purpose.
  82          */
  83         if (q->n_window < TFD_QUEUE_SIZE_MAX)
  84                 max = q->n_window;
  85         else
  86                 max = TFD_QUEUE_SIZE_MAX - 1;
  87
  88         /*
  89          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
  90          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
  91          */
  92         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
  93
  94         if (WARN_ON(used > max))
  95                 return 0;
  96
  97         return max - used;
  98 }
  99
 100 /*
 101  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 102  */
 103 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
 104 {
 105         q->n_window = slots_num;
 106         q->id = id;
 107
 108         /* slots_num must be power-of-two size, otherwise
 109          * get_cmd_index is broken. */
 110         if (WARN_ON(!is_power_of_2(slots_num)))
 111                 return -EINVAL;
 112
 113         q->low_mark = q->n_window / 4;
 114         if (q->low_mark < 4)
 115                 q->low_mark = 4;
 116
 117         q->high_mark = q->n_window / 8;
 118         if (q->high_mark < 2)
 119                 q->high_mark = 2;
 120
 121         q->write_ptr = 0;
 122         q->read_ptr = 0;
 123
 124         return 0;
 125 }
 126
 127 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 128                                   struct iwl_dma_ptr *ptr, size_t size)
 129 {
 130         if (WARN_ON(ptr->addr))
 131                 return -EINVAL;
 132
 133         ptr->addr = dma_alloc_coherent(trans->dev, size,
 134                                        &ptr->dma, GFP_KERNEL);
 135         if (!ptr->addr)
 136                 return -ENOMEM;
 137         ptr->size = size;
 138         return 0;
 139 }
 140
 141 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
 142                                   struct iwl_dma_ptr *ptr)
 143 {
 144         if (unlikely(!ptr->addr))
 145                 return;
 146
 147         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 148         memset(ptr, 0, sizeof(*ptr));
 149 }
 150
 151 static void iwl_pcie_txq_stuck_timer(unsigned long data)
 152 {
 153         struct iwl_txq *txq = (void *)data;
 154         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 155         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 156         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 157                                 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 158         u8 buf[16];
 159         int i;
 160
 161         spin_lock(&txq->lock);
 162         /* check if triggered erroneously */
 163         if (txq->q.read_ptr == txq->q.write_ptr) {
 164                 spin_unlock(&txq->lock);
 165                 return;
 166         }
 167         spin_unlock(&txq->lock);
 168
 169         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 170                 jiffies_to_msecs(txq->wd_timeout));
 171         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 172                 txq->q.read_ptr, txq->q.write_ptr);
 173
 174         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 175
 176         iwl_print_hex_error(trans, buf, sizeof(buf));
 177
 178         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 179                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 180                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 181
 182         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 183                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 184                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 185                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 186                 u32 tbl_dw =
 187                         iwl_trans_read_mem32(trans,
 188                                              trans_pcie->scd_base_addr +
 189                                              SCD_TRANS_TBL_OFFSET_QUEUE(i));
 190
 191                 if (i & 0x1)
 192                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 193                 else
 194                         tbl_dw = tbl_dw & 0x0000FFFF;
 195
 196                 IWL_ERR(trans,
 197                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 198                         i, active ? "" : "in", fifo, tbl_dw,
 199                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
 200                                 (TFD_QUEUE_SIZE_MAX - 1),
 201                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 202         }
 203
 204         iwl_force_nmi(trans);
 205 }
 206
 207 /*
 208  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 209  */
 210 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 211                                              struct iwl_txq *txq, u16 byte_cnt)
 212 {
 213         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 214         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 215         int write_ptr = txq->q.write_ptr;
 216         int txq_id = txq->q.id;
 217         u8 sec_ctl = 0;
 218         u8 sta_id = 0;
 219         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 220         __le16 bc_ent;
 221         struct iwl_tx_cmd *tx_cmd =
 222                 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
 223
 224         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 225
 226         sta_id = tx_cmd->sta_id;
 227         sec_ctl = tx_cmd->sec_ctl;
 228
 229         switch (sec_ctl & TX_CMD_SEC_MSK) {
 230         case TX_CMD_SEC_CCM:
 231                 len += IEEE80211_CCMP_MIC_LEN;
 232                 break;
 233         case TX_CMD_SEC_TKIP:
 234                 len += IEEE80211_TKIP_ICV_LEN;
 235                 break;
 236         case TX_CMD_SEC_WEP:
 237                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 238                 break;
 239         }
 240
 241         if (trans_pcie->bc_table_dword)
 242                 len = DIV_ROUND_UP(len, 4);
 243
 244         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 245                 return;
 246
 247         bc_ent = cpu_to_le16(len | (sta_id << 12));
 248
 249         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 250
 251         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 252                 scd_bc_tbl[txq_id].
 253                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 254 }
 255
 256 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 257                                             struct iwl_txq *txq)
 258 {
 259         struct iwl_trans_pcie *trans_pcie =
 260                 IWL_TRANS_GET_PCIE_TRANS(trans);
 261         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 262         int txq_id = txq->q.id;
 263         int read_ptr = txq->q.read_ptr;
 264         u8 sta_id = 0;
 265         __le16 bc_ent;
 266         struct iwl_tx_cmd *tx_cmd =
 267                 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
 268
 269         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 270
 271         if (txq_id != trans_pcie->cmd_queue)
 272                 sta_id = tx_cmd->sta_id;
 273
 274         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 275         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 276
 277         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 278                 scd_bc_tbl[txq_id].
 279                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 280 }
 281
 282 /*
 283  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 284  */
 285 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 286                                     struct iwl_txq *txq)
 287 {
 288         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 289         u32 reg = 0;
 290         int txq_id = txq->q.id;
 291
 292         lockdep_assert_held(&txq->lock);
 293
 294         /*
 295          * explicitly wake up the NIC if:
 296          * 1. shadow registers aren't enabled
 297          * 2. NIC is woken up for CMD regardless of shadow outside this function
 298          * 3. there is a chance that the NIC is asleep
 299          */
 300         if (!trans->cfg->base_params->shadow_reg_enable &&
 301             txq_id != trans_pcie->cmd_queue &&
 302             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 303                 /*
 304                  * wake up nic if it's powered down ...
 305                  * uCode will wake up, and interrupt us again, so next
 306                  * time we'll skip this part.
 307                  */
 308                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 309
 310                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 311                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 312                                        txq_id, reg);
 313                         iwl_set_bit(trans, CSR_GP_CNTRL,
 314                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 315                         txq->need_update = true;
 316                         return;
 317                 }
 318         }
 319
 320         /*
 321          * if not in power-save mode, uCode will never sleep when we're
 322          * trying to tx (during RFKILL, we're not trying to tx).
 323          */
 324         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
 325         if (!txq->block)
 326                 iwl_write32(trans, HBUS_TARG_WRPTR,
 327                             txq->q.write_ptr | (txq_id << 8));
 328 }
 329
 330 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 331 {
 332         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 333         int i;
 334
 335         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 336                 struct iwl_txq *txq = &trans_pcie->txq[i];
 337
 338                 spin_lock_bh(&txq->lock);
 339                 if (trans_pcie->txq[i].need_update) {
 340                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 341                         trans_pcie->txq[i].need_update = false;
 342                 }
 343                 spin_unlock_bh(&txq->lock);
 344         }
 345 }
 346
 347 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 348 {
 349         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 350
 351         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 352         if (sizeof(dma_addr_t) > sizeof(u32))
 353                 addr |=
 354                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 355
 356         return addr;
 357 }
 358
 359 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 360                                        dma_addr_t addr, u16 len)
 361 {
 362         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 363         u16 hi_n_len = len << 4;
 364
 365         put_unaligned_le32(addr, &tb->lo);
 366         if (sizeof(dma_addr_t) > sizeof(u32))
 367                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 368
 369         tb->hi_n_len = cpu_to_le16(hi_n_len);
 370
 371         tfd->num_tbs = idx + 1;
 372 }
 373
 374 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
 375 {
 376         return tfd->num_tbs & 0x1f;
 377 }
 378
 379 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 380                                struct iwl_cmd_meta *meta,
 381                                struct iwl_tfd *tfd)
 382 {
 383         int i;
 384         int num_tbs;
 385
 386         /* Sanity check on number of chunks */
 387         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 388
 389         if (num_tbs >= IWL_NUM_OF_TBS) {
 390                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 391                 /* @todo issue fatal error, it is quite serious situation */
 392                 return;
 393         }
 394
 395         /* first TB is never freed - it's the scratchbuf data */
 396
 397         for (i = 1; i < num_tbs; i++) {
 398                 if (meta->flags & BIT(i + CMD_TB_BITMAP_POS))
 399                         dma_unmap_page(trans->dev,
 400                                        iwl_pcie_tfd_tb_get_addr(tfd, i),
 401                                        iwl_pcie_tfd_tb_get_len(tfd, i),
 402                                        DMA_TO_DEVICE);
 403                 else
 404                         dma_unmap_single(trans->dev,
 405                                          iwl_pcie_tfd_tb_get_addr(tfd, i),
 406                                          iwl_pcie_tfd_tb_get_len(tfd, i),
 407                                          DMA_TO_DEVICE);
 408         }
 409         tfd->num_tbs = 0;
 410 }
 411
 412 /*
 413  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 414  * @trans - transport private data
 415  * @txq - tx queue
 416  * @dma_dir - the direction of the DMA mapping
 417  *
 418  * Does NOT advance any TFD circular buffer read/write indexes
 419  * Does NOT free the TFD itself (which is within circular buffer)
 420  */
 421 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 422 {
 423         struct iwl_tfd *tfd_tmp = txq->tfds;
 424
 425         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 426          * idx is bounded by n_window
 427          */
 428         int rd_ptr = txq->q.read_ptr;
 429         int idx = get_cmd_index(&txq->q, rd_ptr);
 430
 431         lockdep_assert_held(&txq->lock);
 432
 433         /* We have only q->n_window txq->entries, but we use
 434          * TFD_QUEUE_SIZE_MAX tfds
 435          */
 436         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
 437
 438         /* free SKB */
 439         if (txq->entries) {
 440                 struct sk_buff *skb;
 441
 442                 skb = txq->entries[idx].skb;
 443
 444                 /* Can be called from irqs-disabled context
 445                  * If skb is not NULL, it means that the whole queue is being
 446                  * freed and that the queue is not empty - free the skb
 447                  */
 448                 if (skb) {
 449                         iwl_op_mode_free_skb(trans->op_mode, skb);
 450                         txq->entries[idx].skb = NULL;
 451                 }
 452         }
 453 }
 454
 455 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 456                                   dma_addr_t addr, u16 len, bool reset)
 457 {
 458         struct iwl_queue *q;
 459         struct iwl_tfd *tfd, *tfd_tmp;
 460         u32 num_tbs;
 461
 462         q = &txq->q;
 463         tfd_tmp = txq->tfds;
 464         tfd = &tfd_tmp[q->write_ptr];
 465
 466         if (reset)
 467                 memset(tfd, 0, sizeof(*tfd));
 468
 469         num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
 470
 471         /* Each TFD can point to a maximum 20 Tx buffers */
 472         if (num_tbs >= IWL_NUM_OF_TBS) {
 473                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 474                         IWL_NUM_OF_TBS);
 475                 return -EINVAL;
 476         }
 477
 478         if (WARN(addr & ~IWL_TX_DMA_MASK,
 479                  "Unaligned address = %llx\n", (unsigned long long)addr))
 480                 return -EINVAL;
 481
 482         iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
 483
 484         return num_tbs;
 485 }
 486
 487 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
 488                                struct iwl_txq *txq, int slots_num,
 489                                u32 txq_id)
 490 {
 491         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 492         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 493         size_t scratchbuf_sz;
 494         int i;
 495
 496         if (WARN_ON(txq->entries || txq->tfds))
 497                 return -EINVAL;
 498
 499         setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
 500                     (unsigned long)txq);
 501         txq->trans_pcie = trans_pcie;
 502
 503         txq->q.n_window = slots_num;
 504
 505         txq->entries = kcalloc(slots_num,
 506                                sizeof(struct iwl_pcie_txq_entry),
 507                                GFP_KERNEL);
 508
 509         if (!txq->entries)
 510                 goto error;
 511
 512         if (txq_id == trans_pcie->cmd_queue)
 513                 for (i = 0; i < slots_num; i++) {
 514                         txq->entries[i].cmd =
 515                                 kmalloc(sizeof(struct iwl_device_cmd),
 516                                         GFP_KERNEL);
 517                         if (!txq->entries[i].cmd)
 518                                 goto error;
 519                 }
 520
 521         /* Circular buffer of transmit frame descriptors (TFDs),
 522          * shared with device */
 523         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 524                                        &txq->q.dma_addr, GFP_KERNEL);
 525         if (!txq->tfds)
 526                 goto error;
 527
 528         BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
 529         BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
 530                         sizeof(struct iwl_cmd_header) +
 531                         offsetof(struct iwl_tx_cmd, scratch));
 532
 533         scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
 534
 535         txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
 536                                               &txq->scratchbufs_dma,
 537                                               GFP_KERNEL);
 538         if (!txq->scratchbufs)
 539                 goto err_free_tfds;
 540
 541         txq->q.id = txq_id;
 542
 543         return 0;
 544 err_free_tfds:
 545         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
 546 error:
 547         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 548                 for (i = 0; i < slots_num; i++)
 549                         kfree(txq->entries[i].cmd);
 550         kfree(txq->entries);
 551         txq->entries = NULL;
 552
 553         return -ENOMEM;
 554
 555 }
 556
 557 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 558                               int slots_num, u32 txq_id)
 559 {
 560         int ret;
 561
 562         txq->need_update = false;
 563
 564         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 565          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 566         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 567
 568         /* Initialize queue's high/low-water marks, and head/tail indexes */
 569         ret = iwl_queue_init(&txq->q, slots_num, txq_id);
 570         if (ret)
 571                 return ret;
 572
 573         spin_lock_init(&txq->lock);
 574
 575         /*
 576          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 577          * given Tx queue, and enable the DMA channel used for that queue.
 578          * Circular buffer (TFD queue in DRAM) physical base address */
 579         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 580                            txq->q.dma_addr >> 8);
 581
 582         return 0;
 583 }
 584
 585 static void iwl_pcie_free_tso_page(struct sk_buff *skb)
 586 {
 587         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 588
 589         if (info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]) {
 590                 struct page *page =
 591                         info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA];
 592
 593                 __free_page(page);
 594                 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = NULL;
 595         }
 596 }
 597
 598 /*
 599  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 600  */
 601 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 602 {
 603         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 604         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 605         struct iwl_queue *q = &txq->q;
 606
 607         spin_lock_bh(&txq->lock);
 608         while (q->write_ptr != q->read_ptr) {
 609                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 610                                    txq_id, q->read_ptr);
 611
 612                 if (txq_id != trans_pcie->cmd_queue) {
 613                         struct sk_buff *skb = txq->entries[q->read_ptr].skb;
 614
 615                         if (WARN_ON_ONCE(!skb))
 616                                 continue;
 617
 618                         iwl_pcie_free_tso_page(skb);
 619                 }
 620                 iwl_pcie_txq_free_tfd(trans, txq);
 621                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
 622         }
 623         txq->active = false;
 624         spin_unlock_bh(&txq->lock);
 625
 626         /* just in case - this queue may have been stopped */
 627         iwl_wake_queue(trans, txq);
 628 }
 629
 630 /*
 631  * iwl_pcie_txq_free - Deallocate DMA queue.
 632  * @txq: Transmit queue to deallocate.
 633  *
 634  * Empty queue by removing and destroying all BD's.
 635  * Free all buffers.
 636  * 0-fill, but do not free "txq" descriptor structure.
 637  */
 638 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 639 {
 640         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 641         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 642         struct device *dev = trans->dev;
 643         int i;
 644
 645         if (WARN_ON(!txq))
 646                 return;
 647
 648         iwl_pcie_txq_unmap(trans, txq_id);
 649
 650         /* De-alloc array of command/tx buffers */
 651         if (txq_id == trans_pcie->cmd_queue)
 652                 for (i = 0; i < txq->q.n_window; i++) {
 653                         kzfree(txq->entries[i].cmd);
 654                         kzfree(txq->entries[i].free_buf);
 655                 }
 656
 657         /* De-alloc circular buffer of TFDs */
 658         if (txq->tfds) {
 659                 dma_free_coherent(dev,
 660                                   sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
 661                                   txq->tfds, txq->q.dma_addr);
 662                 txq->q.dma_addr = 0;
 663                 txq->tfds = NULL;
 664
 665                 dma_free_coherent(dev,
 666                                   sizeof(*txq->scratchbufs) * txq->q.n_window,
 667                                   txq->scratchbufs, txq->scratchbufs_dma);
 668         }
 669
 670         kfree(txq->entries);
 671         txq->entries = NULL;
 672
 673         del_timer_sync(&txq->stuck_timer);
 674
 675         /* 0-fill queue descriptor structure */
 676         memset(txq, 0, sizeof(*txq));
 677 }
 678
 679 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 680 {
 681         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 682         int nq = trans->cfg->base_params->num_of_queues;
 683         int chan;
 684         u32 reg_val;
 685         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 686                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 687
 688         /* make sure all queue are not stopped/used */
 689         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 690         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 691
 692         trans_pcie->scd_base_addr =
 693                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 694
 695         WARN_ON(scd_base_addr != 0 &&
 696                 scd_base_addr != trans_pcie->scd_base_addr);
 697
 698         /* reset context data, TX status and translation data */
 699         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 700                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 701                             NULL, clear_dwords);
 702
 703         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 704                        trans_pcie->scd_bc_tbls.dma >> 10);
 705
 706         /* The chain extension of the SCD doesn't work well. This feature is
 707          * enabled by default by the HW, so we need to disable it manually.
 708          */
 709         if (trans->cfg->base_params->scd_chain_ext_wa)
 710                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 711
 712         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 713                                 trans_pcie->cmd_fifo,
 714                                 trans_pcie->cmd_q_wdg_timeout);
 715
 716         /* Activate all Tx DMA/FIFO channels */
 717         iwl_scd_activate_fifos(trans);
 718
 719         /* Enable DMA channel */
 720         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 721                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 722                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 723                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 724
 725         /* Update FH chicken bits */
 726         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 727         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 728                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 729
 730         /* Enable L1-Active */
 731         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 732                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 733                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 734 }
 735
 736 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 737 {
 738         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 739         int txq_id;
 740
 741         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 742              txq_id++) {
 743                 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 744
 745                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 746                                    txq->q.dma_addr >> 8);
 747                 iwl_pcie_txq_unmap(trans, txq_id);
 748                 txq->q.read_ptr = 0;
 749                 txq->q.write_ptr = 0;
 750         }
 751
 752         /* Tell NIC where to find the "keep warm" buffer */
 753         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 754                            trans_pcie->kw.dma >> 4);
 755
 756         /*
 757          * Send 0 as the scd_base_addr since the device may have be reset
 758          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 759          * contain garbage.
 760          */
 761         iwl_pcie_tx_start(trans, 0);
 762 }
 763
 764 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 765 {
 766         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 767         unsigned long flags;
 768         int ch, ret;
 769         u32 mask = 0;
 770
 771         spin_lock(&trans_pcie->irq_lock);
 772
 773         if (!iwl_trans_grab_nic_access(trans, &flags))
 774                 goto out;
 775
 776         /* Stop each Tx DMA channel */
 777         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 778                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 779                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 780         }
 781
 782         /* Wait for DMA channels to be idle */
 783         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 784         if (ret < 0)
 785                 IWL_ERR(trans,
 786                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 787                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 788
 789         iwl_trans_release_nic_access(trans, &flags);
 790
 791 out:
 792         spin_unlock(&trans_pcie->irq_lock);
 793 }
 794
 795 /*
 796  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 797  */
 798 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 799 {
 800         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 801         int txq_id;
 802
 803         /* Turn off all Tx DMA fifos */
 804         iwl_scd_deactivate_fifos(trans);
 805
 806         /* Turn off all Tx DMA channels */
 807         iwl_pcie_tx_stop_fh(trans);
 808
 809         /*
 810          * This function can be called before the op_mode disabled the
 811          * queues. This happens when we have an rfkill interrupt.
 812          * Since we stop Tx altogether - mark the queues as stopped.
 813          */
 814         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 815         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 816
 817         /* This can happen: start_hw, stop_device */
 818         if (!trans_pcie->txq)
 819                 return 0;
 820
 821         /* Unmap DMA from host system and free skb's */
 822         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 823              txq_id++)
 824                 iwl_pcie_txq_unmap(trans, txq_id);
 825
 826         return 0;
 827 }
 828
 829 /*
 830  * iwl_trans_tx_free - Free TXQ Context
 831  *
 832  * Destroy all TX DMA queues and structures
 833  */
 834 void iwl_pcie_tx_free(struct iwl_trans *trans)
 835 {
 836         int txq_id;
 837         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 838
 839         /* Tx queues */
 840         if (trans_pcie->txq) {
 841                 for (txq_id = 0;
 842                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 843                         iwl_pcie_txq_free(trans, txq_id);
 844         }
 845
 846         kfree(trans_pcie->txq);
 847         trans_pcie->txq = NULL;
 848
 849         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 850
 851         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 852 }
 853
 854 /*
 855  * iwl_pcie_tx_alloc - allocate TX context
 856  * Allocate all Tx DMA structures and initialize them
 857  */
 858 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 859 {
 860         int ret;
 861         int txq_id, slots_num;
 862         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 863
 864         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 865                         sizeof(struct iwlagn_scd_bc_tbl);
 866
 867         /*It is not allowed to alloc twice, so warn when this happens.
 868          * We cannot rely on the previous allocation, so free and fail */
 869         if (WARN_ON(trans_pcie->txq)) {
 870                 ret = -EINVAL;
 871                 goto error;
 872         }
 873
 874         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 875                                    scd_bc_tbls_size);
 876         if (ret) {
 877                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 878                 goto error;
 879         }
 880
 881         /* Alloc keep-warm buffer */
 882         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 883         if (ret) {
 884                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 885                 goto error;
 886         }
 887
 888         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 889                                   sizeof(struct iwl_txq), GFP_KERNEL);
 890         if (!trans_pcie->txq) {
 891                 IWL_ERR(trans, "Not enough memory for txq\n");
 892                 ret = -ENOMEM;
 893                 goto error;
 894         }
 895
 896         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 897         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 898              txq_id++) {
 899                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 900                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 901                 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
 902                                           slots_num, txq_id);
 903                 if (ret) {
 904                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 905                         goto error;
 906                 }
 907         }
 908
 909         return 0;
 910
 911 error:
 912         iwl_pcie_tx_free(trans);
 913
 914         return ret;
 915 }
 916 int iwl_pcie_tx_init(struct iwl_trans *trans)
 917 {
 918         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 919         int ret;
 920         int txq_id, slots_num;
 921         bool alloc = false;
 922
 923         if (!trans_pcie->txq) {
 924                 ret = iwl_pcie_tx_alloc(trans);
 925                 if (ret)
 926                         goto error;
 927                 alloc = true;
 928         }
 929
 930         spin_lock(&trans_pcie->irq_lock);
 931
 932         /* Turn off all Tx DMA fifos */
 933         iwl_scd_deactivate_fifos(trans);
 934
 935         /* Tell NIC where to find the "keep warm" buffer */
 936         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 937                            trans_pcie->kw.dma >> 4);
 938
 939         spin_unlock(&trans_pcie->irq_lock);
 940
 941         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 942         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 943              txq_id++) {
 944                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 945                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 946                 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
 947                                          slots_num, txq_id);
 948                 if (ret) {
 949                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 950                         goto error;
 951                 }
 952         }
 953
 954         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
 955         if (trans->cfg->base_params->num_of_queues > 20)
 956                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
 957                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
 958
 959         return 0;
 960 error:
 961         /*Upon error, free only if we allocated something */
 962         if (alloc)
 963                 iwl_pcie_tx_free(trans);
 964         return ret;
 965 }
 966
 967 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
 968 {
 969         lockdep_assert_held(&txq->lock);
 970
 971         if (!txq->wd_timeout)
 972                 return;
 973
 974         /*
 975          * station is asleep and we send data - that must
 976          * be uAPSD or PS-Poll. Don't rearm the timer.
 977          */
 978         if (txq->frozen)
 979                 return;
 980
 981         /*
 982          * if empty delete timer, otherwise move timer forward
 983          * since we're making progress on this queue
 984          */
 985         if (txq->q.read_ptr == txq->q.write_ptr)
 986                 del_timer(&txq->stuck_timer);
 987         else
 988                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
 989 }
 990
 991 /* Frees buffers until index _not_ inclusive */
 992 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
 993                             struct sk_buff_head *skbs)
 994 {
 995         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 996         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
 997         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
 998         struct iwl_queue *q = &txq->q;
 999         int last_to_free;
1000
1001         /* This function is not meant to release cmd queue*/
1002         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1003                 return;
1004
1005         spin_lock_bh(&txq->lock);
1006
1007         if (!txq->active) {
1008                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1009                                     txq_id, ssn);
1010                 goto out;
1011         }
1012
1013         if (txq->q.read_ptr == tfd_num)
1014                 goto out;
1015
1016         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1017                            txq_id, txq->q.read_ptr, tfd_num, ssn);
1018
1019         /*Since we free until index _not_ inclusive, the one before index is
1020          * the last we will free. This one must be used */
1021         last_to_free = iwl_queue_dec_wrap(tfd_num);
1022
1023         if (!iwl_queue_used(q, last_to_free)) {
1024                 IWL_ERR(trans,
1025                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1026                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1027                         q->write_ptr, q->read_ptr);
1028                 goto out;
1029         }
1030
1031         if (WARN_ON(!skb_queue_empty(skbs)))
1032                 goto out;
1033
1034         for (;
1035              q->read_ptr != tfd_num;
1036              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1037                 struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb;
1038
1039                 if (WARN_ON_ONCE(!skb))
1040                         continue;
1041
1042                 iwl_pcie_free_tso_page(skb);
1043
1044                 __skb_queue_tail(skbs, skb);
1045
1046                 txq->entries[txq->q.read_ptr].skb = NULL;
1047
1048                 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1049
1050                 iwl_pcie_txq_free_tfd(trans, txq);
1051         }
1052
1053         iwl_pcie_txq_progress(txq);
1054
1055         if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1056                 iwl_wake_queue(trans, txq);
1057
1058         if (q->read_ptr == q->write_ptr) {
1059                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1060                 iwl_trans_pcie_unref(trans);
1061         }
1062
1063 out:
1064         spin_unlock_bh(&txq->lock);
1065 }
1066
1067 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1068                                       const struct iwl_host_cmd *cmd)
1069 {
1070         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1071         int ret;
1072
1073         lockdep_assert_held(&trans_pcie->reg_lock);
1074
1075         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1076             !trans_pcie->ref_cmd_in_flight) {
1077                 trans_pcie->ref_cmd_in_flight = true;
1078                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1079                 iwl_trans_pcie_ref(trans);
1080         }
1081
1082         /*
1083          * wake up the NIC to make sure that the firmware will see the host
1084          * command - we will let the NIC sleep once all the host commands
1085          * returned. This needs to be done only on NICs that have
1086          * apmg_wake_up_wa set.
1087          */
1088         if (trans->cfg->base_params->apmg_wake_up_wa &&
1089             !trans_pcie->cmd_hold_nic_awake) {
1090                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1091                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1092
1093                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1094                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1095                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1096                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1097                                    15000);
1098                 if (ret < 0) {
1099                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1100                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1101                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1102                         return -EIO;
1103                 }
1104                 trans_pcie->cmd_hold_nic_awake = true;
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1111 {
1112         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1113
1114         lockdep_assert_held(&trans_pcie->reg_lock);
1115
1116         if (trans_pcie->ref_cmd_in_flight) {
1117                 trans_pcie->ref_cmd_in_flight = false;
1118                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1119                 iwl_trans_pcie_unref(trans);
1120         }
1121
1122         if (trans->cfg->base_params->apmg_wake_up_wa) {
1123                 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
1124                         return 0;
1125
1126                 trans_pcie->cmd_hold_nic_awake = false;
1127                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1128                                            CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1129         }
1130         return 0;
1131 }
1132
1133 /*
1134  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1135  *
1136  * When FW advances 'R' index, all entries between old and new 'R' index
1137  * need to be reclaimed. As result, some free space forms.  If there is
1138  * enough free space (> low mark), wake the stack that feeds us.
1139  */
1140 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1141 {
1142         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1143         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1144         struct iwl_queue *q = &txq->q;
1145         unsigned long flags;
1146         int nfreed = 0;
1147
1148         lockdep_assert_held(&txq->lock);
1149
1150         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1151                 IWL_ERR(trans,
1152                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1153                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1154                         q->write_ptr, q->read_ptr);
1155                 return;
1156         }
1157
1158         for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1159              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1160
1161                 if (nfreed++ > 0) {
1162                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1163                                 idx, q->write_ptr, q->read_ptr);
1164                         iwl_force_nmi(trans);
1165                 }
1166         }
1167
1168         if (q->read_ptr == q->write_ptr) {
1169                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1170                 iwl_pcie_clear_cmd_in_flight(trans);
1171                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1172         }
1173
1174         iwl_pcie_txq_progress(txq);
1175 }
1176
1177 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1178                                  u16 txq_id)
1179 {
1180         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1181         u32 tbl_dw_addr;
1182         u32 tbl_dw;
1183         u16 scd_q2ratid;
1184
1185         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1186
1187         tbl_dw_addr = trans_pcie->scd_base_addr +
1188                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1189
1190         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1191
1192         if (txq_id & 0x1)
1193                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1194         else
1195                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1196
1197         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1198
1199         return 0;
1200 }
1201
1202 /* Receiver address (actually, Rx station's index into station table),
1203  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1204 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1205
1206 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1207                                const struct iwl_trans_txq_scd_cfg *cfg,
1208                                unsigned int wdg_timeout)
1209 {
1210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1211         struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1212         int fifo = -1;
1213
1214         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1215                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1216
1217         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1218
1219         if (cfg) {
1220                 fifo = cfg->fifo;
1221
1222                 /* Disable the scheduler prior configuring the cmd queue */
1223                 if (txq_id == trans_pcie->cmd_queue &&
1224                     trans_pcie->scd_set_active)
1225                         iwl_scd_enable_set_active(trans, 0);
1226
1227                 /* Stop this Tx queue before configuring it */
1228                 iwl_scd_txq_set_inactive(trans, txq_id);
1229
1230                 /* Set this queue as a chain-building queue unless it is CMD */
1231                 if (txq_id != trans_pcie->cmd_queue)
1232                         iwl_scd_txq_set_chain(trans, txq_id);
1233
1234                 if (cfg->aggregate) {
1235                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1236
1237                         /* Map receiver-address / traffic-ID to this queue */
1238                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1239
1240                         /* enable aggregations for the queue */
1241                         iwl_scd_txq_enable_agg(trans, txq_id);
1242                         txq->ampdu = true;
1243                 } else {
1244                         /*
1245                          * disable aggregations for the queue, this will also
1246                          * make the ra_tid mapping configuration irrelevant
1247                          * since it is now a non-AGG queue.
1248                          */
1249                         iwl_scd_txq_disable_agg(trans, txq_id);
1250
1251                         ssn = txq->q.read_ptr;
1252                 }
1253         }
1254
1255         /* Place first TFD at index corresponding to start sequence number.
1256          * Assumes that ssn_idx is valid (!= 0xFFF) */
1257         txq->q.read_ptr = (ssn & 0xff);
1258         txq->q.write_ptr = (ssn & 0xff);
1259         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1260                            (ssn & 0xff) | (txq_id << 8));
1261
1262         if (cfg) {
1263                 u8 frame_limit = cfg->frame_limit;
1264
1265                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1266
1267                 /* Set up Tx window size and frame limit for this queue */
1268                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1269                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1270                 iwl_trans_write_mem32(trans,
1271                         trans_pcie->scd_base_addr +
1272                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1273                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1274                                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1275                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1276                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1277
1278                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1279                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1280                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1281                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1282                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1283                                SCD_QUEUE_STTS_REG_MSK);
1284
1285                 /* enable the scheduler for this queue (only) */
1286                 if (txq_id == trans_pcie->cmd_queue &&
1287                     trans_pcie->scd_set_active)
1288                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1289
1290                 IWL_DEBUG_TX_QUEUES(trans,
1291                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1292                                     txq_id, fifo, ssn & 0xff);
1293         } else {
1294                 IWL_DEBUG_TX_QUEUES(trans,
1295                                     "Activate queue %d WrPtr: %d\n",
1296                                     txq_id, ssn & 0xff);
1297         }
1298
1299         txq->active = true;
1300 }
1301
1302 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1303                                 bool configure_scd)
1304 {
1305         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1306         u32 stts_addr = trans_pcie->scd_base_addr +
1307                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1308         static const u32 zero_val[4] = {};
1309
1310         trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1311         trans_pcie->txq[txq_id].frozen = false;
1312
1313         /*
1314          * Upon HW Rfkill - we stop the device, and then stop the queues
1315          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1316          * allow the op_mode to call txq_disable after it already called
1317          * stop_device.
1318          */
1319         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1320                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1321                           "queue %d not used", txq_id);
1322                 return;
1323         }
1324
1325         if (configure_scd) {
1326                 iwl_scd_txq_set_inactive(trans, txq_id);
1327
1328                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1329                                     ARRAY_SIZE(zero_val));
1330         }
1331
1332         iwl_pcie_txq_unmap(trans, txq_id);
1333         trans_pcie->txq[txq_id].ampdu = false;
1334
1335         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1336 }
1337
1338 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1339
1340 /*
1341  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1342  * @priv: device private data point
1343  * @cmd: a pointer to the ucode command structure
1344  *
1345  * The function returns < 0 values to indicate the operation
1346  * failed. On success, it returns the index (>= 0) of command in the
1347  * command queue.
1348  */
1349 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1350                                  struct iwl_host_cmd *cmd)
1351 {
1352         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1353         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1354         struct iwl_queue *q = &txq->q;
1355         struct iwl_device_cmd *out_cmd;
1356         struct iwl_cmd_meta *out_meta;
1357         unsigned long flags;
1358         void *dup_buf = NULL;
1359         dma_addr_t phys_addr;
1360         int idx;
1361         u16 copy_size, cmd_size, scratch_size;
1362         bool had_nocopy = false;
1363         u8 group_id = iwl_cmd_groupid(cmd->id);
1364         int i, ret;
1365         u32 cmd_pos;
1366         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1367         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1368
1369         if (WARN(!trans_pcie->wide_cmd_header &&
1370                  group_id > IWL_ALWAYS_LONG_GROUP,
1371                  "unsupported wide command %#x\n", cmd->id))
1372                 return -EINVAL;
1373
1374         if (group_id != 0) {
1375                 copy_size = sizeof(struct iwl_cmd_header_wide);
1376                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1377         } else {
1378                 copy_size = sizeof(struct iwl_cmd_header);
1379                 cmd_size = sizeof(struct iwl_cmd_header);
1380         }
1381
1382         /* need one for the header if the first is NOCOPY */
1383         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1384
1385         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1386                 cmddata[i] = cmd->data[i];
1387                 cmdlen[i] = cmd->len[i];
1388
1389                 if (!cmd->len[i])
1390                         continue;
1391
1392                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1393                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1394                         int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1395
1396                         if (copy > cmdlen[i])
1397                                 copy = cmdlen[i];
1398                         cmdlen[i] -= copy;
1399                         cmddata[i] += copy;
1400                         copy_size += copy;
1401                 }
1402
1403                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1404                         had_nocopy = true;
1405                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1406                                 idx = -EINVAL;
1407                                 goto free_dup_buf;
1408                         }
1409                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1410                         /*
1411                          * This is also a chunk that isn't copied
1412                          * to the static buffer so set had_nocopy.
1413                          */
1414                         had_nocopy = true;
1415
1416                         /* only allowed once */
1417                         if (WARN_ON(dup_buf)) {
1418                                 idx = -EINVAL;
1419                                 goto free_dup_buf;
1420                         }
1421
1422                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1423                                           GFP_ATOMIC);
1424                         if (!dup_buf)
1425                                 return -ENOMEM;
1426                 } else {
1427                         /* NOCOPY must not be followed by normal! */
1428                         if (WARN_ON(had_nocopy)) {
1429                                 idx = -EINVAL;
1430                                 goto free_dup_buf;
1431                         }
1432                         copy_size += cmdlen[i];
1433                 }
1434                 cmd_size += cmd->len[i];
1435         }
1436
1437         /*
1438          * If any of the command structures end up being larger than
1439          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1440          * allocated into separate TFDs, then we will need to
1441          * increase the size of the buffers.
1442          */
1443         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1444                  "Command %s (%#x) is too large (%d bytes)\n",
1445                  iwl_get_cmd_string(trans, cmd->id),
1446                  cmd->id, copy_size)) {
1447                 idx = -EINVAL;
1448                 goto free_dup_buf;
1449         }
1450
1451         spin_lock_bh(&txq->lock);
1452
1453         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1454                 spin_unlock_bh(&txq->lock);
1455
1456                 IWL_ERR(trans, "No space in command queue\n");
1457                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1458                 idx = -ENOSPC;
1459                 goto free_dup_buf;
1460         }
1461
1462         idx = get_cmd_index(q, q->write_ptr);
1463         out_cmd = txq->entries[idx].cmd;
1464         out_meta = &txq->entries[idx].meta;
1465
1466         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1467         if (cmd->flags & CMD_WANT_SKB)
1468                 out_meta->source = cmd;
1469
1470         /* set up the header */
1471         if (group_id != 0) {
1472                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1473                 out_cmd->hdr_wide.group_id = group_id;
1474                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1475                 out_cmd->hdr_wide.length =
1476                         cpu_to_le16(cmd_size -
1477                                     sizeof(struct iwl_cmd_header_wide));
1478                 out_cmd->hdr_wide.reserved = 0;
1479                 out_cmd->hdr_wide.sequence =
1480                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1481                                                  INDEX_TO_SEQ(q->write_ptr));
1482
1483                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1484                 copy_size = sizeof(struct iwl_cmd_header_wide);
1485         } else {
1486                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1487                 out_cmd->hdr.sequence =
1488                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1489                                                  INDEX_TO_SEQ(q->write_ptr));
1490                 out_cmd->hdr.group_id = 0;
1491
1492                 cmd_pos = sizeof(struct iwl_cmd_header);
1493                 copy_size = sizeof(struct iwl_cmd_header);
1494         }
1495
1496         /* and copy the data that needs to be copied */
1497         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1498                 int copy;
1499
1500                 if (!cmd->len[i])
1501                         continue;
1502
1503                 /* copy everything if not nocopy/dup */
1504                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1505                                            IWL_HCMD_DFL_DUP))) {
1506                         copy = cmd->len[i];
1507
1508                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1509                         cmd_pos += copy;
1510                         copy_size += copy;
1511                         continue;
1512                 }
1513
1514                 /*
1515                  * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1516                  * in total (for the scratchbuf handling), but copy up to what
1517                  * we can fit into the payload for debug dump purposes.
1518                  */
1519                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1520
1521                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1522                 cmd_pos += copy;
1523
1524                 /* However, treat copy_size the proper way, we need it below */
1525                 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1526                         copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1527
1528                         if (copy > cmd->len[i])
1529                                 copy = cmd->len[i];
1530                         copy_size += copy;
1531                 }
1532         }
1533
1534         IWL_DEBUG_HC(trans,
1535                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1536                      iwl_get_cmd_string(trans, cmd->id),
1537                      group_id, out_cmd->hdr.cmd,
1538                      le16_to_cpu(out_cmd->hdr.sequence),
1539                      cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1540
1541         /* start the TFD with the scratchbuf */
1542         scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1543         memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1544         iwl_pcie_txq_build_tfd(trans, txq,
1545                                iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1546                                scratch_size, true);
1547
1548         /* map first command fragment, if any remains */
1549         if (copy_size > scratch_size) {
1550                 phys_addr = dma_map_single(trans->dev,
1551                                            ((u8 *)&out_cmd->hdr) + scratch_size,
1552                                            copy_size - scratch_size,
1553                                            DMA_TO_DEVICE);
1554                 if (dma_mapping_error(trans->dev, phys_addr)) {
1555                         iwl_pcie_tfd_unmap(trans, out_meta,
1556                                            &txq->tfds[q->write_ptr]);
1557                         idx = -ENOMEM;
1558                         goto out;
1559                 }
1560
1561                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1562                                        copy_size - scratch_size, false);
1563         }
1564
1565         /* map the remaining (adjusted) nocopy/dup fragments */
1566         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1567                 const void *data = cmddata[i];
1568
1569                 if (!cmdlen[i])
1570                         continue;
1571                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1572                                            IWL_HCMD_DFL_DUP)))
1573                         continue;
1574                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1575                         data = dup_buf;
1576                 phys_addr = dma_map_single(trans->dev, (void *)data,
1577                                            cmdlen[i], DMA_TO_DEVICE);
1578                 if (dma_mapping_error(trans->dev, phys_addr)) {
1579                         iwl_pcie_tfd_unmap(trans, out_meta,
1580                                            &txq->tfds[q->write_ptr]);
1581                         idx = -ENOMEM;
1582                         goto out;
1583                 }
1584
1585                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1586         }
1587
1588         BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS >
1589                      sizeof(out_meta->flags) * BITS_PER_BYTE);
1590         out_meta->flags = cmd->flags;
1591         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1592                 kzfree(txq->entries[idx].free_buf);
1593         txq->entries[idx].free_buf = dup_buf;
1594
1595         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1596
1597         /* start timer if queue currently empty */
1598         if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1599                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1600
1601         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1602         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1603         if (ret < 0) {
1604                 idx = ret;
1605                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1606                 goto out;
1607         }
1608
1609         /* Increment and update queue's write index */
1610         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1611         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1612
1613         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1614
1615  out:
1616         spin_unlock_bh(&txq->lock);
1617  free_dup_buf:
1618         if (idx < 0)
1619                 kfree(dup_buf);
1620         return idx;
1621 }
1622
1623 /*
1624  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1625  * @rxb: Rx buffer to reclaim
1626  */
1627 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1628                             struct iwl_rx_cmd_buffer *rxb)
1629 {
1630         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1631         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1632         u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id);
1633         u32 cmd_id;
1634         int txq_id = SEQ_TO_QUEUE(sequence);
1635         int index = SEQ_TO_INDEX(sequence);
1636         int cmd_index;
1637         struct iwl_device_cmd *cmd;
1638         struct iwl_cmd_meta *meta;
1639         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1640         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1641
1642         /* If a Tx command is being handled and it isn't in the actual
1643          * command queue then there a command routing bug has been introduced
1644          * in the queue management code. */
1645         if (WARN(txq_id != trans_pcie->cmd_queue,
1646                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1647                  txq_id, trans_pcie->cmd_queue, sequence,
1648                  trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1649                  trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1650                 iwl_print_hex_error(trans, pkt, 32);
1651                 return;
1652         }
1653
1654         spin_lock_bh(&txq->lock);
1655
1656         cmd_index = get_cmd_index(&txq->q, index);
1657         cmd = txq->entries[cmd_index].cmd;
1658         meta = &txq->entries[cmd_index].meta;
1659         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1660
1661         iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1662
1663         /* Input error checking is done when commands are added to queue. */
1664         if (meta->flags & CMD_WANT_SKB) {
1665                 struct page *p = rxb_steal_page(rxb);
1666
1667                 meta->source->resp_pkt = pkt;
1668                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1669                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1670         }
1671
1672         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1673                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1674
1675         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1676
1677         if (!(meta->flags & CMD_ASYNC)) {
1678                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1679                         IWL_WARN(trans,
1680                                  "HCMD_ACTIVE already clear for command %s\n",
1681                                  iwl_get_cmd_string(trans, cmd_id));
1682                 }
1683                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1684                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1685                                iwl_get_cmd_string(trans, cmd_id));
1686                 wake_up(&trans_pcie->wait_command_queue);
1687         }
1688
1689         meta->flags = 0;
1690
1691         spin_unlock_bh(&txq->lock);
1692 }
1693
1694 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1695
1696 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1697                                     struct iwl_host_cmd *cmd)
1698 {
1699         int ret;
1700
1701         /* An asynchronous command can not expect an SKB to be set. */
1702         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1703                 return -EINVAL;
1704
1705         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1706         if (ret < 0) {
1707                 IWL_ERR(trans,
1708                         "Error sending %s: enqueue_hcmd failed: %d\n",
1709                         iwl_get_cmd_string(trans, cmd->id), ret);
1710                 return ret;
1711         }
1712         return 0;
1713 }
1714
1715 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1716                                    struct iwl_host_cmd *cmd)
1717 {
1718         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1719         int cmd_idx;
1720         int ret;
1721
1722         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1723                        iwl_get_cmd_string(trans, cmd->id));
1724
1725         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1726                                   &trans->status),
1727                  "Command %s: a command is already active!\n",
1728                  iwl_get_cmd_string(trans, cmd->id)))
1729                 return -EIO;
1730
1731         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1732                        iwl_get_cmd_string(trans, cmd->id));
1733
1734         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1735         if (cmd_idx < 0) {
1736                 ret = cmd_idx;
1737                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1738                 IWL_ERR(trans,
1739                         "Error sending %s: enqueue_hcmd failed: %d\n",
1740                         iwl_get_cmd_string(trans, cmd->id), ret);
1741                 return ret;
1742         }
1743
1744         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1745                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1746                                            &trans->status),
1747                                  HOST_COMPLETE_TIMEOUT);
1748         if (!ret) {
1749                 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1750                 struct iwl_queue *q = &txq->q;
1751
1752                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1753                         iwl_get_cmd_string(trans, cmd->id),
1754                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1755
1756                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1757                         q->read_ptr, q->write_ptr);
1758
1759                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1760                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1761                                iwl_get_cmd_string(trans, cmd->id));
1762                 ret = -ETIMEDOUT;
1763
1764                 iwl_force_nmi(trans);
1765                 iwl_trans_fw_error(trans);
1766
1767                 goto cancel;
1768         }
1769
1770         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1771                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1772                         iwl_get_cmd_string(trans, cmd->id));
1773                 dump_stack();
1774                 ret = -EIO;
1775                 goto cancel;
1776         }
1777
1778         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1779             test_bit(STATUS_RFKILL, &trans->status)) {
1780                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1781                 ret = -ERFKILL;
1782                 goto cancel;
1783         }
1784
1785         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1786                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1787                         iwl_get_cmd_string(trans, cmd->id));
1788                 ret = -EIO;
1789                 goto cancel;
1790         }
1791
1792         return 0;
1793
1794 cancel:
1795         if (cmd->flags & CMD_WANT_SKB) {
1796                 /*
1797                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1798                  * TX cmd queue. Otherwise in case the cmd comes
1799                  * in later, it will possibly set an invalid
1800                  * address (cmd->meta.source).
1801                  */
1802                 trans_pcie->txq[trans_pcie->cmd_queue].
1803                         entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1804         }
1805
1806         if (cmd->resp_pkt) {
1807                 iwl_free_resp(cmd);
1808                 cmd->resp_pkt = NULL;
1809         }
1810
1811         return ret;
1812 }
1813
1814 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1815 {
1816         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1817             test_bit(STATUS_RFKILL, &trans->status)) {
1818                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1819                                   cmd->id);
1820                 return -ERFKILL;
1821         }
1822
1823         if (cmd->flags & CMD_ASYNC)
1824                 return iwl_pcie_send_hcmd_async(trans, cmd);
1825
1826         /* We still can fail on RFKILL that can be asserted while we wait */
1827         return iwl_pcie_send_hcmd_sync(trans, cmd);
1828 }
1829
1830 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1831                              struct iwl_txq *txq, u8 hdr_len,
1832                              struct iwl_cmd_meta *out_meta,
1833                              struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1834 {
1835         struct iwl_queue *q = &txq->q;
1836         u16 tb2_len;
1837         int i;
1838
1839         /*
1840          * Set up TFD's third entry to point directly to remainder
1841          * of skb's head, if any
1842          */
1843         tb2_len = skb_headlen(skb) - hdr_len;
1844
1845         if (tb2_len > 0) {
1846                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1847                                                      skb->data + hdr_len,
1848                                                      tb2_len, DMA_TO_DEVICE);
1849                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1850                         iwl_pcie_tfd_unmap(trans, out_meta,
1851                                            &txq->tfds[q->write_ptr]);
1852                         return -EINVAL;
1853                 }
1854                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1855         }
1856
1857         /* set up the remaining entries to point to the data */
1858         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1859                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1860                 dma_addr_t tb_phys;
1861                 int tb_idx;
1862
1863                 if (!skb_frag_size(frag))
1864                         continue;
1865
1866                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1867                                            skb_frag_size(frag), DMA_TO_DEVICE);
1868
1869                 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1870                         iwl_pcie_tfd_unmap(trans, out_meta,
1871                                            &txq->tfds[q->write_ptr]);
1872                         return -EINVAL;
1873                 }
1874                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1875                                                 skb_frag_size(frag), false);
1876
1877                 out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS);
1878         }
1879
1880         trace_iwlwifi_dev_tx(trans->dev, skb,
1881                              &txq->tfds[txq->q.write_ptr],
1882                              sizeof(struct iwl_tfd),
1883                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1884                              skb->data + hdr_len, tb2_len);
1885         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1886                                   hdr_len, skb->len - hdr_len);
1887         return 0;
1888 }
1889
1890 #ifdef CONFIG_INET
1891 static struct iwl_tso_hdr_page *
1892 get_page_hdr(struct iwl_trans *trans, size_t len)
1893 {
1894         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1895         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
1896
1897         if (!p->page)
1898                 goto alloc;
1899
1900         /* enough room on this page */
1901         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
1902                 return p;
1903
1904         /* We don't have enough room on this page, get a new one. */
1905         __free_page(p->page);
1906
1907 alloc:
1908         p->page = alloc_page(GFP_ATOMIC);
1909         if (!p->page)
1910                 return NULL;
1911         p->pos = page_address(p->page);
1912         return p;
1913 }
1914
1915 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
1916                                         bool ipv6, unsigned int len)
1917 {
1918         if (ipv6) {
1919                 struct ipv6hdr *iphv6 = iph;
1920
1921                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
1922                                                len + tcph->doff * 4,
1923                                                IPPROTO_TCP, 0);
1924         } else {
1925                 struct iphdr *iphv4 = iph;
1926
1927                 ip_send_check(iphv4);
1928                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
1929                                                  len + tcph->doff * 4,
1930                                                  IPPROTO_TCP, 0);
1931         }
1932 }
1933
1934 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
1935                                    struct iwl_txq *txq, u8 hdr_len,
1936                                    struct iwl_cmd_meta *out_meta,
1937                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1938 {
1939         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1940         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
1941         struct ieee80211_hdr *hdr = (void *)skb->data;
1942         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
1943         unsigned int mss = skb_shinfo(skb)->gso_size;
1944         struct iwl_queue *q = &txq->q;
1945         u16 length, iv_len, amsdu_pad;
1946         u8 *start_hdr;
1947         struct iwl_tso_hdr_page *hdr_page;
1948         int ret;
1949         struct tso_t tso;
1950
1951         /* if the packet is protected, then it must be CCMP or GCMP */
1952         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
1953         iv_len = ieee80211_has_protected(hdr->frame_control) ?
1954                 IEEE80211_CCMP_HDR_LEN : 0;
1955
1956         trace_iwlwifi_dev_tx(trans->dev, skb,
1957                              &txq->tfds[txq->q.write_ptr],
1958                              sizeof(struct iwl_tfd),
1959                              &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1960                              NULL, 0);
1961
1962         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
1963         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
1964         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
1965         amsdu_pad = 0;
1966
1967         /* total amount of header we may need for this A-MSDU */
1968         hdr_room = DIV_ROUND_UP(total_len, mss) *
1969                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
1970
1971         /* Our device supports 9 segments at most, it will fit in 1 page */
1972         hdr_page = get_page_hdr(trans, hdr_room);
1973         if (!hdr_page)
1974                 return -ENOMEM;
1975
1976         get_page(hdr_page->page);
1977         start_hdr = hdr_page->pos;
1978         info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = hdr_page->page;
1979         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
1980         hdr_page->pos += iv_len;
1981
1982         /*
1983          * Pull the ieee80211 header + IV to be able to use TSO core,
1984          * we will restore it for the tx_status flow.
1985          */
1986         skb_pull(skb, hdr_len + iv_len);
1987
1988         tso_start(skb, &tso);
1989
1990         while (total_len) {
1991                 /* this is the data left for this subframe */
1992                 unsigned int data_left =
1993                         min_t(unsigned int, mss, total_len);
1994                 struct sk_buff *csum_skb = NULL;
1995                 unsigned int hdr_tb_len;
1996                 dma_addr_t hdr_tb_phys;
1997                 struct tcphdr *tcph;
1998                 u8 *iph;
1999
2000                 total_len -= data_left;
2001
2002                 memset(hdr_page->pos, 0, amsdu_pad);
2003                 hdr_page->pos += amsdu_pad;
2004                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2005                                   data_left)) & 0x3;
2006                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2007                 hdr_page->pos += ETH_ALEN;
2008                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2009                 hdr_page->pos += ETH_ALEN;
2010
2011                 length = snap_ip_tcp_hdrlen + data_left;
2012                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2013                 hdr_page->pos += sizeof(length);
2014
2015                 /*
2016                  * This will copy the SNAP as well which will be considered
2017                  * as MAC header.
2018                  */
2019                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2020                 iph = hdr_page->pos + 8;
2021                 tcph = (void *)(iph + ip_hdrlen);
2022
2023                 /* For testing on current hardware only */
2024                 if (trans_pcie->sw_csum_tx) {
2025                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2026                                              GFP_ATOMIC);
2027                         if (!csum_skb) {
2028                                 ret = -ENOMEM;
2029                                 goto out_unmap;
2030                         }
2031
2032                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2033                                                     skb->protocol ==
2034                                                         htons(ETH_P_IPV6),
2035                                                     data_left);
2036
2037                         memcpy(skb_put(csum_skb, tcp_hdrlen(skb)),
2038                                tcph, tcp_hdrlen(skb));
2039                         skb_set_transport_header(csum_skb, 0);
2040                         csum_skb->csum_start =
2041                                 (unsigned char *)tcp_hdr(csum_skb) -
2042                                                  csum_skb->head;
2043                 }
2044
2045                 hdr_page->pos += snap_ip_tcp_hdrlen;
2046
2047                 hdr_tb_len = hdr_page->pos - start_hdr;
2048                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2049                                              hdr_tb_len, DMA_TO_DEVICE);
2050                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2051                         dev_kfree_skb(csum_skb);
2052                         ret = -EINVAL;
2053                         goto out_unmap;
2054                 }
2055                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2056                                        hdr_tb_len, false);
2057                 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2058                                                hdr_tb_len);
2059
2060                 /* prepare the start_hdr for the next subframe */
2061                 start_hdr = hdr_page->pos;
2062
2063                 /* put the payload */
2064                 while (data_left) {
2065                         unsigned int size = min_t(unsigned int, tso.size,
2066                                                   data_left);
2067                         dma_addr_t tb_phys;
2068
2069                         if (trans_pcie->sw_csum_tx)
2070                                 memcpy(skb_put(csum_skb, size), tso.data, size);
2071
2072                         tb_phys = dma_map_single(trans->dev, tso.data,
2073                                                  size, DMA_TO_DEVICE);
2074                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2075                                 dev_kfree_skb(csum_skb);
2076                                 ret = -EINVAL;
2077                                 goto out_unmap;
2078                         }
2079
2080                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2081                                                size, false);
2082                         trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2083                                                        size);
2084
2085                         data_left -= size;
2086                         tso_build_data(skb, &tso, size);
2087                 }
2088
2089                 /* For testing on early hardware only */
2090                 if (trans_pcie->sw_csum_tx) {
2091                         __wsum csum;
2092
2093                         csum = skb_checksum(csum_skb,
2094                                             skb_checksum_start_offset(csum_skb),
2095                                             csum_skb->len -
2096                                             skb_checksum_start_offset(csum_skb),
2097                                             0);
2098                         dev_kfree_skb(csum_skb);
2099                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2100                                                 hdr_tb_len, DMA_TO_DEVICE);
2101                         tcph->check = csum_fold(csum);
2102                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2103                                                    hdr_tb_len, DMA_TO_DEVICE);
2104                 }
2105         }
2106
2107         /* re -add the WiFi header and IV */
2108         skb_push(skb, hdr_len + iv_len);
2109
2110         return 0;
2111
2112 out_unmap:
2113         iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]);
2114         return ret;
2115 }
2116 #else /* CONFIG_INET */
2117 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2118                                    struct iwl_txq *txq, u8 hdr_len,
2119                                    struct iwl_cmd_meta *out_meta,
2120                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2121 {
2122         /* No A-MSDU without CONFIG_INET */
2123         WARN_ON(1);
2124
2125         return -1;
2126 }
2127 #endif /* CONFIG_INET */
2128
2129 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2130                       struct iwl_device_cmd *dev_cmd, int txq_id)
2131 {
2132         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2133         struct ieee80211_hdr *hdr;
2134         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2135         struct iwl_cmd_meta *out_meta;
2136         struct iwl_txq *txq;
2137         struct iwl_queue *q;
2138         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2139         void *tb1_addr;
2140         u16 len, tb1_len;
2141         bool wait_write_ptr;
2142         __le16 fc;
2143         u8 hdr_len;
2144         u16 wifi_seq;
2145
2146         txq = &trans_pcie->txq[txq_id];
2147         q = &txq->q;
2148
2149         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2150                       "TX on unused queue %d\n", txq_id))
2151                 return -EINVAL;
2152
2153         if (unlikely(trans_pcie->sw_csum_tx &&
2154                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2155                 int offs = skb_checksum_start_offset(skb);
2156                 int csum_offs = offs + skb->csum_offset;
2157                 __wsum csum;
2158
2159                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2160                         return -1;
2161
2162                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2163                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2164         }
2165
2166         if (skb_is_nonlinear(skb) &&
2167             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS &&
2168             __skb_linearize(skb))
2169                 return -ENOMEM;
2170
2171         /* mac80211 always puts the full header into the SKB's head,
2172          * so there's no need to check if it's readable there
2173          */
2174         hdr = (struct ieee80211_hdr *)skb->data;
2175         fc = hdr->frame_control;
2176         hdr_len = ieee80211_hdrlen(fc);
2177
2178         spin_lock(&txq->lock);
2179
2180         /* In AGG mode, the index in the ring must correspond to the WiFi
2181          * sequence number. This is a HW requirements to help the SCD to parse
2182          * the BA.
2183          * Check here that the packets are in the right place on the ring.
2184          */
2185         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2186         WARN_ONCE(txq->ampdu &&
2187                   (wifi_seq & 0xff) != q->write_ptr,
2188                   "Q: %d WiFi Seq %d tfdNum %d",
2189                   txq_id, wifi_seq, q->write_ptr);
2190
2191         /* Set up driver data for this TFD */
2192         txq->entries[q->write_ptr].skb = skb;
2193         txq->entries[q->write_ptr].cmd = dev_cmd;
2194
2195         dev_cmd->hdr.sequence =
2196                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2197                             INDEX_TO_SEQ(q->write_ptr)));
2198
2199         tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
2200         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2201                        offsetof(struct iwl_tx_cmd, scratch);
2202
2203         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2204         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2205
2206         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2207         out_meta = &txq->entries[q->write_ptr].meta;
2208         out_meta->flags = 0;
2209
2210         /*
2211          * The second TB (tb1) points to the remainder of the TX command
2212          * and the 802.11 header - dword aligned size
2213          * (This calculation modifies the TX command, so do it before the
2214          * setup of the first TB)
2215          */
2216         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2217               hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
2218         tb1_len = ALIGN(len, 4);
2219
2220         /* Tell NIC about any 2-byte padding after MAC header */
2221         if (tb1_len != len)
2222                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2223
2224         /* The first TB points to the scratchbuf data - min_copy bytes */
2225         memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
2226                IWL_HCMD_SCRATCHBUF_SIZE);
2227         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2228                                IWL_HCMD_SCRATCHBUF_SIZE, true);
2229
2230         /* there must be data left over for TB1 or this code must be changed */
2231         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
2232
2233         /* map the data for TB1 */
2234         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
2235         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2236         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2237                 goto out_err;
2238         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2239
2240         if (ieee80211_is_data_qos(fc) &&
2241             (*ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_A_MSDU_PRESENT)) {
2242                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2243                                                      out_meta, dev_cmd,
2244                                                      tb1_len)))
2245                         goto out_err;
2246         } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2247                                        out_meta, dev_cmd, tb1_len))) {
2248                 goto out_err;
2249         }
2250
2251         /* Set up entry for this TFD in Tx byte-count array */
2252         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
2253
2254         wait_write_ptr = ieee80211_has_morefrags(fc);
2255
2256         /* start timer if queue currently empty */
2257         if (q->read_ptr == q->write_ptr) {
2258                 if (txq->wd_timeout) {
2259                         /*
2260                          * If the TXQ is active, then set the timer, if not,
2261                          * set the timer in remainder so that the timer will
2262                          * be armed with the right value when the station will
2263                          * wake up.
2264                          */
2265                         if (!txq->frozen)
2266                                 mod_timer(&txq->stuck_timer,
2267                                           jiffies + txq->wd_timeout);
2268                         else
2269                                 txq->frozen_expiry_remainder = txq->wd_timeout;
2270                 }
2271                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
2272                 iwl_trans_pcie_ref(trans);
2273         }
2274
2275         /* Tell device the write index *just past* this latest filled TFD */
2276         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
2277         if (!wait_write_ptr)
2278                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2279
2280         /*
2281          * At this point the frame is "transmitted" successfully
2282          * and we will get a TX status notification eventually.
2283          */
2284         if (iwl_queue_space(q) < q->high_mark) {
2285                 if (wait_write_ptr)
2286                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
2287                 else
2288                         iwl_stop_queue(trans, txq);
2289         }
2290         spin_unlock(&txq->lock);
2291         return 0;
2292 out_err:
2293         spin_unlock(&txq->lock);
2294         return -1;
2295 }