1 /******************************************************************************
3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 The full GNU General Public License is included in this distribution in the
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #define WEXT_USECHANNELS 1
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/config.h>
35 #include <linux/init.h>
37 #include <linux/version.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/skbuff.h>
42 #include <linux/etherdevice.h>
43 #include <linux/delay.h>
44 #include <linux/random.h>
46 #include <linux/firmware.h>
47 #include <linux/wireless.h>
50 #include <net/ieee80211.h>
52 #define DRV_NAME "ipw2200"
54 #include <linux/workqueue.h>
56 /* Authentication and Association States */
57 enum connection_manager_assoc_states
78 #define IPW_WAIT (1<<0)
79 #define IPW_QUIET (1<<1)
80 #define IPW_ROAMING (1<<2)
82 #define IPW_POWER_MODE_CAM 0x00 //(always on)
83 #define IPW_POWER_INDEX_1 0x01
84 #define IPW_POWER_INDEX_2 0x02
85 #define IPW_POWER_INDEX_3 0x03
86 #define IPW_POWER_INDEX_4 0x04
87 #define IPW_POWER_INDEX_5 0x05
88 #define IPW_POWER_AC 0x06
89 #define IPW_POWER_BATTERY 0x07
90 #define IPW_POWER_LIMIT 0x07
91 #define IPW_POWER_MASK 0x0F
92 #define IPW_POWER_ENABLED 0x10
93 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
95 #define IPW_CMD_HOST_COMPLETE 2
96 #define IPW_CMD_POWER_DOWN 4
97 #define IPW_CMD_SYSTEM_CONFIG 6
98 #define IPW_CMD_MULTICAST_ADDRESS 7
99 #define IPW_CMD_SSID 8
100 #define IPW_CMD_ADAPTER_ADDRESS 11
101 #define IPW_CMD_PORT_TYPE 12
102 #define IPW_CMD_RTS_THRESHOLD 15
103 #define IPW_CMD_FRAG_THRESHOLD 16
104 #define IPW_CMD_POWER_MODE 17
105 #define IPW_CMD_WEP_KEY 18
106 #define IPW_CMD_TGI_TX_KEY 19
107 #define IPW_CMD_SCAN_REQUEST 20
108 #define IPW_CMD_ASSOCIATE 21
109 #define IPW_CMD_SUPPORTED_RATES 22
110 #define IPW_CMD_SCAN_ABORT 23
111 #define IPW_CMD_TX_FLUSH 24
112 #define IPW_CMD_QOS_PARAMETERS 25
113 #define IPW_CMD_SCAN_REQUEST_EXT 26
114 #define IPW_CMD_DINO_CONFIG 30
115 #define IPW_CMD_RSN_CAPABILITIES 31
116 #define IPW_CMD_RX_KEY 32
117 #define IPW_CMD_CARD_DISABLE 33
118 #define IPW_CMD_SEED_NUMBER 34
119 #define IPW_CMD_TX_POWER 35
120 #define IPW_CMD_COUNTRY_INFO 36
121 #define IPW_CMD_AIRONET_INFO 37
122 #define IPW_CMD_AP_TX_POWER 38
123 #define IPW_CMD_CCKM_INFO 39
124 #define IPW_CMD_CCX_VER_INFO 40
125 #define IPW_CMD_SET_CALIBRATION 41
126 #define IPW_CMD_SENSITIVITY_CALIB 42
127 #define IPW_CMD_RETRY_LIMIT 51
128 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
129 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
130 #define IPW_CMD_VAP_DTIM_PERIOD 61
131 #define IPW_CMD_EXT_SUPPORTED_RATES 62
132 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
133 #define IPW_CMD_VAP_QUIET_INTERVALS 64
134 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
135 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
136 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
137 #define IPW_CMD_VAP_CF_PARAM_SET 68
138 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
139 #define IPW_CMD_MEASUREMENT 80
140 #define IPW_CMD_POWER_CAPABILITY 81
141 #define IPW_CMD_SUPPORTED_CHANNELS 82
142 #define IPW_CMD_TPC_REPORT 83
143 #define IPW_CMD_WME_INFO 84
144 #define IPW_CMD_PRODUCTION_COMMAND 85
145 #define IPW_CMD_LINKSYS_EOU_INFO 90
148 #define NUM_TFD_CHUNKS 6
150 #define TX_QUEUE_SIZE 32
151 #define RX_QUEUE_SIZE 32
153 #define DINO_CMD_WEP_KEY 0x08
154 #define DINO_CMD_TX 0x0B
155 #define DCT_ANTENNA_A 0x01
156 #define DCT_ANTENNA_B 0x02
163 * TX Queue Flag Definitions
166 /* abort attempt if mgmt frame is rx'd */
167 #define DCT_FLAG_ABORT_MGMT 0x01
170 #define DCT_FLAG_CTS_REQUIRED 0x02
172 /* use short preamble */
173 #define DCT_FLAG_SHORT_PREMBL 0x04
176 #define DCT_FLAG_RTS_REQD 0x08
178 /* dont calculate duration field */
179 #define DCT_FLAG_DUR_SET 0x10
181 /* even if MAC WEP set (allows pre-encrypt) */
182 #define DCT_FLAG_NO_WEP 0x20
184 /* overwrite TSF field */
185 #define DCT_FLAG_TSF_REQD 0x40
187 /* ACK rx is expected to follow */
188 #define DCT_FLAG_ACK_REQD 0x80
190 #define DCT_FLAG_EXT_MODE_CCK 0x01
191 #define DCT_FLAG_EXT_MODE_OFDM 0x00
194 #define TX_RX_TYPE_MASK 0xFF
195 #define TX_FRAME_TYPE 0x00
196 #define TX_HOST_COMMAND_TYPE 0x01
197 #define RX_FRAME_TYPE 0x09
198 #define RX_HOST_NOTIFICATION_TYPE 0x03
199 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
200 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
201 #define TFD_NEED_IRQ_MASK 0x04
203 #define HOST_CMD_DINO_CONFIG 30
205 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
206 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
207 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
208 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
209 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
210 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
211 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
212 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
213 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
214 #define HOST_NOTIFICATION_TX_STATUS 19
215 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
216 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
217 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
218 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
219 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
220 #define HOST_NOTIFICATION_NOISE_STATS 25
221 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
222 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
224 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
225 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
226 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
227 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
229 #define MACADRR_BYTE_LEN 6
231 #define DCR_TYPE_AP 0x01
232 #define DCR_TYPE_WLAP 0x02
233 #define DCR_TYPE_MU_ESS 0x03
234 #define DCR_TYPE_MU_IBSS 0x04
235 #define DCR_TYPE_MU_PIBSS 0x05
236 #define DCR_TYPE_SNIFFER 0x06
237 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
240 * Generic queue structure
242 * Contains common data for Rx and Tx queues
245 int n_bd; /**< number of BDs in this queue */
246 int first_empty; /**< 1-st empty entry (index) */
247 int last_used; /**< last used entry (index) */
248 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
249 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
250 dma_addr_t dma_addr; /**< physical addr for BD's */
251 int low_mark; /**< low watermark, resume queue if free space more than this */
252 int high_mark; /**< high watermark, stop queue if free space less than this */
253 } __attribute__ ((packed));
258 u16 duration; // watch out for endians!
259 u8 addr1[ MACADRR_BYTE_LEN ];
260 u8 addr2[ MACADRR_BYTE_LEN ];
261 u8 addr3[ MACADRR_BYTE_LEN ];
262 u16 seq_ctrl; // more endians!
263 u8 addr4[ MACADRR_BYTE_LEN ];
265 } __attribute__ ((packed)) ;
270 u16 duration; // watch out for endians!
271 u8 addr1[ MACADRR_BYTE_LEN ];
272 u8 addr2[ MACADRR_BYTE_LEN ];
273 u8 addr3[ MACADRR_BYTE_LEN ];
274 u16 seq_ctrl; // more endians!
275 u8 addr4[ MACADRR_BYTE_LEN ];
276 } __attribute__ ((packed)) ;
281 u16 duration; // watch out for endians!
282 u8 addr1[ MACADRR_BYTE_LEN ];
283 u8 addr2[ MACADRR_BYTE_LEN ];
284 u8 addr3[ MACADRR_BYTE_LEN ];
285 u16 seq_ctrl; // more endians!
287 } __attribute__ ((packed)) ;
292 u16 duration; // watch out for endians!
293 u8 addr1[ MACADRR_BYTE_LEN ];
294 u8 addr2[ MACADRR_BYTE_LEN ];
295 u8 addr3[ MACADRR_BYTE_LEN ];
296 u16 seq_ctrl; // more endians!
297 } __attribute__ ((packed)) ;
299 // TX TFD with 32 byte MAC Header
302 struct machdr32 mchdr; // 32
303 u32 uivplaceholder[2]; // 8
304 } __attribute__ ((packed)) ;
306 // TX TFD with 30 byte MAC Header
309 struct machdr30 mchdr; // 30
311 u32 uivplaceholder[2]; // 8
312 } __attribute__ ((packed)) ;
314 // tx tfd with 26 byte mac header
317 struct machdr26 mchdr; // 26
318 u8 reserved1[2]; // 2
319 u32 uivplaceholder[2]; // 8
320 u8 reserved2[4]; // 4
321 } __attribute__ ((packed)) ;
323 // tx tfd with 24 byte mac header
326 struct machdr24 mchdr; // 24
327 u32 uivplaceholder[2]; // 8
329 } __attribute__ ((packed)) ;
332 #define DCT_WEP_KEY_FIELD_LENGTH 16
340 } __attribute__ ((packed)) ;
345 u8 station_number; /* 0 for BSS */
357 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
360 u16 next_packet_duration;
362 u16 back_off_counter; //////txop;
367 /* 802.11 MAC Header */
370 struct tx_tfd_24 tfd_24;
371 struct tx_tfd_26 tfd_26;
372 struct tx_tfd_30 tfd_30;
373 struct tx_tfd_32 tfd_32;
376 /* Payload DMA info */
378 u32 chunk_ptr[NUM_TFD_CHUNKS];
379 u16 chunk_len[NUM_TFD_CHUNKS];
380 } __attribute__ ((packed));
382 struct txrx_control_flags
388 } __attribute__ ((packed));
391 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
395 struct txrx_control_flags control_flags;
397 struct tfd_data data;
398 struct tfd_command cmd;
399 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
401 } __attribute__ ((packed)) ;
403 typedef void destructor_func(const void*);
406 * Tx Queue for DMA. Queue consists of circular buffer of
407 * BD's and required locking structures.
409 struct clx2_tx_queue {
411 struct tfd_frame* bd;
412 struct ieee80211_txb **txb;
416 * RX related structures and functions
418 #define RX_FREE_BUFFERS 32
419 #define RX_LOW_WATERMARK 8
421 #define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
422 #define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
423 #define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
425 // Used for passing to driver number of successes and failures per rate
426 struct rate_histogram
429 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
430 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
431 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
434 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
435 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
436 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
438 } __attribute__ ((packed));
440 /* statistics command response */
441 struct ipw_cmd_stats {
449 u16 reserved_frame_types;
454 u16 long_distance_ina_fina;
455 u16 dsp_silence_unreachable;
456 u16 accumulated_rssi;
457 u16 rx_ovfl_frame_tossed;
458 u16 rssi_silence_threshold;
459 u16 rx_ovfl_frame_supplied;
460 u16 last_rx_frame_signal;
461 u16 last_rx_frame_noise;
462 u16 rx_autodetec_no_ofdm;
463 u16 rx_autodetec_no_barker;
465 } __attribute__ ((packed));
467 struct notif_channel_result {
469 struct ipw_cmd_stats stats;
471 } __attribute__ ((packed));
473 struct notif_scan_complete {
478 } __attribute__ ((packed));
480 struct notif_frag_length {
483 } __attribute__ ((packed));
485 struct notif_beacon_state {
488 } __attribute__ ((packed));
490 struct notif_tgi_tx_key {
495 } __attribute__ ((packed));
497 struct notif_link_deterioration {
498 struct ipw_cmd_stats stats;
501 struct rate_histogram histogram;
504 } __attribute__ ((packed));
506 struct notif_association {
508 } __attribute__ ((packed));
510 struct notif_authenticate {
512 struct machdr24 addr;
514 } __attribute__ ((packed));
520 } __attribute__ ((packed));
522 struct notif_calibration {
524 } __attribute__ ((packed));
528 } __attribute__ ((packed));
530 struct ipw_rx_notification {
536 struct notif_association assoc;
537 struct notif_authenticate auth;
538 struct notif_channel_result channel_result;
539 struct notif_scan_complete scan_complete;
540 struct notif_frag_length frag_len;
541 struct notif_beacon_state beacon_state;
542 struct notif_tgi_tx_key tgi_tx_key;
543 struct notif_link_deterioration link_deterioration;
544 struct notif_calibration calibration;
545 struct notif_noise noise;
548 } __attribute__ ((packed));
550 struct ipw_rx_frame {
552 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
553 u8 received_channel; // The channel that this frame was received on.
554 // Note that for .11b this does not have to be
555 // the same as the channel that it was sent.
565 u8 control; // control bit should be on in bg
566 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
568 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
571 } __attribute__ ((packed));
573 struct ipw_rx_header {
578 } __attribute__ ((packed));
582 struct ipw_rx_header header;
584 struct ipw_rx_frame frame;
585 struct ipw_rx_notification notification;
587 } __attribute__ ((packed));
589 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
590 #define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
591 sizeof(struct ipw_rx_frame)
593 struct ipw_rx_mem_buffer {
595 struct ipw_rx_buffer *rxb;
597 struct list_head list;
598 }; /* Not transferred over network, so not __attribute__ ((packed)) */
600 struct ipw_rx_queue {
601 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
602 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
603 u32 processed; /* Internal index to last handled Rx packet */
604 u32 read; /* Shared index to newest available Rx buffer */
605 u32 write; /* Shared index to oldest written Rx packet */
606 u32 free_count;/* Number of pre-allocated buffers in rx_free */
607 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
608 struct list_head rx_free; /* Own an SKBs */
609 struct list_head rx_used; /* No SKB allocated */
611 }; /* Not transferred over network, so not __attribute__ ((packed)) */
614 struct alive_command_responce {
617 u16 software_revision;
618 u8 device_identifier;
622 u16 clock_settle_time;
623 u16 powerup_settle_time;
625 u8 time_stamp[5]; /* month, day, year, hours, minutes */
627 } __attribute__ ((packed));
629 #define IPW_MAX_RATES 12
633 u8 rates[IPW_MAX_RATES];
634 } __attribute__ ((packed));
638 unsigned int control;
642 } __attribute__ ((packed));
644 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
647 unsigned long last_cb_index;
648 unsigned long current_cb_index;
649 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
651 unsigned long p_addr;
655 struct ipw_sys_config
659 u8 answer_broadcast_ssid_probe;
660 u8 accept_all_data_frames;
661 u8 accept_non_directed_frames;
662 u8 exclude_unicast_unencrypted;
663 u8 disable_unicast_decryption;
664 u8 exclude_multicast_unencrypted;
665 u8 disable_multicast_decryption;
666 u8 antenna_diversity;
668 u8 dot11g_auto_detection;
669 u8 enable_cts_to_self;
670 u8 enable_multicast_filtering;
671 u8 bt_coexist_collision_thr;
673 u8 accept_all_mgmt_bcpr;
674 u8 accept_all_mgtm_frames;
675 u8 pass_noise_stats_to_host;
677 } __attribute__ ((packed));
679 struct ipw_multicast_addr
681 u8 num_of_multicast_addresses;
687 } __attribute__ ((packed));
696 } __attribute__ ((packed));
698 struct ipw_tgi_tx_key
706 } __attribute__ ((packed));
708 #define IPW_SCAN_CHANNELS 54
710 struct ipw_scan_request
714 u8 channels_list[IPW_SCAN_CHANNELS];
715 u8 channels_reserved[3];
716 } __attribute__ ((packed));
719 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
720 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
721 IPW_SCAN_ACTIVE_DIRECT_SCAN,
722 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
723 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
727 struct ipw_scan_request_ext
730 u8 channels_list[IPW_SCAN_CHANNELS];
731 u8 scan_type[IPW_SCAN_CHANNELS / 2];
733 u16 dwell_time[IPW_SCAN_TYPES];
734 } __attribute__ ((packed));
736 extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
739 return scan->scan_type[index / 2] & 0x0F;
741 return (scan->scan_type[index / 2] & 0xF0) >> 4;
744 extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
745 u8 index, u8 scan_type)
748 scan->scan_type[index / 2] =
749 (scan->scan_type[index / 2] & 0xF0) |
752 scan->scan_type[index / 2] =
753 (scan->scan_type[index / 2] & 0x0F) |
754 ((scan_type & 0x0F) << 4);
778 } __attribute__ ((packed));
780 struct ipw_supported_rates
786 u8 supported_rates[IPW_MAX_RATES];
787 } __attribute__ ((packed));
789 struct ipw_rts_threshold
793 } __attribute__ ((packed));
795 struct ipw_frag_threshold
799 } __attribute__ ((packed));
801 struct ipw_retry_limit
803 u8 short_retry_limit;
806 } __attribute__ ((packed));
808 struct ipw_dino_config
810 u32 dino_config_addr;
811 u16 dino_config_size;
814 } __attribute__ ((packed));
816 struct ipw_aironet_info
821 } __attribute__ ((packed));
830 u8 station_address[6];
833 } __attribute__ ((packed));
835 struct ipw_country_channel_info
840 } __attribute__ ((packed));
842 struct ipw_country_info
847 struct ipw_country_channel_info groups[7];
848 } __attribute__ ((packed));
850 struct ipw_channel_tx_power
854 } __attribute__ ((packed));
856 #define SCAN_ASSOCIATED_INTERVAL (HZ)
857 #define SCAN_INTERVAL (HZ / 10)
858 #define MAX_A_CHANNELS 37
859 #define MAX_B_CHANNELS 14
865 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
866 } __attribute__ ((packed));
868 struct ipw_qos_parameters
875 } __attribute__ ((packed));
877 struct ipw_rsn_capabilities
882 } __attribute__ ((packed));
884 struct ipw_sensitivity_calib
888 } __attribute__ ((packed));
891 * Host command structure.
893 * On input, the following fields should be filled:
897 * - param (if needed)
900 * - \a status contains status;
901 * - \a param filled with status parameters.
904 u32 cmd; /**< Host command */
905 u32 status; /**< Status */
906 u32 status_len; /**< How many 32 bit parameters in the status */
907 u32 len; /**< incoming parameters length, bytes */
909 * command parameters.
910 * There should be enough space for incoming and
911 * outcoming parameters.
912 * Incoming parameters listed 1-st, followed by outcoming params.
913 * nParams=(len+3)/4+status_len
916 } __attribute__ ((packed));
918 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
920 #define STATUS_INT_ENABLED (1<<1)
921 #define STATUS_RF_KILL_HW (1<<2)
922 #define STATUS_RF_KILL_SW (1<<3)
923 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
925 #define STATUS_INIT (1<<5)
926 #define STATUS_AUTH (1<<6)
927 #define STATUS_ASSOCIATED (1<<7)
928 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
930 #define STATUS_ASSOCIATING (1<<8)
931 #define STATUS_DISASSOCIATING (1<<9)
932 #define STATUS_ROAMING (1<<10)
933 #define STATUS_EXIT_PENDING (1<<11)
934 #define STATUS_DISASSOC_PENDING (1<<12)
935 #define STATUS_STATE_PENDING (1<<13)
937 #define STATUS_SCAN_PENDING (1<<20)
938 #define STATUS_SCANNING (1<<21)
939 #define STATUS_SCAN_ABORTING (1<<22)
941 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
942 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
943 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
945 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
947 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
948 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
949 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
950 #define CFG_CUSTOM_MAC (1<<3)
951 #define CFG_PREAMBLE (1<<4)
952 #define CFG_ADHOC_PERSIST (1<<5)
953 #define CFG_ASSOCIATE (1<<6)
954 #define CFG_FIXED_RATE (1<<7)
955 #define CFG_ADHOC_CREATE (1<<8)
957 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
958 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
960 #define MAX_STATIONS 32
961 #define IPW_INVALID_STATION (0xff)
963 struct ipw_station_entry {
964 u8 mac_addr[ETH_ALEN];
969 #define AVG_ENTRIES 8
971 s16 entries[AVG_ENTRIES];
978 /* ieee device used by generic ieee processing code */
979 struct ieee80211_device *ieee;
980 struct ieee80211_security sec;
985 /* basic pci-network driver stuff */
986 struct pci_dev *pci_dev;
987 struct net_device *net_dev;
989 /* pci hardware address support */
990 void __iomem *hw_base;
991 unsigned long hw_len;
993 struct fw_image_desc sram_desc;
995 /* result of ucode download */
996 struct alive_command_responce dino_alive;
998 wait_queue_head_t wait_command_queue;
999 wait_queue_head_t wait_state;
1001 /* Rx and Tx DMA processing queues */
1002 struct ipw_rx_queue *rxq;
1003 struct clx2_tx_queue txq_cmd;
1004 struct clx2_tx_queue txq[4];
1011 struct average average_missed_beacons;
1012 struct average average_rssi;
1013 struct average average_noise;
1015 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1016 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1017 u32 hcmd_seq; /**< sequence number for hcmd */
1018 u32 missed_beacon_threshold;
1019 u32 roaming_threshold;
1021 struct ipw_associate assoc_request;
1022 struct ieee80211_network *assoc_network;
1024 unsigned long ts_scan_abort;
1025 struct ipw_supported_rates rates;
1026 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1027 struct ipw_rates supp; /**< software defined */
1028 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1030 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1031 struct ipw_cmd* hcmd; /**< host command currently executed */
1033 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1034 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1036 struct notif_calibration calib; /**< last calibration */
1038 /* ordinal interface with firmware */
1046 /* context information */
1047 u8 essid[IW_ESSID_MAX_SIZE];
1049 u8 nick[IW_ESSID_MAX_SIZE];
1052 struct ipw_sys_config sys_config;
1056 u8 mac_addr[ETH_ALEN];
1058 u8 stations[MAX_STATIONS][ETH_ALEN];
1060 u32 notif_missed_beacons;
1062 /* Statistics and counters normalized with each association */
1063 u32 last_missed_beacons;
1064 u32 last_tx_packets;
1065 u32 last_rx_packets;
1066 u32 last_tx_failures;
1070 u32 missed_adhoc_beacons;
1077 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1080 struct iw_statistics wstats;
1082 struct workqueue_struct *workqueue;
1084 struct work_struct adhoc_check;
1085 struct work_struct associate;
1086 struct work_struct disassociate;
1087 struct work_struct rx_replenish;
1088 struct work_struct request_scan;
1089 struct work_struct adapter_restart;
1090 struct work_struct rf_kill;
1091 struct work_struct up;
1092 struct work_struct down;
1093 struct work_struct gather_stats;
1094 struct work_struct abort_scan;
1095 struct work_struct roam;
1096 struct work_struct scan_check;
1098 struct tasklet_struct irq_tasklet;
1101 #define IPW_2200BG 1
1102 #define IPW_2915ABG 2
1105 #define IPW_DEFAULT_TX_POWER 0x14
1114 /* Used to pass the current INTA value from ISR to Tasklet */
1117 /* debugging info */
1126 #ifdef CONFIG_IPW_DEBUG
1127 #define IPW_DEBUG(level, fmt, args...) \
1128 do { if (ipw_debug_level & (level)) \
1129 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1130 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1132 #define IPW_DEBUG(level, fmt, args...) do {} while (0)
1133 #endif /* CONFIG_IPW_DEBUG */
1136 * To use the debug system;
1138 * If you are defining a new debug classification, simply add it to the #define
1139 * list here in the form of:
1141 * #define IPW_DL_xxxx VALUE
1143 * shifting value to the left one bit from the previous entry. xxxx should be
1144 * the name of the classification (for example, WEP)
1146 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1147 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1148 * to send output to that classification.
1150 * To add your debug level to the list of levels seen when you perform
1152 * % cat /proc/net/ipw/debug_level
1154 * you simply need to add your entry to the ipw_debug_levels array.
1156 * If you do not see debug_level in /proc/net/ipw then you do not have
1157 * CONFIG_IPW_DEBUG defined in your kernel configuration
1161 #define IPW_DL_ERROR (1<<0)
1162 #define IPW_DL_WARNING (1<<1)
1163 #define IPW_DL_INFO (1<<2)
1164 #define IPW_DL_WX (1<<3)
1165 #define IPW_DL_HOST_COMMAND (1<<5)
1166 #define IPW_DL_STATE (1<<6)
1168 #define IPW_DL_NOTIF (1<<10)
1169 #define IPW_DL_SCAN (1<<11)
1170 #define IPW_DL_ASSOC (1<<12)
1171 #define IPW_DL_DROP (1<<13)
1172 #define IPW_DL_IOCTL (1<<14)
1174 #define IPW_DL_MANAGE (1<<15)
1175 #define IPW_DL_FW (1<<16)
1176 #define IPW_DL_RF_KILL (1<<17)
1177 #define IPW_DL_FW_ERRORS (1<<18)
1180 #define IPW_DL_ORD (1<<20)
1182 #define IPW_DL_FRAG (1<<21)
1183 #define IPW_DL_WEP (1<<22)
1184 #define IPW_DL_TX (1<<23)
1185 #define IPW_DL_RX (1<<24)
1186 #define IPW_DL_ISR (1<<25)
1187 #define IPW_DL_FW_INFO (1<<26)
1188 #define IPW_DL_IO (1<<27)
1189 #define IPW_DL_TRACE (1<<28)
1191 #define IPW_DL_STATS (1<<29)
1194 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1195 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1196 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1198 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1199 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1200 #define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1201 #define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1202 #define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1203 #define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1204 #define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1205 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1206 #define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1207 #define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1208 #define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1209 #define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1210 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1211 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1212 #define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1213 #define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1214 #define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1215 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1216 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1217 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1218 #define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1220 #include <linux/ctype.h>
1223 * Register bit definitions
1226 /* Dino control registers bits */
1228 #define DINO_ENABLE_SYSTEM 0x80
1229 #define DINO_ENABLE_CS 0x40
1230 #define DINO_RXFIFO_DATA 0x01
1231 #define DINO_CONTROL_REG 0x00200000
1233 #define CX2_INTA_RW 0x00000008
1234 #define CX2_INTA_MASK_R 0x0000000C
1235 #define CX2_INDIRECT_ADDR 0x00000010
1236 #define CX2_INDIRECT_DATA 0x00000014
1237 #define CX2_AUTOINC_ADDR 0x00000018
1238 #define CX2_AUTOINC_DATA 0x0000001C
1239 #define CX2_RESET_REG 0x00000020
1240 #define CX2_GP_CNTRL_RW 0x00000024
1242 #define CX2_READ_INT_REGISTER 0xFF4
1244 #define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1246 #define CX2_REGISTER_DOMAIN1_END 0x00001000
1247 #define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1249 #define CX2_SHARED_LOWER_BOUND 0x00000200
1250 #define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1252 #define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1253 #define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1255 #define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1256 #define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1257 #define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1260 * RESET Register Bit Indexes
1262 #define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */
1263 #define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */
1264 #define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */
1265 #define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */
1266 #define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */
1267 #define CX2_START_STANDBY 0x00000004 /* Bit 2 */
1269 #define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1270 #define CX2_DOMAIN_0_END 0x1000
1271 #define CLX_MEM_BAR_SIZE 0x1000
1273 #define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1274 #define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1275 #define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1276 #define CX2_BASEBAND_CONTROL_STORE 0X00200010
1278 #define CX2_INTERNAL_CMD_EVENT 0X00300004
1279 #define CX2_BASEBAND_POWER_DOWN 0x00000001
1281 #define CX2_MEM_HALT_AND_RESET 0x003000e0
1283 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1284 #define CX2_BIT_HALT_RESET_ON 0x80000000
1285 #define CX2_BIT_HALT_RESET_OFF 0x00000000
1287 #define CB_LAST_VALID 0x20000000
1288 #define CB_INT_ENABLED 0x40000000
1289 #define CB_VALID 0x80000000
1290 #define CB_SRC_LE 0x08000000
1291 #define CB_DEST_LE 0x04000000
1292 #define CB_SRC_AUTOINC 0x00800000
1293 #define CB_SRC_IO_GATED 0x00400000
1294 #define CB_DEST_AUTOINC 0x00080000
1295 #define CB_SRC_SIZE_LONG 0x00200000
1296 #define CB_DEST_SIZE_LONG 0x00020000
1301 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1302 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1303 #define DMA_CB_START 0x00000100
1306 #define CX2_SHARED_SRAM_SIZE 0x00030000
1307 #define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1308 #define CB_MAX_LENGTH 0x1FFF
1310 #define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1311 #define CX2_EEPROM_IMAGE_SIZE 0x100
1315 #define CX2_DMA_I_CURRENT_CB 0x003000D0
1316 #define CX2_DMA_O_CURRENT_CB 0x003000D4
1317 #define CX2_DMA_I_DMA_CONTROL 0x003000A4
1318 #define CX2_DMA_I_CB_BASE 0x003000A0
1320 #define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
1321 #define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
1322 #define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
1323 #define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
1324 #define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
1325 #define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
1326 #define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
1327 #define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
1328 #define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
1329 #define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
1330 #define CX2_RX_BD_BASE (0x00000240)
1331 #define CX2_RX_BD_SIZE (0x00000244)
1332 #define CX2_RFDS_TABLE_LOWER (0x00000500)
1334 #define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
1335 #define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
1336 #define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
1337 #define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
1338 #define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
1339 #define CX2_RX_READ_INDEX (0x000002A0)
1341 #define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1342 #define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1343 #define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1344 #define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1345 #define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1346 #define CX2_RX_WRITE_INDEX (0x00000FA0)
1349 * EEPROM Related Definitions
1352 #define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1353 #define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1354 #define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1355 #define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1356 #define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1358 #define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1359 #define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1360 #define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1361 #define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1362 #define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1363 #define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1368 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1370 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1371 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1373 /* EEPROM access by BYTE */
1374 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1375 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1376 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1377 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1378 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1379 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1380 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1381 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1382 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1383 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1385 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1386 #define EEPROM_NIC_TYPE_STANDARD 0
1387 #define EEPROM_NIC_TYPE_DELL 1
1388 #define EEPROM_NIC_TYPE_FUJITSU 2
1389 #define EEPROM_NIC_TYPE_IBM 3
1390 #define EEPROM_NIC_TYPE_HP 4
1392 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1393 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1395 #define EEPROM_BIT_SK (1<<0)
1396 #define EEPROM_BIT_CS (1<<1)
1397 #define EEPROM_BIT_DI (1<<2)
1398 #define EEPROM_BIT_DO (1<<4)
1400 #define EEPROM_CMD_READ 0x2
1402 /* Interrupts masks */
1403 #define CX2_INTA_NONE 0x00000000
1405 #define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1406 #define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1407 #define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1410 #define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1411 #define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1412 #define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1413 #define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1414 #define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1416 #define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1418 #define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1419 #define CX2_INTA_BIT_POWER_DOWN 0x00200000
1421 #define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1422 #define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1423 #define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1424 #define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1425 #define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1427 /* Interrupts enabled at init time. */
1428 #define CX2_INTA_MASK_ALL \
1429 (CX2_INTA_BIT_TX_QUEUE_1 | \
1430 CX2_INTA_BIT_TX_QUEUE_2 | \
1431 CX2_INTA_BIT_TX_QUEUE_3 | \
1432 CX2_INTA_BIT_TX_QUEUE_4 | \
1433 CX2_INTA_BIT_TX_CMD_QUEUE | \
1434 CX2_INTA_BIT_RX_TRANSFER | \
1435 CX2_INTA_BIT_FATAL_ERROR | \
1436 CX2_INTA_BIT_PARITY_ERROR | \
1437 CX2_INTA_BIT_STATUS_CHANGE | \
1438 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1439 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1440 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1441 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1442 CX2_INTA_BIT_POWER_DOWN | \
1443 CX2_INTA_BIT_RF_KILL_DONE )
1445 #define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1446 #define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1448 /* FW event log definitions */
1449 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1450 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1452 /* FW error log definitions */
1453 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1454 #define ERROR_START_OFFSET (1 * sizeof(u32))
1457 IPW_FW_ERROR_OK = 0,
1459 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1460 IPW_FW_ERROR_MEMORY_OVERFLOW,
1461 IPW_FW_ERROR_BAD_PARAM,
1462 IPW_FW_ERROR_BAD_CHECKSUM,
1463 IPW_FW_ERROR_NMI_INTERRUPT,
1464 IPW_FW_ERROR_BAD_DATABASE,
1465 IPW_FW_ERROR_ALLOC_FAIL,
1466 IPW_FW_ERROR_DMA_UNDERRUN,
1467 IPW_FW_ERROR_DMA_STATUS,
1468 IPW_FW_ERROR_DINOSTATUS_ERROR,
1469 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1470 IPW_FW_ERROR_SYSASSERT,
1471 IPW_FW_ERROR_FATAL_ERROR
1475 #define AUTH_SHARED_KEY 1
1476 #define AUTH_IGNORE 3
1478 #define HC_ASSOCIATE 0
1479 #define HC_REASSOCIATE 1
1480 #define HC_DISASSOCIATE 2
1481 #define HC_IBSS_START 3
1482 #define HC_IBSS_RECONF 4
1483 #define HC_DISASSOC_QUIET 5
1485 #define IPW_RATE_CAPABILITIES 1
1486 #define IPW_RATE_CONNECT 0
1490 * Rate values and masks
1492 #define IPW_TX_RATE_1MB 0x0A
1493 #define IPW_TX_RATE_2MB 0x14
1494 #define IPW_TX_RATE_5MB 0x37
1495 #define IPW_TX_RATE_6MB 0x0D
1496 #define IPW_TX_RATE_9MB 0x0F
1497 #define IPW_TX_RATE_11MB 0x6E
1498 #define IPW_TX_RATE_12MB 0x05
1499 #define IPW_TX_RATE_18MB 0x07
1500 #define IPW_TX_RATE_24MB 0x09
1501 #define IPW_TX_RATE_36MB 0x0B
1502 #define IPW_TX_RATE_48MB 0x01
1503 #define IPW_TX_RATE_54MB 0x03
1505 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1506 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1508 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1509 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1510 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1511 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1512 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1513 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1514 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1515 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1518 * Table 0 Entries (all entries are 32 bits)
1521 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1522 IPW_ORD_STAT_FRAG_TRESHOLD,
1523 IPW_ORD_STAT_RTS_THRESHOLD,
1524 IPW_ORD_STAT_TX_HOST_REQUESTS,
1525 IPW_ORD_STAT_TX_HOST_COMPLETE,
1526 IPW_ORD_STAT_TX_DIR_DATA,
1527 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1528 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1529 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1530 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1539 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1540 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1541 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1542 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1543 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1544 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1545 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1546 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1547 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1548 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1549 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1550 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1551 IPW_ORD_STAT_TX_NON_DIR_DATA,
1552 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1553 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1554 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1555 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1564 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1565 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1566 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1567 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1568 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1569 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1570 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1571 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1572 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1573 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1574 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1575 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1576 IPW_ORD_STAT_TX_RETRY,
1577 IPW_ORD_STAT_TX_FAILURE,
1578 IPW_ORD_STAT_RX_ERR_CRC,
1579 IPW_ORD_STAT_RX_ERR_ICV,
1580 IPW_ORD_STAT_RX_NO_BUFFER,
1581 IPW_ORD_STAT_FULL_SCANS,
1582 IPW_ORD_STAT_PARTIAL_SCANS,
1583 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1584 IPW_ORD_STAT_TX_TOTAL_BYTES,
1585 IPW_ORD_STAT_CURR_RSSI_RAW,
1586 IPW_ORD_STAT_RX_BEACON,
1587 IPW_ORD_STAT_MISSED_BEACONS,
1588 IPW_ORD_TABLE_0_LAST
1591 #define IPW_RSSI_TO_DBM 112
1596 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1602 * FW_VERSION: 16 byte string
1603 * FW_DATE: 16 byte string (only 14 bytes used)
1604 * UCODE_VERSION: 4 byte version code
1605 * UCODE_DATE: 5 bytes code code
1606 * ADDAPTER_MAC: 6 byte MAC address
1610 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1611 IPW_ORD_STAT_FW_DATE,
1612 IPW_ORD_STAT_UCODE_VERSION,
1613 IPW_ORD_STAT_UCODE_DATE,
1614 IPW_ORD_STAT_ADAPTER_MAC,
1616 IPW_ORD_TABLE_2_LAST
1621 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1622 IPW_ORD_STAT_TX_PACKET_FAILURE,
1623 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1624 IPW_ORD_STAT_TX_PACKET_ABORTED,
1625 IPW_ORD_TABLE_3_LAST
1630 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1635 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1636 IPW_ORD_STAT_AP_ASSNS,
1638 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1639 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1640 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1641 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1642 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1643 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1644 IPW_ORD_STAT_LINK_UP,
1645 IPW_ORD_STAT_LINK_DOWN,
1646 IPW_ORD_ANTENNA_DIVERSITY,
1648 IPW_ORD_TABLE_5_LAST
1653 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1656 IPW_ORD_TABLE_6_LAST
1661 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1662 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1663 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1664 IPW_ORD_STAT_CURR_RSSI_DBM,
1665 IPW_ORD_TABLE_7_LAST
1668 #define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1669 #define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1670 #define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1671 #define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1672 #define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1674 struct ipw_fixed_rate {
1677 } __attribute__ ((packed));
1679 #define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1685 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1686 } __attribute__ ((packed));
1688 #define CFG_BT_COEXISTENCE_MIN 0x00
1689 #define CFG_BT_COEXISTENCE_DEFER 0x02
1690 #define CFG_BT_COEXISTENCE_KILL 0x04
1691 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1692 #define CFG_BT_COEXISTENCE_OOB 0x10
1693 #define CFG_BT_COEXISTENCE_MAX 0xFF
1694 #define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM*/
1696 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1697 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1698 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1700 #define CFG_SYS_ANTENNA_BOTH 0x000
1701 #define CFG_SYS_ANTENNA_A 0x001
1702 #define CFG_SYS_ANTENNA_B 0x003
1705 * The definitions below were lifted off the ipw2100 driver, which only
1706 * supports 'b' mode, so I'm sure these are not exactly correct.
1708 * Somebody fix these!!
1710 #define REG_MIN_CHANNEL 0
1711 #define REG_MAX_CHANNEL 14
1713 #define REG_CHANNEL_MASK 0x00003FFF
1714 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1716 static const long ipw_frequencies[] = {
1717 2412, 2417, 2422, 2427,
1718 2432, 2437, 2442, 2447,
1719 2452, 2457, 2462, 2467,
1723 #define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1725 #define IPW_MAX_CONFIG_RETRIES 10
1727 static inline u32 frame_hdr_len(struct ieee80211_hdr *hdr)
1732 retval = sizeof(struct ieee80211_hdr);
1733 fc = le16_to_cpu(hdr->frame_ctl);
1736 * Function ToDS FromDS
1742 * Only WDS frames use Address4 among them. --YZ
1744 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1750 #endif /* __ipw2200_h__ */