1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
45 /* Send led command */
47 il3945_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd)
49 struct il_host_cmd cmd = {
51 .len = sizeof(struct il_led_cmd),
57 return il_send_cmd(il, &cmd);
60 #define IL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
61 [RATE_##r##M_IDX] = { RATE_##r##M_PLCP, \
69 RATE_##r##M_IDX_TBL, \
70 RATE_##ip##M_IDX_TBL }
74 * rate, prev rate, next rate, prev tgg rate, next tgg rate
76 * If there isn't a valid next or previous rate then INV is used which
77 * maps to RATE_INVALID
80 const struct il3945_rate_info il3945_rates[RATE_COUNT_3945] = {
81 IL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
82 IL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
83 IL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
84 IL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
85 IL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
86 IL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
87 IL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
88 IL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
89 IL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
90 IL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
91 IL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
92 IL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV), /* 54mbps */
96 il3945_get_prev_ieee_rate(u8 rate_idx)
98 u8 rate = il3945_rates[rate_idx].prev_ieee;
100 if (rate == RATE_INVALID)
105 /* 1 = enable the il3945_disable_events() function */
106 #define IL_EVT_DISABLE (0)
107 #define IL_EVT_DISABLE_SIZE (1532/32)
110 * il3945_disable_events - Disable selected events in uCode event log
112 * Disable an event by writing "1"s into "disable"
113 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
114 * Default values of 0 enable uCode events to be logged.
115 * Use for only special debugging. This function is just a placeholder as-is,
116 * you'll need to provide the special bits! ...
117 * ... and set IL_EVT_DISABLE to 1. */
119 il3945_disable_events(struct il_priv *il)
122 u32 base; /* SRAM address of event log header */
123 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
124 u32 array_size; /* # of u32 entries in array */
125 static const u32 evt_disable[IL_EVT_DISABLE_SIZE] = {
126 0x00000000, /* 31 - 0 Event id numbers */
127 0x00000000, /* 63 - 32 */
128 0x00000000, /* 95 - 64 */
129 0x00000000, /* 127 - 96 */
130 0x00000000, /* 159 - 128 */
131 0x00000000, /* 191 - 160 */
132 0x00000000, /* 223 - 192 */
133 0x00000000, /* 255 - 224 */
134 0x00000000, /* 287 - 256 */
135 0x00000000, /* 319 - 288 */
136 0x00000000, /* 351 - 320 */
137 0x00000000, /* 383 - 352 */
138 0x00000000, /* 415 - 384 */
139 0x00000000, /* 447 - 416 */
140 0x00000000, /* 479 - 448 */
141 0x00000000, /* 511 - 480 */
142 0x00000000, /* 543 - 512 */
143 0x00000000, /* 575 - 544 */
144 0x00000000, /* 607 - 576 */
145 0x00000000, /* 639 - 608 */
146 0x00000000, /* 671 - 640 */
147 0x00000000, /* 703 - 672 */
148 0x00000000, /* 735 - 704 */
149 0x00000000, /* 767 - 736 */
150 0x00000000, /* 799 - 768 */
151 0x00000000, /* 831 - 800 */
152 0x00000000, /* 863 - 832 */
153 0x00000000, /* 895 - 864 */
154 0x00000000, /* 927 - 896 */
155 0x00000000, /* 959 - 928 */
156 0x00000000, /* 991 - 960 */
157 0x00000000, /* 1023 - 992 */
158 0x00000000, /* 1055 - 1024 */
159 0x00000000, /* 1087 - 1056 */
160 0x00000000, /* 1119 - 1088 */
161 0x00000000, /* 1151 - 1120 */
162 0x00000000, /* 1183 - 1152 */
163 0x00000000, /* 1215 - 1184 */
164 0x00000000, /* 1247 - 1216 */
165 0x00000000, /* 1279 - 1248 */
166 0x00000000, /* 1311 - 1280 */
167 0x00000000, /* 1343 - 1312 */
168 0x00000000, /* 1375 - 1344 */
169 0x00000000, /* 1407 - 1376 */
170 0x00000000, /* 1439 - 1408 */
171 0x00000000, /* 1471 - 1440 */
172 0x00000000, /* 1503 - 1472 */
175 base = le32_to_cpu(il->card_alive.log_event_table_ptr);
176 if (!il3945_hw_valid_rtc_data_addr(base)) {
177 IL_ERR("Invalid event log pointer 0x%08X\n", base);
181 disable_ptr = il_read_targ_mem(il, base + (4 * sizeof(u32)));
182 array_size = il_read_targ_mem(il, base + (5 * sizeof(u32)));
184 if (IL_EVT_DISABLE && array_size == IL_EVT_DISABLE_SIZE) {
185 D_INFO("Disabling selected uCode log events at 0x%x\n",
187 for (i = 0; i < IL_EVT_DISABLE_SIZE; i++)
188 il_write_targ_mem(il, disable_ptr + (i * sizeof(u32)),
192 D_INFO("Selected uCode log events may be disabled\n");
193 D_INFO(" by writing \"1\"s into disable bitmap\n");
194 D_INFO(" in SRAM at 0x%x, size %d u32s\n", disable_ptr,
201 il3945_hwrate_to_plcp_idx(u8 plcp)
205 for (idx = 0; idx < RATE_COUNT_3945; idx++)
206 if (il3945_rates[idx].plcp == plcp)
211 #ifdef CONFIG_IWLEGACY_DEBUG
212 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
215 il3945_get_tx_fail_reason(u32 status)
217 switch (status & TX_STATUS_MSK) {
218 case TX_3945_STATUS_SUCCESS:
220 TX_STATUS_ENTRY(SHORT_LIMIT);
221 TX_STATUS_ENTRY(LONG_LIMIT);
222 TX_STATUS_ENTRY(FIFO_UNDERRUN);
223 TX_STATUS_ENTRY(MGMNT_ABORT);
224 TX_STATUS_ENTRY(NEXT_FRAG);
225 TX_STATUS_ENTRY(LIFE_EXPIRE);
226 TX_STATUS_ENTRY(DEST_PS);
227 TX_STATUS_ENTRY(ABORTED);
228 TX_STATUS_ENTRY(BT_RETRY);
229 TX_STATUS_ENTRY(STA_INVALID);
230 TX_STATUS_ENTRY(FRAG_DROPPED);
231 TX_STATUS_ENTRY(TID_DISABLE);
232 TX_STATUS_ENTRY(FRAME_FLUSHED);
233 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
234 TX_STATUS_ENTRY(TX_LOCKED);
235 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
241 static inline const char *
242 il3945_get_tx_fail_reason(u32 status)
249 * get ieee prev rate from rate scale table.
250 * for A and B mode we need to overright prev
254 il3945_rs_next_rate(struct il_priv *il, int rate)
256 int next_rate = il3945_get_prev_ieee_rate(rate);
259 case IEEE80211_BAND_5GHZ:
260 if (rate == RATE_12M_IDX)
261 next_rate = RATE_9M_IDX;
262 else if (rate == RATE_6M_IDX)
263 next_rate = RATE_6M_IDX;
265 case IEEE80211_BAND_2GHZ:
266 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
267 il_is_associated(il)) {
268 if (rate == RATE_11M_IDX)
269 next_rate = RATE_5M_IDX;
281 * il3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
283 * When FW advances 'R' idx, all entries between old and new 'R' idx
284 * need to be reclaimed. As result, some free space forms. If there is
285 * enough free space (> low mark), wake the stack that feeds us.
288 il3945_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
290 struct il_tx_queue *txq = &il->txq[txq_id];
291 struct il_queue *q = &txq->q;
294 BUG_ON(txq_id == IL39_CMD_QUEUE_NUM);
296 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
297 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
299 skb = txq->skbs[txq->q.read_ptr];
300 ieee80211_tx_status_irqsafe(il->hw, skb);
301 txq->skbs[txq->q.read_ptr] = NULL;
302 il->ops->txq_free_tfd(il, txq);
305 if (il_queue_space(q) > q->low_mark && txq_id >= 0 &&
306 txq_id != IL39_CMD_QUEUE_NUM && il->mac80211_registered)
307 il_wake_queue(il, txq);
311 * il3945_hdl_tx - Handle Tx response
314 il3945_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb)
316 struct il_rx_pkt *pkt = rxb_addr(rxb);
317 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
318 int txq_id = SEQ_TO_QUEUE(sequence);
319 int idx = SEQ_TO_IDX(sequence);
320 struct il_tx_queue *txq = &il->txq[txq_id];
321 struct ieee80211_tx_info *info;
322 struct il3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
323 u32 status = le32_to_cpu(tx_resp->status);
327 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) {
328 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d "
329 "is out of range [0-%d] %d %d\n", txq_id, idx,
330 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr);
334 txq->time_stamp = jiffies;
335 info = IEEE80211_SKB_CB(txq->skbs[txq->q.read_ptr]);
336 ieee80211_tx_info_clear_status(info);
338 /* Fill the MRR chain with some info about on-chip retransmissions */
339 rate_idx = il3945_hwrate_to_plcp_idx(tx_resp->rate);
340 if (info->band == IEEE80211_BAND_5GHZ)
341 rate_idx -= IL_FIRST_OFDM_RATE;
343 fail = tx_resp->failure_frame;
345 info->status.rates[0].idx = rate_idx;
346 info->status.rates[0].count = fail + 1; /* add final attempt */
348 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
350 ((status & TX_STATUS_MSK) ==
351 TX_STATUS_SUCCESS) ? IEEE80211_TX_STAT_ACK : 0;
353 D_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", txq_id,
354 il3945_get_tx_fail_reason(status), status, tx_resp->rate,
355 tx_resp->failure_frame);
357 D_TX_REPLY("Tx queue reclaim %d\n", idx);
358 il3945_tx_queue_reclaim(il, txq_id, idx);
360 if (status & TX_ABORT_REQUIRED_MSK)
361 IL_ERR("TODO: Implement Tx ABORT REQUIRED!!!\n");
364 /*****************************************************************************
366 * Intel PRO/Wireless 3945ABG/BG Network Connection
368 * RX handler implementations
370 *****************************************************************************/
371 #ifdef CONFIG_IWLEGACY_DEBUGFS
373 il3945_accumulative_stats(struct il_priv *il, __le32 * stats)
378 u32 *delta, *max_delta;
380 prev_stats = (__le32 *) &il->_3945.stats;
381 accum_stats = (u32 *) &il->_3945.accum_stats;
382 delta = (u32 *) &il->_3945.delta_stats;
383 max_delta = (u32 *) &il->_3945.max_delta;
385 for (i = sizeof(__le32); i < sizeof(struct il3945_notif_stats);
387 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
389 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
391 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
392 *accum_stats += *delta;
393 if (*delta > *max_delta)
398 /* reset accumulative stats for "no-counter" type stats */
399 il->_3945.accum_stats.general.temperature =
400 il->_3945.stats.general.temperature;
401 il->_3945.accum_stats.general.ttl_timestamp =
402 il->_3945.stats.general.ttl_timestamp;
407 il3945_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
409 struct il_rx_pkt *pkt = rxb_addr(rxb);
411 D_RX("Statistics notification received (%d vs %d).\n",
412 (int)sizeof(struct il3945_notif_stats),
413 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
414 #ifdef CONFIG_IWLEGACY_DEBUGFS
415 il3945_accumulative_stats(il, (__le32 *) &pkt->u.raw);
418 memcpy(&il->_3945.stats, pkt->u.raw, sizeof(il->_3945.stats));
422 il3945_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
424 struct il_rx_pkt *pkt = rxb_addr(rxb);
425 __le32 *flag = (__le32 *) &pkt->u.raw;
427 if (le32_to_cpu(*flag) & UCODE_STATS_CLEAR_MSK) {
428 #ifdef CONFIG_IWLEGACY_DEBUGFS
429 memset(&il->_3945.accum_stats, 0,
430 sizeof(struct il3945_notif_stats));
431 memset(&il->_3945.delta_stats, 0,
432 sizeof(struct il3945_notif_stats));
433 memset(&il->_3945.max_delta, 0,
434 sizeof(struct il3945_notif_stats));
436 D_RX("Statistics have been cleared\n");
438 il3945_hdl_stats(il, rxb);
441 /******************************************************************************
443 * Misc. internal state and helper functions
445 ******************************************************************************/
447 /* This is necessary only for a number of stats, see the caller. */
449 il3945_is_network_packet(struct il_priv *il, struct ieee80211_hdr *header)
451 /* Filter incoming packets to determine if they are targeted toward
452 * this network, discarding packets coming from ourselves */
453 switch (il->iw_mode) {
454 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
455 /* packets to our IBSS update information */
456 return !compare_ether_addr(header->addr3, il->bssid);
457 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
458 /* packets to our IBSS update information */
459 return !compare_ether_addr(header->addr2, il->bssid);
466 il3945_pass_packet_to_mac80211(struct il_priv *il, struct il_rx_buf *rxb,
467 struct ieee80211_rx_status *stats)
469 struct il_rx_pkt *pkt = rxb_addr(rxb);
470 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
471 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
472 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
473 u16 len = le16_to_cpu(rx_hdr->len);
475 __le16 fc = hdr->frame_control;
477 /* We received data from the HW, so stop the watchdog */
479 (len + IL39_RX_FRAME_SIZE >
480 PAGE_SIZE << il->hw_params.rx_page_order)) {
481 D_DROP("Corruption detected!\n");
485 /* We only process data packets if the interface is open */
486 if (unlikely(!il->is_open)) {
487 D_DROP("Dropping packet while interface is not open.\n");
491 skb = dev_alloc_skb(128);
493 IL_ERR("dev_alloc_skb failed\n");
497 if (!il3945_mod_params.sw_crypto)
498 il_set_decrypted_flag(il, (struct ieee80211_hdr *)rxb_addr(rxb),
499 le32_to_cpu(rx_end->status), stats);
501 skb_add_rx_frag(skb, 0, rxb->page,
502 (void *)rx_hdr->payload - (void *)pkt, len);
504 il_update_stats(il, false, fc, len);
505 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
507 ieee80211_rx(il->hw, skb);
508 il->alloc_rxb_page--;
512 #define IL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
515 il3945_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
517 struct ieee80211_hdr *header;
518 struct ieee80211_rx_status rx_status;
519 struct il_rx_pkt *pkt = rxb_addr(rxb);
520 struct il3945_rx_frame_stats *rx_stats = IL_RX_STATS(pkt);
521 struct il3945_rx_frame_hdr *rx_hdr = IL_RX_HDR(pkt);
522 struct il3945_rx_frame_end *rx_end = IL_RX_END(pkt);
523 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
524 u16 rx_stats_noise_diff __maybe_unused =
525 le16_to_cpu(rx_stats->noise_diff);
529 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
532 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
535 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
538 rx_status.rate_idx = il3945_hwrate_to_plcp_idx(rx_hdr->rate);
539 if (rx_status.band == IEEE80211_BAND_5GHZ)
540 rx_status.rate_idx -= IL_FIRST_OFDM_RATE;
543 (le16_to_cpu(rx_hdr->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
546 /* set the preamble flag if appropriate */
547 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
548 rx_status.flag |= RX_FLAG_SHORTPRE;
550 if ((unlikely(rx_stats->phy_count > 20))) {
551 D_DROP("dsp size out of range [0,20]: %d/n",
552 rx_stats->phy_count);
556 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) ||
557 !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
558 D_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
562 /* Convert 3945's rssi indicator to dBm */
563 rx_status.signal = rx_stats->rssi - IL39_RSSI_OFFSET;
565 D_STATS("Rssi %d sig_avg %d noise_diff %d\n", rx_status.signal,
566 rx_stats_sig_avg, rx_stats_noise_diff);
568 header = (struct ieee80211_hdr *)IL_RX_DATA(pkt);
570 network_packet = il3945_is_network_packet(il, header);
572 D_STATS("[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
573 network_packet ? '*' : ' ', le16_to_cpu(rx_hdr->channel),
574 rx_status.signal, rx_status.signal, rx_status.rate_idx);
576 if (network_packet) {
577 il->_3945.last_beacon_time =
578 le32_to_cpu(rx_end->beacon_timestamp);
579 il->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
580 il->_3945.last_rx_rssi = rx_status.signal;
583 il3945_pass_packet_to_mac80211(il, rxb, &rx_status);
587 il3945_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
588 dma_addr_t addr, u16 len, u8 reset, u8 pad)
592 struct il3945_tfd *tfd, *tfd_tmp;
595 tfd_tmp = (struct il3945_tfd *)txq->tfds;
596 tfd = &tfd_tmp[q->write_ptr];
599 memset(tfd, 0, sizeof(*tfd));
601 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
603 if (count >= NUM_TFD_CHUNKS || count < 0) {
604 IL_ERR("Error can not send more than %d chunks\n",
609 tfd->tbs[count].addr = cpu_to_le32(addr);
610 tfd->tbs[count].len = cpu_to_le32(len);
615 cpu_to_le32(TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad));
621 * il3945_hw_txq_free_tfd - Free one TFD, those at idx [txq->q.read_ptr]
623 * Does NOT advance any idxes
626 il3945_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
628 struct il3945_tfd *tfd_tmp = (struct il3945_tfd *)txq->tfds;
629 int idx = txq->q.read_ptr;
630 struct il3945_tfd *tfd = &tfd_tmp[idx];
631 struct pci_dev *dev = il->pci_dev;
636 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
637 if (counter > NUM_TFD_CHUNKS) {
638 IL_ERR("Too many chunks: %i\n", counter);
639 /* @todo issue fatal error, it is quite serious situation */
645 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
646 dma_unmap_len(&txq->meta[idx], len),
649 /* unmap chunks if any */
651 for (i = 1; i < counter; i++)
652 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
653 le32_to_cpu(tfd->tbs[i].len),
658 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
660 /* can be called from irqs-disabled context */
662 dev_kfree_skb_any(skb);
663 txq->skbs[txq->q.read_ptr] = NULL;
669 * il3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
673 il3945_hw_build_tx_cmd_rate(struct il_priv *il, struct il_device_cmd *cmd,
674 struct ieee80211_tx_info *info,
675 struct ieee80211_hdr *hdr, int sta_id)
677 u16 hw_value = ieee80211_get_tx_rate(il->hw, info)->hw_value;
678 u16 rate_idx = min(hw_value & 0xffff, RATE_COUNT_3945 - 1);
681 const u8 rts_retry_limit = 7;
684 __le16 fc = hdr->frame_control;
685 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
687 rate = il3945_rates[rate_idx].plcp;
688 tx_flags = tx_cmd->tx_flags;
690 /* We need to figure out how to get the sta->supp_rates while
691 * in this running context */
692 rate_mask = RATES_MASK_3945;
694 /* Set retry limit on DATA packets and Probe Responses */
695 if (ieee80211_is_probe_resp(fc))
696 data_retry_limit = 3;
698 data_retry_limit = IL_DEFAULT_TX_RETRY;
699 tx_cmd->data_retry_limit = data_retry_limit;
700 /* Set retry limit on RTS packets */
701 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
704 tx_cmd->tx_flags = tx_flags;
707 tx_cmd->supp_rates[0] =
708 ((rate_mask & IL_OFDM_RATES_MASK) >> IL_FIRST_OFDM_RATE) & 0xFF;
711 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
713 D_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
714 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, tx_cmd->rate,
715 le32_to_cpu(tx_cmd->tx_flags), tx_cmd->supp_rates[1],
716 tx_cmd->supp_rates[0]);
720 il3945_sync_sta(struct il_priv *il, int sta_id, u16 tx_rate)
722 unsigned long flags_spin;
723 struct il_station_entry *station;
725 if (sta_id == IL_INVALID_STATION)
726 return IL_INVALID_STATION;
728 spin_lock_irqsave(&il->sta_lock, flags_spin);
729 station = &il->stations[sta_id];
731 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
732 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
733 station->sta.mode = STA_CONTROL_MODIFY_MSK;
734 il_send_add_sta(il, &station->sta, CMD_ASYNC);
735 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
737 D_RATE("SCALE sync station %d to rate %d\n", sta_id, tx_rate);
742 il3945_set_pwr_vmain(struct il_priv *il)
745 * (for documentation purposes)
746 * to set power to V_AUX, do
748 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) {
749 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
750 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
751 ~APMG_PS_CTRL_MSK_PWR_SRC);
753 _il_poll_bit(il, CSR_GPIO_IN,
754 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
755 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
759 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
760 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
761 ~APMG_PS_CTRL_MSK_PWR_SRC);
763 _il_poll_bit(il, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
764 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
768 il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
770 il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
771 il_wr(il, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
772 il_wr(il, FH39_RCSR_WPTR(0), 0);
773 il_wr(il, FH39_RCSR_CONFIG(0),
774 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
775 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
776 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
777 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | (RX_QUEUE_SIZE_LOG
779 FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE)
780 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | (1 <<
781 FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH)
782 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
784 /* fake read to flush all prev I/O */
785 il_rd(il, FH39_RSSR_CTRL);
791 il3945_tx_reset(struct il_priv *il)
795 il_wr_prph(il, ALM_SCD_MODE_REG, 0x2);
798 il_wr_prph(il, ALM_SCD_ARASTAT_REG, 0x01);
800 /* all 6 fifo are active */
801 il_wr_prph(il, ALM_SCD_TXFACT_REG, 0x3f);
803 il_wr_prph(il, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
804 il_wr_prph(il, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
805 il_wr_prph(il, ALM_SCD_TXF4MF_REG, 0x000004);
806 il_wr_prph(il, ALM_SCD_TXF5MF_REG, 0x000005);
808 il_wr(il, FH39_TSSR_CBB_BASE, il->_3945.shared_phys);
810 il_wr(il, FH39_TSSR_MSG_CONFIG,
811 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
812 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
813 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
814 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
815 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
816 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
817 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
823 * il3945_txq_ctx_reset - Reset TX queue context
825 * Destroys all DMA structures and initialize them again
828 il3945_txq_ctx_reset(struct il_priv *il)
831 int txq_id, slots_num;
833 il3945_hw_txq_ctx_free(il);
835 /* allocate tx queue structure */
836 rc = il_alloc_txq_mem(il);
841 rc = il3945_tx_reset(il);
846 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
849 IL39_CMD_QUEUE_NUM) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
850 rc = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
852 IL_ERR("Tx %d queue init failed\n", txq_id);
860 il3945_hw_txq_ctx_free(il);
865 * Start up 3945's basic functionality after it has been reset
866 * (e.g. after platform boot, or shutdown via il_apm_stop())
867 * NOTE: This does not load uCode nor start the embedded processor
870 il3945_apm_init(struct il_priv *il)
872 int ret = il_apm_init(il);
874 /* Clear APMG (NIC's internal power management) interrupts */
875 il_wr_prph(il, APMG_RTC_INT_MSK_REG, 0x0);
876 il_wr_prph(il, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
878 /* Reset radio chip */
879 il_set_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
881 il_clear_bits_prph(il, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
887 il3945_nic_config(struct il_priv *il)
889 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
891 u8 rev_id = il->pci_dev->revision;
893 spin_lock_irqsave(&il->lock, flags);
895 /* Determine HW type */
896 D_INFO("HW Revision ID = 0x%X\n", rev_id);
898 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
899 D_INFO("RTP type\n");
900 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
901 D_INFO("3945 RADIO-MB type\n");
902 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
903 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
905 D_INFO("3945 RADIO-MM type\n");
906 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
907 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
910 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
911 D_INFO("SKU OP mode is mrc\n");
912 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
913 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
915 D_INFO("SKU OP mode is basic\n");
917 if ((eeprom->board_revision & 0xF0) == 0xD0) {
918 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
919 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
920 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
922 D_INFO("3945ABG revision is 0x%X\n", eeprom->board_revision);
923 il_clear_bit(il, CSR_HW_IF_CONFIG_REG,
924 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
927 if (eeprom->almgor_m_version <= 1) {
928 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
929 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
930 D_INFO("Card M type A version is 0x%X\n",
931 eeprom->almgor_m_version);
933 D_INFO("Card M type B version is 0x%X\n",
934 eeprom->almgor_m_version);
935 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
936 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
938 spin_unlock_irqrestore(&il->lock, flags);
940 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
941 D_RF_KILL("SW RF KILL supported in EEPROM.\n");
943 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
944 D_RF_KILL("HW RF KILL supported in EEPROM.\n");
948 il3945_hw_nic_init(struct il_priv *il)
952 struct il_rx_queue *rxq = &il->rxq;
954 spin_lock_irqsave(&il->lock, flags);
956 spin_unlock_irqrestore(&il->lock, flags);
958 il3945_set_pwr_vmain(il);
959 il3945_nic_config(il);
961 /* Allocate the RX queue, or reset if it is already allocated */
963 rc = il_rx_queue_alloc(il);
965 IL_ERR("Unable to initialize Rx queue\n");
969 il3945_rx_queue_reset(il, rxq);
971 il3945_rx_replenish(il);
973 il3945_rx_init(il, rxq);
975 /* Look at using this instead:
976 rxq->need_update = 1;
977 il_rx_queue_update_write_ptr(il, rxq);
980 il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7);
982 rc = il3945_txq_ctx_reset(il);
986 set_bit(S_INIT, &il->status);
992 * il3945_hw_txq_ctx_free - Free TXQ Context
994 * Destroy all TX DMA queues and structures
997 il3945_hw_txq_ctx_free(struct il_priv *il)
1003 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1004 if (txq_id == IL39_CMD_QUEUE_NUM)
1005 il_cmd_queue_free(il);
1007 il_tx_queue_free(il, txq_id);
1009 /* free tx queue structure */
1014 il3945_hw_txq_ctx_stop(struct il_priv *il)
1019 _il_wr_prph(il, ALM_SCD_MODE_REG, 0);
1020 _il_wr_prph(il, ALM_SCD_TXFACT_REG, 0);
1022 /* reset TFD queues */
1023 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1024 _il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0);
1025 _il_poll_bit(il, FH39_TSSR_TX_STATUS,
1026 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1027 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1033 * il3945_hw_reg_adjust_power_by_temp
1034 * return idx delta into power gain settings table
1037 il3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1039 return (new_reading - old_reading) * (-11) / 100;
1043 * il3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1046 il3945_hw_reg_temp_out_of_range(int temperature)
1048 return (temperature < -260 || temperature > 25) ? 1 : 0;
1052 il3945_hw_get_temperature(struct il_priv *il)
1054 return _il_rd(il, CSR_UCODE_DRV_GP2);
1058 * il3945_hw_reg_txpower_get_temperature
1059 * get the current temperature by reading from NIC
1062 il3945_hw_reg_txpower_get_temperature(struct il_priv *il)
1064 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1067 temperature = il3945_hw_get_temperature(il);
1069 /* driver's okay range is -260 to +25.
1070 * human readable okay range is 0 to +285 */
1071 D_INFO("Temperature: %d\n", temperature + IL_TEMP_CONVERT);
1073 /* handle insane temp reading */
1074 if (il3945_hw_reg_temp_out_of_range(temperature)) {
1075 IL_ERR("Error bad temperature value %d\n", temperature);
1077 /* if really really hot(?),
1078 * substitute the 3rd band/group's temp measured at factory */
1079 if (il->last_temperature > 100)
1080 temperature = eeprom->groups[2].temperature;
1081 else /* else use most recent "sane" value from driver */
1082 temperature = il->last_temperature;
1085 return temperature; /* raw, not "human readable" */
1088 /* Adjust Txpower only if temperature variance is greater than threshold.
1090 * Both are lower than older versions' 9 degrees */
1091 #define IL_TEMPERATURE_LIMIT_TIMER 6
1094 * il3945_is_temp_calib_needed - determines if new calibration is needed
1096 * records new temperature in tx_mgr->temperature.
1097 * replaces tx_mgr->last_temperature *only* if calib needed
1098 * (assumes caller will actually do the calibration!). */
1100 il3945_is_temp_calib_needed(struct il_priv *il)
1104 il->temperature = il3945_hw_reg_txpower_get_temperature(il);
1105 temp_diff = il->temperature - il->last_temperature;
1107 /* get absolute value */
1108 if (temp_diff < 0) {
1109 D_POWER("Getting cooler, delta %d,\n", temp_diff);
1110 temp_diff = -temp_diff;
1111 } else if (temp_diff == 0)
1112 D_POWER("Same temp,\n");
1114 D_POWER("Getting warmer, delta %d,\n", temp_diff);
1116 /* if we don't need calibration, *don't* update last_temperature */
1117 if (temp_diff < IL_TEMPERATURE_LIMIT_TIMER) {
1118 D_POWER("Timed thermal calib not needed\n");
1122 D_POWER("Timed thermal calib needed\n");
1124 /* assume that caller will actually do calib ...
1125 * update the "last temperature" value */
1126 il->last_temperature = il->temperature;
1130 #define IL_MAX_GAIN_ENTRIES 78
1131 #define IL_CCK_FROM_OFDM_POWER_DIFF -5
1132 #define IL_CCK_FROM_OFDM_IDX_DIFF (10)
1134 /* radio and DSP power table, each step is 1/2 dB.
1135 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1136 static struct il3945_tx_power power_gain_table[2][IL_MAX_GAIN_ENTRIES] = {
1138 {251, 127}, /* 2.4 GHz, highest power */
1215 {3, 95} /* 2.4 GHz, lowest power */
1218 {251, 127}, /* 5.x GHz, highest power */
1295 {3, 120} /* 5.x GHz, lowest power */
1300 il3945_hw_reg_fix_power_idx(int idx)
1304 if (idx >= IL_MAX_GAIN_ENTRIES)
1305 return IL_MAX_GAIN_ENTRIES - 1;
1309 /* Kick off thermal recalibration check every 60 seconds */
1310 #define REG_RECALIB_PERIOD (60)
1313 * il3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1315 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1316 * or 6 Mbit (OFDM) rates.
1319 il3945_hw_reg_set_scan_power(struct il_priv *il, u32 scan_tbl_idx, s32 rate_idx,
1320 const s8 *clip_pwrs,
1321 struct il_channel_info *ch_info, int band_idx)
1323 struct il3945_scan_power_info *scan_power_info;
1327 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_idx];
1329 /* use this channel group's 6Mbit clipping/saturation pwr,
1330 * but cap at regulatory scan power restriction (set during init
1331 * based on eeprom channel data) for this channel. */
1332 power = min(ch_info->scan_power, clip_pwrs[RATE_6M_IDX_TBL]);
1334 power = min(power, il->tx_power_user_lmt);
1335 scan_power_info->requested_power = power;
1337 /* find difference between new scan *power* and current "normal"
1338 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1339 * current "normal" temperature-compensated Tx power *idx* for
1340 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1343 ch_info->power_info[rate_idx].power_table_idx - (power -
1350 /* store reference idx that we use when adjusting *all* scan
1351 * powers. So we can accommodate user (all channel) or spectrum
1352 * management (single channel) power changes "between" temperature
1353 * feedback compensation procedures.
1354 * don't force fit this reference idx into gain table; it may be a
1355 * negative number. This will help avoid errors when we're at
1356 * the lower bounds (highest gains, for warmest temperatures)
1359 /* don't exceed table bounds for "real" setting */
1360 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1362 scan_power_info->power_table_idx = power_idx;
1363 scan_power_info->tpc.tx_gain =
1364 power_gain_table[band_idx][power_idx].tx_gain;
1365 scan_power_info->tpc.dsp_atten =
1366 power_gain_table[band_idx][power_idx].dsp_atten;
1370 * il3945_send_tx_power - fill in Tx Power command with gain settings
1372 * Configures power settings for all rates for the current channel,
1373 * using values from channel info struct, and send to NIC
1376 il3945_send_tx_power(struct il_priv *il)
1379 const struct il_channel_info *ch_info = NULL;
1380 struct il3945_txpowertable_cmd txpower = {
1381 .channel = il->active.channel,
1386 (test_bit(S_SCAN_HW, &il->status),
1387 "TX Power requested while scanning!\n"))
1390 chan = le16_to_cpu(il->active.channel);
1392 txpower.band = (il->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1393 ch_info = il_get_channel_info(il, il->band, chan);
1395 IL_ERR("Failed to get channel info for channel %d [%d]\n", chan,
1400 if (!il_is_channel_valid(ch_info)) {
1401 D_POWER("Not calling TX_PWR_TBL_CMD on " "non-Tx channel.\n");
1405 /* fill cmd with power settings for all rates for current channel */
1406 /* Fill OFDM rate */
1407 for (rate_idx = IL_FIRST_OFDM_RATE, i = 0;
1408 rate_idx <= IL39_LAST_OFDM_RATE; rate_idx++, i++) {
1410 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1411 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1413 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1414 le16_to_cpu(txpower.channel), txpower.band,
1415 txpower.power[i].tpc.tx_gain,
1416 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1418 /* Fill CCK rates */
1419 for (rate_idx = IL_FIRST_CCK_RATE; rate_idx <= IL_LAST_CCK_RATE;
1421 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1422 txpower.power[i].rate = il3945_rates[rate_idx].plcp;
1424 D_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1425 le16_to_cpu(txpower.channel), txpower.band,
1426 txpower.power[i].tpc.tx_gain,
1427 txpower.power[i].tpc.dsp_atten, txpower.power[i].rate);
1430 return il_send_cmd_pdu(il, C_TX_PWR_TBL,
1431 sizeof(struct il3945_txpowertable_cmd),
1437 * il3945_hw_reg_set_new_power - Configures power tables at new levels
1438 * @ch_info: Channel to update. Uses power_info.requested_power.
1440 * Replace requested_power and base_power_idx ch_info fields for
1443 * Called if user or spectrum management changes power preferences.
1444 * Takes into account h/w and modulation limitations (clip power).
1446 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1448 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1449 * properly fill out the scan powers, and actual h/w gain settings,
1450 * and send changes to NIC
1453 il3945_hw_reg_set_new_power(struct il_priv *il, struct il_channel_info *ch_info)
1455 struct il3945_channel_power_info *power_info;
1456 int power_changed = 0;
1458 const s8 *clip_pwrs;
1461 /* Get this chnlgrp's rate-to-max/clip-powers table */
1462 clip_pwrs = il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1464 /* Get this channel's rate-to-current-power settings table */
1465 power_info = ch_info->power_info;
1467 /* update OFDM Txpower settings */
1468 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++, ++power_info) {
1471 /* limit new power to be no more than h/w capability */
1472 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1473 if (power == power_info->requested_power)
1476 /* find difference between old and new requested powers,
1477 * update base (non-temp-compensated) power idx */
1478 delta_idx = (power - power_info->requested_power) * 2;
1479 power_info->base_power_idx -= delta_idx;
1481 /* save new requested power value */
1482 power_info->requested_power = power;
1487 /* update CCK Txpower settings, based on OFDM 12M setting ...
1488 * ... all CCK power settings for a given channel are the *same*. */
1489 if (power_changed) {
1491 ch_info->power_info[RATE_12M_IDX_TBL].requested_power +
1492 IL_CCK_FROM_OFDM_POWER_DIFF;
1494 /* do all CCK rates' il3945_channel_power_info structures */
1495 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++) {
1496 power_info->requested_power = power;
1497 power_info->base_power_idx =
1498 ch_info->power_info[RATE_12M_IDX_TBL].
1499 base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
1508 * il3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1510 * NOTE: Returned power limit may be less (but not more) than requested,
1511 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1512 * (no consideration for h/w clipping limitations).
1515 il3945_hw_reg_get_ch_txpower_limit(struct il_channel_info *ch_info)
1520 /* if we're using TGd limits, use lower of TGd or EEPROM */
1521 if (ch_info->tgd_data.max_power != 0)
1523 min(ch_info->tgd_data.max_power,
1524 ch_info->eeprom.max_power_avg);
1526 /* else just use EEPROM limits */
1529 max_power = ch_info->eeprom.max_power_avg;
1531 return min(max_power, ch_info->max_power_avg);
1535 * il3945_hw_reg_comp_txpower_temp - Compensate for temperature
1537 * Compensate txpower settings of *all* channels for temperature.
1538 * This only accounts for the difference between current temperature
1539 * and the factory calibration temperatures, and bases the new settings
1540 * on the channel's base_power_idx.
1542 * If RxOn is "associated", this sends the new Txpower to NIC!
1545 il3945_hw_reg_comp_txpower_temp(struct il_priv *il)
1547 struct il_channel_info *ch_info = NULL;
1548 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1550 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1556 int temperature = il->temperature;
1558 if (il->disable_tx_power_cal || test_bit(S_SCANNING, &il->status)) {
1559 /* do not perform tx power calibration */
1562 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1563 for (i = 0; i < il->channel_count; i++) {
1564 ch_info = &il->channel_info[i];
1565 a_band = il_is_channel_a_band(ch_info);
1567 /* Get this chnlgrp's factory calibration temperature */
1568 ref_temp = (s16) eeprom->groups[ch_info->group_idx].temperature;
1570 /* get power idx adjustment based on current and factory
1573 il3945_hw_reg_adjust_power_by_temp(temperature, ref_temp);
1575 /* set tx power value for all rates, OFDM and CCK */
1576 for (rate_idx = 0; rate_idx < RATE_COUNT_3945; rate_idx++) {
1578 ch_info->power_info[rate_idx].base_power_idx;
1580 /* temperature compensate */
1581 power_idx += delta_idx;
1583 /* stay within table range */
1584 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
1585 ch_info->power_info[rate_idx].power_table_idx =
1587 ch_info->power_info[rate_idx].tpc =
1588 power_gain_table[a_band][power_idx];
1591 /* Get this chnlgrp's rate-to-max/clip-powers table */
1593 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
1595 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1596 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
1600 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
1601 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
1602 actual_idx, clip_pwrs,
1607 /* send Txpower command for current channel to ucode */
1608 return il->ops->send_tx_power(il);
1612 il3945_hw_reg_set_txpower(struct il_priv *il, s8 power)
1614 struct il_channel_info *ch_info;
1619 if (il->tx_power_user_lmt == power) {
1620 D_POWER("Requested Tx power same as current " "limit: %ddBm.\n",
1625 D_POWER("Setting upper limit clamp to %ddBm.\n", power);
1626 il->tx_power_user_lmt = power;
1628 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1630 for (i = 0; i < il->channel_count; i++) {
1631 ch_info = &il->channel_info[i];
1632 a_band = il_is_channel_a_band(ch_info);
1634 /* find minimum power of all user and regulatory constraints
1635 * (does not consider h/w clipping limitations) */
1636 max_power = il3945_hw_reg_get_ch_txpower_limit(ch_info);
1637 max_power = min(power, max_power);
1638 if (max_power != ch_info->curr_txpow) {
1639 ch_info->curr_txpow = max_power;
1641 /* this considers the h/w clipping limitations */
1642 il3945_hw_reg_set_new_power(il, ch_info);
1646 /* update txpower settings for all channels,
1647 * send to NIC if associated. */
1648 il3945_is_temp_calib_needed(il);
1649 il3945_hw_reg_comp_txpower_temp(il);
1655 il3945_send_rxon_assoc(struct il_priv *il)
1658 struct il_rx_pkt *pkt;
1659 struct il3945_rxon_assoc_cmd rxon_assoc;
1660 struct il_host_cmd cmd = {
1662 .len = sizeof(rxon_assoc),
1663 .flags = CMD_WANT_SKB,
1664 .data = &rxon_assoc,
1666 const struct il_rxon_cmd *rxon1 = &il->staging;
1667 const struct il_rxon_cmd *rxon2 = &il->active;
1669 if (rxon1->flags == rxon2->flags &&
1670 rxon1->filter_flags == rxon2->filter_flags &&
1671 rxon1->cck_basic_rates == rxon2->cck_basic_rates &&
1672 rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) {
1673 D_INFO("Using current RXON_ASSOC. Not resending.\n");
1677 rxon_assoc.flags = il->staging.flags;
1678 rxon_assoc.filter_flags = il->staging.filter_flags;
1679 rxon_assoc.ofdm_basic_rates = il->staging.ofdm_basic_rates;
1680 rxon_assoc.cck_basic_rates = il->staging.cck_basic_rates;
1681 rxon_assoc.reserved = 0;
1683 rc = il_send_cmd_sync(il, &cmd);
1687 pkt = (struct il_rx_pkt *)cmd.reply_page;
1688 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1689 IL_ERR("Bad return from C_RXON_ASSOC command\n");
1693 il_free_pages(il, cmd.reply_page);
1699 * il3945_commit_rxon - commit staging_rxon to hardware
1701 * The RXON command in staging_rxon is committed to the hardware and
1702 * the active_rxon structure is updated with the new data. This
1703 * function correctly transitions out of the RXON_ASSOC_MSK state if
1704 * a HW tune is required based on the RXON structure changes.
1707 il3945_commit_rxon(struct il_priv *il)
1709 /* cast away the const for active_rxon in this function */
1710 struct il3945_rxon_cmd *active_rxon = (void *)&il->active;
1711 struct il3945_rxon_cmd *staging_rxon = (void *)&il->staging;
1713 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1715 if (test_bit(S_EXIT_PENDING, &il->status))
1718 if (!il_is_alive(il))
1721 /* always get timestamp with Rx frame */
1722 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1724 /* select antenna */
1725 staging_rxon->flags &= ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1726 staging_rxon->flags |= il3945_get_antenna_flags(il);
1728 rc = il_check_rxon_cmd(il);
1730 IL_ERR("Invalid RXON configuration. Not committing.\n");
1734 /* If we don't need to send a full RXON, we can use
1735 * il3945_rxon_assoc_cmd which is used to reconfigure filter
1736 * and other flags for the current radio configuration. */
1737 if (!il_full_rxon_required(il)) {
1738 rc = il_send_rxon_assoc(il);
1740 IL_ERR("Error setting RXON_ASSOC "
1741 "configuration (%d).\n", rc);
1745 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1747 * We do not commit tx power settings while channel changing,
1748 * do it now if tx power changed.
1750 il_set_tx_power(il, il->tx_power_next, false);
1754 /* If we are currently associated and the new config requires
1755 * an RXON_ASSOC and the new config wants the associated mask enabled,
1756 * we must clear the associated from the active configuration
1757 * before we apply the new config */
1758 if (il_is_associated(il) && new_assoc) {
1759 D_INFO("Toggling associated bit on current RXON\n");
1760 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1763 * reserved4 and 5 could have been filled by the iwlcore code.
1764 * Let's clear them before pushing to the 3945.
1766 active_rxon->reserved4 = 0;
1767 active_rxon->reserved5 = 0;
1768 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1771 /* If the mask clearing failed then we set
1772 * active_rxon back to what it was previously */
1774 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1775 IL_ERR("Error clearing ASSOC_MSK on current "
1776 "configuration (%d).\n", rc);
1779 il_clear_ucode_stations(il);
1780 il_restore_stations(il);
1783 D_INFO("Sending RXON\n" "* with%s RXON_FILTER_ASSOC_MSK\n"
1784 "* channel = %d\n" "* bssid = %pM\n", (new_assoc ? "" : "out"),
1785 le16_to_cpu(staging_rxon->channel), staging_rxon->bssid_addr);
1788 * reserved4 and 5 could have been filled by the iwlcore code.
1789 * Let's clear them before pushing to the 3945.
1791 staging_rxon->reserved4 = 0;
1792 staging_rxon->reserved5 = 0;
1794 il_set_rxon_hwcrypto(il, !il3945_mod_params.sw_crypto);
1796 /* Apply the new configuration */
1797 rc = il_send_cmd_pdu(il, C_RXON, sizeof(struct il3945_rxon_cmd),
1800 IL_ERR("Error setting new configuration (%d).\n", rc);
1804 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1807 il_clear_ucode_stations(il);
1808 il_restore_stations(il);
1811 /* If we issue a new RXON command which required a tune then we must
1812 * send a new TXPOWER command or we won't be able to Tx any frames */
1813 rc = il_set_tx_power(il, il->tx_power_next, true);
1815 IL_ERR("Error setting Tx power (%d).\n", rc);
1819 /* Init the hardware's rate fallback order based on the band */
1820 rc = il3945_init_hw_rate_table(il);
1822 IL_ERR("Error setting HW rate table: %02X\n", rc);
1830 * il3945_reg_txpower_periodic - called when time to check our temperature.
1832 * -- reset periodic timer
1833 * -- see if temp has changed enough to warrant re-calibration ... if so:
1834 * -- correct coeffs for temp (can reset temp timer)
1835 * -- save this temp as "last",
1836 * -- send new set of gain settings to NIC
1837 * NOTE: This should continue working, even when we're not associated,
1838 * so we can keep our internal table of scan powers current. */
1840 il3945_reg_txpower_periodic(struct il_priv *il)
1842 /* This will kick in the "brute force"
1843 * il3945_hw_reg_comp_txpower_temp() below */
1844 if (!il3945_is_temp_calib_needed(il))
1847 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1848 * This is based *only* on current temperature,
1849 * ignoring any previous power measurements */
1850 il3945_hw_reg_comp_txpower_temp(il);
1853 queue_delayed_work(il->workqueue, &il->_3945.thermal_periodic,
1854 REG_RECALIB_PERIOD * HZ);
1858 il3945_bg_reg_txpower_periodic(struct work_struct *work)
1860 struct il_priv *il = container_of(work, struct il_priv,
1861 _3945.thermal_periodic.work);
1863 if (test_bit(S_EXIT_PENDING, &il->status))
1866 mutex_lock(&il->mutex);
1867 il3945_reg_txpower_periodic(il);
1868 mutex_unlock(&il->mutex);
1872 * il3945_hw_reg_get_ch_grp_idx - find the channel-group idx (0-4) for channel.
1874 * This function is used when initializing channel-info structs.
1876 * NOTE: These channel groups do *NOT* match the bands above!
1877 * These channel groups are based on factory-tested channels;
1878 * on A-band, EEPROM's "group frequency" entries represent the top
1879 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1882 il3945_hw_reg_get_ch_grp_idx(struct il_priv *il,
1883 const struct il_channel_info *ch_info)
1885 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1886 struct il3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1888 u16 group_idx = 0; /* based on factory calib frequencies */
1891 /* Find the group idx for the channel ... don't use idx 1(?) */
1892 if (il_is_channel_a_band(ch_info)) {
1893 for (group = 1; group < 5; group++) {
1894 grp_channel = ch_grp[group].group_channel;
1895 if (ch_info->channel <= grp_channel) {
1900 /* group 4 has a few channels *above* its factory cal freq */
1904 group_idx = 0; /* 2.4 GHz, group 0 */
1906 D_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, group_idx);
1911 * il3945_hw_reg_get_matched_power_idx - Interpolate to get nominal idx
1913 * Interpolate to get nominal (i.e. at factory calibration temperature) idx
1914 * into radio/DSP gain settings table for requested power.
1917 il3945_hw_reg_get_matched_power_idx(struct il_priv *il, s8 requested_power,
1918 s32 setting_idx, s32 *new_idx)
1920 const struct il3945_eeprom_txpower_group *chnl_grp = NULL;
1921 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1923 s32 power = 2 * requested_power;
1925 const struct il3945_eeprom_txpower_sample *samples;
1930 chnl_grp = &eeprom->groups[setting_idx];
1931 samples = chnl_grp->samples;
1932 for (i = 0; i < 5; i++) {
1933 if (power == samples[i].power) {
1934 *new_idx = samples[i].gain_idx;
1939 if (power > samples[1].power) {
1942 } else if (power > samples[2].power) {
1945 } else if (power > samples[3].power) {
1953 denominator = (s32) samples[idx1].power - (s32) samples[idx0].power;
1954 if (denominator == 0)
1956 gains0 = (s32) samples[idx0].gain_idx * (1 << 19);
1957 gains1 = (s32) samples[idx1].gain_idx * (1 << 19);
1959 gains0 + (gains1 - gains0) * ((s32) power -
1960 (s32) samples[idx0].power) /
1961 denominator + (1 << 18);
1962 *new_idx = res >> 19;
1967 il3945_hw_reg_init_channel_groups(struct il_priv *il)
1971 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
1972 const struct il3945_eeprom_txpower_group *group;
1974 D_POWER("Initializing factory calib info from EEPROM\n");
1976 for (i = 0; i < IL_NUM_TX_CALIB_GROUPS; i++) {
1977 s8 *clip_pwrs; /* table of power levels for each rate */
1978 s8 satur_pwr; /* saturation power for each chnl group */
1979 group = &eeprom->groups[i];
1981 /* sanity check on factory saturation power value */
1982 if (group->saturation_power < 40) {
1983 IL_WARN("Error: saturation power is %d, "
1984 "less than minimum expected 40\n",
1985 group->saturation_power);
1990 * Derive requested power levels for each rate, based on
1991 * hardware capabilities (saturation power for band).
1992 * Basic value is 3dB down from saturation, with further
1993 * power reductions for highest 3 data rates. These
1994 * backoffs provide headroom for high rate modulation
1995 * power peaks, without too much distortion (clipping).
1997 /* we'll fill in this array with h/w max power levels */
1998 clip_pwrs = (s8 *) il->_3945.clip_groups[i].clip_powers;
2000 /* divide factory saturation power by 2 to find -3dB level */
2001 satur_pwr = (s8) (group->saturation_power >> 1);
2003 /* fill in channel group's nominal powers for each rate */
2004 for (rate_idx = 0; rate_idx < RATE_COUNT_3945;
2005 rate_idx++, clip_pwrs++) {
2007 case RATE_36M_IDX_TBL:
2008 if (i == 0) /* B/G */
2009 *clip_pwrs = satur_pwr;
2011 *clip_pwrs = satur_pwr - 5;
2013 case RATE_48M_IDX_TBL:
2015 *clip_pwrs = satur_pwr - 7;
2017 *clip_pwrs = satur_pwr - 10;
2019 case RATE_54M_IDX_TBL:
2021 *clip_pwrs = satur_pwr - 9;
2023 *clip_pwrs = satur_pwr - 12;
2026 *clip_pwrs = satur_pwr;
2034 * il3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2036 * Second pass (during init) to set up il->channel_info
2038 * Set up Tx-power settings in our channel info database for each VALID
2039 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2040 * and current temperature.
2042 * Since this is based on current temperature (at init time), these values may
2043 * not be valid for very long, but it gives us a starting/default point,
2044 * and allows us to active (i.e. using Tx) scan.
2046 * This does *not* write values to NIC, just sets up our internal table.
2049 il3945_txpower_set_from_eeprom(struct il_priv *il)
2051 struct il_channel_info *ch_info = NULL;
2052 struct il3945_channel_power_info *pwr_info;
2053 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
2057 const s8 *clip_pwrs; /* array of power levels for each rate */
2060 u8 pwr_idx, base_pwr_idx, a_band;
2064 /* save temperature reference,
2065 * so we can determine next time to calibrate */
2066 temperature = il3945_hw_reg_txpower_get_temperature(il);
2067 il->last_temperature = temperature;
2069 il3945_hw_reg_init_channel_groups(il);
2071 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2072 for (i = 0, ch_info = il->channel_info; i < il->channel_count;
2074 a_band = il_is_channel_a_band(ch_info);
2075 if (!il_is_channel_valid(ch_info))
2078 /* find this channel's channel group (*not* "band") idx */
2079 ch_info->group_idx = il3945_hw_reg_get_ch_grp_idx(il, ch_info);
2081 /* Get this chnlgrp's rate->max/clip-powers table */
2083 il->_3945.clip_groups[ch_info->group_idx].clip_powers;
2085 /* calculate power idx *adjustment* value according to
2086 * diff between current temperature and factory temperature */
2088 il3945_hw_reg_adjust_power_by_temp(temperature,
2089 eeprom->groups[ch_info->
2093 D_POWER("Delta idx for channel %d: %d [%d]\n", ch_info->channel,
2094 delta_idx, temperature + IL_TEMP_CONVERT);
2096 /* set tx power value for all OFDM rates */
2097 for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) {
2098 s32 uninitialized_var(power_idx);
2101 /* use channel group's clip-power table,
2102 * but don't exceed channel's max power */
2103 s8 pwr = min(ch_info->max_power_avg,
2104 clip_pwrs[rate_idx]);
2106 pwr_info = &ch_info->power_info[rate_idx];
2108 /* get base (i.e. at factory-measured temperature)
2109 * power table idx for this rate's power */
2110 rc = il3945_hw_reg_get_matched_power_idx(il, pwr,
2115 IL_ERR("Invalid power idx\n");
2118 pwr_info->base_power_idx = (u8) power_idx;
2120 /* temperature compensate */
2121 power_idx += delta_idx;
2123 /* stay within range of gain table */
2124 power_idx = il3945_hw_reg_fix_power_idx(power_idx);
2126 /* fill 1 OFDM rate's il3945_channel_power_info struct */
2127 pwr_info->requested_power = pwr;
2128 pwr_info->power_table_idx = (u8) power_idx;
2129 pwr_info->tpc.tx_gain =
2130 power_gain_table[a_band][power_idx].tx_gain;
2131 pwr_info->tpc.dsp_atten =
2132 power_gain_table[a_band][power_idx].dsp_atten;
2135 /* set tx power for CCK rates, based on OFDM 12 Mbit settings */
2136 pwr_info = &ch_info->power_info[RATE_12M_IDX_TBL];
2137 power = pwr_info->requested_power + IL_CCK_FROM_OFDM_POWER_DIFF;
2138 pwr_idx = pwr_info->power_table_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2140 pwr_info->base_power_idx + IL_CCK_FROM_OFDM_IDX_DIFF;
2142 /* stay within table range */
2143 pwr_idx = il3945_hw_reg_fix_power_idx(pwr_idx);
2144 gain = power_gain_table[a_band][pwr_idx].tx_gain;
2145 dsp_atten = power_gain_table[a_band][pwr_idx].dsp_atten;
2147 /* fill each CCK rate's il3945_channel_power_info structure
2148 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2149 * NOTE: CCK rates start at end of OFDM rates! */
2150 for (rate_idx = 0; rate_idx < IL_CCK_RATES; rate_idx++) {
2152 &ch_info->power_info[rate_idx + IL_OFDM_RATES];
2153 pwr_info->requested_power = power;
2154 pwr_info->power_table_idx = pwr_idx;
2155 pwr_info->base_power_idx = base_pwr_idx;
2156 pwr_info->tpc.tx_gain = gain;
2157 pwr_info->tpc.dsp_atten = dsp_atten;
2160 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2161 for (scan_tbl_idx = 0; scan_tbl_idx < IL_NUM_SCAN_RATES;
2165 0) ? RATE_1M_IDX_TBL : RATE_6M_IDX_TBL;
2166 il3945_hw_reg_set_scan_power(il, scan_tbl_idx,
2167 actual_idx, clip_pwrs,
2176 il3945_hw_rxq_stop(struct il_priv *il)
2180 _il_wr(il, FH39_RCSR_CONFIG(0), 0);
2181 ret = _il_poll_bit(il, FH39_RSSR_STATUS,
2182 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
2183 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
2186 IL_ERR("Can't stop Rx DMA.\n");
2192 il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
2194 int txq_id = txq->q.id;
2196 struct il3945_shared *shared_data = il->_3945.shared_virt;
2198 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32) txq->q.dma_addr);
2200 il_wr(il, FH39_CBCC_CTRL(txq_id), 0);
2201 il_wr(il, FH39_CBCC_BASE(txq_id), 0);
2203 il_wr(il, FH39_TCSR_CONFIG(txq_id),
2204 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2205 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2206 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2207 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2208 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2210 /* fake read to flush all prev. writes */
2211 _il_rd(il, FH39_TSSR_CBB_BASE);
2220 il3945_get_hcmd_size(u8 cmd_id, u16 len)
2224 return sizeof(struct il3945_rxon_cmd);
2226 return sizeof(struct il3945_powertable_cmd);
2233 il3945_build_addsta_hcmd(const struct il_addsta_cmd *cmd, u8 * data)
2235 struct il3945_addsta_cmd *addsta = (struct il3945_addsta_cmd *)data;
2236 addsta->mode = cmd->mode;
2237 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2238 memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo));
2239 addsta->station_flags = cmd->station_flags;
2240 addsta->station_flags_msk = cmd->station_flags_msk;
2241 addsta->tid_disable_tx = cpu_to_le16(0);
2242 addsta->rate_n_flags = cmd->rate_n_flags;
2243 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2244 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2245 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2247 return (u16) sizeof(struct il3945_addsta_cmd);
2251 il3945_add_bssid_station(struct il_priv *il, const u8 * addr, u8 * sta_id_r)
2255 unsigned long flags;
2258 *sta_id_r = IL_INVALID_STATION;
2260 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
2262 IL_ERR("Unable to add station %pM\n", addr);
2269 spin_lock_irqsave(&il->sta_lock, flags);
2270 il->stations[sta_id].used |= IL_STA_LOCAL;
2271 spin_unlock_irqrestore(&il->sta_lock, flags);
2277 il3945_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
2280 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
2285 il3945_add_bssid_station(il, vif->bss_conf.bssid,
2286 &vif_priv->ibss_bssid_sta_id);
2290 il3945_sync_sta(il, vif_priv->ibss_bssid_sta_id,
2292 IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP :
2294 il3945_rate_scale_init(il->hw, vif_priv->ibss_bssid_sta_id);
2299 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
2300 vif->bss_conf.bssid);
2304 * il3945_init_hw_rate_table - Initialize the hardware rate fallback table
2307 il3945_init_hw_rate_table(struct il_priv *il)
2309 int rc, i, idx, prev_idx;
2310 struct il3945_rate_scaling_cmd rate_cmd = {
2311 .reserved = {0, 0, 0},
2313 struct il3945_rate_scaling_info *table = rate_cmd.table;
2315 for (i = 0; i < ARRAY_SIZE(il3945_rates); i++) {
2316 idx = il3945_rates[i].table_rs_idx;
2318 table[idx].rate_n_flags = cpu_to_le16(il3945_rates[i].plcp);
2319 table[idx].try_cnt = il->retry_rate;
2320 prev_idx = il3945_get_prev_ieee_rate(i);
2321 table[idx].next_rate_idx = il3945_rates[prev_idx].table_rs_idx;
2325 case IEEE80211_BAND_5GHZ:
2326 D_RATE("Select A mode rate scale\n");
2327 /* If one of the following CCK rates is used,
2328 * have it fall back to the 6M OFDM rate */
2329 for (i = RATE_1M_IDX_TBL; i <= RATE_11M_IDX_TBL; i++)
2330 table[i].next_rate_idx =
2331 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2333 /* Don't fall back to CCK rates */
2334 table[RATE_12M_IDX_TBL].next_rate_idx = RATE_9M_IDX_TBL;
2336 /* Don't drop out of OFDM rates */
2337 table[RATE_6M_IDX_TBL].next_rate_idx =
2338 il3945_rates[IL_FIRST_OFDM_RATE].table_rs_idx;
2341 case IEEE80211_BAND_2GHZ:
2342 D_RATE("Select B/G mode rate scale\n");
2343 /* If an OFDM rate is used, have it fall back to the
2346 if (!(il->_3945.sta_supp_rates & IL_OFDM_RATES_MASK) &&
2347 il_is_associated(il)) {
2349 idx = IL_FIRST_CCK_RATE;
2350 for (i = RATE_6M_IDX_TBL; i <= RATE_54M_IDX_TBL; i++)
2351 table[i].next_rate_idx =
2352 il3945_rates[idx].table_rs_idx;
2354 idx = RATE_11M_IDX_TBL;
2355 /* CCK shouldn't fall back to OFDM... */
2356 table[idx].next_rate_idx = RATE_5M_IDX_TBL;
2365 /* Update the rate scaling for control frame Tx */
2366 rate_cmd.table_id = 0;
2367 rc = il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2371 /* Update the rate scaling for data frame Tx */
2372 rate_cmd.table_id = 1;
2373 return il_send_cmd_pdu(il, C_RATE_SCALE, sizeof(rate_cmd), &rate_cmd);
2376 /* Called when initializing driver */
2378 il3945_hw_set_hw_params(struct il_priv *il)
2380 memset((void *)&il->hw_params, 0, sizeof(struct il_hw_params));
2382 il->_3945.shared_virt =
2383 dma_alloc_coherent(&il->pci_dev->dev, sizeof(struct il3945_shared),
2384 &il->_3945.shared_phys, GFP_KERNEL);
2385 if (!il->_3945.shared_virt) {
2386 IL_ERR("failed to allocate pci memory\n");
2390 il->hw_params.bcast_id = IL3945_BROADCAST_ID;
2392 /* Assign number of Usable TX queues */
2393 il->hw_params.max_txq_num = il->cfg->num_of_queues;
2395 il->hw_params.tfd_size = sizeof(struct il3945_tfd);
2396 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_3K);
2397 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2398 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2399 il->hw_params.max_stations = IL3945_STATION_COUNT;
2401 il->sta_key_max_num = STA_KEY_MAX_NUM;
2403 il->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2404 il->hw_params.max_beacon_itrvl = IL39_MAX_UCODE_BEACON_INTERVAL;
2405 il->hw_params.beacon_time_tsf_bits = IL3945_EXT_BEACON_TIME_POS;
2411 il3945_hw_get_beacon_cmd(struct il_priv *il, struct il3945_frame *frame,
2414 struct il3945_tx_beacon_cmd *tx_beacon_cmd;
2415 unsigned int frame_size;
2417 tx_beacon_cmd = (struct il3945_tx_beacon_cmd *)&frame->u;
2418 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2420 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
2421 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2424 il3945_fill_beacon_frame(il, tx_beacon_cmd->frame,
2425 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2427 BUG_ON(frame_size > MAX_MPDU_SIZE);
2428 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
2430 tx_beacon_cmd->tx.rate = rate;
2431 tx_beacon_cmd->tx.tx_flags =
2432 (TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
2434 /* supp_rates[0] == OFDM start at IL_FIRST_OFDM_RATE */
2435 tx_beacon_cmd->tx.supp_rates[0] =
2436 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
2438 tx_beacon_cmd->tx.supp_rates[1] = (IL_CCK_BASIC_RATES_MASK & 0xF);
2440 return sizeof(struct il3945_tx_beacon_cmd) + frame_size;
2444 il3945_hw_handler_setup(struct il_priv *il)
2446 il->handlers[C_TX] = il3945_hdl_tx;
2447 il->handlers[N_3945_RX] = il3945_hdl_rx;
2451 il3945_hw_setup_deferred_work(struct il_priv *il)
2453 INIT_DELAYED_WORK(&il->_3945.thermal_periodic,
2454 il3945_bg_reg_txpower_periodic);
2458 il3945_hw_cancel_deferred_work(struct il_priv *il)
2460 cancel_delayed_work(&il->_3945.thermal_periodic);
2463 /* check contents of special bootstrap uCode SRAM */
2465 il3945_verify_bsm(struct il_priv *il)
2467 __le32 *image = il->ucode_boot.v_addr;
2468 u32 len = il->ucode_boot.len;
2472 D_INFO("Begin verify bsm\n");
2474 /* verify BSM SRAM contents */
2475 val = il_rd_prph(il, BSM_WR_DWCOUNT_REG);
2476 for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len;
2477 reg += sizeof(u32), image++) {
2478 val = il_rd_prph(il, reg);
2479 if (val != le32_to_cpu(*image)) {
2480 IL_ERR("BSM uCode verification failed at "
2481 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2482 BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND,
2483 len, val, le32_to_cpu(*image));
2488 D_INFO("BSM bootstrap uCode image OK\n");
2493 /******************************************************************************
2495 * EEPROM related functions
2497 ******************************************************************************/
2500 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2501 * embedded controller) as EEPROM reader; each read is a series of pulses
2502 * to/from the EEPROM chip, not a single event, so even reads could conflict
2503 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2504 * simply claims ownership, which should be safe when this function is called
2505 * (i.e. before loading uCode!).
2508 il3945_eeprom_acquire_semaphore(struct il_priv *il)
2510 _il_clear_bit(il, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2515 il3945_eeprom_release_semaphore(struct il_priv *il)
2521 * il3945_load_bsm - Load bootstrap instructions
2525 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2526 * in special SRAM that does not power down during RFKILL. When powering back
2527 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2528 * the bootstrap program into the on-board processor, and starts it.
2530 * The bootstrap program loads (via DMA) instructions and data for a new
2531 * program from host DRAM locations indicated by the host driver in the
2532 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2535 * When initializing the NIC, the host driver points the BSM to the
2536 * "initialize" uCode image. This uCode sets up some internal data, then
2537 * notifies host via "initialize alive" that it is complete.
2539 * The host then replaces the BSM_DRAM_* pointer values to point to the
2540 * normal runtime uCode instructions and a backup uCode data cache buffer
2541 * (filled initially with starting data values for the on-board processor),
2542 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2543 * which begins normal operation.
2545 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2546 * the backup data cache in DRAM before SRAM is powered down.
2548 * When powering back up, the BSM loads the bootstrap program. This reloads
2549 * the runtime uCode instructions and the backup data cache into SRAM,
2550 * and re-launches the runtime uCode from where it left off.
2553 il3945_load_bsm(struct il_priv *il)
2555 __le32 *image = il->ucode_boot.v_addr;
2556 u32 len = il->ucode_boot.len;
2566 D_INFO("Begin load bsm\n");
2568 /* make sure bootstrap program is no larger than BSM's SRAM size */
2569 if (len > IL39_MAX_BSM_SIZE)
2572 /* Tell bootstrap uCode where to find the "Initialize" uCode
2573 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2574 * NOTE: il3945_initialize_alive_start() will replace these values,
2575 * after the "initialize" uCode has run, to point to
2576 * runtime/protocol instructions and backup data cache. */
2577 pinst = il->ucode_init.p_addr;
2578 pdata = il->ucode_init_data.p_addr;
2579 inst_len = il->ucode_init.len;
2580 data_len = il->ucode_init_data.len;
2582 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2583 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2584 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2585 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2587 /* Fill BSM memory with bootstrap instructions */
2588 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2589 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2590 reg_offset += sizeof(u32), image++)
2591 _il_wr_prph(il, reg_offset, le32_to_cpu(*image));
2593 rc = il3945_verify_bsm(il);
2597 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2598 il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0);
2599 il_wr_prph(il, BSM_WR_MEM_DST_REG, IL39_RTC_INST_LOWER_BOUND);
2600 il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2602 /* Load bootstrap code into instruction SRAM now,
2603 * to prepare to load "initialize" uCode */
2604 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2606 /* Wait for load of bootstrap uCode to finish */
2607 for (i = 0; i < 100; i++) {
2608 done = il_rd_prph(il, BSM_WR_CTRL_REG);
2609 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2614 D_INFO("BSM write complete, poll %d iterations\n", i);
2616 IL_ERR("BSM write did not complete!\n");
2620 /* Enable future boot loads whenever power management unit triggers it
2621 * (e.g. when powering back up after power-save shutdown) */
2622 il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2627 const struct il_ops il3945_ops = {
2628 .txq_attach_buf_to_tfd = il3945_hw_txq_attach_buf_to_tfd,
2629 .txq_free_tfd = il3945_hw_txq_free_tfd,
2630 .txq_init = il3945_hw_tx_queue_init,
2631 .load_ucode = il3945_load_bsm,
2632 .dump_nic_error_log = il3945_dump_nic_error_log,
2633 .apm_init = il3945_apm_init,
2634 .send_tx_power = il3945_send_tx_power,
2635 .is_valid_rtc_data_addr = il3945_hw_valid_rtc_data_addr,
2636 .eeprom_acquire_semaphore = il3945_eeprom_acquire_semaphore,
2637 .eeprom_release_semaphore = il3945_eeprom_release_semaphore,
2639 .rxon_assoc = il3945_send_rxon_assoc,
2640 .commit_rxon = il3945_commit_rxon,
2642 .get_hcmd_size = il3945_get_hcmd_size,
2643 .build_addsta_hcmd = il3945_build_addsta_hcmd,
2644 .request_scan = il3945_request_scan,
2645 .post_scan = il3945_post_scan,
2647 .post_associate = il3945_post_associate,
2648 .config_ap = il3945_config_ap,
2649 .manage_ibss_station = il3945_manage_ibss_station,
2651 .send_led_cmd = il3945_send_led_cmd,
2654 static struct il_cfg il3945_bg_cfg = {
2656 .fw_name_pre = IL3945_FW_PRE,
2657 .ucode_api_max = IL3945_UCODE_API_MAX,
2658 .ucode_api_min = IL3945_UCODE_API_MIN,
2660 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2661 .mod_params = &il3945_mod_params,
2662 .led_mode = IL_LED_BLINK,
2664 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2665 .num_of_queues = IL39_NUM_QUEUES,
2666 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2669 .led_compensation = 64,
2670 .wd_timeout = IL_DEF_WD_TIMEOUT,
2672 .regulatory_bands = {
2673 EEPROM_REGULATORY_BAND_1_CHANNELS,
2674 EEPROM_REGULATORY_BAND_2_CHANNELS,
2675 EEPROM_REGULATORY_BAND_3_CHANNELS,
2676 EEPROM_REGULATORY_BAND_4_CHANNELS,
2677 EEPROM_REGULATORY_BAND_5_CHANNELS,
2678 EEPROM_REGULATORY_BAND_NO_HT40,
2679 EEPROM_REGULATORY_BAND_NO_HT40,
2683 static struct il_cfg il3945_abg_cfg = {
2685 .fw_name_pre = IL3945_FW_PRE,
2686 .ucode_api_max = IL3945_UCODE_API_MAX,
2687 .ucode_api_min = IL3945_UCODE_API_MIN,
2688 .sku = IL_SKU_A | IL_SKU_G,
2689 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2690 .mod_params = &il3945_mod_params,
2691 .led_mode = IL_LED_BLINK,
2693 .eeprom_size = IL3945_EEPROM_IMG_SIZE,
2694 .num_of_queues = IL39_NUM_QUEUES,
2695 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2698 .led_compensation = 64,
2699 .wd_timeout = IL_DEF_WD_TIMEOUT,
2701 .regulatory_bands = {
2702 EEPROM_REGULATORY_BAND_1_CHANNELS,
2703 EEPROM_REGULATORY_BAND_2_CHANNELS,
2704 EEPROM_REGULATORY_BAND_3_CHANNELS,
2705 EEPROM_REGULATORY_BAND_4_CHANNELS,
2706 EEPROM_REGULATORY_BAND_5_CHANNELS,
2707 EEPROM_REGULATORY_BAND_NO_HT40,
2708 EEPROM_REGULATORY_BAND_NO_HT40,
2712 DEFINE_PCI_DEVICE_TABLE(il3945_hw_card_ids) = {
2713 {IL_PCI_DEVICE(0x4222, 0x1005, il3945_bg_cfg)},
2714 {IL_PCI_DEVICE(0x4222, 0x1034, il3945_bg_cfg)},
2715 {IL_PCI_DEVICE(0x4222, 0x1044, il3945_bg_cfg)},
2716 {IL_PCI_DEVICE(0x4227, 0x1014, il3945_bg_cfg)},
2717 {IL_PCI_DEVICE(0x4222, PCI_ANY_ID, il3945_abg_cfg)},
2718 {IL_PCI_DEVICE(0x4227, PCI_ANY_ID, il3945_abg_cfg)},
2722 MODULE_DEVICE_TABLE(pci, il3945_hw_card_ids);