1 /******************************************************************************
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
37 struct il_rxon_context;
39 /* configuration for the _4965 devices */
40 extern struct il_cfg il4965_cfg;
42 extern struct il_mod_params il4965_mod_params;
44 extern struct ieee80211_ops il4965_hw_ops;
47 void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid,
51 void il4965_set_rxon_chain(struct il_priv *il, struct il_rxon_context *ctx);
54 int il4965_verify_ucode(struct il_priv *il);
57 void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status);
59 void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
60 int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
61 int il4965_hw_nic_init(struct il_priv *il);
62 int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
65 void il4965_rx_queue_restock(struct il_priv *il);
66 void il4965_rx_replenish(struct il_priv *il);
67 void il4965_rx_replenish_now(struct il_priv *il);
68 void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
69 int il4965_rxq_stop(struct il_priv *il);
70 int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
71 void il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb);
72 void il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb);
73 void il4965_rx_handle(struct il_priv *il);
76 void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
77 int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
78 dma_addr_t addr, u16 len, u8 reset, u8 pad);
79 int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
80 void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
81 struct ieee80211_tx_info *info);
82 int il4965_tx_skb(struct il_priv *il, struct sk_buff *skb);
83 int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
84 struct ieee80211_sta *sta, u16 tid, u16 * ssn);
85 int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
86 struct ieee80211_sta *sta, u16 tid);
87 int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id);
88 void il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb);
89 int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
90 void il4965_hw_txq_ctx_free(struct il_priv *il);
91 int il4965_txq_ctx_alloc(struct il_priv *il);
92 void il4965_txq_ctx_reset(struct il_priv *il);
93 void il4965_txq_ctx_stop(struct il_priv *il);
94 void il4965_txq_set_sched(struct il_priv *il, u32 mask);
97 * Acquire il->lock before calling this function !
99 void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
101 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
102 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
103 * @scd_retry: (1) Indicates queue will be used in aggregation mode
105 * NOTE: Acquire il->lock before calling this function !
107 void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
108 int tx_fifo_id, int scd_retry);
110 u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant_idx, u8 valid);
113 void il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb);
114 bool il4965_good_plcp_health(struct il_priv *il, struct il_rx_pkt *pkt);
115 void il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
116 void il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
119 int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
122 int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
126 int il4965_send_beacon_cmd(struct il_priv *il);
128 #ifdef CONFIG_IWLEGACY_DEBUG
129 const char *il4965_get_tx_fail_reason(u32 status);
131 static inline const char *
132 il4965_get_tx_fail_reason(u32 status)
138 /* station management */
139 int il4965_alloc_bcast_station(struct il_priv *il, struct il_rxon_context *ctx);
140 int il4965_add_bssid_station(struct il_priv *il, struct il_rxon_context *ctx,
141 const u8 *addr, u8 *sta_id_r);
142 int il4965_remove_default_wep_key(struct il_priv *il,
143 struct il_rxon_context *ctx,
144 struct ieee80211_key_conf *key);
145 int il4965_set_default_wep_key(struct il_priv *il, struct il_rxon_context *ctx,
146 struct ieee80211_key_conf *key);
147 int il4965_restore_default_wep_keys(struct il_priv *il,
148 struct il_rxon_context *ctx);
149 int il4965_set_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx,
150 struct ieee80211_key_conf *key, u8 sta_id);
151 int il4965_remove_dynamic_key(struct il_priv *il, struct il_rxon_context *ctx,
152 struct ieee80211_key_conf *key, u8 sta_id);
153 void il4965_update_tkip_key(struct il_priv *il, struct il_rxon_context *ctx,
154 struct ieee80211_key_conf *keyconf,
155 struct ieee80211_sta *sta, u32 iv32,
157 int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid);
158 int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
160 int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
162 void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt);
163 int il4965_update_bcast_stations(struct il_priv *il);
167 il4965_hw_get_rate(__le32 rate_n_flags)
169 return le32_to_cpu(rate_n_flags) & 0xFF;
173 il4965_hw_set_rate_n_flags(u8 rate, u32 flags)
175 return cpu_to_le32(flags | (u32) rate);
179 void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac);
180 int il4965_eeprom_acquire_semaphore(struct il_priv *il);
181 void il4965_eeprom_release_semaphore(struct il_priv *il);
182 int il4965_eeprom_check_version(struct il_priv *il);
184 /* mac80211 handlers (for 4965) */
185 void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
186 int il4965_mac_start(struct ieee80211_hw *hw);
187 void il4965_mac_stop(struct ieee80211_hw *hw);
188 void il4965_configure_filter(struct ieee80211_hw *hw,
189 unsigned int changed_flags,
190 unsigned int *total_flags, u64 multicast);
191 int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
192 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
193 struct ieee80211_key_conf *key);
194 void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
195 struct ieee80211_vif *vif,
196 struct ieee80211_key_conf *keyconf,
197 struct ieee80211_sta *sta, u32 iv32,
199 int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
200 enum ieee80211_ampdu_mlme_action action,
201 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
203 int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
204 struct ieee80211_sta *sta);
205 void il4965_mac_channel_switch(struct ieee80211_hw *hw,
206 struct ieee80211_channel_switch *ch_switch);
208 void il4965_led_enable(struct il_priv *il);
211 #define IL4965_EEPROM_IMG_SIZE 1024
214 * uCode queue management definitions ...
215 * The first queue used for block-ack aggregation is #7 (4965 only).
216 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
218 #define IL49_FIRST_AMPDU_QUEUE 7
220 /* Sizes and addresses for instruction and data memory (SRAM) in
221 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
222 #define IL49_RTC_INST_LOWER_BOUND (0x000000)
223 #define IL49_RTC_INST_UPPER_BOUND (0x018000)
225 #define IL49_RTC_DATA_LOWER_BOUND (0x800000)
226 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
228 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
229 IL49_RTC_INST_LOWER_BOUND)
230 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
231 IL49_RTC_DATA_LOWER_BOUND)
233 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
234 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
236 /* Size of uCode instruction memory in bootstrap state machine */
237 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
240 il4965_hw_valid_rtc_data_addr(u32 addr)
242 return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
243 addr < IL49_RTC_DATA_UPPER_BOUND);
246 /********************* START TEMPERATURE *************************************/
249 * 4965 temperature calculation.
251 * The driver must calculate the device temperature before calculating
252 * a txpower setting (amplifier gain is temperature dependent). The
253 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
254 * values used for the life of the driver, and one of which (R4) is the
255 * real-time temperature indicator.
257 * uCode provides all 4 values to the driver via the "initialize alive"
258 * notification (see struct il4965_init_alive_resp). After the runtime uCode
259 * image loads, uCode updates the R4 value via stats notifications
260 * (see N_STATS), which occur after each received beacon
261 * when associated, or can be requested via C_STATS.
263 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
264 * must sign-extend to 32 bits before applying formula below.
268 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
270 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
271 * an additional correction, which should be centered around 0 degrees
272 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
273 * centering the 97/100 correction around 0 degrees K.
275 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
276 * temperature with factory-measured temperatures when calculating txpower
279 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
280 #define TEMPERATURE_CALIB_A_VAL 259
282 /* Limit range of calculated temperature to be between these Kelvin values */
283 #define IL_TX_POWER_TEMPERATURE_MIN (263)
284 #define IL_TX_POWER_TEMPERATURE_MAX (410)
286 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
287 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
288 (t) > IL_TX_POWER_TEMPERATURE_MAX)
290 /********************* END TEMPERATURE ***************************************/
292 /********************* START TXPOWER *****************************************/
295 * 4965 txpower calculations rely on information from three sources:
298 * 2) "initialize" alive notification
299 * 3) stats notifications
301 * EEPROM data consists of:
303 * 1) Regulatory information (max txpower and channel usage flags) is provided
304 * separately for each channel that can possibly supported by 4965.
305 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
308 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom
309 * for locations in EEPROM.
311 * 2) Factory txpower calibration information is provided separately for
312 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
313 * but 5 GHz has several sub-bands.
315 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
317 * See struct il4965_eeprom_calib_info (and the tree of structures
318 * contained within it) for format, and struct il4965_eeprom for
319 * locations in EEPROM.
321 * "Initialization alive" notification (see struct il4965_init_alive_resp)
324 * 1) Temperature calculation parameters.
326 * 2) Power supply voltage measurement.
328 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
330 * Statistics notifications deliver:
332 * 1) Current values for temperature param R4.
336 * To calculate a txpower setting for a given desired target txpower, channel,
337 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
338 * support MIMO and transmit diversity), driver must do the following:
340 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
341 * Do not exceed regulatory limit; reduce target txpower if necessary.
343 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
344 * 2 transmitters will be used simultaneously; driver must reduce the
345 * regulatory limit by 3 dB (half-power) for each transmitter, so the
346 * combined total output of the 2 transmitters is within regulatory limits.
349 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
350 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
351 * reduce target txpower if necessary.
353 * Backoff values below are in 1/2 dB units (equivalent to steps in
354 * txpower gain tables):
356 * OFDM 6 - 36 MBit: 10 steps (5 dB)
357 * OFDM 48 MBit: 15 steps (7.5 dB)
358 * OFDM 54 MBit: 17 steps (8.5 dB)
359 * OFDM 60 MBit: 20 steps (10 dB)
360 * CCK all rates: 10 steps (5 dB)
362 * Backoff values apply to saturation txpower on a per-transmitter basis;
363 * when using MIMO (2 transmitters), each transmitter uses the same
364 * saturation level provided in EEPROM, and the same backoff values;
365 * no reduction (such as with regulatory txpower limits) is required.
367 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
368 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate
369 * factory measurement for ht40 channels.
371 * The result of this step is the final target txpower. The rest of
372 * the steps figure out the proper settings for the device to achieve
373 * that target txpower.
376 * 3) Determine (EEPROM) calibration sub band for the target channel, by
377 * comparing against first and last channels in each sub band
378 * (see struct il4965_eeprom_calib_subband_info).
381 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
382 * referencing the 2 factory-measured (sample) channels within the sub band.
384 * Interpolation is based on difference between target channel's frequency
385 * and the sample channels' frequencies. Since channel numbers are based
386 * on frequency (5 MHz between each channel number), this is equivalent
387 * to interpolating based on channel number differences.
389 * Note that the sample channels may or may not be the channels at the
390 * edges of the sub band. The target channel may be "outside" of the
391 * span of the sampled channels.
393 * Driver may choose the pair (for 2 Tx chains) of measurements (see
394 * struct il4965_eeprom_calib_ch_info) for which the actual measured
395 * txpower comes closest to the desired txpower. Usually, though,
396 * the middle set of measurements is closest to the regulatory limits,
397 * and is therefore a good choice for all txpower calculations (this
398 * assumes that high accuracy is needed for maximizing legal txpower,
399 * while lower txpower configurations do not need as much accuracy).
401 * Driver should interpolate both members of the chosen measurement pair,
402 * i.e. for both Tx chains (radio transmitters), unless the driver knows
403 * that only one of the chains will be used (e.g. only one tx antenna
404 * connected, but this should be unusual). The rate scaling algorithm
405 * switches antennas to find best performance, so both Tx chains will
406 * be used (although only one at a time) even for non-MIMO transmissions.
408 * Driver should interpolate factory values for temperature, gain table
409 * idx, and actual power. The power amplifier detector values are
410 * not used by the driver.
412 * Sanity check: If the target channel happens to be one of the sample
413 * channels, the results should agree with the sample channel's
417 * 5) Find difference between desired txpower and (interpolated)
418 * factory-measured txpower. Using (interpolated) factory gain table idx
419 * (shown elsewhere) as a starting point, adjust this idx lower to
420 * increase txpower, or higher to decrease txpower, until the target
421 * txpower is reached. Each step in the gain table is 1/2 dB.
423 * For example, if factory measured txpower is 16 dBm, and target txpower
424 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
428 * 6) Find difference between current device temperature and (interpolated)
429 * factory-measured temperature for sub-band. Factory values are in
430 * degrees Celsius. To calculate current temperature, see comments for
431 * "4965 temperature calculation".
433 * If current temperature is higher than factory temperature, driver must
434 * increase gain (lower gain table idx), and vice verse.
436 * Temperature affects gain differently for different channels:
438 * 2.4 GHz all channels: 3.5 degrees per half-dB step
439 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
440 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
442 * NOTE: Temperature can increase rapidly when transmitting, especially
443 * with heavy traffic at high txpowers. Driver should update
444 * temperature calculations often under these conditions to
445 * maintain strong txpower in the face of rising temperature.
448 * 7) Find difference between current power supply voltage indicator
449 * (from "initialize alive") and factory-measured power supply voltage
450 * indicator (EEPROM).
452 * If the current voltage is higher (indicator is lower) than factory
453 * voltage, gain should be reduced (gain table idx increased) by:
455 * (eeprom - current) / 7
457 * If the current voltage is lower (indicator is higher) than factory
458 * voltage, gain should be increased (gain table idx decreased) by:
460 * 2 * (current - eeprom) / 7
462 * If number of idx steps in either direction turns out to be > 2,
463 * something is wrong ... just use 0.
465 * NOTE: Voltage compensation is independent of band/channel.
467 * NOTE: "Initialize" uCode measures current voltage, which is assumed
468 * to be constant after this initial measurement. Voltage
469 * compensation for txpower (number of steps in gain table)
470 * may be calculated once and used until the next uCode bootload.
473 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
474 * adjust txpower for each transmitter chain, so txpower is balanced
475 * between the two chains. There are 5 pairs of tx_atten[group][chain]
476 * values in "initialize alive", one pair for each of 5 channel ranges:
478 * Group 0: 5 GHz channel 34-43
479 * Group 1: 5 GHz channel 44-70
480 * Group 2: 5 GHz channel 71-124
481 * Group 3: 5 GHz channel 125-200
482 * Group 4: 2.4 GHz all channels
484 * Add the tx_atten[group][chain] value to the idx for the target chain.
485 * The values are signed, but are in pairs of 0 and a non-negative number,
486 * so as to reduce gain (if necessary) of the "hotter" channel. This
487 * avoids any need to double-check for regulatory compliance after
491 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
494 * Hardware rev B: 9 steps (4.5 dB)
495 * Hardware rev C: 5 steps (2.5 dB)
497 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
498 * bits [3:2], 1 = B, 2 = C.
500 * NOTE: This compensation is in addition to any saturation backoff that
501 * might have been applied in an earlier step.
504 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
506 * Limit the adjusted idx to stay within the table!
509 * 11) Read gain table entries for DSP and radio gain, place into appropriate
510 * location(s) in command (struct il4965_txpowertable_cmd).
514 * When MIMO is used (2 transmitters operating simultaneously), driver should
515 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
516 * for the device. That is, use half power for each transmitter, so total
517 * txpower is within regulatory limits.
519 * The value "6" represents number of steps in gain table to reduce power 3 dB.
520 * Each step is 1/2 dB.
522 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
525 * CCK gain compensation.
527 * When calculating txpowers for CCK, after making sure that the target power
528 * is within regulatory and saturation limits, driver must additionally
529 * back off gain by adding these values to the gain table idx.
531 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
532 * bits [3:2], 1 = B, 2 = C.
534 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
535 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
538 * 4965 power supply voltage compensation for txpower
540 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
545 * The following tables contain pair of values for setting txpower, i.e.
546 * gain settings for the output of the device's digital signal processor (DSP),
547 * and for the analog gain structure of the transmitter.
549 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
550 * are *relative* steps, not indications of absolute output power. Output
551 * power varies with temperature, voltage, and channel frequency, and also
552 * requires consideration of average power (to satisfy regulatory constraints),
553 * and peak power (to avoid distortion of the output signal).
555 * Each entry contains two values:
556 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
557 * linear value that multiplies the output of the digital signal processor,
558 * before being sent to the analog radio.
559 * 2) Radio gain. This sets the analog gain of the radio Tx path.
560 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
562 * EEPROM contains factory calibration data for txpower. This maps actual
563 * measured txpower levels to gain settings in the "well known" tables
564 * below ("well-known" means here that both factory calibration *and* the
565 * driver work with the same table).
567 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
568 * has an extension (into negative idxes), in case the driver needs to
569 * boost power setting for high device temperatures (higher than would be
570 * present during factory calibration). A 5 Ghz EEPROM idx of "40"
571 * corresponds to the 49th entry in the table used by the driver.
573 #define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */
574 #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
579 * Index Dsp gain Radio gain
580 * 0 110 0x3f (highest gain)
684 * Index Dsp gain Radio gain
685 * -9 123 0x3F (highest gain)
796 * Sanity checks and default values for EEPROM regulatory levels.
797 * If EEPROM values fall outside MIN/MAX range, use default values.
799 * Regulatory limits refer to the maximum average txpower allowed by
800 * regulatory agencies in the geographies in which the device is meant
801 * to be operated. These limits are SKU-specific (i.e. geography-specific),
802 * and channel-specific; each channel has an individual regulatory limit
803 * listed in the EEPROM.
805 * Units are in half-dBm (i.e. "34" means 17 dBm).
807 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
808 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
809 #define IL_TX_POWER_REGULATORY_MIN (0)
810 #define IL_TX_POWER_REGULATORY_MAX (34)
813 * Sanity checks and default values for EEPROM saturation levels.
814 * If EEPROM values fall outside MIN/MAX range, use default values.
816 * Saturation is the highest level that the output power amplifier can produce
817 * without significant clipping distortion. This is a "peak" power level.
818 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
819 * require differing amounts of backoff, relative to their average power output,
820 * in order to avoid clipping distortion.
822 * Driver must make sure that it is violating neither the saturation limit,
823 * nor the regulatory limit, when calculating Tx power settings for various
826 * Units are in half-dBm (i.e. "38" means 19 dBm).
828 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
829 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
830 #define IL_TX_POWER_SATURATION_MIN (20)
831 #define IL_TX_POWER_SATURATION_MAX (50)
834 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
835 * and thermal Txpower calibration.
837 * When calculating txpower, driver must compensate for current device
838 * temperature; higher temperature requires higher gain. Driver must calculate
839 * current temperature (see "4965 temperature calculation"), then compare vs.
840 * factory calibration temperature in EEPROM; if current temperature is higher
841 * than factory temperature, driver must *increase* gain by proportions shown
842 * in table below. If current temperature is lower than factory, driver must
845 * Different frequency ranges require different compensation, as shown below.
847 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
848 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
849 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
851 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
852 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
853 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
855 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
856 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
857 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
859 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
860 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
861 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
863 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
864 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
865 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
868 CALIB_CH_GROUP_1 = 0,
869 CALIB_CH_GROUP_2 = 1,
870 CALIB_CH_GROUP_3 = 2,
871 CALIB_CH_GROUP_4 = 3,
872 CALIB_CH_GROUP_5 = 4,
876 /********************* END TXPOWER *****************************************/
881 * Most communication between driver and 4965 is via queues of data buffers.
882 * For example, all commands that the driver issues to device's embedded
883 * controller (uCode) are via the command queue (one of the Tx queues). All
884 * uCode command responses/replies/notifications, including Rx frames, are
885 * conveyed from uCode to driver via the Rx queue.
887 * Most support for these queues, including handshake support, resides in
888 * structures in host DRAM, shared between the driver and the device. When
889 * allocating this memory, the driver must make sure that data written by
890 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
891 * cache memory), so DRAM and cache are consistent, and the device can
892 * immediately see changes made by the driver.
894 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
895 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
896 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
898 #define IL49_NUM_FIFOS 7
899 #define IL49_CMD_FIFO_NUM 4
900 #define IL49_NUM_QUEUES 16
901 #define IL49_NUM_AMPDU_QUEUES 8
904 * struct il4965_schedq_bc_tbl
908 * Each Tx queue uses a byte-count table containing 320 entries:
909 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
910 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
911 * max Tx win is 64 TFDs).
913 * When driver sets up a new TFD, it must also enter the total byte count
914 * of the frame to be transmitted into the corresponding entry in the byte
915 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
916 * must duplicate the byte count entry in corresponding idx 256-319.
918 * padding puts each byte count table on a 1024-byte boundary;
919 * 4965 assumes tables are separated by 1024 bytes.
921 struct il4965_scd_bc_tbl {
922 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
923 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
926 #define IL4965_RTC_INST_LOWER_BOUND (0x000000)
929 #define IL4965_RSSI_OFFSET 44
932 #define PCI_CFG_RETRY_TIMEOUT 0x041
934 /* PCI register values */
935 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
936 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
938 #define IL4965_DEFAULT_TX_RETRY 15
941 #define IL4965_FIRST_AMPDU_QUEUE 10
944 void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
945 void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
946 void il4965_init_sensitivity(struct il_priv *il);
947 void il4965_reset_run_time_calib(struct il_priv *il);
948 void il4965_calib_free_results(struct il_priv *il);
951 #ifdef CONFIG_IWLEGACY_DEBUGFS
952 ssize_t il4965_ucode_rx_stats_read(struct file *file, char __user *user_buf,
953 size_t count, loff_t *ppos);
954 ssize_t il4965_ucode_tx_stats_read(struct file *file, char __user *user_buf,
955 size_t count, loff_t *ppos);
956 ssize_t il4965_ucode_general_stats_read(struct file *file,
957 char __user *user_buf, size_t count,
961 /****************************/
962 /* Flow Handler Definitions */
963 /****************************/
966 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
967 * Addresses are offsets from device's PCI hardware base address.
969 #define FH49_MEM_LOWER_BOUND (0x1000)
970 #define FH49_MEM_UPPER_BOUND (0x2000)
973 * Keep-Warm (KW) buffer base address.
975 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
976 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
977 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
978 * from going into a power-savings mode that would cause higher DRAM latency,
979 * and possible data over/under-runs, before all Tx/Rx is complete.
981 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
982 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
983 * automatically invokes keep-warm accesses when normal accesses might not
984 * be sufficient to maintain fast DRAM response.
987 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
989 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
992 * TFD Circular Buffers Base (CBBC) addresses
994 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
995 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
996 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
997 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
998 * aligned (address bits 0-7 must be 0).
1000 * Bit fields in each pointer register:
1001 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1003 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1004 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
1006 /* Find TFD CB base pointer for given queue (range 0-15). */
1007 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
1010 * Rx SRAM Control and Status Registers (RSCSR)
1012 * These registers provide handshake between driver and 4965 for the Rx queue
1013 * (this queue handles *all* command responses, notifications, Rx data, etc.
1014 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
1015 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1016 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1017 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1018 * mapping between RBDs and RBs.
1020 * Driver must allocate host DRAM memory for the following, and set the
1021 * physical address of each into 4965 registers:
1023 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1024 * entries (although any power of 2, up to 4096, is selectable by driver).
1025 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1026 * (typically 4K, although 8K or 16K are also selectable by driver).
1027 * Driver sets up RB size and number of RBDs in the CB via Rx config
1028 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
1030 * Bit fields within one RBD:
1031 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1033 * Driver sets physical address [35:8] of base of RBD circular buffer
1034 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1036 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1037 * (RBs) have been filled, via a "write pointer", actually the idx of
1038 * the RB's corresponding RBD within the circular buffer. Driver sets
1039 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1041 * Bit fields in lower dword of Rx status buffer (upper dword not used
1042 * by driver; see struct il4965_shared, val0):
1043 * 31-12: Not used by driver
1044 * 11- 0: Index of last filled Rx buffer descriptor
1045 * (4965 writes, driver reads this value)
1047 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1048 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1049 * and update the 4965's "write" idx register,
1050 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1052 * This "write" idx corresponds to the *next* RBD that the driver will make
1053 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1054 * the circular buffer. This value should initially be 0 (before preparing any
1055 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1056 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1057 * "read" idx has advanced past 1! See below).
1058 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1060 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1061 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1062 * to tell the driver the idx of the latest filled RBD. The driver must
1063 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1065 * The driver must also internally keep track of a third idx, which is the
1066 * next RBD to process. When receiving an Rx interrupt, driver should process
1067 * all filled but unprocessed RBs up to, but not including, the RB
1068 * corresponding to the "read" idx. For example, if "read" idx becomes "1",
1069 * driver may process the RB pointed to by RBD 0. Depending on volume of
1070 * traffic, there may be many RBs to process.
1072 * If read idx == write idx, 4965 thinks there is no room to put new data.
1073 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1074 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1075 * and "read" idxes; that is, make sure that there are no more than 254
1076 * buffers waiting to be filled.
1078 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1079 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1080 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1083 * Physical base address of 8-byte Rx Status buffer.
1085 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1087 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1090 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1092 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1094 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1097 * Rx write pointer (idx, really!).
1099 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1100 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1102 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1103 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1106 * Rx Config/Status Registers (RCSR)
1107 * Rx Config Reg for channel 0 (only channel used)
1109 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1110 * normal operation (see bit fields).
1112 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1113 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
1114 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1117 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1118 * '10' operate normally
1120 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1121 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1123 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1124 * '10' 12K, '11' 16K.
1126 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1127 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1128 * typical value 0x10 (about 1/2 msec)
1131 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1132 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1133 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1135 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1137 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1138 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1139 #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1140 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1141 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1142 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */
1144 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1145 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1146 #define RX_RB_TIMEOUT (0x10)
1148 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1149 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1150 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1152 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1153 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1154 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1155 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1157 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1158 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1159 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1162 * Rx Shared Status Registers (RSSR)
1164 * After stopping Rx DMA channel (writing 0 to
1165 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1166 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1169 * 24: 1 = Channel 0 is idle
1171 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1172 * contain default values that should not be altered by the driver.
1174 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1175 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1177 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1178 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1179 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1180 (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1182 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1184 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1186 /* TFDB Area - TFDs buffer table */
1187 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1188 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1189 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1190 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1191 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1194 * Transmit DMA Channel Control/Status Registers (TCSR)
1196 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1197 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1198 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1200 * To use a Tx DMA channel, driver must initialize its
1201 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1203 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1204 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1206 * All other bits should be 0.
1209 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1210 * '10' operate normally
1211 * 29- 4: Reserved, set to "0"
1212 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1213 * 2- 0: Reserved, set to "0"
1215 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1216 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1218 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1219 #define FH49_TCSR_CHNL_NUM (7)
1220 #define FH50_TCSR_CHNL_NUM (8)
1222 /* TCSR: tx_config register values */
1223 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1224 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1225 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1226 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1227 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1228 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1230 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1231 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1233 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1234 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1236 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1237 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1238 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1240 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1241 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1242 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1244 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1245 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1246 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1248 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1249 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1250 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1252 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1253 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1256 * Tx Shared Status Registers (TSSR)
1258 * After stopping Tx DMA channel (writing 0 to
1259 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1260 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1261 * (channel's buffers empty | no pending requests).
1264 * 31-24: 1 = Channel buffers empty (channel 7:0)
1265 * 23-16: 1 = No pending requests (channel 7:0)
1267 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1268 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1270 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1273 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1274 * 31: Indicates an address error when accessed to internal memory
1275 * uCode/driver must write "1" in order to clear this flag
1276 * 30: Indicates that Host did not send the expected number of dwords to FH
1277 * uCode/driver must write "1" in order to clear this flag
1278 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1279 * command was received from the scheduler while the TRB was already full
1280 * with previous command
1281 * uCode/driver must write "1" in order to clear this flag
1282 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1283 * bit is set, it indicates that the FH has received a full indication
1284 * from the RTC TxFIFO and the current value of the TxCredit counter was
1285 * not equal to zero. This mean that the credit mechanism was not
1286 * synchronized to the TxFIFO status
1287 * uCode/driver must write "1" in order to clear this flag
1289 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1291 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1293 /* Tx service channels */
1294 #define FH49_SRVC_CHNL (9)
1295 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1296 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1297 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1298 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1300 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1301 /* Instruct FH to increment the retry count of a packet when
1302 * it is brought from the memory to TX-FIFO
1304 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1306 /* Keep Warm Size */
1307 #define IL_KW_SIZE 0x1000 /* 4k */
1309 #endif /* __il_4965_h__ */