1 /******************************************************************************
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
37 struct il_rxon_context;
39 /* configuration for the _4965 devices */
40 extern struct il_cfg il4965_cfg;
41 extern const struct il_ops il4965_ops;
43 extern struct il_mod_params il4965_mod_params;
46 void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid,
50 void il4965_set_rxon_chain(struct il_priv *il);
53 int il4965_verify_ucode(struct il_priv *il);
56 void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status);
58 void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
59 int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
60 int il4965_hw_nic_init(struct il_priv *il);
61 int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
64 void il4965_rx_queue_restock(struct il_priv *il);
65 void il4965_rx_replenish(struct il_priv *il);
66 void il4965_rx_replenish_now(struct il_priv *il);
67 void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
68 int il4965_rxq_stop(struct il_priv *il);
69 int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
70 void il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb);
71 void il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb);
72 void il4965_rx_handle(struct il_priv *il);
75 void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
76 int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
77 dma_addr_t addr, u16 len, u8 reset, u8 pad);
78 int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
79 void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
80 struct ieee80211_tx_info *info);
81 int il4965_tx_skb(struct il_priv *il, struct sk_buff *skb);
82 int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
83 struct ieee80211_sta *sta, u16 tid, u16 * ssn);
84 int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
85 struct ieee80211_sta *sta, u16 tid);
86 int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id);
87 void il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb);
88 int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
89 void il4965_hw_txq_ctx_free(struct il_priv *il);
90 int il4965_txq_ctx_alloc(struct il_priv *il);
91 void il4965_txq_ctx_reset(struct il_priv *il);
92 void il4965_txq_ctx_stop(struct il_priv *il);
93 void il4965_txq_set_sched(struct il_priv *il, u32 mask);
96 * Acquire il->lock before calling this function !
98 void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
100 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
101 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
102 * @scd_retry: (1) Indicates queue will be used in aggregation mode
104 * NOTE: Acquire il->lock before calling this function !
106 void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
107 int tx_fifo_id, int scd_retry);
110 void il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb);
111 bool il4965_good_plcp_health(struct il_priv *il, struct il_rx_pkt *pkt);
112 void il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb);
113 void il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb);
116 int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
119 int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
123 int il4965_send_beacon_cmd(struct il_priv *il);
125 #ifdef CONFIG_IWLEGACY_DEBUG
126 const char *il4965_get_tx_fail_reason(u32 status);
128 static inline const char *
129 il4965_get_tx_fail_reason(u32 status)
135 /* station management */
136 int il4965_alloc_bcast_station(struct il_priv *il);
137 int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r);
138 int il4965_remove_default_wep_key(struct il_priv *il,
139 struct ieee80211_key_conf *key);
140 int il4965_set_default_wep_key(struct il_priv *il,
141 struct ieee80211_key_conf *key);
142 int il4965_restore_default_wep_keys(struct il_priv *il);
143 int il4965_set_dynamic_key(struct il_priv *il,
144 struct ieee80211_key_conf *key, u8 sta_id);
145 int il4965_remove_dynamic_key(struct il_priv *il,
146 struct ieee80211_key_conf *key, u8 sta_id);
147 void il4965_update_tkip_key(struct il_priv *il,
148 struct ieee80211_key_conf *keyconf,
149 struct ieee80211_sta *sta, u32 iv32,
151 int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid);
152 int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
154 int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
156 void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt);
157 int il4965_update_bcast_stations(struct il_priv *il);
161 il4965_hw_get_rate(__le32 rate_n_flags)
163 return le32_to_cpu(rate_n_flags) & 0xFF;
167 void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac);
168 int il4965_eeprom_acquire_semaphore(struct il_priv *il);
169 void il4965_eeprom_release_semaphore(struct il_priv *il);
170 int il4965_eeprom_check_version(struct il_priv *il);
172 /* mac80211 handlers (for 4965) */
173 void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
174 int il4965_mac_start(struct ieee80211_hw *hw);
175 void il4965_mac_stop(struct ieee80211_hw *hw);
176 void il4965_configure_filter(struct ieee80211_hw *hw,
177 unsigned int changed_flags,
178 unsigned int *total_flags, u64 multicast);
179 int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
180 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
181 struct ieee80211_key_conf *key);
182 void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
183 struct ieee80211_vif *vif,
184 struct ieee80211_key_conf *keyconf,
185 struct ieee80211_sta *sta, u32 iv32,
187 int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
188 enum ieee80211_ampdu_mlme_action action,
189 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
191 int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
192 struct ieee80211_sta *sta);
193 void il4965_mac_channel_switch(struct ieee80211_hw *hw,
194 struct ieee80211_channel_switch *ch_switch);
196 void il4965_led_enable(struct il_priv *il);
199 #define IL4965_EEPROM_IMG_SIZE 1024
202 * uCode queue management definitions ...
203 * The first queue used for block-ack aggregation is #7 (4965 only).
204 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
206 #define IL49_FIRST_AMPDU_QUEUE 7
208 /* Sizes and addresses for instruction and data memory (SRAM) in
209 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
210 #define IL49_RTC_INST_LOWER_BOUND (0x000000)
211 #define IL49_RTC_INST_UPPER_BOUND (0x018000)
213 #define IL49_RTC_DATA_LOWER_BOUND (0x800000)
214 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
216 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
217 IL49_RTC_INST_LOWER_BOUND)
218 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
219 IL49_RTC_DATA_LOWER_BOUND)
221 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
222 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
224 /* Size of uCode instruction memory in bootstrap state machine */
225 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
228 il4965_hw_valid_rtc_data_addr(u32 addr)
230 return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
231 addr < IL49_RTC_DATA_UPPER_BOUND);
234 /********************* START TEMPERATURE *************************************/
237 * 4965 temperature calculation.
239 * The driver must calculate the device temperature before calculating
240 * a txpower setting (amplifier gain is temperature dependent). The
241 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
242 * values used for the life of the driver, and one of which (R4) is the
243 * real-time temperature indicator.
245 * uCode provides all 4 values to the driver via the "initialize alive"
246 * notification (see struct il4965_init_alive_resp). After the runtime uCode
247 * image loads, uCode updates the R4 value via stats notifications
248 * (see N_STATS), which occur after each received beacon
249 * when associated, or can be requested via C_STATS.
251 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
252 * must sign-extend to 32 bits before applying formula below.
256 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
258 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
259 * an additional correction, which should be centered around 0 degrees
260 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for
261 * centering the 97/100 correction around 0 degrees K.
263 * Add 273 to Kelvin value to find degrees Celsius, for comparing current
264 * temperature with factory-measured temperatures when calculating txpower
267 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
268 #define TEMPERATURE_CALIB_A_VAL 259
270 /* Limit range of calculated temperature to be between these Kelvin values */
271 #define IL_TX_POWER_TEMPERATURE_MIN (263)
272 #define IL_TX_POWER_TEMPERATURE_MAX (410)
274 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
275 ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
276 (t) > IL_TX_POWER_TEMPERATURE_MAX)
278 /********************* END TEMPERATURE ***************************************/
280 /********************* START TXPOWER *****************************************/
283 * 4965 txpower calculations rely on information from three sources:
286 * 2) "initialize" alive notification
287 * 3) stats notifications
289 * EEPROM data consists of:
291 * 1) Regulatory information (max txpower and channel usage flags) is provided
292 * separately for each channel that can possibly supported by 4965.
293 * 40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
296 * See struct il4965_eeprom_channel for format, and struct il4965_eeprom
297 * for locations in EEPROM.
299 * 2) Factory txpower calibration information is provided separately for
300 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
301 * but 5 GHz has several sub-bands.
303 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
305 * See struct il4965_eeprom_calib_info (and the tree of structures
306 * contained within it) for format, and struct il4965_eeprom for
307 * locations in EEPROM.
309 * "Initialization alive" notification (see struct il4965_init_alive_resp)
312 * 1) Temperature calculation parameters.
314 * 2) Power supply voltage measurement.
316 * 3) Tx gain compensation to balance 2 transmitters for MIMO use.
318 * Statistics notifications deliver:
320 * 1) Current values for temperature param R4.
324 * To calculate a txpower setting for a given desired target txpower, channel,
325 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
326 * support MIMO and transmit diversity), driver must do the following:
328 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
329 * Do not exceed regulatory limit; reduce target txpower if necessary.
331 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
332 * 2 transmitters will be used simultaneously; driver must reduce the
333 * regulatory limit by 3 dB (half-power) for each transmitter, so the
334 * combined total output of the 2 transmitters is within regulatory limits.
337 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by
338 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
339 * reduce target txpower if necessary.
341 * Backoff values below are in 1/2 dB units (equivalent to steps in
342 * txpower gain tables):
344 * OFDM 6 - 36 MBit: 10 steps (5 dB)
345 * OFDM 48 MBit: 15 steps (7.5 dB)
346 * OFDM 54 MBit: 17 steps (8.5 dB)
347 * OFDM 60 MBit: 20 steps (10 dB)
348 * CCK all rates: 10 steps (5 dB)
350 * Backoff values apply to saturation txpower on a per-transmitter basis;
351 * when using MIMO (2 transmitters), each transmitter uses the same
352 * saturation level provided in EEPROM, and the same backoff values;
353 * no reduction (such as with regulatory txpower limits) is required.
355 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
356 * widths and 40 Mhz (.11n HT40) channel widths; there is no separate
357 * factory measurement for ht40 channels.
359 * The result of this step is the final target txpower. The rest of
360 * the steps figure out the proper settings for the device to achieve
361 * that target txpower.
364 * 3) Determine (EEPROM) calibration sub band for the target channel, by
365 * comparing against first and last channels in each sub band
366 * (see struct il4965_eeprom_calib_subband_info).
369 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets,
370 * referencing the 2 factory-measured (sample) channels within the sub band.
372 * Interpolation is based on difference between target channel's frequency
373 * and the sample channels' frequencies. Since channel numbers are based
374 * on frequency (5 MHz between each channel number), this is equivalent
375 * to interpolating based on channel number differences.
377 * Note that the sample channels may or may not be the channels at the
378 * edges of the sub band. The target channel may be "outside" of the
379 * span of the sampled channels.
381 * Driver may choose the pair (for 2 Tx chains) of measurements (see
382 * struct il4965_eeprom_calib_ch_info) for which the actual measured
383 * txpower comes closest to the desired txpower. Usually, though,
384 * the middle set of measurements is closest to the regulatory limits,
385 * and is therefore a good choice for all txpower calculations (this
386 * assumes that high accuracy is needed for maximizing legal txpower,
387 * while lower txpower configurations do not need as much accuracy).
389 * Driver should interpolate both members of the chosen measurement pair,
390 * i.e. for both Tx chains (radio transmitters), unless the driver knows
391 * that only one of the chains will be used (e.g. only one tx antenna
392 * connected, but this should be unusual). The rate scaling algorithm
393 * switches antennas to find best performance, so both Tx chains will
394 * be used (although only one at a time) even for non-MIMO transmissions.
396 * Driver should interpolate factory values for temperature, gain table
397 * idx, and actual power. The power amplifier detector values are
398 * not used by the driver.
400 * Sanity check: If the target channel happens to be one of the sample
401 * channels, the results should agree with the sample channel's
405 * 5) Find difference between desired txpower and (interpolated)
406 * factory-measured txpower. Using (interpolated) factory gain table idx
407 * (shown elsewhere) as a starting point, adjust this idx lower to
408 * increase txpower, or higher to decrease txpower, until the target
409 * txpower is reached. Each step in the gain table is 1/2 dB.
411 * For example, if factory measured txpower is 16 dBm, and target txpower
412 * is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
416 * 6) Find difference between current device temperature and (interpolated)
417 * factory-measured temperature for sub-band. Factory values are in
418 * degrees Celsius. To calculate current temperature, see comments for
419 * "4965 temperature calculation".
421 * If current temperature is higher than factory temperature, driver must
422 * increase gain (lower gain table idx), and vice verse.
424 * Temperature affects gain differently for different channels:
426 * 2.4 GHz all channels: 3.5 degrees per half-dB step
427 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
428 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
430 * NOTE: Temperature can increase rapidly when transmitting, especially
431 * with heavy traffic at high txpowers. Driver should update
432 * temperature calculations often under these conditions to
433 * maintain strong txpower in the face of rising temperature.
436 * 7) Find difference between current power supply voltage indicator
437 * (from "initialize alive") and factory-measured power supply voltage
438 * indicator (EEPROM).
440 * If the current voltage is higher (indicator is lower) than factory
441 * voltage, gain should be reduced (gain table idx increased) by:
443 * (eeprom - current) / 7
445 * If the current voltage is lower (indicator is higher) than factory
446 * voltage, gain should be increased (gain table idx decreased) by:
448 * 2 * (current - eeprom) / 7
450 * If number of idx steps in either direction turns out to be > 2,
451 * something is wrong ... just use 0.
453 * NOTE: Voltage compensation is independent of band/channel.
455 * NOTE: "Initialize" uCode measures current voltage, which is assumed
456 * to be constant after this initial measurement. Voltage
457 * compensation for txpower (number of steps in gain table)
458 * may be calculated once and used until the next uCode bootload.
461 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
462 * adjust txpower for each transmitter chain, so txpower is balanced
463 * between the two chains. There are 5 pairs of tx_atten[group][chain]
464 * values in "initialize alive", one pair for each of 5 channel ranges:
466 * Group 0: 5 GHz channel 34-43
467 * Group 1: 5 GHz channel 44-70
468 * Group 2: 5 GHz channel 71-124
469 * Group 3: 5 GHz channel 125-200
470 * Group 4: 2.4 GHz all channels
472 * Add the tx_atten[group][chain] value to the idx for the target chain.
473 * The values are signed, but are in pairs of 0 and a non-negative number,
474 * so as to reduce gain (if necessary) of the "hotter" channel. This
475 * avoids any need to double-check for regulatory compliance after
479 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation
482 * Hardware rev B: 9 steps (4.5 dB)
483 * Hardware rev C: 5 steps (2.5 dB)
485 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
486 * bits [3:2], 1 = B, 2 = C.
488 * NOTE: This compensation is in addition to any saturation backoff that
489 * might have been applied in an earlier step.
492 * 10) Select the gain table, based on band (2.4 vs 5 GHz).
494 * Limit the adjusted idx to stay within the table!
497 * 11) Read gain table entries for DSP and radio gain, place into appropriate
498 * location(s) in command (struct il4965_txpowertable_cmd).
502 * When MIMO is used (2 transmitters operating simultaneously), driver should
503 * limit each transmitter to deliver a max of 3 dB below the regulatory limit
504 * for the device. That is, use half power for each transmitter, so total
505 * txpower is within regulatory limits.
507 * The value "6" represents number of steps in gain table to reduce power 3 dB.
508 * Each step is 1/2 dB.
510 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
513 * CCK gain compensation.
515 * When calculating txpowers for CCK, after making sure that the target power
516 * is within regulatory and saturation limits, driver must additionally
517 * back off gain by adding these values to the gain table idx.
519 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
520 * bits [3:2], 1 = B, 2 = C.
522 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
523 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
526 * 4965 power supply voltage compensation for txpower
528 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
533 * The following tables contain pair of values for setting txpower, i.e.
534 * gain settings for the output of the device's digital signal processor (DSP),
535 * and for the analog gain structure of the transmitter.
537 * Each entry in the gain tables represents a step of 1/2 dB. Note that these
538 * are *relative* steps, not indications of absolute output power. Output
539 * power varies with temperature, voltage, and channel frequency, and also
540 * requires consideration of average power (to satisfy regulatory constraints),
541 * and peak power (to avoid distortion of the output signal).
543 * Each entry contains two values:
544 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
545 * linear value that multiplies the output of the digital signal processor,
546 * before being sent to the analog radio.
547 * 2) Radio gain. This sets the analog gain of the radio Tx path.
548 * It is a coarser setting, and behaves in a logarithmic (dB) fashion.
550 * EEPROM contains factory calibration data for txpower. This maps actual
551 * measured txpower levels to gain settings in the "well known" tables
552 * below ("well-known" means here that both factory calibration *and* the
553 * driver work with the same table).
555 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table
556 * has an extension (into negative idxes), in case the driver needs to
557 * boost power setting for high device temperatures (higher than would be
558 * present during factory calibration). A 5 Ghz EEPROM idx of "40"
559 * corresponds to the 49th entry in the table used by the driver.
561 #define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */
562 #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
567 * Index Dsp gain Radio gain
568 * 0 110 0x3f (highest gain)
672 * Index Dsp gain Radio gain
673 * -9 123 0x3F (highest gain)
784 * Sanity checks and default values for EEPROM regulatory levels.
785 * If EEPROM values fall outside MIN/MAX range, use default values.
787 * Regulatory limits refer to the maximum average txpower allowed by
788 * regulatory agencies in the geographies in which the device is meant
789 * to be operated. These limits are SKU-specific (i.e. geography-specific),
790 * and channel-specific; each channel has an individual regulatory limit
791 * listed in the EEPROM.
793 * Units are in half-dBm (i.e. "34" means 17 dBm).
795 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
796 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
797 #define IL_TX_POWER_REGULATORY_MIN (0)
798 #define IL_TX_POWER_REGULATORY_MAX (34)
801 * Sanity checks and default values for EEPROM saturation levels.
802 * If EEPROM values fall outside MIN/MAX range, use default values.
804 * Saturation is the highest level that the output power amplifier can produce
805 * without significant clipping distortion. This is a "peak" power level.
806 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
807 * require differing amounts of backoff, relative to their average power output,
808 * in order to avoid clipping distortion.
810 * Driver must make sure that it is violating neither the saturation limit,
811 * nor the regulatory limit, when calculating Tx power settings for various
814 * Units are in half-dBm (i.e. "38" means 19 dBm).
816 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
817 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
818 #define IL_TX_POWER_SATURATION_MIN (20)
819 #define IL_TX_POWER_SATURATION_MAX (50)
822 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
823 * and thermal Txpower calibration.
825 * When calculating txpower, driver must compensate for current device
826 * temperature; higher temperature requires higher gain. Driver must calculate
827 * current temperature (see "4965 temperature calculation"), then compare vs.
828 * factory calibration temperature in EEPROM; if current temperature is higher
829 * than factory temperature, driver must *increase* gain by proportions shown
830 * in table below. If current temperature is lower than factory, driver must
833 * Different frequency ranges require different compensation, as shown below.
835 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
836 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
837 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
839 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
840 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
841 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
843 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
844 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
845 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
847 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
848 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
849 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
851 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
852 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
853 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
856 CALIB_CH_GROUP_1 = 0,
857 CALIB_CH_GROUP_2 = 1,
858 CALIB_CH_GROUP_3 = 2,
859 CALIB_CH_GROUP_4 = 3,
860 CALIB_CH_GROUP_5 = 4,
864 /********************* END TXPOWER *****************************************/
869 * Most communication between driver and 4965 is via queues of data buffers.
870 * For example, all commands that the driver issues to device's embedded
871 * controller (uCode) are via the command queue (one of the Tx queues). All
872 * uCode command responses/replies/notifications, including Rx frames, are
873 * conveyed from uCode to driver via the Rx queue.
875 * Most support for these queues, including handshake support, resides in
876 * structures in host DRAM, shared between the driver and the device. When
877 * allocating this memory, the driver must make sure that data written by
878 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
879 * cache memory), so DRAM and cache are consistent, and the device can
880 * immediately see changes made by the driver.
882 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
883 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
884 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
886 #define IL49_NUM_FIFOS 7
887 #define IL49_CMD_FIFO_NUM 4
888 #define IL49_NUM_QUEUES 16
889 #define IL49_NUM_AMPDU_QUEUES 8
892 * struct il4965_schedq_bc_tbl
896 * Each Tx queue uses a byte-count table containing 320 entries:
897 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
898 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
899 * max Tx win is 64 TFDs).
901 * When driver sets up a new TFD, it must also enter the total byte count
902 * of the frame to be transmitted into the corresponding entry in the byte
903 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
904 * must duplicate the byte count entry in corresponding idx 256-319.
906 * padding puts each byte count table on a 1024-byte boundary;
907 * 4965 assumes tables are separated by 1024 bytes.
909 struct il4965_scd_bc_tbl {
910 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
911 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
914 #define IL4965_RTC_INST_LOWER_BOUND (0x000000)
917 #define IL4965_RSSI_OFFSET 44
920 #define PCI_CFG_RETRY_TIMEOUT 0x041
922 /* PCI register values */
923 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
924 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
926 #define IL4965_DEFAULT_TX_RETRY 15
929 #define IL4965_FIRST_AMPDU_QUEUE 10
932 void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
933 void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
934 void il4965_init_sensitivity(struct il_priv *il);
935 void il4965_reset_run_time_calib(struct il_priv *il);
936 void il4965_calib_free_results(struct il_priv *il);
939 #ifdef CONFIG_IWLEGACY_DEBUGFS
940 ssize_t il4965_ucode_rx_stats_read(struct file *file, char __user *user_buf,
941 size_t count, loff_t *ppos);
942 ssize_t il4965_ucode_tx_stats_read(struct file *file, char __user *user_buf,
943 size_t count, loff_t *ppos);
944 ssize_t il4965_ucode_general_stats_read(struct file *file,
945 char __user *user_buf, size_t count,
949 /****************************/
950 /* Flow Handler Definitions */
951 /****************************/
954 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
955 * Addresses are offsets from device's PCI hardware base address.
957 #define FH49_MEM_LOWER_BOUND (0x1000)
958 #define FH49_MEM_UPPER_BOUND (0x2000)
961 * Keep-Warm (KW) buffer base address.
963 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
964 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
965 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
966 * from going into a power-savings mode that would cause higher DRAM latency,
967 * and possible data over/under-runs, before all Tx/Rx is complete.
969 * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
970 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
971 * automatically invokes keep-warm accesses when normal accesses might not
972 * be sufficient to maintain fast DRAM response.
975 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
977 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
980 * TFD Circular Buffers Base (CBBC) addresses
982 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
983 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
984 * (see struct il_tfd_frame). These 16 pointer registers are offset by 0x04
985 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
986 * aligned (address bits 0-7 must be 0).
988 * Bit fields in each pointer register:
989 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
991 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
992 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
994 /* Find TFD CB base pointer for given queue (range 0-15). */
995 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
998 * Rx SRAM Control and Status Registers (RSCSR)
1000 * These registers provide handshake between driver and 4965 for the Rx queue
1001 * (this queue handles *all* command responses, notifications, Rx data, etc.
1002 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
1003 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1004 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1005 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1006 * mapping between RBDs and RBs.
1008 * Driver must allocate host DRAM memory for the following, and set the
1009 * physical address of each into 4965 registers:
1011 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1012 * entries (although any power of 2, up to 4096, is selectable by driver).
1013 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1014 * (typically 4K, although 8K or 16K are also selectable by driver).
1015 * Driver sets up RB size and number of RBDs in the CB via Rx config
1016 * register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
1018 * Bit fields within one RBD:
1019 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1021 * Driver sets physical address [35:8] of base of RBD circular buffer
1022 * into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1024 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1025 * (RBs) have been filled, via a "write pointer", actually the idx of
1026 * the RB's corresponding RBD within the circular buffer. Driver sets
1027 * physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1029 * Bit fields in lower dword of Rx status buffer (upper dword not used
1030 * by driver; see struct il4965_shared, val0):
1031 * 31-12: Not used by driver
1032 * 11- 0: Index of last filled Rx buffer descriptor
1033 * (4965 writes, driver reads this value)
1035 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1036 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1037 * and update the 4965's "write" idx register,
1038 * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1040 * This "write" idx corresponds to the *next* RBD that the driver will make
1041 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1042 * the circular buffer. This value should initially be 0 (before preparing any
1043 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1044 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1045 * "read" idx has advanced past 1! See below).
1046 * NOTE: 4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1048 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1049 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1050 * to tell the driver the idx of the latest filled RBD. The driver must
1051 * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1053 * The driver must also internally keep track of a third idx, which is the
1054 * next RBD to process. When receiving an Rx interrupt, driver should process
1055 * all filled but unprocessed RBs up to, but not including, the RB
1056 * corresponding to the "read" idx. For example, if "read" idx becomes "1",
1057 * driver may process the RB pointed to by RBD 0. Depending on volume of
1058 * traffic, there may be many RBs to process.
1060 * If read idx == write idx, 4965 thinks there is no room to put new data.
1061 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1062 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1063 * and "read" idxes; that is, make sure that there are no more than 254
1064 * buffers waiting to be filled.
1066 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1067 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1068 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1071 * Physical base address of 8-byte Rx Status buffer.
1073 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1075 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1078 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1080 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1082 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1085 * Rx write pointer (idx, really!).
1087 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1088 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1090 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1091 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1094 * Rx Config/Status Registers (RCSR)
1095 * Rx Config Reg for channel 0 (only channel used)
1097 * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1098 * normal operation (see bit fields).
1100 * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1101 * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG for
1102 * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1105 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1106 * '10' operate normally
1108 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1109 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1111 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1112 * '10' 12K, '11' 16K.
1114 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1115 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1116 * typical value 0x10 (about 1/2 msec)
1119 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1120 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1121 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1123 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1125 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1126 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1127 #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1128 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1129 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1130 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */
1132 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1133 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1134 #define RX_RB_TIMEOUT (0x10)
1136 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1137 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1138 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1140 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1141 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1142 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1143 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1145 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1146 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1147 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1150 * Rx Shared Status Registers (RSSR)
1152 * After stopping Rx DMA channel (writing 0 to
1153 * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1154 * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1157 * 24: 1 = Channel 0 is idle
1159 * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1160 * contain default values that should not be altered by the driver.
1162 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1163 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1165 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1166 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1167 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1168 (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1170 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1172 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1174 /* TFDB Area - TFDs buffer table */
1175 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1176 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1177 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1178 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1179 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1182 * Transmit DMA Channel Control/Status Registers (TCSR)
1184 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1185 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1186 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1188 * To use a Tx DMA channel, driver must initialize its
1189 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1191 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1192 * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1194 * All other bits should be 0.
1197 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1198 * '10' operate normally
1199 * 29- 4: Reserved, set to "0"
1200 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1201 * 2- 0: Reserved, set to "0"
1203 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1204 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1206 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1207 #define FH49_TCSR_CHNL_NUM (7)
1208 #define FH50_TCSR_CHNL_NUM (8)
1210 /* TCSR: tx_config register values */
1211 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1212 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1213 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1214 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1215 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1216 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1218 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1219 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1221 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1222 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1224 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1225 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1226 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1228 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1229 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1230 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1232 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1233 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1234 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1236 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1237 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1238 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1240 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1241 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1244 * Tx Shared Status Registers (TSSR)
1246 * After stopping Tx DMA channel (writing 0 to
1247 * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1248 * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1249 * (channel's buffers empty | no pending requests).
1252 * 31-24: 1 = Channel buffers empty (channel 7:0)
1253 * 23-16: 1 = No pending requests (channel 7:0)
1255 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1256 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1258 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1261 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1262 * 31: Indicates an address error when accessed to internal memory
1263 * uCode/driver must write "1" in order to clear this flag
1264 * 30: Indicates that Host did not send the expected number of dwords to FH
1265 * uCode/driver must write "1" in order to clear this flag
1266 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1267 * command was received from the scheduler while the TRB was already full
1268 * with previous command
1269 * uCode/driver must write "1" in order to clear this flag
1270 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1271 * bit is set, it indicates that the FH has received a full indication
1272 * from the RTC TxFIFO and the current value of the TxCredit counter was
1273 * not equal to zero. This mean that the credit mechanism was not
1274 * synchronized to the TxFIFO status
1275 * uCode/driver must write "1" in order to clear this flag
1277 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1279 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1281 /* Tx service channels */
1282 #define FH49_SRVC_CHNL (9)
1283 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1284 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1285 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1286 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1288 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1289 /* Instruct FH to increment the retry count of a packet when
1290 * it is brought from the memory to TX-FIFO
1292 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1294 /* Keep Warm Size */
1295 #define IL_KW_SIZE 0x1000 /* 4k */
1297 #endif /* __il_4965_h__ */