drivers/net/wireless/iwlegacy/iwl-io.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  19  *
  20  * The full GNU General Public License is included in this distribution in the
  21  * file called LICENSE.
  22  *
  23  * Contact Information:
  24  *  Intel Linux Wireless <ilw@linux.intel.com>
  25  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26  *
  27  *****************************************************************************/
  28
  29 #ifndef __il_io_h__
  30 #define __il_io_h__
  31
  32 #include <linux/io.h>
  33
  34 #include "iwl-dev.h"
  35 #include "iwl-debug.h"
  36
  37 static inline void _il_write8(struct il_priv *il, u32 ofs, u8 val)
  38 {
  39         iowrite8(val, il->hw_base + ofs);
  40 }
  41 #define il_write8(il, ofs, val) _il_write8(il, ofs, val)
  42
  43 static inline void _il_wr(struct il_priv *il, u32 ofs, u32 val)
  44 {
  45         iowrite32(val, il->hw_base + ofs);
  46 }
  47
  48 static inline u32 _il_rd(struct il_priv *il, u32 ofs)
  49 {
  50         return ioread32(il->hw_base + ofs);
  51 }
  52
  53 #define IL_POLL_INTERVAL 10     /* microseconds */
  54 static inline int
  55 _il_poll_bit(struct il_priv *il, u32 addr,
  56                                 u32 bits, u32 mask, int timeout)
  57 {
  58         int t = 0;
  59
  60         do {
  61                 if ((_il_rd(il, addr) & mask) == (bits & mask))
  62                         return t;
  63                 udelay(IL_POLL_INTERVAL);
  64                 t += IL_POLL_INTERVAL;
  65         } while (t < timeout);
  66
  67         return -ETIMEDOUT;
  68 }
  69
  70 static inline void _il_set_bit(struct il_priv *il, u32 reg, u32 mask)
  71 {
  72         _il_wr(il, reg, _il_rd(il, reg) | mask);
  73 }
  74
  75 static inline void il_set_bit(struct il_priv *p, u32 r, u32 m)
  76 {
  77         unsigned long reg_flags;
  78
  79         spin_lock_irqsave(&p->reg_lock, reg_flags);
  80         _il_set_bit(p, r, m);
  81         spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  82 }
  83
  84 static inline void
  85 _il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
  86 {
  87         _il_wr(il, reg, _il_rd(il, reg) & ~mask);
  88 }
  89
  90 static inline void il_clear_bit(struct il_priv *p, u32 r, u32 m)
  91 {
  92         unsigned long reg_flags;
  93
  94         spin_lock_irqsave(&p->reg_lock, reg_flags);
  95         _il_clear_bit(p, r, m);
  96         spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  97 }
  98
  99 static inline int _il_grab_nic_access(struct il_priv *il)
 100 {
 101         int ret;
 102         u32 val;
 103
 104         /* this bit wakes up the NIC */
 105         _il_set_bit(il, CSR_GP_CNTRL,
 106                                 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 107
 108         /*
 109          * These bits say the device is running, and should keep running for
 110          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 111          * but they do not indicate that embedded SRAM is restored yet;
 112          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 113          * to/from host DRAM when sleeping/waking for power-saving.
 114          * Each direction takes approximately 1/4 millisecond; with this
 115          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 116          * series of register accesses are expected (e.g. reading Event Log),
 117          * to keep device from sleeping.
 118          *
 119          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 120          * SRAM is okay/restored.  We don't check that here because this call
 121          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 122          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 123          *
 124          */
 125         ret = _il_poll_bit(il, CSR_GP_CNTRL,
 126                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 127                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 128                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 129         if (ret < 0) {
 130                 val = _il_rd(il, CSR_GP_CNTRL);
 131                 IL_ERR(
 132                         "MAC is in deep sleep!.  CSR_GP_CNTRL = 0x%08X\n", val);
 133                 _il_wr(il, CSR_RESET,
 134                                 CSR_RESET_REG_FLAG_FORCE_NMI);
 135                 return -EIO;
 136         }
 137
 138         return 0;
 139 }
 140
 141 static inline void _il_release_nic_access(struct il_priv *il)
 142 {
 143         _il_clear_bit(il, CSR_GP_CNTRL,
 144                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 145 }
 146
 147 static inline u32 il_rd(struct il_priv *il, u32 reg)
 148 {
 149         u32 value;
 150         unsigned long reg_flags;
 151
 152         spin_lock_irqsave(&il->reg_lock, reg_flags);
 153         _il_grab_nic_access(il);
 154         value = _il_rd(il, reg);
 155         _il_release_nic_access(il);
 156         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 157         return value;
 158
 159 }
 160
 161 static inline void
 162 il_wr(struct il_priv *il, u32 reg, u32 value)
 163 {
 164         unsigned long reg_flags;
 165
 166         spin_lock_irqsave(&il->reg_lock, reg_flags);
 167         if (!_il_grab_nic_access(il)) {
 168                 _il_wr(il, reg, value);
 169                 _il_release_nic_access(il);
 170         }
 171         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 172 }
 173
 174 static inline void il_write_reg_buf(struct il_priv *il,
 175                                                u32 reg, u32 len, u32 *values)
 176 {
 177         u32 count = sizeof(u32);
 178
 179         if (il != NULL && values != NULL) {
 180                 for (; 0 < len; len -= count, reg += count, values++)
 181                         il_wr(il, reg, *values);
 182         }
 183 }
 184
 185 static inline int il_poll_bit(struct il_priv *il, u32 addr,
 186                                        u32 mask, int timeout)
 187 {
 188         int t = 0;
 189
 190         do {
 191                 if ((il_rd(il, addr) & mask) == mask)
 192                         return t;
 193                 udelay(IL_POLL_INTERVAL);
 194                 t += IL_POLL_INTERVAL;
 195         } while (t < timeout);
 196
 197         return -ETIMEDOUT;
 198 }
 199
 200 static inline u32 _il_rd_prph(struct il_priv *il, u32 reg)
 201 {
 202         _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
 203         rmb();
 204         return _il_rd(il, HBUS_TARG_PRPH_RDAT);
 205 }
 206
 207 static inline u32 il_rd_prph(struct il_priv *il, u32 reg)
 208 {
 209         unsigned long reg_flags;
 210         u32 val;
 211
 212         spin_lock_irqsave(&il->reg_lock, reg_flags);
 213         _il_grab_nic_access(il);
 214         val = _il_rd_prph(il, reg);
 215         _il_release_nic_access(il);
 216         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 217         return val;
 218 }
 219
 220 static inline void _il_wr_prph(struct il_priv *il,
 221                                              u32 addr, u32 val)
 222 {
 223         _il_wr(il, HBUS_TARG_PRPH_WADDR,
 224                               ((addr & 0x0000FFFF) | (3 << 24)));
 225         wmb();
 226         _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
 227 }
 228
 229 static inline void
 230 il_wr_prph(struct il_priv *il, u32 addr, u32 val)
 231 {
 232         unsigned long reg_flags;
 233
 234         spin_lock_irqsave(&il->reg_lock, reg_flags);
 235         if (!_il_grab_nic_access(il)) {
 236                 _il_wr_prph(il, addr, val);
 237                 _il_release_nic_access(il);
 238         }
 239         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 240 }
 241
 242 #define _il_set_bits_prph(il, reg, mask) \
 243 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask))
 244
 245 static inline void
 246 il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
 247 {
 248         unsigned long reg_flags;
 249
 250         spin_lock_irqsave(&il->reg_lock, reg_flags);
 251         _il_grab_nic_access(il);
 252         _il_set_bits_prph(il, reg, mask);
 253         _il_release_nic_access(il);
 254         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 255 }
 256
 257 #define _il_set_bits_mask_prph(il, reg, bits, mask) \
 258 _il_wr_prph(il, reg,                            \
 259                  ((_il_rd_prph(il, reg) & mask) | bits))
 260
 261 static inline void il_set_bits_mask_prph(struct il_priv *il, u32 reg,
 262                                 u32 bits, u32 mask)
 263 {
 264         unsigned long reg_flags;
 265
 266         spin_lock_irqsave(&il->reg_lock, reg_flags);
 267         _il_grab_nic_access(il);
 268         _il_set_bits_mask_prph(il, reg, bits, mask);
 269         _il_release_nic_access(il);
 270         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 271 }
 272
 273 static inline void il_clear_bits_prph(struct il_priv
 274                                                  *il, u32 reg, u32 mask)
 275 {
 276         unsigned long reg_flags;
 277         u32 val;
 278
 279         spin_lock_irqsave(&il->reg_lock, reg_flags);
 280         _il_grab_nic_access(il);
 281         val = _il_rd_prph(il, reg);
 282         _il_wr_prph(il, reg, (val & ~mask));
 283         _il_release_nic_access(il);
 284         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 285 }
 286
 287 static inline u32 il_read_targ_mem(struct il_priv *il, u32 addr)
 288 {
 289         unsigned long reg_flags;
 290         u32 value;
 291
 292         spin_lock_irqsave(&il->reg_lock, reg_flags);
 293         _il_grab_nic_access(il);
 294
 295         _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
 296         rmb();
 297         value = _il_rd(il, HBUS_TARG_MEM_RDAT);
 298
 299         _il_release_nic_access(il);
 300         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 301         return value;
 302 }
 303
 304 static inline void
 305 il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
 306 {
 307         unsigned long reg_flags;
 308
 309         spin_lock_irqsave(&il->reg_lock, reg_flags);
 310         if (!_il_grab_nic_access(il)) {
 311                 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
 312                 wmb();
 313                 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
 314                 _il_release_nic_access(il);
 315         }
 316         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 317 }
 318
 319 static inline void
 320 il_write_targ_mem_buf(struct il_priv *il, u32 addr,
 321                                           u32 len, u32 *values)
 322 {
 323         unsigned long reg_flags;
 324
 325         spin_lock_irqsave(&il->reg_lock, reg_flags);
 326         if (!_il_grab_nic_access(il)) {
 327                 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
 328                 wmb();
 329                 for (; 0 < len; len -= sizeof(u32), values++)
 330                         _il_wr(il,
 331                                         HBUS_TARG_MEM_WDAT, *values);
 332
 333                 _il_release_nic_access(il);
 334         }
 335         spin_unlock_irqrestore(&il->reg_lock, reg_flags);
 336 }
 337 #endif