1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/delay.h>
34 #include <linux/sched.h>
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/wireless.h>
38 #include <linux/firmware.h>
39 #include <linux/etherdevice.h>
40 #include <asm/unaligned.h>
41 #include <net/mac80211.h>
44 #include "iwl-3945-fh.h"
45 #include "iwl-commands.h"
48 #include "iwl-eeprom.h"
50 #include "iwl-helpers.h"
52 #include "iwl-3945-led.h"
53 #include "iwl-3945-debugfs.h"
55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
90 /* 1 = enable the iwl3945_disable_events() function */
91 #define IWL_EVT_DISABLE (0)
92 #define IWL_EVT_DISABLE_SIZE (1532/32)
95 * iwl3945_disable_events - Disable selected events in uCode event log
97 * Disable an event by writing "1"s into "disable"
98 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
99 * Default values of 0 enable uCode events to be logged.
100 * Use for only special debugging. This function is just a placeholder as-is,
101 * you'll need to provide the special bits! ...
102 * ... and set IWL_EVT_DISABLE to 1. */
103 void iwl3945_disable_events(struct iwl_priv *priv)
106 u32 base; /* SRAM address of event log header */
107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
108 u32 array_size; /* # of u32 entries in array */
109 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
110 0x00000000, /* 31 - 0 Event id numbers */
111 0x00000000, /* 63 - 32 */
112 0x00000000, /* 95 - 64 */
113 0x00000000, /* 127 - 96 */
114 0x00000000, /* 159 - 128 */
115 0x00000000, /* 191 - 160 */
116 0x00000000, /* 223 - 192 */
117 0x00000000, /* 255 - 224 */
118 0x00000000, /* 287 - 256 */
119 0x00000000, /* 319 - 288 */
120 0x00000000, /* 351 - 320 */
121 0x00000000, /* 383 - 352 */
122 0x00000000, /* 415 - 384 */
123 0x00000000, /* 447 - 416 */
124 0x00000000, /* 479 - 448 */
125 0x00000000, /* 511 - 480 */
126 0x00000000, /* 543 - 512 */
127 0x00000000, /* 575 - 544 */
128 0x00000000, /* 607 - 576 */
129 0x00000000, /* 639 - 608 */
130 0x00000000, /* 671 - 640 */
131 0x00000000, /* 703 - 672 */
132 0x00000000, /* 735 - 704 */
133 0x00000000, /* 767 - 736 */
134 0x00000000, /* 799 - 768 */
135 0x00000000, /* 831 - 800 */
136 0x00000000, /* 863 - 832 */
137 0x00000000, /* 895 - 864 */
138 0x00000000, /* 927 - 896 */
139 0x00000000, /* 959 - 928 */
140 0x00000000, /* 991 - 960 */
141 0x00000000, /* 1023 - 992 */
142 0x00000000, /* 1055 - 1024 */
143 0x00000000, /* 1087 - 1056 */
144 0x00000000, /* 1119 - 1088 */
145 0x00000000, /* 1151 - 1120 */
146 0x00000000, /* 1183 - 1152 */
147 0x00000000, /* 1215 - 1184 */
148 0x00000000, /* 1247 - 1216 */
149 0x00000000, /* 1279 - 1248 */
150 0x00000000, /* 1311 - 1280 */
151 0x00000000, /* 1343 - 1312 */
152 0x00000000, /* 1375 - 1344 */
153 0x00000000, /* 1407 - 1376 */
154 0x00000000, /* 1439 - 1408 */
155 0x00000000, /* 1471 - 1440 */
156 0x00000000, /* 1503 - 1472 */
159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
160 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
161 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
169 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
172 iwl_write_targ_mem(priv,
173 disable_ptr + (i * sizeof(u32)),
177 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
178 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
179 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
180 disable_ptr, array_size);
185 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
189 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
190 if (iwl3945_rates[idx].plcp == plcp)
195 #ifdef CONFIG_IWLWIFI_DEBUG
196 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
198 static const char *iwl3945_get_tx_fail_reason(u32 status)
200 switch (status & TX_STATUS_MSK) {
201 case TX_3945_STATUS_SUCCESS:
203 TX_STATUS_ENTRY(SHORT_LIMIT);
204 TX_STATUS_ENTRY(LONG_LIMIT);
205 TX_STATUS_ENTRY(FIFO_UNDERRUN);
206 TX_STATUS_ENTRY(MGMNT_ABORT);
207 TX_STATUS_ENTRY(NEXT_FRAG);
208 TX_STATUS_ENTRY(LIFE_EXPIRE);
209 TX_STATUS_ENTRY(DEST_PS);
210 TX_STATUS_ENTRY(ABORTED);
211 TX_STATUS_ENTRY(BT_RETRY);
212 TX_STATUS_ENTRY(STA_INVALID);
213 TX_STATUS_ENTRY(FRAG_DROPPED);
214 TX_STATUS_ENTRY(TID_DISABLE);
215 TX_STATUS_ENTRY(FRAME_FLUSHED);
216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
217 TX_STATUS_ENTRY(TX_LOCKED);
218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
224 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
231 * get ieee prev rate from rate scale table.
232 * for A and B mode we need to overright prev
235 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
237 int next_rate = iwl3945_get_prev_ieee_rate(rate);
239 switch (priv->band) {
240 case IEEE80211_BAND_5GHZ:
241 if (rate == IWL_RATE_12M_INDEX)
242 next_rate = IWL_RATE_9M_INDEX;
243 else if (rate == IWL_RATE_6M_INDEX)
244 next_rate = IWL_RATE_6M_INDEX;
246 case IEEE80211_BAND_2GHZ:
247 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
248 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
249 if (rate == IWL_RATE_11M_INDEX)
250 next_rate = IWL_RATE_5M_INDEX;
263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
265 * When FW advances 'R' index, all entries between old and new 'R' index
266 * need to be reclaimed. As result, some free space forms. If there is
267 * enough free space (> low mark), wake the stack that feeds us.
269 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
270 int txq_id, int index)
272 struct iwl_tx_queue *txq = &priv->txq[txq_id];
273 struct iwl_queue *q = &txq->q;
274 struct iwl_tx_info *tx_info;
276 BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
278 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
281 tx_info = &txq->txb[txq->q.read_ptr];
282 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
284 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
288 (txq_id != IWL39_CMD_QUEUE_NUM) &&
289 priv->mac80211_registered)
290 iwl_wake_queue(priv, txq_id);
294 * iwl3945_rx_reply_tx - Handle Tx response
296 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
297 struct iwl_rx_mem_buffer *rxb)
299 struct iwl_rx_packet *pkt = rxb_addr(rxb);
300 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
301 int txq_id = SEQ_TO_QUEUE(sequence);
302 int index = SEQ_TO_INDEX(sequence);
303 struct iwl_tx_queue *txq = &priv->txq[txq_id];
304 struct ieee80211_tx_info *info;
305 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
306 u32 status = le32_to_cpu(tx_resp->status);
310 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
312 "is out of range [0-%d] %d %d\n", txq_id,
313 index, txq->q.n_bd, txq->q.write_ptr,
318 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
319 ieee80211_tx_info_clear_status(info);
321 /* Fill the MRR chain with some info about on-chip retransmissions */
322 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
323 if (info->band == IEEE80211_BAND_5GHZ)
324 rate_idx -= IWL_FIRST_OFDM_RATE;
326 fail = tx_resp->failure_frame;
328 info->status.rates[0].idx = rate_idx;
329 info->status.rates[0].count = fail + 1; /* add final attempt */
331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
332 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
333 IEEE80211_TX_STAT_ACK : 0;
335 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
336 txq_id, iwl3945_get_tx_fail_reason(status), status,
337 tx_resp->rate, tx_resp->failure_frame);
339 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
340 iwl3945_tx_queue_reclaim(priv, txq_id, index);
342 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
343 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
348 /*****************************************************************************
350 * Intel PRO/Wireless 3945ABG/BG Network Connection
352 * RX handler implementations
354 *****************************************************************************/
355 #ifdef CONFIG_IWLWIFI_DEBUGFS
357 * based on the assumption of all statistics counter are in DWORD
358 * FIXME: This function is for debugging, do not deal with
359 * the case of counters roll-over.
361 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
367 u32 *delta, *max_delta;
369 prev_stats = (__le32 *)&priv->_3945.statistics;
370 accum_stats = (u32 *)&priv->_3945.accum_statistics;
371 delta = (u32 *)&priv->_3945.delta_statistics;
372 max_delta = (u32 *)&priv->_3945.max_delta;
374 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
375 i += sizeof(__le32), stats++, prev_stats++, delta++,
376 max_delta++, accum_stats++) {
377 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
378 *delta = (le32_to_cpu(*stats) -
379 le32_to_cpu(*prev_stats));
380 *accum_stats += *delta;
381 if (*delta > *max_delta)
386 /* reset accumulative statistics for "no-counter" type statistics */
387 priv->_3945.accum_statistics.general.temperature =
388 priv->_3945.statistics.general.temperature;
389 priv->_3945.accum_statistics.general.ttl_timestamp =
390 priv->_3945.statistics.general.ttl_timestamp;
395 * iwl3945_good_plcp_health - checks for plcp error.
397 * When the plcp error is exceeding the thresholds, reset the radio
398 * to improve the throughput.
400 static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
401 struct iwl_rx_packet *pkt)
404 struct iwl3945_notif_statistics current_stat;
405 int combined_plcp_delta;
406 unsigned int plcp_msec;
407 unsigned long plcp_received_jiffies;
409 if (priv->cfg->plcp_delta_threshold ==
410 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
411 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
414 memcpy(¤t_stat, pkt->u.raw, sizeof(struct
415 iwl3945_notif_statistics));
417 * check for plcp_err and trigger radio reset if it exceeds
418 * the plcp error threshold plcp_delta.
420 plcp_received_jiffies = jiffies;
421 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
422 (long) priv->plcp_jiffies);
423 priv->plcp_jiffies = plcp_received_jiffies;
425 * check to make sure plcp_msec is not 0 to prevent division
429 combined_plcp_delta =
430 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
431 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
433 if ((combined_plcp_delta > 0) &&
434 ((combined_plcp_delta * 100) / plcp_msec) >
435 priv->cfg->plcp_delta_threshold) {
437 * if plcp_err exceed the threshold, the following
438 * data is printed in csv format:
439 * Text: plcp_err exceeded %d,
440 * Received ofdm.plcp_err,
441 * Current ofdm.plcp_err,
442 * combined_plcp_delta,
445 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
446 "%u, %d, %u mSecs\n",
447 priv->cfg->plcp_delta_threshold,
448 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
449 combined_plcp_delta, plcp_msec);
451 * Reset the RF radio due to the high plcp
460 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
461 struct iwl_rx_mem_buffer *rxb)
463 struct iwl_rx_packet *pkt = rxb_addr(rxb);
465 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
466 (int)sizeof(struct iwl3945_notif_statistics),
467 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
468 #ifdef CONFIG_IWLWIFI_DEBUGFS
469 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
471 iwl_recover_from_statistics(priv, pkt);
473 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
476 void iwl3945_reply_statistics(struct iwl_priv *priv,
477 struct iwl_rx_mem_buffer *rxb)
479 struct iwl_rx_packet *pkt = rxb_addr(rxb);
480 __le32 *flag = (__le32 *)&pkt->u.raw;
482 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
483 #ifdef CONFIG_IWLWIFI_DEBUGFS
484 memset(&priv->_3945.accum_statistics, 0,
485 sizeof(struct iwl3945_notif_statistics));
486 memset(&priv->_3945.delta_statistics, 0,
487 sizeof(struct iwl3945_notif_statistics));
488 memset(&priv->_3945.max_delta, 0,
489 sizeof(struct iwl3945_notif_statistics));
491 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
493 iwl3945_hw_rx_statistics(priv, rxb);
497 /******************************************************************************
499 * Misc. internal state and helper functions
501 ******************************************************************************/
503 /* This is necessary only for a number of statistics, see the caller. */
504 static int iwl3945_is_network_packet(struct iwl_priv *priv,
505 struct ieee80211_hdr *header)
507 /* Filter incoming packets to determine if they are targeted toward
508 * this network, discarding packets coming from ourselves */
509 switch (priv->iw_mode) {
510 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
511 /* packets to our IBSS update information */
512 return !compare_ether_addr(header->addr3, priv->bssid);
513 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
514 /* packets to our IBSS update information */
515 return !compare_ether_addr(header->addr2, priv->bssid);
521 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
522 struct iwl_rx_mem_buffer *rxb,
523 struct ieee80211_rx_status *stats)
525 struct iwl_rx_packet *pkt = rxb_addr(rxb);
526 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
527 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
528 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
529 u16 len = le16_to_cpu(rx_hdr->len);
531 __le16 fc = hdr->frame_control;
533 /* We received data from the HW, so stop the watchdog */
534 if (unlikely(len + IWL39_RX_FRAME_SIZE >
535 PAGE_SIZE << priv->hw_params.rx_page_order)) {
536 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
540 /* We only process data packets if the interface is open */
541 if (unlikely(!priv->is_open)) {
542 IWL_DEBUG_DROP_LIMIT(priv,
543 "Dropping packet while interface is not open.\n");
547 skb = dev_alloc_skb(128);
549 IWL_ERR(priv, "dev_alloc_skb failed\n");
553 if (!iwl3945_mod_params.sw_crypto)
554 iwl_set_decrypted_flag(priv,
555 (struct ieee80211_hdr *)rxb_addr(rxb),
556 le32_to_cpu(rx_end->status), stats);
558 skb_add_rx_frag(skb, 0, rxb->page,
559 (void *)rx_hdr->payload - (void *)pkt, len);
561 iwl_update_stats(priv, false, fc, len);
562 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
564 ieee80211_rx(priv->hw, skb);
565 priv->alloc_rxb_page--;
569 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
571 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
572 struct iwl_rx_mem_buffer *rxb)
574 struct ieee80211_hdr *header;
575 struct ieee80211_rx_status rx_status;
576 struct iwl_rx_packet *pkt = rxb_addr(rxb);
577 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
578 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
579 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
580 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
581 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
585 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
587 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
588 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
589 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
591 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
592 if (rx_status.band == IEEE80211_BAND_5GHZ)
593 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
595 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
596 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
598 /* set the preamble flag if appropriate */
599 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
600 rx_status.flag |= RX_FLAG_SHORTPRE;
602 if ((unlikely(rx_stats->phy_count > 20))) {
603 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
604 rx_stats->phy_count);
608 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
609 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
610 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
616 /* Convert 3945's rssi indicator to dBm */
617 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
619 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
620 rx_status.signal, rx_stats_sig_avg,
621 rx_stats_noise_diff);
623 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
625 network_packet = iwl3945_is_network_packet(priv, header);
627 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
628 network_packet ? '*' : ' ',
629 le16_to_cpu(rx_hdr->channel),
630 rx_status.signal, rx_status.signal,
633 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
635 if (network_packet) {
636 priv->_3945.last_beacon_time =
637 le32_to_cpu(rx_end->beacon_timestamp);
638 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
639 priv->_3945.last_rx_rssi = rx_status.signal;
642 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
645 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
646 struct iwl_tx_queue *txq,
647 dma_addr_t addr, u16 len, u8 reset, u8 pad)
651 struct iwl3945_tfd *tfd, *tfd_tmp;
654 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
655 tfd = &tfd_tmp[q->write_ptr];
658 memset(tfd, 0, sizeof(*tfd));
660 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
662 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
663 IWL_ERR(priv, "Error can not send more than %d chunks\n",
668 tfd->tbs[count].addr = cpu_to_le32(addr);
669 tfd->tbs[count].len = cpu_to_le32(len);
673 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
674 TFD_CTL_PAD_SET(pad));
680 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
682 * Does NOT advance any indexes
684 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
686 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
687 int index = txq->q.read_ptr;
688 struct iwl3945_tfd *tfd = &tfd_tmp[index];
689 struct pci_dev *dev = priv->pci_dev;
694 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
695 if (counter > NUM_TFD_CHUNKS) {
696 IWL_ERR(priv, "Too many chunks: %i\n", counter);
697 /* @todo issue fatal error, it is quite serious situation */
703 pci_unmap_single(dev,
704 dma_unmap_addr(&txq->meta[index], mapping),
705 dma_unmap_len(&txq->meta[index], len),
708 /* unmap chunks if any */
710 for (i = 1; i < counter; i++)
711 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
712 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
718 skb = txq->txb[txq->q.read_ptr].skb;
720 /* can be called from irqs-disabled context */
722 dev_kfree_skb_any(skb);
723 txq->txb[txq->q.read_ptr].skb = NULL;
729 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
732 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
733 struct iwl_device_cmd *cmd,
734 struct ieee80211_tx_info *info,
735 struct ieee80211_hdr *hdr,
736 int sta_id, int tx_id)
738 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
739 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
745 __le16 fc = hdr->frame_control;
746 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
748 rate = iwl3945_rates[rate_index].plcp;
749 tx_flags = tx_cmd->tx_flags;
751 /* We need to figure out how to get the sta->supp_rates while
752 * in this running context */
753 rate_mask = IWL_RATES_MASK;
756 /* Set retry limit on DATA packets and Probe Responses*/
757 if (ieee80211_is_probe_resp(fc))
758 data_retry_limit = 3;
760 data_retry_limit = IWL_DEFAULT_TX_RETRY;
761 tx_cmd->data_retry_limit = data_retry_limit;
763 if (tx_id >= IWL39_CMD_QUEUE_NUM)
768 if (data_retry_limit < rts_retry_limit)
769 rts_retry_limit = data_retry_limit;
770 tx_cmd->rts_retry_limit = rts_retry_limit;
773 tx_cmd->tx_flags = tx_flags;
776 tx_cmd->supp_rates[0] =
777 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
780 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
782 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
783 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
784 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
785 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
788 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
790 unsigned long flags_spin;
791 struct iwl_station_entry *station;
793 if (sta_id == IWL_INVALID_STATION)
794 return IWL_INVALID_STATION;
796 spin_lock_irqsave(&priv->sta_lock, flags_spin);
797 station = &priv->stations[sta_id];
799 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
800 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
801 station->sta.mode = STA_CONTROL_MODIFY_MSK;
802 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
803 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
805 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
810 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
812 if (src == IWL_PWR_SRC_VAUX) {
813 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
814 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
815 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
816 ~APMG_PS_CTRL_MSK_PWR_SRC);
818 iwl_poll_bit(priv, CSR_GPIO_IN,
819 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
820 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
823 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
824 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
825 ~APMG_PS_CTRL_MSK_PWR_SRC);
827 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
828 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
834 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
836 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
837 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
838 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
839 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
840 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
841 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
842 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
843 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
844 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
845 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
846 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
847 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
849 /* fake read to flush all prev I/O */
850 iwl_read_direct32(priv, FH39_RSSR_CTRL);
855 static int iwl3945_tx_reset(struct iwl_priv *priv)
859 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
862 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
864 /* all 6 fifo are active */
865 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
867 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
868 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
869 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
870 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
872 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
873 priv->_3945.shared_phys);
875 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
876 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
877 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
878 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
879 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
880 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
881 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
882 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
889 * iwl3945_txq_ctx_reset - Reset TX queue context
891 * Destroys all DMA structures and initialize them again
893 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
896 int txq_id, slots_num;
898 iwl3945_hw_txq_ctx_free(priv);
900 /* allocate tx queue structure */
901 rc = iwl_alloc_txq_mem(priv);
906 rc = iwl3945_tx_reset(priv);
911 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
912 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
913 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
914 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
917 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
925 iwl3945_hw_txq_ctx_free(priv);
931 * Start up 3945's basic functionality after it has been reset
932 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
933 * NOTE: This does not load uCode nor start the embedded processor
935 static int iwl3945_apm_init(struct iwl_priv *priv)
937 int ret = iwl_apm_init(priv);
939 /* Clear APMG (NIC's internal power management) interrupts */
940 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
941 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
943 /* Reset radio chip */
944 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
946 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
951 static void iwl3945_nic_config(struct iwl_priv *priv)
953 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
957 spin_lock_irqsave(&priv->lock, flags);
959 /* Determine HW type */
960 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
962 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
964 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
965 IWL_DEBUG_INFO(priv, "RTP type\n");
966 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
967 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
968 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
969 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
971 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
972 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
973 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
976 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
977 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
978 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
979 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
981 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
983 if ((eeprom->board_revision & 0xF0) == 0xD0) {
984 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
985 eeprom->board_revision);
986 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
987 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
989 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
990 eeprom->board_revision);
991 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
992 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
995 if (eeprom->almgor_m_version <= 1) {
996 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
997 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
998 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
999 eeprom->almgor_m_version);
1001 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1002 eeprom->almgor_m_version);
1003 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1004 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1006 spin_unlock_irqrestore(&priv->lock, flags);
1008 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1009 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1011 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1012 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1015 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1018 unsigned long flags;
1019 struct iwl_rx_queue *rxq = &priv->rxq;
1021 spin_lock_irqsave(&priv->lock, flags);
1022 priv->cfg->ops->lib->apm_ops.init(priv);
1023 spin_unlock_irqrestore(&priv->lock, flags);
1025 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1029 priv->cfg->ops->lib->apm_ops.config(priv);
1031 /* Allocate the RX queue, or reset if it is already allocated */
1033 rc = iwl_rx_queue_alloc(priv);
1035 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1039 iwl3945_rx_queue_reset(priv, rxq);
1041 iwl3945_rx_replenish(priv);
1043 iwl3945_rx_init(priv, rxq);
1046 /* Look at using this instead:
1047 rxq->need_update = 1;
1048 iwl_rx_queue_update_write_ptr(priv, rxq);
1051 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1053 rc = iwl3945_txq_ctx_reset(priv);
1057 set_bit(STATUS_INIT, &priv->status);
1063 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1065 * Destroy all TX DMA queues and structures
1067 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1073 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1075 if (txq_id == IWL39_CMD_QUEUE_NUM)
1076 iwl_cmd_queue_free(priv);
1078 iwl_tx_queue_free(priv, txq_id);
1080 /* free tx queue structure */
1081 iwl_free_txq_mem(priv);
1084 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1089 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1090 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1092 /* reset TFD queues */
1093 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1094 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1095 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1096 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1100 iwl3945_hw_txq_ctx_free(priv);
1104 * iwl3945_hw_reg_adjust_power_by_temp
1105 * return index delta into power gain settings table
1107 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1109 return (new_reading - old_reading) * (-11) / 100;
1113 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1115 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1117 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1120 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1122 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1126 * iwl3945_hw_reg_txpower_get_temperature
1127 * get the current temperature by reading from NIC
1129 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1131 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1134 temperature = iwl3945_hw_get_temperature(priv);
1136 /* driver's okay range is -260 to +25.
1137 * human readable okay range is 0 to +285 */
1138 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1140 /* handle insane temp reading */
1141 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1142 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1144 /* if really really hot(?),
1145 * substitute the 3rd band/group's temp measured at factory */
1146 if (priv->last_temperature > 100)
1147 temperature = eeprom->groups[2].temperature;
1148 else /* else use most recent "sane" value from driver */
1149 temperature = priv->last_temperature;
1152 return temperature; /* raw, not "human readable" */
1155 /* Adjust Txpower only if temperature variance is greater than threshold.
1157 * Both are lower than older versions' 9 degrees */
1158 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1161 * is_temp_calib_needed - determines if new calibration is needed
1163 * records new temperature in tx_mgr->temperature.
1164 * replaces tx_mgr->last_temperature *only* if calib needed
1165 * (assumes caller will actually do the calibration!). */
1166 static int is_temp_calib_needed(struct iwl_priv *priv)
1170 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1171 temp_diff = priv->temperature - priv->last_temperature;
1173 /* get absolute value */
1174 if (temp_diff < 0) {
1175 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1176 temp_diff = -temp_diff;
1177 } else if (temp_diff == 0)
1178 IWL_DEBUG_POWER(priv, "Same temp,\n");
1180 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1182 /* if we don't need calibration, *don't* update last_temperature */
1183 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1184 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1188 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1190 /* assume that caller will actually do calib ...
1191 * update the "last temperature" value */
1192 priv->last_temperature = priv->temperature;
1196 #define IWL_MAX_GAIN_ENTRIES 78
1197 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1198 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1200 /* radio and DSP power table, each step is 1/2 dB.
1201 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1202 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1204 {251, 127}, /* 2.4 GHz, highest power */
1281 {3, 95} }, /* 2.4 GHz, lowest power */
1283 {251, 127}, /* 5.x GHz, highest power */
1360 {3, 120} } /* 5.x GHz, lowest power */
1363 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1367 if (index >= IWL_MAX_GAIN_ENTRIES)
1368 return IWL_MAX_GAIN_ENTRIES - 1;
1372 /* Kick off thermal recalibration check every 60 seconds */
1373 #define REG_RECALIB_PERIOD (60)
1376 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1378 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1379 * or 6 Mbit (OFDM) rates.
1381 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1382 s32 rate_index, const s8 *clip_pwrs,
1383 struct iwl_channel_info *ch_info,
1386 struct iwl3945_scan_power_info *scan_power_info;
1390 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1392 /* use this channel group's 6Mbit clipping/saturation pwr,
1393 * but cap at regulatory scan power restriction (set during init
1394 * based on eeprom channel data) for this channel. */
1395 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1397 /* further limit to user's max power preference.
1398 * FIXME: Other spectrum management power limitations do not
1399 * seem to apply?? */
1400 power = min(power, priv->tx_power_user_lmt);
1401 scan_power_info->requested_power = power;
1403 /* find difference between new scan *power* and current "normal"
1404 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1405 * current "normal" temperature-compensated Tx power *index* for
1406 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1408 power_index = ch_info->power_info[rate_index].power_table_index
1409 - (power - ch_info->power_info
1410 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1412 /* store reference index that we use when adjusting *all* scan
1413 * powers. So we can accommodate user (all channel) or spectrum
1414 * management (single channel) power changes "between" temperature
1415 * feedback compensation procedures.
1416 * don't force fit this reference index into gain table; it may be a
1417 * negative number. This will help avoid errors when we're at
1418 * the lower bounds (highest gains, for warmest temperatures)
1421 /* don't exceed table bounds for "real" setting */
1422 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1424 scan_power_info->power_table_index = power_index;
1425 scan_power_info->tpc.tx_gain =
1426 power_gain_table[band_index][power_index].tx_gain;
1427 scan_power_info->tpc.dsp_atten =
1428 power_gain_table[band_index][power_index].dsp_atten;
1432 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1434 * Configures power settings for all rates for the current channel,
1435 * using values from channel info struct, and send to NIC
1437 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1440 const struct iwl_channel_info *ch_info = NULL;
1441 struct iwl3945_txpowertable_cmd txpower = {
1442 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1446 chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1448 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1449 ch_info = iwl_get_channel_info(priv, priv->band, chan);
1452 "Failed to get channel info for channel %d [%d]\n",
1457 if (!is_channel_valid(ch_info)) {
1458 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1459 "non-Tx channel.\n");
1463 /* fill cmd with power settings for all rates for current channel */
1464 /* Fill OFDM rate */
1465 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1466 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1468 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1469 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1471 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1472 le16_to_cpu(txpower.channel),
1474 txpower.power[i].tpc.tx_gain,
1475 txpower.power[i].tpc.dsp_atten,
1476 txpower.power[i].rate);
1478 /* Fill CCK rates */
1479 for (rate_idx = IWL_FIRST_CCK_RATE;
1480 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1481 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1482 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1484 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1485 le16_to_cpu(txpower.channel),
1487 txpower.power[i].tpc.tx_gain,
1488 txpower.power[i].tpc.dsp_atten,
1489 txpower.power[i].rate);
1492 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1493 sizeof(struct iwl3945_txpowertable_cmd),
1499 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1500 * @ch_info: Channel to update. Uses power_info.requested_power.
1502 * Replace requested_power and base_power_index ch_info fields for
1505 * Called if user or spectrum management changes power preferences.
1506 * Takes into account h/w and modulation limitations (clip power).
1508 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1510 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1511 * properly fill out the scan powers, and actual h/w gain settings,
1512 * and send changes to NIC
1514 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1515 struct iwl_channel_info *ch_info)
1517 struct iwl3945_channel_power_info *power_info;
1518 int power_changed = 0;
1520 const s8 *clip_pwrs;
1523 /* Get this chnlgrp's rate-to-max/clip-powers table */
1524 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1526 /* Get this channel's rate-to-current-power settings table */
1527 power_info = ch_info->power_info;
1529 /* update OFDM Txpower settings */
1530 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1531 i++, ++power_info) {
1534 /* limit new power to be no more than h/w capability */
1535 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1536 if (power == power_info->requested_power)
1539 /* find difference between old and new requested powers,
1540 * update base (non-temp-compensated) power index */
1541 delta_idx = (power - power_info->requested_power) * 2;
1542 power_info->base_power_index -= delta_idx;
1544 /* save new requested power value */
1545 power_info->requested_power = power;
1550 /* update CCK Txpower settings, based on OFDM 12M setting ...
1551 * ... all CCK power settings for a given channel are the *same*. */
1552 if (power_changed) {
1554 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1555 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1557 /* do all CCK rates' iwl3945_channel_power_info structures */
1558 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1559 power_info->requested_power = power;
1560 power_info->base_power_index =
1561 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1562 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1571 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1573 * NOTE: Returned power limit may be less (but not more) than requested,
1574 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1575 * (no consideration for h/w clipping limitations).
1577 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1582 /* if we're using TGd limits, use lower of TGd or EEPROM */
1583 if (ch_info->tgd_data.max_power != 0)
1584 max_power = min(ch_info->tgd_data.max_power,
1585 ch_info->eeprom.max_power_avg);
1587 /* else just use EEPROM limits */
1590 max_power = ch_info->eeprom.max_power_avg;
1592 return min(max_power, ch_info->max_power_avg);
1596 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1598 * Compensate txpower settings of *all* channels for temperature.
1599 * This only accounts for the difference between current temperature
1600 * and the factory calibration temperatures, and bases the new settings
1601 * on the channel's base_power_index.
1603 * If RxOn is "associated", this sends the new Txpower to NIC!
1605 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1607 struct iwl_channel_info *ch_info = NULL;
1608 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1610 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1616 int temperature = priv->temperature;
1618 if (priv->disable_tx_power_cal ||
1619 test_bit(STATUS_SCANNING, &priv->status)) {
1620 /* do not perform tx power calibration */
1623 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1624 for (i = 0; i < priv->channel_count; i++) {
1625 ch_info = &priv->channel_info[i];
1626 a_band = is_channel_a_band(ch_info);
1628 /* Get this chnlgrp's factory calibration temperature */
1629 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1632 /* get power index adjustment based on current and factory
1634 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1637 /* set tx power value for all rates, OFDM and CCK */
1638 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1641 ch_info->power_info[rate_index].base_power_index;
1643 /* temperature compensate */
1644 power_idx += delta_index;
1646 /* stay within table range */
1647 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1648 ch_info->power_info[rate_index].
1649 power_table_index = (u8) power_idx;
1650 ch_info->power_info[rate_index].tpc =
1651 power_gain_table[a_band][power_idx];
1654 /* Get this chnlgrp's rate-to-max/clip-powers table */
1655 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1657 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1658 for (scan_tbl_index = 0;
1659 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1660 s32 actual_index = (scan_tbl_index == 0) ?
1661 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1662 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1663 actual_index, clip_pwrs,
1668 /* send Txpower command for current channel to ucode */
1669 return priv->cfg->ops->lib->send_tx_power(priv);
1672 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1674 struct iwl_channel_info *ch_info;
1679 if (priv->tx_power_user_lmt == power) {
1680 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1681 "limit: %ddBm.\n", power);
1685 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1686 priv->tx_power_user_lmt = power;
1688 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1690 for (i = 0; i < priv->channel_count; i++) {
1691 ch_info = &priv->channel_info[i];
1692 a_band = is_channel_a_band(ch_info);
1694 /* find minimum power of all user and regulatory constraints
1695 * (does not consider h/w clipping limitations) */
1696 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1697 max_power = min(power, max_power);
1698 if (max_power != ch_info->curr_txpow) {
1699 ch_info->curr_txpow = max_power;
1701 /* this considers the h/w clipping limitations */
1702 iwl3945_hw_reg_set_new_power(priv, ch_info);
1706 /* update txpower settings for all channels,
1707 * send to NIC if associated. */
1708 is_temp_calib_needed(priv);
1709 iwl3945_hw_reg_comp_txpower_temp(priv);
1714 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1715 struct iwl_rxon_context *ctx)
1718 struct iwl_rx_packet *pkt;
1719 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1720 struct iwl_host_cmd cmd = {
1721 .id = REPLY_RXON_ASSOC,
1722 .len = sizeof(rxon_assoc),
1723 .flags = CMD_WANT_SKB,
1724 .data = &rxon_assoc,
1726 const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1727 const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1729 if ((rxon1->flags == rxon2->flags) &&
1730 (rxon1->filter_flags == rxon2->filter_flags) &&
1731 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1732 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1733 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1737 rxon_assoc.flags = ctx->staging.flags;
1738 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1739 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1740 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1741 rxon_assoc.reserved = 0;
1743 rc = iwl_send_cmd_sync(priv, &cmd);
1747 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1748 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1749 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1753 iwl_free_pages(priv, cmd.reply_page);
1759 * iwl3945_commit_rxon - commit staging_rxon to hardware
1761 * The RXON command in staging_rxon is committed to the hardware and
1762 * the active_rxon structure is updated with the new data. This
1763 * function correctly transitions out of the RXON_ASSOC_MSK state if
1764 * a HW tune is required based on the RXON structure changes.
1766 static int iwl3945_commit_rxon(struct iwl_priv *priv,
1767 struct iwl_rxon_context *ctx)
1769 /* cast away the const for active_rxon in this function */
1770 struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1771 struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1773 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1775 if (!iwl_is_alive(priv))
1778 /* always get timestamp with Rx frame */
1779 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1781 /* select antenna */
1782 staging_rxon->flags &=
1783 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1784 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1786 rc = iwl_check_rxon_cmd(priv, ctx);
1788 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1792 /* If we don't need to send a full RXON, we can use
1793 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1794 * and other flags for the current radio configuration. */
1795 if (!iwl_full_rxon_required(priv, &priv->contexts[IWL_RXON_CTX_BSS])) {
1796 rc = iwl_send_rxon_assoc(priv,
1797 &priv->contexts[IWL_RXON_CTX_BSS]);
1799 IWL_ERR(priv, "Error setting RXON_ASSOC "
1800 "configuration (%d).\n", rc);
1804 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1809 /* If we are currently associated and the new config requires
1810 * an RXON_ASSOC and the new config wants the associated mask enabled,
1811 * we must clear the associated from the active configuration
1812 * before we apply the new config */
1813 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1814 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1815 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1818 * reserved4 and 5 could have been filled by the iwlcore code.
1819 * Let's clear them before pushing to the 3945.
1821 active_rxon->reserved4 = 0;
1822 active_rxon->reserved5 = 0;
1823 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1824 sizeof(struct iwl3945_rxon_cmd),
1825 &priv->contexts[IWL_RXON_CTX_BSS].active);
1827 /* If the mask clearing failed then we set
1828 * active_rxon back to what it was previously */
1830 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1831 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1832 "configuration (%d).\n", rc);
1835 iwl_clear_ucode_stations(priv,
1836 &priv->contexts[IWL_RXON_CTX_BSS]);
1837 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1840 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1841 "* with%s RXON_FILTER_ASSOC_MSK\n"
1844 (new_assoc ? "" : "out"),
1845 le16_to_cpu(staging_rxon->channel),
1846 staging_rxon->bssid_addr);
1849 * reserved4 and 5 could have been filled by the iwlcore code.
1850 * Let's clear them before pushing to the 3945.
1852 staging_rxon->reserved4 = 0;
1853 staging_rxon->reserved5 = 0;
1855 iwl_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1857 /* Apply the new configuration */
1858 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1859 sizeof(struct iwl3945_rxon_cmd),
1862 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1866 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1869 iwl_clear_ucode_stations(priv,
1870 &priv->contexts[IWL_RXON_CTX_BSS]);
1871 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1874 /* If we issue a new RXON command which required a tune then we must
1875 * send a new TXPOWER command or we won't be able to Tx any frames */
1876 rc = priv->cfg->ops->lib->send_tx_power(priv);
1878 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1882 /* Init the hardware's rate fallback order based on the band */
1883 rc = iwl3945_init_hw_rate_table(priv);
1885 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1893 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1895 * -- reset periodic timer
1896 * -- see if temp has changed enough to warrant re-calibration ... if so:
1897 * -- correct coeffs for temp (can reset temp timer)
1898 * -- save this temp as "last",
1899 * -- send new set of gain settings to NIC
1900 * NOTE: This should continue working, even when we're not associated,
1901 * so we can keep our internal table of scan powers current. */
1902 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1904 /* This will kick in the "brute force"
1905 * iwl3945_hw_reg_comp_txpower_temp() below */
1906 if (!is_temp_calib_needed(priv))
1909 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1910 * This is based *only* on current temperature,
1911 * ignoring any previous power measurements */
1912 iwl3945_hw_reg_comp_txpower_temp(priv);
1915 queue_delayed_work(priv->workqueue,
1916 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1919 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1921 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1922 _3945.thermal_periodic.work);
1924 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1927 mutex_lock(&priv->mutex);
1928 iwl3945_reg_txpower_periodic(priv);
1929 mutex_unlock(&priv->mutex);
1933 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1936 * This function is used when initializing channel-info structs.
1938 * NOTE: These channel groups do *NOT* match the bands above!
1939 * These channel groups are based on factory-tested channels;
1940 * on A-band, EEPROM's "group frequency" entries represent the top
1941 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1943 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1944 const struct iwl_channel_info *ch_info)
1946 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1947 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1949 u16 group_index = 0; /* based on factory calib frequencies */
1952 /* Find the group index for the channel ... don't use index 1(?) */
1953 if (is_channel_a_band(ch_info)) {
1954 for (group = 1; group < 5; group++) {
1955 grp_channel = ch_grp[group].group_channel;
1956 if (ch_info->channel <= grp_channel) {
1957 group_index = group;
1961 /* group 4 has a few channels *above* its factory cal freq */
1965 group_index = 0; /* 2.4 GHz, group 0 */
1967 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1973 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1975 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1976 * into radio/DSP gain settings table for requested power.
1978 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1980 s32 setting_index, s32 *new_index)
1982 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1983 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1985 s32 power = 2 * requested_power;
1987 const struct iwl3945_eeprom_txpower_sample *samples;
1992 chnl_grp = &eeprom->groups[setting_index];
1993 samples = chnl_grp->samples;
1994 for (i = 0; i < 5; i++) {
1995 if (power == samples[i].power) {
1996 *new_index = samples[i].gain_index;
2001 if (power > samples[1].power) {
2004 } else if (power > samples[2].power) {
2007 } else if (power > samples[3].power) {
2015 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2016 if (denominator == 0)
2018 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2019 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2020 res = gains0 + (gains1 - gains0) *
2021 ((s32) power - (s32) samples[index0].power) / denominator +
2023 *new_index = res >> 19;
2027 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2031 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2032 const struct iwl3945_eeprom_txpower_group *group;
2034 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2036 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2037 s8 *clip_pwrs; /* table of power levels for each rate */
2038 s8 satur_pwr; /* saturation power for each chnl group */
2039 group = &eeprom->groups[i];
2041 /* sanity check on factory saturation power value */
2042 if (group->saturation_power < 40) {
2043 IWL_WARN(priv, "Error: saturation power is %d, "
2044 "less than minimum expected 40\n",
2045 group->saturation_power);
2050 * Derive requested power levels for each rate, based on
2051 * hardware capabilities (saturation power for band).
2052 * Basic value is 3dB down from saturation, with further
2053 * power reductions for highest 3 data rates. These
2054 * backoffs provide headroom for high rate modulation
2055 * power peaks, without too much distortion (clipping).
2057 /* we'll fill in this array with h/w max power levels */
2058 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2060 /* divide factory saturation power by 2 to find -3dB level */
2061 satur_pwr = (s8) (group->saturation_power >> 1);
2063 /* fill in channel group's nominal powers for each rate */
2064 for (rate_index = 0;
2065 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2066 switch (rate_index) {
2067 case IWL_RATE_36M_INDEX_TABLE:
2068 if (i == 0) /* B/G */
2069 *clip_pwrs = satur_pwr;
2071 *clip_pwrs = satur_pwr - 5;
2073 case IWL_RATE_48M_INDEX_TABLE:
2075 *clip_pwrs = satur_pwr - 7;
2077 *clip_pwrs = satur_pwr - 10;
2079 case IWL_RATE_54M_INDEX_TABLE:
2081 *clip_pwrs = satur_pwr - 9;
2083 *clip_pwrs = satur_pwr - 12;
2086 *clip_pwrs = satur_pwr;
2094 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2096 * Second pass (during init) to set up priv->channel_info
2098 * Set up Tx-power settings in our channel info database for each VALID
2099 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2100 * and current temperature.
2102 * Since this is based on current temperature (at init time), these values may
2103 * not be valid for very long, but it gives us a starting/default point,
2104 * and allows us to active (i.e. using Tx) scan.
2106 * This does *not* write values to NIC, just sets up our internal table.
2108 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2110 struct iwl_channel_info *ch_info = NULL;
2111 struct iwl3945_channel_power_info *pwr_info;
2112 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2116 const s8 *clip_pwrs; /* array of power levels for each rate */
2119 u8 pwr_index, base_pwr_index, a_band;
2123 /* save temperature reference,
2124 * so we can determine next time to calibrate */
2125 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2126 priv->last_temperature = temperature;
2128 iwl3945_hw_reg_init_channel_groups(priv);
2130 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2131 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2133 a_band = is_channel_a_band(ch_info);
2134 if (!is_channel_valid(ch_info))
2137 /* find this channel's channel group (*not* "band") index */
2138 ch_info->group_index =
2139 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2141 /* Get this chnlgrp's rate->max/clip-powers table */
2142 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2144 /* calculate power index *adjustment* value according to
2145 * diff between current temperature and factory temperature */
2146 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2147 eeprom->groups[ch_info->group_index].
2150 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2151 ch_info->channel, delta_index, temperature +
2154 /* set tx power value for all OFDM rates */
2155 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2157 s32 uninitialized_var(power_idx);
2160 /* use channel group's clip-power table,
2161 * but don't exceed channel's max power */
2162 s8 pwr = min(ch_info->max_power_avg,
2163 clip_pwrs[rate_index]);
2165 pwr_info = &ch_info->power_info[rate_index];
2167 /* get base (i.e. at factory-measured temperature)
2168 * power table index for this rate's power */
2169 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2170 ch_info->group_index,
2173 IWL_ERR(priv, "Invalid power index\n");
2176 pwr_info->base_power_index = (u8) power_idx;
2178 /* temperature compensate */
2179 power_idx += delta_index;
2181 /* stay within range of gain table */
2182 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2184 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2185 pwr_info->requested_power = pwr;
2186 pwr_info->power_table_index = (u8) power_idx;
2187 pwr_info->tpc.tx_gain =
2188 power_gain_table[a_band][power_idx].tx_gain;
2189 pwr_info->tpc.dsp_atten =
2190 power_gain_table[a_band][power_idx].dsp_atten;
2193 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2194 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2195 power = pwr_info->requested_power +
2196 IWL_CCK_FROM_OFDM_POWER_DIFF;
2197 pwr_index = pwr_info->power_table_index +
2198 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2199 base_pwr_index = pwr_info->base_power_index +
2200 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2202 /* stay within table range */
2203 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2204 gain = power_gain_table[a_band][pwr_index].tx_gain;
2205 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2207 /* fill each CCK rate's iwl3945_channel_power_info structure
2208 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2209 * NOTE: CCK rates start at end of OFDM rates! */
2210 for (rate_index = 0;
2211 rate_index < IWL_CCK_RATES; rate_index++) {
2212 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2213 pwr_info->requested_power = power;
2214 pwr_info->power_table_index = pwr_index;
2215 pwr_info->base_power_index = base_pwr_index;
2216 pwr_info->tpc.tx_gain = gain;
2217 pwr_info->tpc.dsp_atten = dsp_atten;
2220 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2221 for (scan_tbl_index = 0;
2222 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2223 s32 actual_index = (scan_tbl_index == 0) ?
2224 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2225 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2226 actual_index, clip_pwrs, ch_info, a_band);
2233 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2237 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2238 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2239 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2241 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2246 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2248 int txq_id = txq->q.id;
2250 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2252 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2254 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2255 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2257 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2258 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2259 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2260 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2261 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2262 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2264 /* fake read to flush all prev. writes */
2265 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2273 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2277 return sizeof(struct iwl3945_rxon_cmd);
2278 case POWER_TABLE_CMD:
2279 return sizeof(struct iwl3945_powertable_cmd);
2286 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2288 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2289 addsta->mode = cmd->mode;
2290 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2291 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2292 addsta->station_flags = cmd->station_flags;
2293 addsta->station_flags_msk = cmd->station_flags_msk;
2294 addsta->tid_disable_tx = cpu_to_le16(0);
2295 addsta->rate_n_flags = cmd->rate_n_flags;
2296 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2297 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2298 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2300 return (u16)sizeof(struct iwl3945_addsta_cmd);
2303 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2304 struct ieee80211_vif *vif, bool add)
2306 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2310 ret = iwl_add_bssid_station(
2311 priv, &priv->contexts[IWL_RXON_CTX_BSS],
2312 vif->bss_conf.bssid, false,
2313 &vif_priv->ibss_bssid_sta_id);
2317 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2318 (priv->band == IEEE80211_BAND_5GHZ) ?
2319 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2320 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2325 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2326 vif->bss_conf.bssid);
2330 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2332 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2334 int rc, i, index, prev_index;
2335 struct iwl3945_rate_scaling_cmd rate_cmd = {
2336 .reserved = {0, 0, 0},
2338 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2340 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2341 index = iwl3945_rates[i].table_rs_index;
2343 table[index].rate_n_flags =
2344 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2345 table[index].try_cnt = priv->retry_rate;
2346 prev_index = iwl3945_get_prev_ieee_rate(i);
2347 table[index].next_rate_index =
2348 iwl3945_rates[prev_index].table_rs_index;
2351 switch (priv->band) {
2352 case IEEE80211_BAND_5GHZ:
2353 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2354 /* If one of the following CCK rates is used,
2355 * have it fall back to the 6M OFDM rate */
2356 for (i = IWL_RATE_1M_INDEX_TABLE;
2357 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2358 table[i].next_rate_index =
2359 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2361 /* Don't fall back to CCK rates */
2362 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2363 IWL_RATE_9M_INDEX_TABLE;
2365 /* Don't drop out of OFDM rates */
2366 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2367 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2370 case IEEE80211_BAND_2GHZ:
2371 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2372 /* If an OFDM rate is used, have it fall back to the
2375 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2376 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
2378 index = IWL_FIRST_CCK_RATE;
2379 for (i = IWL_RATE_6M_INDEX_TABLE;
2380 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2381 table[i].next_rate_index =
2382 iwl3945_rates[index].table_rs_index;
2384 index = IWL_RATE_11M_INDEX_TABLE;
2385 /* CCK shouldn't fall back to OFDM... */
2386 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2395 /* Update the rate scaling for control frame Tx */
2396 rate_cmd.table_id = 0;
2397 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2402 /* Update the rate scaling for data frame Tx */
2403 rate_cmd.table_id = 1;
2404 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2408 /* Called when initializing driver */
2409 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2411 memset((void *)&priv->hw_params, 0,
2412 sizeof(struct iwl_hw_params));
2414 priv->_3945.shared_virt =
2415 dma_alloc_coherent(&priv->pci_dev->dev,
2416 sizeof(struct iwl3945_shared),
2417 &priv->_3945.shared_phys, GFP_KERNEL);
2418 if (!priv->_3945.shared_virt) {
2419 IWL_ERR(priv, "failed to allocate pci memory\n");
2423 /* Assign number of Usable TX queues */
2424 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2426 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2427 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2428 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2429 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2430 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2431 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2433 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2435 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2436 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2437 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2442 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2443 struct iwl3945_frame *frame, u8 rate)
2445 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2446 unsigned int frame_size;
2448 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2449 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2451 tx_beacon_cmd->tx.sta_id =
2452 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2453 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2455 frame_size = iwl3945_fill_beacon_frame(priv,
2456 tx_beacon_cmd->frame,
2457 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2459 BUG_ON(frame_size > MAX_MPDU_SIZE);
2460 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2462 tx_beacon_cmd->tx.rate = rate;
2463 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2464 TX_CMD_FLG_TSF_MSK);
2466 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2467 tx_beacon_cmd->tx.supp_rates[0] =
2468 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2470 tx_beacon_cmd->tx.supp_rates[1] =
2471 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2473 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2476 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2478 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2479 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2482 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2484 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2485 iwl3945_bg_reg_txpower_periodic);
2488 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2490 cancel_delayed_work(&priv->_3945.thermal_periodic);
2493 /* check contents of special bootstrap uCode SRAM */
2494 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2496 __le32 *image = priv->ucode_boot.v_addr;
2497 u32 len = priv->ucode_boot.len;
2501 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2503 /* verify BSM SRAM contents */
2504 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2505 for (reg = BSM_SRAM_LOWER_BOUND;
2506 reg < BSM_SRAM_LOWER_BOUND + len;
2507 reg += sizeof(u32), image++) {
2508 val = iwl_read_prph(priv, reg);
2509 if (val != le32_to_cpu(*image)) {
2510 IWL_ERR(priv, "BSM uCode verification failed at "
2511 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2512 BSM_SRAM_LOWER_BOUND,
2513 reg - BSM_SRAM_LOWER_BOUND, len,
2514 val, le32_to_cpu(*image));
2519 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2525 /******************************************************************************
2527 * EEPROM related functions
2529 ******************************************************************************/
2532 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2533 * embedded controller) as EEPROM reader; each read is a series of pulses
2534 * to/from the EEPROM chip, not a single event, so even reads could conflict
2535 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2536 * simply claims ownership, which should be safe when this function is called
2537 * (i.e. before loading uCode!).
2539 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2541 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2546 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2552 * iwl3945_load_bsm - Load bootstrap instructions
2556 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2557 * in special SRAM that does not power down during RFKILL. When powering back
2558 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2559 * the bootstrap program into the on-board processor, and starts it.
2561 * The bootstrap program loads (via DMA) instructions and data for a new
2562 * program from host DRAM locations indicated by the host driver in the
2563 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2566 * When initializing the NIC, the host driver points the BSM to the
2567 * "initialize" uCode image. This uCode sets up some internal data, then
2568 * notifies host via "initialize alive" that it is complete.
2570 * The host then replaces the BSM_DRAM_* pointer values to point to the
2571 * normal runtime uCode instructions and a backup uCode data cache buffer
2572 * (filled initially with starting data values for the on-board processor),
2573 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2574 * which begins normal operation.
2576 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2577 * the backup data cache in DRAM before SRAM is powered down.
2579 * When powering back up, the BSM loads the bootstrap program. This reloads
2580 * the runtime uCode instructions and the backup data cache into SRAM,
2581 * and re-launches the runtime uCode from where it left off.
2583 static int iwl3945_load_bsm(struct iwl_priv *priv)
2585 __le32 *image = priv->ucode_boot.v_addr;
2586 u32 len = priv->ucode_boot.len;
2596 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2598 /* make sure bootstrap program is no larger than BSM's SRAM size */
2599 if (len > IWL39_MAX_BSM_SIZE)
2602 /* Tell bootstrap uCode where to find the "Initialize" uCode
2603 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2604 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2605 * after the "initialize" uCode has run, to point to
2606 * runtime/protocol instructions and backup data cache. */
2607 pinst = priv->ucode_init.p_addr;
2608 pdata = priv->ucode_init_data.p_addr;
2609 inst_len = priv->ucode_init.len;
2610 data_len = priv->ucode_init_data.len;
2612 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2613 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2614 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2615 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2617 /* Fill BSM memory with bootstrap instructions */
2618 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2619 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2620 reg_offset += sizeof(u32), image++)
2621 _iwl_write_prph(priv, reg_offset,
2622 le32_to_cpu(*image));
2624 rc = iwl3945_verify_bsm(priv);
2628 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2629 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2630 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2631 IWL39_RTC_INST_LOWER_BOUND);
2632 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2634 /* Load bootstrap code into instruction SRAM now,
2635 * to prepare to load "initialize" uCode */
2636 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2637 BSM_WR_CTRL_REG_BIT_START);
2639 /* Wait for load of bootstrap uCode to finish */
2640 for (i = 0; i < 100; i++) {
2641 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2642 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2647 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2649 IWL_ERR(priv, "BSM write did not complete!\n");
2653 /* Enable future boot loads whenever power management unit triggers it
2654 * (e.g. when powering back up after power-save shutdown) */
2655 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2656 BSM_WR_CTRL_REG_BIT_START_EN);
2661 static struct iwl_hcmd_ops iwl3945_hcmd = {
2662 .rxon_assoc = iwl3945_send_rxon_assoc,
2663 .commit_rxon = iwl3945_commit_rxon,
2664 .send_bt_config = iwl_send_bt_config,
2667 static struct iwl_lib_ops iwl3945_lib = {
2668 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2669 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2670 .txq_init = iwl3945_hw_tx_queue_init,
2671 .load_ucode = iwl3945_load_bsm,
2672 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2673 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2675 .init = iwl3945_apm_init,
2676 .stop = iwl_apm_stop,
2677 .config = iwl3945_nic_config,
2678 .set_pwr_src = iwl3945_set_pwr_src,
2681 .regulatory_bands = {
2682 EEPROM_REGULATORY_BAND_1_CHANNELS,
2683 EEPROM_REGULATORY_BAND_2_CHANNELS,
2684 EEPROM_REGULATORY_BAND_3_CHANNELS,
2685 EEPROM_REGULATORY_BAND_4_CHANNELS,
2686 EEPROM_REGULATORY_BAND_5_CHANNELS,
2687 EEPROM_REGULATORY_BAND_NO_HT40,
2688 EEPROM_REGULATORY_BAND_NO_HT40,
2690 .verify_signature = iwlcore_eeprom_verify_signature,
2691 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2692 .release_semaphore = iwl3945_eeprom_release_semaphore,
2693 .query_addr = iwlcore_eeprom_query_addr,
2695 .send_tx_power = iwl3945_send_tx_power,
2696 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2697 .post_associate = iwl3945_post_associate,
2698 .isr = iwl_isr_legacy,
2699 .config_ap = iwl3945_config_ap,
2700 .manage_ibss_station = iwl3945_manage_ibss_station,
2701 .recover_from_tx_stall = iwl_bg_monitor_recover,
2702 .check_plcp_health = iwl3945_good_plcp_health,
2705 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2706 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2707 .general_stats_read = iwl3945_ucode_general_stats_read,
2711 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2712 .get_hcmd_size = iwl3945_get_hcmd_size,
2713 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2714 .tx_cmd_protection = iwlcore_tx_cmd_protection,
2715 .request_scan = iwl3945_request_scan,
2718 static const struct iwl_ops iwl3945_ops = {
2719 .lib = &iwl3945_lib,
2720 .hcmd = &iwl3945_hcmd,
2721 .utils = &iwl3945_hcmd_utils,
2722 .led = &iwl3945_led_ops,
2725 static struct iwl_cfg iwl3945_bg_cfg = {
2727 .fw_name_pre = IWL3945_FW_PRE,
2728 .ucode_api_max = IWL3945_UCODE_API_MAX,
2729 .ucode_api_min = IWL3945_UCODE_API_MIN,
2731 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2732 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2733 .ops = &iwl3945_ops,
2734 .num_of_queues = IWL39_NUM_QUEUES,
2735 .mod_params = &iwl3945_mod_params,
2736 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2739 .use_isr_legacy = true,
2740 .ht_greenfield_support = false,
2741 .led_compensation = 64,
2742 .broken_powersave = true,
2743 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2744 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
2745 .max_event_log_size = 512,
2746 .tx_power_by_driver = true,
2749 static struct iwl_cfg iwl3945_abg_cfg = {
2751 .fw_name_pre = IWL3945_FW_PRE,
2752 .ucode_api_max = IWL3945_UCODE_API_MAX,
2753 .ucode_api_min = IWL3945_UCODE_API_MIN,
2754 .sku = IWL_SKU_A|IWL_SKU_G,
2755 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2756 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2757 .ops = &iwl3945_ops,
2758 .num_of_queues = IWL39_NUM_QUEUES,
2759 .mod_params = &iwl3945_mod_params,
2760 .use_isr_legacy = true,
2761 .ht_greenfield_support = false,
2762 .led_compensation = 64,
2763 .broken_powersave = true,
2764 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2765 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
2766 .max_event_log_size = 512,
2767 .tx_power_by_driver = true,
2770 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2771 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2772 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2773 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2774 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2775 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2776 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2780 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);