drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-3945.h"
  46 #include "iwl-eeprom.h"
  47 #include "iwl-helpers.h"
  48 #include "iwl-core.h"
  49 #include "iwl-led.h"
  50 #include "iwl-3945-led.h"
  51
  52 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  53         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  54                                     IWL_RATE_##r##M_IEEE,   \
  55                                     IWL_RATE_##ip##M_INDEX, \
  56                                     IWL_RATE_##in##M_INDEX, \
  57                                     IWL_RATE_##rp##M_INDEX, \
  58                                     IWL_RATE_##rn##M_INDEX, \
  59                                     IWL_RATE_##pp##M_INDEX, \
  60                                     IWL_RATE_##np##M_INDEX, \
  61                                     IWL_RATE_##r##M_INDEX_TABLE, \
  62                                     IWL_RATE_##ip##M_INDEX_TABLE }
  63
  64 /*
  65  * Parameter order:
  66  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  67  *
  68  * If there isn't a valid next or previous rate then INV is used which
  69  * maps to IWL_RATE_INVALID
  70  *
  71  */
  72 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  73         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  74         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  75         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  76         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  77         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  78         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  79         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  80         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  81         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  82         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  83         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  84         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  85 };
  86
  87 /* 1 = enable the iwl3945_disable_events() function */
  88 #define IWL_EVT_DISABLE (0)
  89 #define IWL_EVT_DISABLE_SIZE (1532/32)
  90
  91 /**
  92  * iwl3945_disable_events - Disable selected events in uCode event log
  93  *
  94  * Disable an event by writing "1"s into "disable"
  95  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  96  *   Default values of 0 enable uCode events to be logged.
  97  * Use for only special debugging.  This function is just a placeholder as-is,
  98  *   you'll need to provide the special bits! ...
  99  *   ... and set IWL_EVT_DISABLE to 1. */
 100 void iwl3945_disable_events(struct iwl_priv *priv)
 101 {
 102         int i;
 103         u32 base;               /* SRAM address of event log header */
 104         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 105         u32 array_size;         /* # of u32 entries in array */
 106         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 107                 0x00000000,     /*   31 -    0  Event id numbers */
 108                 0x00000000,     /*   63 -   32 */
 109                 0x00000000,     /*   95 -   64 */
 110                 0x00000000,     /*  127 -   96 */
 111                 0x00000000,     /*  159 -  128 */
 112                 0x00000000,     /*  191 -  160 */
 113                 0x00000000,     /*  223 -  192 */
 114                 0x00000000,     /*  255 -  224 */
 115                 0x00000000,     /*  287 -  256 */
 116                 0x00000000,     /*  319 -  288 */
 117                 0x00000000,     /*  351 -  320 */
 118                 0x00000000,     /*  383 -  352 */
 119                 0x00000000,     /*  415 -  384 */
 120                 0x00000000,     /*  447 -  416 */
 121                 0x00000000,     /*  479 -  448 */
 122                 0x00000000,     /*  511 -  480 */
 123                 0x00000000,     /*  543 -  512 */
 124                 0x00000000,     /*  575 -  544 */
 125                 0x00000000,     /*  607 -  576 */
 126                 0x00000000,     /*  639 -  608 */
 127                 0x00000000,     /*  671 -  640 */
 128                 0x00000000,     /*  703 -  672 */
 129                 0x00000000,     /*  735 -  704 */
 130                 0x00000000,     /*  767 -  736 */
 131                 0x00000000,     /*  799 -  768 */
 132                 0x00000000,     /*  831 -  800 */
 133                 0x00000000,     /*  863 -  832 */
 134                 0x00000000,     /*  895 -  864 */
 135                 0x00000000,     /*  927 -  896 */
 136                 0x00000000,     /*  959 -  928 */
 137                 0x00000000,     /*  991 -  960 */
 138                 0x00000000,     /* 1023 -  992 */
 139                 0x00000000,     /* 1055 - 1024 */
 140                 0x00000000,     /* 1087 - 1056 */
 141                 0x00000000,     /* 1119 - 1088 */
 142                 0x00000000,     /* 1151 - 1120 */
 143                 0x00000000,     /* 1183 - 1152 */
 144                 0x00000000,     /* 1215 - 1184 */
 145                 0x00000000,     /* 1247 - 1216 */
 146                 0x00000000,     /* 1279 - 1248 */
 147                 0x00000000,     /* 1311 - 1280 */
 148                 0x00000000,     /* 1343 - 1312 */
 149                 0x00000000,     /* 1375 - 1344 */
 150                 0x00000000,     /* 1407 - 1376 */
 151                 0x00000000,     /* 1439 - 1408 */
 152                 0x00000000,     /* 1471 - 1440 */
 153                 0x00000000,     /* 1503 - 1472 */
 154         };
 155
 156         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 157         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 158                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 159                 return;
 160         }
 161
 162         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 163         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 164
 165         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 166                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 167                                disable_ptr);
 168                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 169                         iwl_write_targ_mem(priv,
 170                                            disable_ptr + (i * sizeof(u32)),
 171                                            evt_disable[i]);
 172
 173         } else {
 174                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 175                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 176                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 177                                disable_ptr, array_size);
 178         }
 179
 180 }
 181
 182 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 183 {
 184         int idx;
 185
 186         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 187                 if (iwl3945_rates[idx].plcp == plcp)
 188                         return idx;
 189         return -1;
 190 }
 191
 192 #ifdef CONFIG_IWLWIFI_DEBUG
 193 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 194
 195 static const char *iwl3945_get_tx_fail_reason(u32 status)
 196 {
 197         switch (status & TX_STATUS_MSK) {
 198         case TX_STATUS_SUCCESS:
 199                 return "SUCCESS";
 200                 TX_STATUS_ENTRY(SHORT_LIMIT);
 201                 TX_STATUS_ENTRY(LONG_LIMIT);
 202                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 203                 TX_STATUS_ENTRY(MGMNT_ABORT);
 204                 TX_STATUS_ENTRY(NEXT_FRAG);
 205                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 206                 TX_STATUS_ENTRY(DEST_PS);
 207                 TX_STATUS_ENTRY(ABORTED);
 208                 TX_STATUS_ENTRY(BT_RETRY);
 209                 TX_STATUS_ENTRY(STA_INVALID);
 210                 TX_STATUS_ENTRY(FRAG_DROPPED);
 211                 TX_STATUS_ENTRY(TID_DISABLE);
 212                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 213                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 214                 TX_STATUS_ENTRY(TX_LOCKED);
 215                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 216         }
 217
 218         return "UNKNOWN";
 219 }
 220 #else
 221 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 222 {
 223         return "";
 224 }
 225 #endif
 226
 227 /*
 228  * get ieee prev rate from rate scale table.
 229  * for A and B mode we need to overright prev
 230  * value
 231  */
 232 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 233 {
 234         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 235
 236         switch (priv->band) {
 237         case IEEE80211_BAND_5GHZ:
 238                 if (rate == IWL_RATE_12M_INDEX)
 239                         next_rate = IWL_RATE_9M_INDEX;
 240                 else if (rate == IWL_RATE_6M_INDEX)
 241                         next_rate = IWL_RATE_6M_INDEX;
 242                 break;
 243         case IEEE80211_BAND_2GHZ:
 244                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 245                     iwl_is_associated(priv)) {
 246                         if (rate == IWL_RATE_11M_INDEX)
 247                                 next_rate = IWL_RATE_5M_INDEX;
 248                 }
 249                 break;
 250
 251         default:
 252                 break;
 253         }
 254
 255         return next_rate;
 256 }
 257
 258
 259 /**
 260  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 261  *
 262  * When FW advances 'R' index, all entries between old and new 'R' index
 263  * need to be reclaimed. As result, some free space forms. If there is
 264  * enough free space (> low mark), wake the stack that feeds us.
 265  */
 266 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 267                                      int txq_id, int index)
 268 {
 269         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 270         struct iwl_queue *q = &txq->q;
 271         struct iwl_tx_info *tx_info;
 272
 273         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 274
 275         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 276                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 277
 278                 tx_info = &txq->txb[txq->q.read_ptr];
 279                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 280                 tx_info->skb[0] = NULL;
 281                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 282         }
 283
 284         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 285                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 286                         priv->mac80211_registered)
 287                 iwl_wake_queue(priv, txq_id);
 288 }
 289
 290 /**
 291  * iwl3945_rx_reply_tx - Handle Tx response
 292  */
 293 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 294                             struct iwl_rx_mem_buffer *rxb)
 295 {
 296         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 297         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 298         int txq_id = SEQ_TO_QUEUE(sequence);
 299         int index = SEQ_TO_INDEX(sequence);
 300         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 301         struct ieee80211_tx_info *info;
 302         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 303         u32  status = le32_to_cpu(tx_resp->status);
 304         int rate_idx;
 305         int fail;
 306
 307         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 308                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 309                           "is out of range [0-%d] %d %d\n", txq_id,
 310                           index, txq->q.n_bd, txq->q.write_ptr,
 311                           txq->q.read_ptr);
 312                 return;
 313         }
 314
 315         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 316         ieee80211_tx_info_clear_status(info);
 317
 318         /* Fill the MRR chain with some info about on-chip retransmissions */
 319         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 320         if (info->band == IEEE80211_BAND_5GHZ)
 321                 rate_idx -= IWL_FIRST_OFDM_RATE;
 322
 323         fail = tx_resp->failure_frame;
 324
 325         info->status.rates[0].idx = rate_idx;
 326         info->status.rates[0].count = fail + 1; /* add final attempt */
 327
 328         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 329         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 330                                 IEEE80211_TX_STAT_ACK : 0;
 331
 332         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 333                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 334                         tx_resp->rate, tx_resp->failure_frame);
 335
 336         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 337         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 338
 339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 340                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 341 }
 342
 343
 344
 345 /*****************************************************************************
 346  *
 347  * Intel PRO/Wireless 3945ABG/BG Network Connection
 348  *
 349  *  RX handler implementations
 350  *
 351  *****************************************************************************/
 352
 353 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 354                 struct iwl_rx_mem_buffer *rxb)
 355 {
 356         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 357         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 358                      (int)sizeof(struct iwl3945_notif_statistics),
 359                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 360
 361         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 362
 363         iwl_leds_background(priv);
 364
 365         priv->last_statistics_time = jiffies;
 366 }
 367
 368 /******************************************************************************
 369  *
 370  * Misc. internal state and helper functions
 371  *
 372  ******************************************************************************/
 373 #ifdef CONFIG_IWLWIFI_DEBUG
 374
 375 /**
 376  * iwl3945_report_frame - dump frame to syslog during debug sessions
 377  *
 378  * You may hack this function to show different aspects of received frames,
 379  * including selective frame dumps.
 380  * group100 parameter selects whether to show 1 out of 100 good frames.
 381  */
 382 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 383                       struct iwl_rx_packet *pkt,
 384                       struct ieee80211_hdr *header, int group100)
 385 {
 386         u32 to_us;
 387         u32 print_summary = 0;
 388         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 389         u32 hundred = 0;
 390         u32 dataframe = 0;
 391         __le16 fc;
 392         u16 seq_ctl;
 393         u16 channel;
 394         u16 phy_flags;
 395         u16 length;
 396         u16 status;
 397         u16 bcn_tmr;
 398         u32 tsf_low;
 399         u64 tsf;
 400         u8 rssi;
 401         u8 agc;
 402         u16 sig_avg;
 403         u16 noise_diff;
 404         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 405         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 406         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 407         u8 *data = IWL_RX_DATA(pkt);
 408
 409         /* MAC header */
 410         fc = header->frame_control;
 411         seq_ctl = le16_to_cpu(header->seq_ctrl);
 412
 413         /* metadata */
 414         channel = le16_to_cpu(rx_hdr->channel);
 415         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 416         length = le16_to_cpu(rx_hdr->len);
 417
 418         /* end-of-frame status and timestamp */
 419         status = le32_to_cpu(rx_end->status);
 420         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 421         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 422         tsf = le64_to_cpu(rx_end->timestamp);
 423
 424         /* signal statistics */
 425         rssi = rx_stats->rssi;
 426         agc = rx_stats->agc;
 427         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 428         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 429
 430         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 431
 432         /* if data frame is to us and all is good,
 433          *   (optionally) print summary for only 1 out of every 100 */
 434         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 435             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 436                 dataframe = 1;
 437                 if (!group100)
 438                         print_summary = 1;      /* print each frame */
 439                 else if (priv->framecnt_to_us < 100) {
 440                         priv->framecnt_to_us++;
 441                         print_summary = 0;
 442                 } else {
 443                         priv->framecnt_to_us = 0;
 444                         print_summary = 1;
 445                         hundred = 1;
 446                 }
 447         } else {
 448                 /* print summary for all other frames */
 449                 print_summary = 1;
 450         }
 451
 452         if (print_summary) {
 453                 char *title;
 454                 int rate;
 455
 456                 if (hundred)
 457                         title = "100Frames";
 458                 else if (ieee80211_has_retry(fc))
 459                         title = "Retry";
 460                 else if (ieee80211_is_assoc_resp(fc))
 461                         title = "AscRsp";
 462                 else if (ieee80211_is_reassoc_resp(fc))
 463                         title = "RasRsp";
 464                 else if (ieee80211_is_probe_resp(fc)) {
 465                         title = "PrbRsp";
 466                         print_dump = 1; /* dump frame contents */
 467                 } else if (ieee80211_is_beacon(fc)) {
 468                         title = "Beacon";
 469                         print_dump = 1; /* dump frame contents */
 470                 } else if (ieee80211_is_atim(fc))
 471                         title = "ATIM";
 472                 else if (ieee80211_is_auth(fc))
 473                         title = "Auth";
 474                 else if (ieee80211_is_deauth(fc))
 475                         title = "DeAuth";
 476                 else if (ieee80211_is_disassoc(fc))
 477                         title = "DisAssoc";
 478                 else
 479                         title = "Frame";
 480
 481                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 482                 if (rate == -1)
 483                         rate = 0;
 484                 else
 485                         rate = iwl3945_rates[rate].ieee / 2;
 486
 487                 /* print frame summary.
 488                  * MAC addresses show just the last byte (for brevity),
 489                  *    but you can hack it to show more, if you'd like to. */
 490                 if (dataframe)
 491                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 492                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 493                                      title, le16_to_cpu(fc), header->addr1[5],
 494                                      length, rssi, channel, rate);
 495                 else {
 496                         /* src/dst addresses assume managed mode */
 497                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 498                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 499                                      "phy=0x%02x, chnl=%d\n",
 500                                      title, le16_to_cpu(fc), header->addr1[5],
 501                                      header->addr3[5], rssi,
 502                                      tsf_low - priv->scan_start_tsf,
 503                                      phy_flags, channel);
 504                 }
 505         }
 506         if (print_dump)
 507                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 508 }
 509
 510 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 511                       struct iwl_rx_packet *pkt,
 512                       struct ieee80211_hdr *header, int group100)
 513 {
 514         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 515                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 516 }
 517
 518 #else
 519 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 520                       struct iwl_rx_packet *pkt,
 521                       struct ieee80211_hdr *header, int group100)
 522 {
 523 }
 524 #endif
 525
 526 /* This is necessary only for a number of statistics, see the caller. */
 527 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 528                 struct ieee80211_hdr *header)
 529 {
 530         /* Filter incoming packets to determine if they are targeted toward
 531          * this network, discarding packets coming from ourselves */
 532         switch (priv->iw_mode) {
 533         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 534                 /* packets to our IBSS update information */
 535                 return !compare_ether_addr(header->addr3, priv->bssid);
 536         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 537                 /* packets to our IBSS update information */
 538                 return !compare_ether_addr(header->addr2, priv->bssid);
 539         default:
 540                 return 1;
 541         }
 542 }
 543
 544 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 545                                    struct iwl_rx_mem_buffer *rxb,
 546                                    struct ieee80211_rx_status *stats)
 547 {
 548         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 549         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 550         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 551         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 552         short len = le16_to_cpu(rx_hdr->len);
 553
 554         /* We received data from the HW, so stop the watchdog */
 555         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 556                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 557                 return;
 558         }
 559
 560         /* We only process data packets if the interface is open */
 561         if (unlikely(!priv->is_open)) {
 562                 IWL_DEBUG_DROP_LIMIT(priv,
 563                         "Dropping packet while interface is not open.\n");
 564                 return;
 565         }
 566
 567         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 568         /* Set the size of the skb to the size of the frame */
 569         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 570
 571         if (!iwl3945_mod_params.sw_crypto)
 572                 iwl_set_decrypted_flag(priv,
 573                                        (struct ieee80211_hdr *)rxb->skb->data,
 574                                        le32_to_cpu(rx_end->status), stats);
 575
 576         iwl_update_stats(priv, false, hdr->frame_control, len);
 577
 578         memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
 579         ieee80211_rx_irqsafe(priv->hw, rxb->skb);
 580         rxb->skb = NULL;
 581 }
 582
 583 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 584
 585 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 586                                 struct iwl_rx_mem_buffer *rxb)
 587 {
 588         struct ieee80211_hdr *header;
 589         struct ieee80211_rx_status rx_status;
 590         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 591         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 592         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 593         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 594         int snr;
 595         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 596         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 597         u8 network_packet;
 598
 599         rx_status.flag = 0;
 600         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 601         rx_status.freq =
 602                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 603         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 604                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 605
 606         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 607         if (rx_status.band == IEEE80211_BAND_5GHZ)
 608                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 609
 610         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 611                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 612
 613         /* set the preamble flag if appropriate */
 614         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 615                 rx_status.flag |= RX_FLAG_SHORTPRE;
 616
 617         if ((unlikely(rx_stats->phy_count > 20))) {
 618                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 619                                 rx_stats->phy_count);
 620                 return;
 621         }
 622
 623         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 624             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 625                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 626                 return;
 627         }
 628
 629
 630
 631         /* Convert 3945's rssi indicator to dBm */
 632         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 633
 634         /* Set default noise value to -127 */
 635         if (priv->last_rx_noise == 0)
 636                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 637
 638         /* 3945 provides noise info for OFDM frames only.
 639          * sig_avg and noise_diff are measured by the 3945's digital signal
 640          *   processor (DSP), and indicate linear levels of signal level and
 641          *   distortion/noise within the packet preamble after
 642          *   automatic gain control (AGC).  sig_avg should stay fairly
 643          *   constant if the radio's AGC is working well.
 644          * Since these values are linear (not dB or dBm), linear
 645          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 646          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 647          *   to obtain noise level in dBm.
 648          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 649         if (rx_stats_noise_diff) {
 650                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 651                 rx_status.noise = rx_status.signal -
 652                                         iwl3945_calc_db_from_ratio(snr);
 653                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 654                                                          rx_status.noise);
 655
 656         /* If noise info not available, calculate signal quality indicator (%)
 657          *   using just the dBm signal level. */
 658         } else {
 659                 rx_status.noise = priv->last_rx_noise;
 660                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 661         }
 662
 663
 664         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 665                         rx_status.signal, rx_status.noise, rx_status.qual,
 666                         rx_stats_sig_avg, rx_stats_noise_diff);
 667
 668         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 669
 670         network_packet = iwl3945_is_network_packet(priv, header);
 671
 672         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 673                               network_packet ? '*' : ' ',
 674                               le16_to_cpu(rx_hdr->channel),
 675                               rx_status.signal, rx_status.signal,
 676                               rx_status.noise, rx_status.rate_idx);
 677
 678         /* Set "1" to report good data frames in groups of 100 */
 679         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 680         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 681
 682         if (network_packet) {
 683                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 684                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 685                 priv->last_rx_rssi = rx_status.signal;
 686                 priv->last_rx_noise = rx_status.noise;
 687         }
 688
 689         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 690 }
 691
 692 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 693                                      struct iwl_tx_queue *txq,
 694                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 695 {
 696         int count;
 697         struct iwl_queue *q;
 698         struct iwl3945_tfd *tfd, *tfd_tmp;
 699
 700         q = &txq->q;
 701         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 702         tfd = &tfd_tmp[q->write_ptr];
 703
 704         if (reset)
 705                 memset(tfd, 0, sizeof(*tfd));
 706
 707         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 708
 709         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 710                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 711                           NUM_TFD_CHUNKS);
 712                 return -EINVAL;
 713         }
 714
 715         tfd->tbs[count].addr = cpu_to_le32(addr);
 716         tfd->tbs[count].len = cpu_to_le32(len);
 717
 718         count++;
 719
 720         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 721                                          TFD_CTL_PAD_SET(pad));
 722
 723         return 0;
 724 }
 725
 726 /**
 727  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 728  *
 729  * Does NOT advance any indexes
 730  */
 731 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 732 {
 733         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 734         int index = txq->q.read_ptr;
 735         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 736         struct pci_dev *dev = priv->pci_dev;
 737         int i;
 738         int counter;
 739
 740         /* sanity check */
 741         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 742         if (counter > NUM_TFD_CHUNKS) {
 743                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 744                 /* @todo issue fatal error, it is quite serious situation */
 745                 return;
 746         }
 747
 748         /* Unmap tx_cmd */
 749         if (counter)
 750                 pci_unmap_single(dev,
 751                                 pci_unmap_addr(&txq->meta[index], mapping),
 752                                 pci_unmap_len(&txq->meta[index], len),
 753                                 PCI_DMA_TODEVICE);
 754
 755         /* unmap chunks if any */
 756
 757         for (i = 1; i < counter; i++) {
 758                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 759                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 760                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 761                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 762                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 763                                 /* Can be called from interrupt context */
 764                                 dev_kfree_skb_any(skb);
 765                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 766                         }
 767                 }
 768         }
 769         return ;
 770 }
 771
 772 /**
 773  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 774  *
 775 */
 776 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 777                                   struct iwl_device_cmd *cmd,
 778                                   struct ieee80211_tx_info *info,
 779                                   struct ieee80211_hdr *hdr,
 780                                   int sta_id, int tx_id)
 781 {
 782         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 783         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 784         u16 rate_mask;
 785         int rate;
 786         u8 rts_retry_limit;
 787         u8 data_retry_limit;
 788         __le32 tx_flags;
 789         __le16 fc = hdr->frame_control;
 790         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 791
 792         rate = iwl3945_rates[rate_index].plcp;
 793         tx_flags = tx->tx_flags;
 794
 795         /* We need to figure out how to get the sta->supp_rates while
 796          * in this running context */
 797         rate_mask = IWL_RATES_MASK;
 798
 799         if (tx_id >= IWL_CMD_QUEUE_NUM)
 800                 rts_retry_limit = 3;
 801         else
 802                 rts_retry_limit = 7;
 803
 804         if (ieee80211_is_probe_resp(fc)) {
 805                 data_retry_limit = 3;
 806                 if (data_retry_limit < rts_retry_limit)
 807                         rts_retry_limit = data_retry_limit;
 808         } else
 809                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 810
 811         if (priv->data_retry_limit != -1)
 812                 data_retry_limit = priv->data_retry_limit;
 813
 814         if (ieee80211_is_mgmt(fc)) {
 815                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 816                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 817                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 818                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 819                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 820                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 821                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 822                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 823                         }
 824                         break;
 825                 default:
 826                         break;
 827                 }
 828         }
 829
 830         tx->rts_retry_limit = rts_retry_limit;
 831         tx->data_retry_limit = data_retry_limit;
 832         tx->rate = rate;
 833         tx->tx_flags = tx_flags;
 834
 835         /* OFDM */
 836         tx->supp_rates[0] =
 837            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 838
 839         /* CCK */
 840         tx->supp_rates[1] = (rate_mask & 0xF);
 841
 842         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 843                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 844                        tx->rate, le32_to_cpu(tx->tx_flags),
 845                        tx->supp_rates[1], tx->supp_rates[0]);
 846 }
 847
 848 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 849 {
 850         unsigned long flags_spin;
 851         struct iwl_station_entry *station;
 852
 853         if (sta_id == IWL_INVALID_STATION)
 854                 return IWL_INVALID_STATION;
 855
 856         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 857         station = &priv->stations[sta_id];
 858
 859         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 860         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 861         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 862
 863         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 864
 865         iwl_send_add_sta(priv, &station->sta, flags);
 866         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 867                         sta_id, tx_rate);
 868         return sta_id;
 869 }
 870
 871 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 872 {
 873         if (src == IWL_PWR_SRC_VAUX) {
 874                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 875                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 876                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 877                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 878
 879                         iwl_poll_bit(priv, CSR_GPIO_IN,
 880                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 881                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 882                 }
 883         } else {
 884                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 885                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 886                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 887
 888                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 889                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 896 {
 897         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 898         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 899         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 900         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 901                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 902                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 903                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 904                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 905                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 906                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 907                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 908                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 909
 910         /* fake read to flush all prev I/O */
 911         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 912
 913         return 0;
 914 }
 915
 916 static int iwl3945_tx_reset(struct iwl_priv *priv)
 917 {
 918
 919         /* bypass mode */
 920         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 921
 922         /* RA 0 is active */
 923         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 924
 925         /* all 6 fifo are active */
 926         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 927
 928         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 929         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 930         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 931         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 932
 933         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 934                              priv->shared_phys);
 935
 936         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 937                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 938                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 939                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 940                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 941                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 942                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 943                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 944
 945
 946         return 0;
 947 }
 948
 949 /**
 950  * iwl3945_txq_ctx_reset - Reset TX queue context
 951  *
 952  * Destroys all DMA structures and initialize them again
 953  */
 954 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 955 {
 956         int rc;
 957         int txq_id, slots_num;
 958
 959         iwl3945_hw_txq_ctx_free(priv);
 960
 961         /* Tx CMD queue */
 962         rc = iwl3945_tx_reset(priv);
 963         if (rc)
 964                 goto error;
 965
 966         /* Tx queue(s) */
 967         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 968                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 969                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 970                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 971                                        txq_id);
 972                 if (rc) {
 973                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 974                         goto error;
 975                 }
 976         }
 977
 978         return rc;
 979
 980  error:
 981         iwl3945_hw_txq_ctx_free(priv);
 982         return rc;
 983 }
 984
 985 static int iwl3945_apm_init(struct iwl_priv *priv)
 986 {
 987         int ret;
 988
 989         iwl_power_initialize(priv);
 990
 991         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 992                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 993
 994         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 995         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 996                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 997
 998         /* set "initialization complete" bit to move adapter
 999         * D0U* --> D0A* state */
1000         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1001
1002         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1003                             CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1004         if (ret < 0) {
1005                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1006                 goto out;
1007         }
1008
1009         /* enable DMA */
1010         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1011                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1012
1013         udelay(20);
1014
1015         /* disable L1-Active */
1016         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1017                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1018
1019 out:
1020         return ret;
1021 }
1022
1023 static void iwl3945_nic_config(struct iwl_priv *priv)
1024 {
1025         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1026         unsigned long flags;
1027         u8 rev_id = 0;
1028
1029         spin_lock_irqsave(&priv->lock, flags);
1030
1031         /* Determine HW type */
1032         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1033
1034         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1035
1036         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1037                 IWL_DEBUG_INFO(priv, "RTP type \n");
1038         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1039                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1040                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1041                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1042         } else {
1043                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1044                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1045                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1046         }
1047
1048         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1049                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1050                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1051                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1052         } else
1053                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1054
1055         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1056                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1057                                eeprom->board_revision);
1058                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1059                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1060         } else {
1061                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1062                                eeprom->board_revision);
1063                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1064                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1065         }
1066
1067         if (eeprom->almgor_m_version <= 1) {
1068                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1069                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1070                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1071                                eeprom->almgor_m_version);
1072         } else {
1073                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1074                                eeprom->almgor_m_version);
1075                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1076                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1077         }
1078         spin_unlock_irqrestore(&priv->lock, flags);
1079
1080         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1081                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1082
1083         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1084                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1085 }
1086
1087 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1088 {
1089         int rc;
1090         unsigned long flags;
1091         struct iwl_rx_queue *rxq = &priv->rxq;
1092
1093         spin_lock_irqsave(&priv->lock, flags);
1094         priv->cfg->ops->lib->apm_ops.init(priv);
1095         spin_unlock_irqrestore(&priv->lock, flags);
1096
1097         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1098         if (rc)
1099                 return rc;
1100
1101         priv->cfg->ops->lib->apm_ops.config(priv);
1102
1103         /* Allocate the RX queue, or reset if it is already allocated */
1104         if (!rxq->bd) {
1105                 rc = iwl_rx_queue_alloc(priv);
1106                 if (rc) {
1107                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1108                         return -ENOMEM;
1109                 }
1110         } else
1111                 iwl3945_rx_queue_reset(priv, rxq);
1112
1113         iwl3945_rx_replenish(priv);
1114
1115         iwl3945_rx_init(priv, rxq);
1116
1117
1118         /* Look at using this instead:
1119         rxq->need_update = 1;
1120         iwl_rx_queue_update_write_ptr(priv, rxq);
1121         */
1122
1123         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1124
1125         rc = iwl3945_txq_ctx_reset(priv);
1126         if (rc)
1127                 return rc;
1128
1129         set_bit(STATUS_INIT, &priv->status);
1130
1131         return 0;
1132 }
1133
1134 /**
1135  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1136  *
1137  * Destroy all TX DMA queues and structures
1138  */
1139 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1140 {
1141         int txq_id;
1142
1143         /* Tx queues */
1144         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1145                 if (txq_id == IWL_CMD_QUEUE_NUM)
1146                         iwl_cmd_queue_free(priv);
1147                 else
1148                         iwl_tx_queue_free(priv, txq_id);
1149
1150 }
1151
1152 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1153 {
1154         int txq_id;
1155
1156         /* stop SCD */
1157         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1158
1159         /* reset TFD queues */
1160         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1161                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1162                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1163                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1164                                 1000);
1165         }
1166
1167         iwl3945_hw_txq_ctx_free(priv);
1168 }
1169
1170 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1171 {
1172         int ret = 0;
1173         unsigned long flags;
1174
1175         spin_lock_irqsave(&priv->lock, flags);
1176
1177         /* set stop master bit */
1178         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1179
1180         iwl_poll_direct_bit(priv, CSR_RESET,
1181                             CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1182
1183         if (ret < 0)
1184                 goto out;
1185
1186 out:
1187         spin_unlock_irqrestore(&priv->lock, flags);
1188         IWL_DEBUG_INFO(priv, "stop master\n");
1189
1190         return ret;
1191 }
1192
1193 static void iwl3945_apm_stop(struct iwl_priv *priv)
1194 {
1195         unsigned long flags;
1196
1197         iwl3945_apm_stop_master(priv);
1198
1199         spin_lock_irqsave(&priv->lock, flags);
1200
1201         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1202
1203         udelay(10);
1204         /* clear "init complete"  move adapter D0A* --> D0U state */
1205         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1206         spin_unlock_irqrestore(&priv->lock, flags);
1207 }
1208
1209 static int iwl3945_apm_reset(struct iwl_priv *priv)
1210 {
1211         iwl3945_apm_stop_master(priv);
1212
1213
1214         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1215         udelay(10);
1216
1217         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1218
1219         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1220                          CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1221
1222         iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1223                                 APMG_CLK_VAL_BSM_CLK_RQT);
1224
1225         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1226         iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1227                                         0xFFFFFFFF);
1228
1229         /* enable DMA */
1230         iwl_write_prph(priv, APMG_CLK_EN_REG,
1231                                 APMG_CLK_VAL_DMA_CLK_RQT |
1232                                 APMG_CLK_VAL_BSM_CLK_RQT);
1233         udelay(10);
1234
1235         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1236                                 APMG_PS_CTRL_VAL_RESET_REQ);
1237         udelay(5);
1238         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1239                                 APMG_PS_CTRL_VAL_RESET_REQ);
1240
1241         /* Clear the 'host command active' bit... */
1242         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1243
1244         wake_up_interruptible(&priv->wait_command_queue);
1245
1246         return 0;
1247 }
1248
1249 /**
1250  * iwl3945_hw_reg_adjust_power_by_temp
1251  * return index delta into power gain settings table
1252 */
1253 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1254 {
1255         return (new_reading - old_reading) * (-11) / 100;
1256 }
1257
1258 /**
1259  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1260  */
1261 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1262 {
1263         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1264 }
1265
1266 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1267 {
1268         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1269 }
1270
1271 /**
1272  * iwl3945_hw_reg_txpower_get_temperature
1273  * get the current temperature by reading from NIC
1274 */
1275 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1276 {
1277         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1278         int temperature;
1279
1280         temperature = iwl3945_hw_get_temperature(priv);
1281
1282         /* driver's okay range is -260 to +25.
1283          *   human readable okay range is 0 to +285 */
1284         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1285
1286         /* handle insane temp reading */
1287         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1288                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1289
1290                 /* if really really hot(?),
1291                  *   substitute the 3rd band/group's temp measured at factory */
1292                 if (priv->last_temperature > 100)
1293                         temperature = eeprom->groups[2].temperature;
1294                 else /* else use most recent "sane" value from driver */
1295                         temperature = priv->last_temperature;
1296         }
1297
1298         return temperature;     /* raw, not "human readable" */
1299 }
1300
1301 /* Adjust Txpower only if temperature variance is greater than threshold.
1302  *
1303  * Both are lower than older versions' 9 degrees */
1304 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1305
1306 /**
1307  * is_temp_calib_needed - determines if new calibration is needed
1308  *
1309  * records new temperature in tx_mgr->temperature.
1310  * replaces tx_mgr->last_temperature *only* if calib needed
1311  *    (assumes caller will actually do the calibration!). */
1312 static int is_temp_calib_needed(struct iwl_priv *priv)
1313 {
1314         int temp_diff;
1315
1316         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1317         temp_diff = priv->temperature - priv->last_temperature;
1318
1319         /* get absolute value */
1320         if (temp_diff < 0) {
1321                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1322                 temp_diff = -temp_diff;
1323         } else if (temp_diff == 0)
1324                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1325         else
1326                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1327
1328         /* if we don't need calibration, *don't* update last_temperature */
1329         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1330                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1331                 return 0;
1332         }
1333
1334         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1335
1336         /* assume that caller will actually do calib ...
1337          *   update the "last temperature" value */
1338         priv->last_temperature = priv->temperature;
1339         return 1;
1340 }
1341
1342 #define IWL_MAX_GAIN_ENTRIES 78
1343 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1344 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1345
1346 /* radio and DSP power table, each step is 1/2 dB.
1347  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1348 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1349         {
1350          {251, 127},            /* 2.4 GHz, highest power */
1351          {251, 127},
1352          {251, 127},
1353          {251, 127},
1354          {251, 125},
1355          {251, 110},
1356          {251, 105},
1357          {251, 98},
1358          {187, 125},
1359          {187, 115},
1360          {187, 108},
1361          {187, 99},
1362          {243, 119},
1363          {243, 111},
1364          {243, 105},
1365          {243, 97},
1366          {243, 92},
1367          {211, 106},
1368          {211, 100},
1369          {179, 120},
1370          {179, 113},
1371          {179, 107},
1372          {147, 125},
1373          {147, 119},
1374          {147, 112},
1375          {147, 106},
1376          {147, 101},
1377          {147, 97},
1378          {147, 91},
1379          {115, 107},
1380          {235, 121},
1381          {235, 115},
1382          {235, 109},
1383          {203, 127},
1384          {203, 121},
1385          {203, 115},
1386          {203, 108},
1387          {203, 102},
1388          {203, 96},
1389          {203, 92},
1390          {171, 110},
1391          {171, 104},
1392          {171, 98},
1393          {139, 116},
1394          {227, 125},
1395          {227, 119},
1396          {227, 113},
1397          {227, 107},
1398          {227, 101},
1399          {227, 96},
1400          {195, 113},
1401          {195, 106},
1402          {195, 102},
1403          {195, 95},
1404          {163, 113},
1405          {163, 106},
1406          {163, 102},
1407          {163, 95},
1408          {131, 113},
1409          {131, 106},
1410          {131, 102},
1411          {131, 95},
1412          {99, 113},
1413          {99, 106},
1414          {99, 102},
1415          {99, 95},
1416          {67, 113},
1417          {67, 106},
1418          {67, 102},
1419          {67, 95},
1420          {35, 113},
1421          {35, 106},
1422          {35, 102},
1423          {35, 95},
1424          {3, 113},
1425          {3, 106},
1426          {3, 102},
1427          {3, 95} },             /* 2.4 GHz, lowest power */
1428         {
1429          {251, 127},            /* 5.x GHz, highest power */
1430          {251, 120},
1431          {251, 114},
1432          {219, 119},
1433          {219, 101},
1434          {187, 113},
1435          {187, 102},
1436          {155, 114},
1437          {155, 103},
1438          {123, 117},
1439          {123, 107},
1440          {123, 99},
1441          {123, 92},
1442          {91, 108},
1443          {59, 125},
1444          {59, 118},
1445          {59, 109},
1446          {59, 102},
1447          {59, 96},
1448          {59, 90},
1449          {27, 104},
1450          {27, 98},
1451          {27, 92},
1452          {115, 118},
1453          {115, 111},
1454          {115, 104},
1455          {83, 126},
1456          {83, 121},
1457          {83, 113},
1458          {83, 105},
1459          {83, 99},
1460          {51, 118},
1461          {51, 111},
1462          {51, 104},
1463          {51, 98},
1464          {19, 116},
1465          {19, 109},
1466          {19, 102},
1467          {19, 98},
1468          {19, 93},
1469          {171, 113},
1470          {171, 107},
1471          {171, 99},
1472          {139, 120},
1473          {139, 113},
1474          {139, 107},
1475          {139, 99},
1476          {107, 120},
1477          {107, 113},
1478          {107, 107},
1479          {107, 99},
1480          {75, 120},
1481          {75, 113},
1482          {75, 107},
1483          {75, 99},
1484          {43, 120},
1485          {43, 113},
1486          {43, 107},
1487          {43, 99},
1488          {11, 120},
1489          {11, 113},
1490          {11, 107},
1491          {11, 99},
1492          {131, 107},
1493          {131, 99},
1494          {99, 120},
1495          {99, 113},
1496          {99, 107},
1497          {99, 99},
1498          {67, 120},
1499          {67, 113},
1500          {67, 107},
1501          {67, 99},
1502          {35, 120},
1503          {35, 113},
1504          {35, 107},
1505          {35, 99},
1506          {3, 120} }             /* 5.x GHz, lowest power */
1507 };
1508
1509 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1510 {
1511         if (index < 0)
1512                 return 0;
1513         if (index >= IWL_MAX_GAIN_ENTRIES)
1514                 return IWL_MAX_GAIN_ENTRIES - 1;
1515         return (u8) index;
1516 }
1517
1518 /* Kick off thermal recalibration check every 60 seconds */
1519 #define REG_RECALIB_PERIOD (60)
1520
1521 /**
1522  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1523  *
1524  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1525  * or 6 Mbit (OFDM) rates.
1526  */
1527 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1528                                s32 rate_index, const s8 *clip_pwrs,
1529                                struct iwl_channel_info *ch_info,
1530                                int band_index)
1531 {
1532         struct iwl3945_scan_power_info *scan_power_info;
1533         s8 power;
1534         u8 power_index;
1535
1536         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1537
1538         /* use this channel group's 6Mbit clipping/saturation pwr,
1539          *   but cap at regulatory scan power restriction (set during init
1540          *   based on eeprom channel data) for this channel.  */
1541         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1542
1543         /* further limit to user's max power preference.
1544          * FIXME:  Other spectrum management power limitations do not
1545          *   seem to apply?? */
1546         power = min(power, priv->tx_power_user_lmt);
1547         scan_power_info->requested_power = power;
1548
1549         /* find difference between new scan *power* and current "normal"
1550          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1551          *   current "normal" temperature-compensated Tx power *index* for
1552          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1553          *   *index*. */
1554         power_index = ch_info->power_info[rate_index].power_table_index
1555             - (power - ch_info->power_info
1556                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1557
1558         /* store reference index that we use when adjusting *all* scan
1559          *   powers.  So we can accommodate user (all channel) or spectrum
1560          *   management (single channel) power changes "between" temperature
1561          *   feedback compensation procedures.
1562          * don't force fit this reference index into gain table; it may be a
1563          *   negative number.  This will help avoid errors when we're at
1564          *   the lower bounds (highest gains, for warmest temperatures)
1565          *   of the table. */
1566
1567         /* don't exceed table bounds for "real" setting */
1568         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1569
1570         scan_power_info->power_table_index = power_index;
1571         scan_power_info->tpc.tx_gain =
1572             power_gain_table[band_index][power_index].tx_gain;
1573         scan_power_info->tpc.dsp_atten =
1574             power_gain_table[band_index][power_index].dsp_atten;
1575 }
1576
1577 /**
1578  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1579  *
1580  * Configures power settings for all rates for the current channel,
1581  * using values from channel info struct, and send to NIC
1582  */
1583 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1584 {
1585         int rate_idx, i;
1586         const struct iwl_channel_info *ch_info = NULL;
1587         struct iwl3945_txpowertable_cmd txpower = {
1588                 .channel = priv->active_rxon.channel,
1589         };
1590
1591         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1592         ch_info = iwl_get_channel_info(priv,
1593                                        priv->band,
1594                                        le16_to_cpu(priv->active_rxon.channel));
1595         if (!ch_info) {
1596                 IWL_ERR(priv,
1597                         "Failed to get channel info for channel %d [%d]\n",
1598                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1599                 return -EINVAL;
1600         }
1601
1602         if (!is_channel_valid(ch_info)) {
1603                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1604                                 "non-Tx channel.\n");
1605                 return 0;
1606         }
1607
1608         /* fill cmd with power settings for all rates for current channel */
1609         /* Fill OFDM rate */
1610         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1611              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1612
1613                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1614                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1615
1616                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1617                                 le16_to_cpu(txpower.channel),
1618                                 txpower.band,
1619                                 txpower.power[i].tpc.tx_gain,
1620                                 txpower.power[i].tpc.dsp_atten,
1621                                 txpower.power[i].rate);
1622         }
1623         /* Fill CCK rates */
1624         for (rate_idx = IWL_FIRST_CCK_RATE;
1625              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1626                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1627                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1628
1629                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1630                                 le16_to_cpu(txpower.channel),
1631                                 txpower.band,
1632                                 txpower.power[i].tpc.tx_gain,
1633                                 txpower.power[i].tpc.dsp_atten,
1634                                 txpower.power[i].rate);
1635         }
1636
1637         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1638                                 sizeof(struct iwl3945_txpowertable_cmd),
1639                                 &txpower);
1640
1641 }
1642
1643 /**
1644  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1645  * @ch_info: Channel to update.  Uses power_info.requested_power.
1646  *
1647  * Replace requested_power and base_power_index ch_info fields for
1648  * one channel.
1649  *
1650  * Called if user or spectrum management changes power preferences.
1651  * Takes into account h/w and modulation limitations (clip power).
1652  *
1653  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1654  *
1655  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1656  *       properly fill out the scan powers, and actual h/w gain settings,
1657  *       and send changes to NIC
1658  */
1659 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1660                              struct iwl_channel_info *ch_info)
1661 {
1662         struct iwl3945_channel_power_info *power_info;
1663         int power_changed = 0;
1664         int i;
1665         const s8 *clip_pwrs;
1666         int power;
1667
1668         /* Get this chnlgrp's rate-to-max/clip-powers table */
1669         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1670
1671         /* Get this channel's rate-to-current-power settings table */
1672         power_info = ch_info->power_info;
1673
1674         /* update OFDM Txpower settings */
1675         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1676              i++, ++power_info) {
1677                 int delta_idx;
1678
1679                 /* limit new power to be no more than h/w capability */
1680                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1681                 if (power == power_info->requested_power)
1682                         continue;
1683
1684                 /* find difference between old and new requested powers,
1685                  *    update base (non-temp-compensated) power index */
1686                 delta_idx = (power - power_info->requested_power) * 2;
1687                 power_info->base_power_index -= delta_idx;
1688
1689                 /* save new requested power value */
1690                 power_info->requested_power = power;
1691
1692                 power_changed = 1;
1693         }
1694
1695         /* update CCK Txpower settings, based on OFDM 12M setting ...
1696          *    ... all CCK power settings for a given channel are the *same*. */
1697         if (power_changed) {
1698                 power =
1699                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1700                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1701
1702                 /* do all CCK rates' iwl3945_channel_power_info structures */
1703                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1704                         power_info->requested_power = power;
1705                         power_info->base_power_index =
1706                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1707                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1708                         ++power_info;
1709                 }
1710         }
1711
1712         return 0;
1713 }
1714
1715 /**
1716  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1717  *
1718  * NOTE: Returned power limit may be less (but not more) than requested,
1719  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1720  *       (no consideration for h/w clipping limitations).
1721  */
1722 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1723 {
1724         s8 max_power;
1725
1726 #if 0
1727         /* if we're using TGd limits, use lower of TGd or EEPROM */
1728         if (ch_info->tgd_data.max_power != 0)
1729                 max_power = min(ch_info->tgd_data.max_power,
1730                                 ch_info->eeprom.max_power_avg);
1731
1732         /* else just use EEPROM limits */
1733         else
1734 #endif
1735                 max_power = ch_info->eeprom.max_power_avg;
1736
1737         return min(max_power, ch_info->max_power_avg);
1738 }
1739
1740 /**
1741  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1742  *
1743  * Compensate txpower settings of *all* channels for temperature.
1744  * This only accounts for the difference between current temperature
1745  *   and the factory calibration temperatures, and bases the new settings
1746  *   on the channel's base_power_index.
1747  *
1748  * If RxOn is "associated", this sends the new Txpower to NIC!
1749  */
1750 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1751 {
1752         struct iwl_channel_info *ch_info = NULL;
1753         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1754         int delta_index;
1755         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1756         u8 a_band;
1757         u8 rate_index;
1758         u8 scan_tbl_index;
1759         u8 i;
1760         int ref_temp;
1761         int temperature = priv->temperature;
1762
1763         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1764         for (i = 0; i < priv->channel_count; i++) {
1765                 ch_info = &priv->channel_info[i];
1766                 a_band = is_channel_a_band(ch_info);
1767
1768                 /* Get this chnlgrp's factory calibration temperature */
1769                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1770                     temperature;
1771
1772                 /* get power index adjustment based on current and factory
1773                  * temps */
1774                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1775                                                               ref_temp);
1776
1777                 /* set tx power value for all rates, OFDM and CCK */
1778                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1779                      rate_index++) {
1780                         int power_idx =
1781                             ch_info->power_info[rate_index].base_power_index;
1782
1783                         /* temperature compensate */
1784                         power_idx += delta_index;
1785
1786                         /* stay within table range */
1787                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1788                         ch_info->power_info[rate_index].
1789                             power_table_index = (u8) power_idx;
1790                         ch_info->power_info[rate_index].tpc =
1791                             power_gain_table[a_band][power_idx];
1792                 }
1793
1794                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1795                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1796
1797                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1798                 for (scan_tbl_index = 0;
1799                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1800                         s32 actual_index = (scan_tbl_index == 0) ?
1801                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1802                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1803                                            actual_index, clip_pwrs,
1804                                            ch_info, a_band);
1805                 }
1806         }
1807
1808         /* send Txpower command for current channel to ucode */
1809         return priv->cfg->ops->lib->send_tx_power(priv);
1810 }
1811
1812 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1813 {
1814         struct iwl_channel_info *ch_info;
1815         s8 max_power;
1816         u8 a_band;
1817         u8 i;
1818
1819         if (priv->tx_power_user_lmt == power) {
1820                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1821                                 "limit: %ddBm.\n", power);
1822                 return 0;
1823         }
1824
1825         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1826         priv->tx_power_user_lmt = power;
1827
1828         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1829
1830         for (i = 0; i < priv->channel_count; i++) {
1831                 ch_info = &priv->channel_info[i];
1832                 a_band = is_channel_a_band(ch_info);
1833
1834                 /* find minimum power of all user and regulatory constraints
1835                  *    (does not consider h/w clipping limitations) */
1836                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1837                 max_power = min(power, max_power);
1838                 if (max_power != ch_info->curr_txpow) {
1839                         ch_info->curr_txpow = max_power;
1840
1841                         /* this considers the h/w clipping limitations */
1842                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1843                 }
1844         }
1845
1846         /* update txpower settings for all channels,
1847          *   send to NIC if associated. */
1848         is_temp_calib_needed(priv);
1849         iwl3945_hw_reg_comp_txpower_temp(priv);
1850
1851         return 0;
1852 }
1853
1854 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1855 {
1856         int rc = 0;
1857         struct iwl_rx_packet *res = NULL;
1858         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1859         struct iwl_host_cmd cmd = {
1860                 .id = REPLY_RXON_ASSOC,
1861                 .len = sizeof(rxon_assoc),
1862                 .flags = CMD_WANT_SKB,
1863                 .data = &rxon_assoc,
1864         };
1865         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1866         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1867
1868         if ((rxon1->flags == rxon2->flags) &&
1869             (rxon1->filter_flags == rxon2->filter_flags) &&
1870             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1871             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1872                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1873                 return 0;
1874         }
1875
1876         rxon_assoc.flags = priv->staging_rxon.flags;
1877         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1878         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1879         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1880         rxon_assoc.reserved = 0;
1881
1882         rc = iwl_send_cmd_sync(priv, &cmd);
1883         if (rc)
1884                 return rc;
1885
1886         res = (struct iwl_rx_packet *)cmd.reply_skb->data;
1887         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1888                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1889                 rc = -EIO;
1890         }
1891
1892         priv->alloc_rxb_skb--;
1893         dev_kfree_skb_any(cmd.reply_skb);
1894
1895         return rc;
1896 }
1897
1898 /**
1899  * iwl3945_commit_rxon - commit staging_rxon to hardware
1900  *
1901  * The RXON command in staging_rxon is committed to the hardware and
1902  * the active_rxon structure is updated with the new data.  This
1903  * function correctly transitions out of the RXON_ASSOC_MSK state if
1904  * a HW tune is required based on the RXON structure changes.
1905  */
1906 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1907 {
1908         /* cast away the const for active_rxon in this function */
1909         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1910         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1911         int rc = 0;
1912         bool new_assoc =
1913                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1914
1915         if (!iwl_is_alive(priv))
1916                 return -1;
1917
1918         /* always get timestamp with Rx frame */
1919         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1920
1921         /* select antenna */
1922         staging_rxon->flags &=
1923             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1924         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1925
1926         rc = iwl_check_rxon_cmd(priv);
1927         if (rc) {
1928                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1929                 return -EINVAL;
1930         }
1931
1932         /* If we don't need to send a full RXON, we can use
1933          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1934          * and other flags for the current radio configuration. */
1935         if (!iwl_full_rxon_required(priv)) {
1936                 rc = iwl_send_rxon_assoc(priv);
1937                 if (rc) {
1938                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1939                                   "configuration (%d).\n", rc);
1940                         return rc;
1941                 }
1942
1943                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1944
1945                 return 0;
1946         }
1947
1948         /* If we are currently associated and the new config requires
1949          * an RXON_ASSOC and the new config wants the associated mask enabled,
1950          * we must clear the associated from the active configuration
1951          * before we apply the new config */
1952         if (iwl_is_associated(priv) && new_assoc) {
1953                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1954                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1955
1956                 /*
1957                  * reserved4 and 5 could have been filled by the iwlcore code.
1958                  * Let's clear them before pushing to the 3945.
1959                  */
1960                 active_rxon->reserved4 = 0;
1961                 active_rxon->reserved5 = 0;
1962                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1963                                       sizeof(struct iwl3945_rxon_cmd),
1964                                       &priv->active_rxon);
1965
1966                 /* If the mask clearing failed then we set
1967                  * active_rxon back to what it was previously */
1968                 if (rc) {
1969                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1970                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1971                                   "configuration (%d).\n", rc);
1972                         return rc;
1973                 }
1974         }
1975
1976         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1977                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1978                        "* channel = %d\n"
1979                        "* bssid = %pM\n",
1980                        (new_assoc ? "" : "out"),
1981                        le16_to_cpu(staging_rxon->channel),
1982                        staging_rxon->bssid_addr);
1983
1984         /*
1985          * reserved4 and 5 could have been filled by the iwlcore code.
1986          * Let's clear them before pushing to the 3945.
1987          */
1988         staging_rxon->reserved4 = 0;
1989         staging_rxon->reserved5 = 0;
1990
1991         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1992
1993         /* Apply the new configuration */
1994         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1995                               sizeof(struct iwl3945_rxon_cmd),
1996                               staging_rxon);
1997         if (rc) {
1998                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1999                 return rc;
2000         }
2001
2002         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
2003
2004         iwl_clear_stations_table(priv);
2005
2006         /* If we issue a new RXON command which required a tune then we must
2007          * send a new TXPOWER command or we won't be able to Tx any frames */
2008         rc = priv->cfg->ops->lib->send_tx_power(priv);
2009         if (rc) {
2010                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
2011                 return rc;
2012         }
2013
2014         /* Add the broadcast address so we can send broadcast frames */
2015         if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
2016             IWL_INVALID_STATION) {
2017                 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2018                 return -EIO;
2019         }
2020
2021         /* If we have set the ASSOC_MSK and we are in BSS mode then
2022          * add the IWL_AP_ID to the station rate table */
2023         if (iwl_is_associated(priv) &&
2024             (priv->iw_mode == NL80211_IFTYPE_STATION))
2025                 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
2026                                 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
2027                         IWL_ERR(priv, "Error adding AP address for transmit\n");
2028                         return -EIO;
2029                 }
2030
2031         /* Init the hardware's rate fallback order based on the band */
2032         rc = iwl3945_init_hw_rate_table(priv);
2033         if (rc) {
2034                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2035                 return -EIO;
2036         }
2037
2038         return 0;
2039 }
2040
2041 /* will add 3945 channel switch cmd handling later */
2042 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2043 {
2044         return 0;
2045 }
2046
2047 /**
2048  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
2049  *
2050  * -- reset periodic timer
2051  * -- see if temp has changed enough to warrant re-calibration ... if so:
2052  *     -- correct coeffs for temp (can reset temp timer)
2053  *     -- save this temp as "last",
2054  *     -- send new set of gain settings to NIC
2055  * NOTE:  This should continue working, even when we're not associated,
2056  *   so we can keep our internal table of scan powers current. */
2057 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2058 {
2059         /* This will kick in the "brute force"
2060          * iwl3945_hw_reg_comp_txpower_temp() below */
2061         if (!is_temp_calib_needed(priv))
2062                 goto reschedule;
2063
2064         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2065          * This is based *only* on current temperature,
2066          * ignoring any previous power measurements */
2067         iwl3945_hw_reg_comp_txpower_temp(priv);
2068
2069  reschedule:
2070         queue_delayed_work(priv->workqueue,
2071                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2072 }
2073
2074 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2075 {
2076         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2077                                              thermal_periodic.work);
2078
2079         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2080                 return;
2081
2082         mutex_lock(&priv->mutex);
2083         iwl3945_reg_txpower_periodic(priv);
2084         mutex_unlock(&priv->mutex);
2085 }
2086
2087 /**
2088  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2089  *                                 for the channel.
2090  *
2091  * This function is used when initializing channel-info structs.
2092  *
2093  * NOTE: These channel groups do *NOT* match the bands above!
2094  *       These channel groups are based on factory-tested channels;
2095  *       on A-band, EEPROM's "group frequency" entries represent the top
2096  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2097  */
2098 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2099                                        const struct iwl_channel_info *ch_info)
2100 {
2101         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2102         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2103         u8 group;
2104         u16 group_index = 0;    /* based on factory calib frequencies */
2105         u8 grp_channel;
2106
2107         /* Find the group index for the channel ... don't use index 1(?) */
2108         if (is_channel_a_band(ch_info)) {
2109                 for (group = 1; group < 5; group++) {
2110                         grp_channel = ch_grp[group].group_channel;
2111                         if (ch_info->channel <= grp_channel) {
2112                                 group_index = group;
2113                                 break;
2114                         }
2115                 }
2116                 /* group 4 has a few channels *above* its factory cal freq */
2117                 if (group == 5)
2118                         group_index = 4;
2119         } else
2120                 group_index = 0;        /* 2.4 GHz, group 0 */
2121
2122         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2123                         group_index);
2124         return group_index;
2125 }
2126
2127 /**
2128  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2129  *
2130  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2131  *   into radio/DSP gain settings table for requested power.
2132  */
2133 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2134                                        s8 requested_power,
2135                                        s32 setting_index, s32 *new_index)
2136 {
2137         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2138         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2139         s32 index0, index1;
2140         s32 power = 2 * requested_power;
2141         s32 i;
2142         const struct iwl3945_eeprom_txpower_sample *samples;
2143         s32 gains0, gains1;
2144         s32 res;
2145         s32 denominator;
2146
2147         chnl_grp = &eeprom->groups[setting_index];
2148         samples = chnl_grp->samples;
2149         for (i = 0; i < 5; i++) {
2150                 if (power == samples[i].power) {
2151                         *new_index = samples[i].gain_index;
2152                         return 0;
2153                 }
2154         }
2155
2156         if (power > samples[1].power) {
2157                 index0 = 0;
2158                 index1 = 1;
2159         } else if (power > samples[2].power) {
2160                 index0 = 1;
2161                 index1 = 2;
2162         } else if (power > samples[3].power) {
2163                 index0 = 2;
2164                 index1 = 3;
2165         } else {
2166                 index0 = 3;
2167                 index1 = 4;
2168         }
2169
2170         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2171         if (denominator == 0)
2172                 return -EINVAL;
2173         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2174         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2175         res = gains0 + (gains1 - gains0) *
2176             ((s32) power - (s32) samples[index0].power) / denominator +
2177             (1 << 18);
2178         *new_index = res >> 19;
2179         return 0;
2180 }
2181
2182 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2183 {
2184         u32 i;
2185         s32 rate_index;
2186         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2187         const struct iwl3945_eeprom_txpower_group *group;
2188
2189         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2190
2191         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2192                 s8 *clip_pwrs;  /* table of power levels for each rate */
2193                 s8 satur_pwr;   /* saturation power for each chnl group */
2194                 group = &eeprom->groups[i];
2195
2196                 /* sanity check on factory saturation power value */
2197                 if (group->saturation_power < 40) {
2198                         IWL_WARN(priv, "Error: saturation power is %d, "
2199                                     "less than minimum expected 40\n",
2200                                     group->saturation_power);
2201                         return;
2202                 }
2203
2204                 /*
2205                  * Derive requested power levels for each rate, based on
2206                  *   hardware capabilities (saturation power for band).
2207                  * Basic value is 3dB down from saturation, with further
2208                  *   power reductions for highest 3 data rates.  These
2209                  *   backoffs provide headroom for high rate modulation
2210                  *   power peaks, without too much distortion (clipping).
2211                  */
2212                 /* we'll fill in this array with h/w max power levels */
2213                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2214
2215                 /* divide factory saturation power by 2 to find -3dB level */
2216                 satur_pwr = (s8) (group->saturation_power >> 1);
2217
2218                 /* fill in channel group's nominal powers for each rate */
2219                 for (rate_index = 0;
2220                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2221                         switch (rate_index) {
2222                         case IWL_RATE_36M_INDEX_TABLE:
2223                                 if (i == 0)     /* B/G */
2224                                         *clip_pwrs = satur_pwr;
2225                                 else    /* A */
2226                                         *clip_pwrs = satur_pwr - 5;
2227                                 break;
2228                         case IWL_RATE_48M_INDEX_TABLE:
2229                                 if (i == 0)
2230                                         *clip_pwrs = satur_pwr - 7;
2231                                 else
2232                                         *clip_pwrs = satur_pwr - 10;
2233                                 break;
2234                         case IWL_RATE_54M_INDEX_TABLE:
2235                                 if (i == 0)
2236                                         *clip_pwrs = satur_pwr - 9;
2237                                 else
2238                                         *clip_pwrs = satur_pwr - 12;
2239                                 break;
2240                         default:
2241                                 *clip_pwrs = satur_pwr;
2242                                 break;
2243                         }
2244                 }
2245         }
2246 }
2247
2248 /**
2249  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2250  *
2251  * Second pass (during init) to set up priv->channel_info
2252  *
2253  * Set up Tx-power settings in our channel info database for each VALID
2254  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2255  * and current temperature.
2256  *
2257  * Since this is based on current temperature (at init time), these values may
2258  * not be valid for very long, but it gives us a starting/default point,
2259  * and allows us to active (i.e. using Tx) scan.
2260  *
2261  * This does *not* write values to NIC, just sets up our internal table.
2262  */
2263 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2264 {
2265         struct iwl_channel_info *ch_info = NULL;
2266         struct iwl3945_channel_power_info *pwr_info;
2267         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2268         int delta_index;
2269         u8 rate_index;
2270         u8 scan_tbl_index;
2271         const s8 *clip_pwrs;    /* array of power levels for each rate */
2272         u8 gain, dsp_atten;
2273         s8 power;
2274         u8 pwr_index, base_pwr_index, a_band;
2275         u8 i;
2276         int temperature;
2277
2278         /* save temperature reference,
2279          *   so we can determine next time to calibrate */
2280         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2281         priv->last_temperature = temperature;
2282
2283         iwl3945_hw_reg_init_channel_groups(priv);
2284
2285         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2286         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2287              i++, ch_info++) {
2288                 a_band = is_channel_a_band(ch_info);
2289                 if (!is_channel_valid(ch_info))
2290                         continue;
2291
2292                 /* find this channel's channel group (*not* "band") index */
2293                 ch_info->group_index =
2294                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2295
2296                 /* Get this chnlgrp's rate->max/clip-powers table */
2297                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2298
2299                 /* calculate power index *adjustment* value according to
2300                  *  diff between current temperature and factory temperature */
2301                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2302                                 eeprom->groups[ch_info->group_index].
2303                                 temperature);
2304
2305                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2306                                 ch_info->channel, delta_index, temperature +
2307                                 IWL_TEMP_CONVERT);
2308
2309                 /* set tx power value for all OFDM rates */
2310                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2311                      rate_index++) {
2312                         s32 uninitialized_var(power_idx);
2313                         int rc;
2314
2315                         /* use channel group's clip-power table,
2316                          *   but don't exceed channel's max power */
2317                         s8 pwr = min(ch_info->max_power_avg,
2318                                      clip_pwrs[rate_index]);
2319
2320                         pwr_info = &ch_info->power_info[rate_index];
2321
2322                         /* get base (i.e. at factory-measured temperature)
2323                          *    power table index for this rate's power */
2324                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2325                                                          ch_info->group_index,
2326                                                          &power_idx);
2327                         if (rc) {
2328                                 IWL_ERR(priv, "Invalid power index\n");
2329                                 return rc;
2330                         }
2331                         pwr_info->base_power_index = (u8) power_idx;
2332
2333                         /* temperature compensate */
2334                         power_idx += delta_index;
2335
2336                         /* stay within range of gain table */
2337                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2338
2339                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2340                         pwr_info->requested_power = pwr;
2341                         pwr_info->power_table_index = (u8) power_idx;
2342                         pwr_info->tpc.tx_gain =
2343                             power_gain_table[a_band][power_idx].tx_gain;
2344                         pwr_info->tpc.dsp_atten =
2345                             power_gain_table[a_band][power_idx].dsp_atten;
2346                 }
2347
2348                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2349                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2350                 power = pwr_info->requested_power +
2351                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2352                 pwr_index = pwr_info->power_table_index +
2353                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2354                 base_pwr_index = pwr_info->base_power_index +
2355                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2356
2357                 /* stay within table range */
2358                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2359                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2360                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2361
2362                 /* fill each CCK rate's iwl3945_channel_power_info structure
2363                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2364                  * NOTE:  CCK rates start at end of OFDM rates! */
2365                 for (rate_index = 0;
2366                      rate_index < IWL_CCK_RATES; rate_index++) {
2367                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2368                         pwr_info->requested_power = power;
2369                         pwr_info->power_table_index = pwr_index;
2370                         pwr_info->base_power_index = base_pwr_index;
2371                         pwr_info->tpc.tx_gain = gain;
2372                         pwr_info->tpc.dsp_atten = dsp_atten;
2373                 }
2374
2375                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2376                 for (scan_tbl_index = 0;
2377                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2378                         s32 actual_index = (scan_tbl_index == 0) ?
2379                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2380                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2381                                 actual_index, clip_pwrs, ch_info, a_band);
2382                 }
2383         }
2384
2385         return 0;
2386 }
2387
2388 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2389 {
2390         int rc;
2391
2392         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2393         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2394                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2395         if (rc < 0)
2396                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2397
2398         return 0;
2399 }
2400
2401 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2402 {
2403         int txq_id = txq->q.id;
2404
2405         struct iwl3945_shared *shared_data = priv->shared_virt;
2406
2407         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2408
2409         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2410         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2411
2412         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2413                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2414                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2415                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2416                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2417                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2418
2419         /* fake read to flush all prev. writes */
2420         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2421
2422         return 0;
2423 }
2424
2425 /*
2426  * HCMD utils
2427  */
2428 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2429 {
2430         switch (cmd_id) {
2431         case REPLY_RXON:
2432                 return sizeof(struct iwl3945_rxon_cmd);
2433         case POWER_TABLE_CMD:
2434                 return sizeof(struct iwl3945_powertable_cmd);
2435         default:
2436                 return len;
2437         }
2438 }
2439
2440
2441 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2442 {
2443         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2444         addsta->mode = cmd->mode;
2445         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2446         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2447         addsta->station_flags = cmd->station_flags;
2448         addsta->station_flags_msk = cmd->station_flags_msk;
2449         addsta->tid_disable_tx = cpu_to_le16(0);
2450         addsta->rate_n_flags = cmd->rate_n_flags;
2451         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2452         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2453         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2454
2455         return (u16)sizeof(struct iwl3945_addsta_cmd);
2456 }
2457
2458
2459 /**
2460  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2461  */
2462 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2463 {
2464         int rc, i, index, prev_index;
2465         struct iwl3945_rate_scaling_cmd rate_cmd = {
2466                 .reserved = {0, 0, 0},
2467         };
2468         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2469
2470         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2471                 index = iwl3945_rates[i].table_rs_index;
2472
2473                 table[index].rate_n_flags =
2474                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2475                 table[index].try_cnt = priv->retry_rate;
2476                 prev_index = iwl3945_get_prev_ieee_rate(i);
2477                 table[index].next_rate_index =
2478                                 iwl3945_rates[prev_index].table_rs_index;
2479         }
2480
2481         switch (priv->band) {
2482         case IEEE80211_BAND_5GHZ:
2483                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2484                 /* If one of the following CCK rates is used,
2485                  * have it fall back to the 6M OFDM rate */
2486                 for (i = IWL_RATE_1M_INDEX_TABLE;
2487                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2488                         table[i].next_rate_index =
2489                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2490
2491                 /* Don't fall back to CCK rates */
2492                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2493                                                 IWL_RATE_9M_INDEX_TABLE;
2494
2495                 /* Don't drop out of OFDM rates */
2496                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2497                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2498                 break;
2499
2500         case IEEE80211_BAND_2GHZ:
2501                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2502                 /* If an OFDM rate is used, have it fall back to the
2503                  * 1M CCK rates */
2504
2505                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2506                     iwl_is_associated(priv)) {
2507
2508                         index = IWL_FIRST_CCK_RATE;
2509                         for (i = IWL_RATE_6M_INDEX_TABLE;
2510                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2511                                 table[i].next_rate_index =
2512                                         iwl3945_rates[index].table_rs_index;
2513
2514                         index = IWL_RATE_11M_INDEX_TABLE;
2515                         /* CCK shouldn't fall back to OFDM... */
2516                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2517                 }
2518                 break;
2519
2520         default:
2521                 WARN_ON(1);
2522                 break;
2523         }
2524
2525         /* Update the rate scaling for control frame Tx */
2526         rate_cmd.table_id = 0;
2527         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2528                               &rate_cmd);
2529         if (rc)
2530                 return rc;
2531
2532         /* Update the rate scaling for data frame Tx */
2533         rate_cmd.table_id = 1;
2534         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2535                                 &rate_cmd);
2536 }
2537
2538 /* Called when initializing driver */
2539 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2540 {
2541         memset((void *)&priv->hw_params, 0,
2542                sizeof(struct iwl_hw_params));
2543
2544         priv->shared_virt =
2545             pci_alloc_consistent(priv->pci_dev,
2546                                  sizeof(struct iwl3945_shared),
2547                                  &priv->shared_phys);
2548
2549         if (!priv->shared_virt) {
2550                 IWL_ERR(priv, "failed to allocate pci memory\n");
2551                 mutex_unlock(&priv->mutex);
2552                 return -ENOMEM;
2553         }
2554
2555         /* Assign number of Usable TX queues */
2556         priv->hw_params.max_txq_num = IWL39_NUM_QUEUES;
2557
2558         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2559         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2560         priv->hw_params.max_pkt_size = 2342;
2561         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2562         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2563         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2564         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2565
2566         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2567         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2568
2569         return 0;
2570 }
2571
2572 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2573                           struct iwl3945_frame *frame, u8 rate)
2574 {
2575         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2576         unsigned int frame_size;
2577
2578         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2579         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2580
2581         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2582         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2583
2584         frame_size = iwl3945_fill_beacon_frame(priv,
2585                                 tx_beacon_cmd->frame,
2586                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2587
2588         BUG_ON(frame_size > MAX_MPDU_SIZE);
2589         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2590
2591         tx_beacon_cmd->tx.rate = rate;
2592         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2593                                       TX_CMD_FLG_TSF_MSK);
2594
2595         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2596         tx_beacon_cmd->tx.supp_rates[0] =
2597                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2598
2599         tx_beacon_cmd->tx.supp_rates[1] =
2600                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2601
2602         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2603 }
2604
2605 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2606 {
2607         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2608         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2609 }
2610
2611 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2612 {
2613         INIT_DELAYED_WORK(&priv->thermal_periodic,
2614                           iwl3945_bg_reg_txpower_periodic);
2615 }
2616
2617 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2618 {
2619         cancel_delayed_work(&priv->thermal_periodic);
2620 }
2621
2622 /* check contents of special bootstrap uCode SRAM */
2623 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2624  {
2625         __le32 *image = priv->ucode_boot.v_addr;
2626         u32 len = priv->ucode_boot.len;
2627         u32 reg;
2628         u32 val;
2629
2630         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2631
2632         /* verify BSM SRAM contents */
2633         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2634         for (reg = BSM_SRAM_LOWER_BOUND;
2635              reg < BSM_SRAM_LOWER_BOUND + len;
2636              reg += sizeof(u32), image++) {
2637                 val = iwl_read_prph(priv, reg);
2638                 if (val != le32_to_cpu(*image)) {
2639                         IWL_ERR(priv, "BSM uCode verification failed at "
2640                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2641                                   BSM_SRAM_LOWER_BOUND,
2642                                   reg - BSM_SRAM_LOWER_BOUND, len,
2643                                   val, le32_to_cpu(*image));
2644                         return -EIO;
2645                 }
2646         }
2647
2648         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2649
2650         return 0;
2651 }
2652
2653
2654 /******************************************************************************
2655  *
2656  * EEPROM related functions
2657  *
2658  ******************************************************************************/
2659
2660 /*
2661  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2662  * embedded controller) as EEPROM reader; each read is a series of pulses
2663  * to/from the EEPROM chip, not a single event, so even reads could conflict
2664  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2665  * simply claims ownership, which should be safe when this function is called
2666  * (i.e. before loading uCode!).
2667  */
2668 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2669 {
2670         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2671         return 0;
2672 }
2673
2674
2675 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2676 {
2677         return;
2678 }
2679
2680  /**
2681   * iwl3945_load_bsm - Load bootstrap instructions
2682   *
2683   * BSM operation:
2684   *
2685   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2686   * in special SRAM that does not power down during RFKILL.  When powering back
2687   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2688   * the bootstrap program into the on-board processor, and starts it.
2689   *
2690   * The bootstrap program loads (via DMA) instructions and data for a new
2691   * program from host DRAM locations indicated by the host driver in the
2692   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2693   * automatically.
2694   *
2695   * When initializing the NIC, the host driver points the BSM to the
2696   * "initialize" uCode image.  This uCode sets up some internal data, then
2697   * notifies host via "initialize alive" that it is complete.
2698   *
2699   * The host then replaces the BSM_DRAM_* pointer values to point to the
2700   * normal runtime uCode instructions and a backup uCode data cache buffer
2701   * (filled initially with starting data values for the on-board processor),
2702   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2703   * which begins normal operation.
2704   *
2705   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2706   * the backup data cache in DRAM before SRAM is powered down.
2707   *
2708   * When powering back up, the BSM loads the bootstrap program.  This reloads
2709   * the runtime uCode instructions and the backup data cache into SRAM,
2710   * and re-launches the runtime uCode from where it left off.
2711   */
2712 static int iwl3945_load_bsm(struct iwl_priv *priv)
2713 {
2714         __le32 *image = priv->ucode_boot.v_addr;
2715         u32 len = priv->ucode_boot.len;
2716         dma_addr_t pinst;
2717         dma_addr_t pdata;
2718         u32 inst_len;
2719         u32 data_len;
2720         int rc;
2721         int i;
2722         u32 done;
2723         u32 reg_offset;
2724
2725         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2726
2727         /* make sure bootstrap program is no larger than BSM's SRAM size */
2728         if (len > IWL39_MAX_BSM_SIZE)
2729                 return -EINVAL;
2730
2731         /* Tell bootstrap uCode where to find the "Initialize" uCode
2732         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2733         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2734         *        after the "initialize" uCode has run, to point to
2735         *        runtime/protocol instructions and backup data cache. */
2736         pinst = priv->ucode_init.p_addr;
2737         pdata = priv->ucode_init_data.p_addr;
2738         inst_len = priv->ucode_init.len;
2739         data_len = priv->ucode_init_data.len;
2740
2741         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2742         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2743         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2744         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2745
2746         /* Fill BSM memory with bootstrap instructions */
2747         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2748              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2749              reg_offset += sizeof(u32), image++)
2750                 _iwl_write_prph(priv, reg_offset,
2751                                           le32_to_cpu(*image));
2752
2753         rc = iwl3945_verify_bsm(priv);
2754         if (rc)
2755                 return rc;
2756
2757         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2758         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2759         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2760                                  IWL39_RTC_INST_LOWER_BOUND);
2761         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2762
2763         /* Load bootstrap code into instruction SRAM now,
2764          *   to prepare to load "initialize" uCode */
2765         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2766                 BSM_WR_CTRL_REG_BIT_START);
2767
2768         /* Wait for load of bootstrap uCode to finish */
2769         for (i = 0; i < 100; i++) {
2770                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2771                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2772                         break;
2773                 udelay(10);
2774         }
2775         if (i < 100)
2776                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2777         else {
2778                 IWL_ERR(priv, "BSM write did not complete!\n");
2779                 return -EIO;
2780         }
2781
2782         /* Enable future boot loads whenever power management unit triggers it
2783          *   (e.g. when powering back up after power-save shutdown) */
2784         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2785                 BSM_WR_CTRL_REG_BIT_START_EN);
2786
2787         return 0;
2788 }
2789
2790 #define IWL3945_UCODE_GET(item)                                         \
2791 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2792                                     u32 api_ver)                        \
2793 {                                                                       \
2794         return le32_to_cpu(ucode->u.v1.item);                           \
2795 }
2796
2797 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2798 {
2799         return UCODE_HEADER_SIZE(1);
2800 }
2801 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2802                                    u32 api_ver)
2803 {
2804         return 0;
2805 }
2806 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2807                                   u32 api_ver)
2808 {
2809         return (u8 *) ucode->u.v1.data;
2810 }
2811
2812 IWL3945_UCODE_GET(inst_size);
2813 IWL3945_UCODE_GET(data_size);
2814 IWL3945_UCODE_GET(init_size);
2815 IWL3945_UCODE_GET(init_data_size);
2816 IWL3945_UCODE_GET(boot_size);
2817
2818 static struct iwl_hcmd_ops iwl3945_hcmd = {
2819         .rxon_assoc = iwl3945_send_rxon_assoc,
2820         .commit_rxon = iwl3945_commit_rxon,
2821 };
2822
2823 static struct iwl_ucode_ops iwl3945_ucode = {
2824         .get_header_size = iwl3945_ucode_get_header_size,
2825         .get_build = iwl3945_ucode_get_build,
2826         .get_inst_size = iwl3945_ucode_get_inst_size,
2827         .get_data_size = iwl3945_ucode_get_data_size,
2828         .get_init_size = iwl3945_ucode_get_init_size,
2829         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2830         .get_boot_size = iwl3945_ucode_get_boot_size,
2831         .get_data = iwl3945_ucode_get_data,
2832 };
2833
2834 static struct iwl_lib_ops iwl3945_lib = {
2835         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2836         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2837         .txq_init = iwl3945_hw_tx_queue_init,
2838         .load_ucode = iwl3945_load_bsm,
2839         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2840         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2841         .apm_ops = {
2842                 .init = iwl3945_apm_init,
2843                 .reset = iwl3945_apm_reset,
2844                 .stop = iwl3945_apm_stop,
2845                 .config = iwl3945_nic_config,
2846                 .set_pwr_src = iwl3945_set_pwr_src,
2847         },
2848         .eeprom_ops = {
2849                 .regulatory_bands = {
2850                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2851                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2852                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2853                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2854                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2855                         EEPROM_REGULATORY_BAND_NO_HT40,
2856                         EEPROM_REGULATORY_BAND_NO_HT40,
2857                 },
2858                 .verify_signature  = iwlcore_eeprom_verify_signature,
2859                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2860                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2861                 .query_addr = iwlcore_eeprom_query_addr,
2862         },
2863         .send_tx_power  = iwl3945_send_tx_power,
2864         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2865         .post_associate = iwl3945_post_associate,
2866         .isr = iwl_isr_legacy,
2867         .config_ap = iwl3945_config_ap,
2868 };
2869
2870 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2871         .get_hcmd_size = iwl3945_get_hcmd_size,
2872         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2873 };
2874
2875 static struct iwl_ops iwl3945_ops = {
2876         .ucode = &iwl3945_ucode,
2877         .lib = &iwl3945_lib,
2878         .hcmd = &iwl3945_hcmd,
2879         .utils = &iwl3945_hcmd_utils,
2880         .led = &iwl3945_led_ops,
2881 };
2882
2883 static struct iwl_cfg iwl3945_bg_cfg = {
2884         .name = "3945BG",
2885         .fw_name_pre = IWL3945_FW_PRE,
2886         .ucode_api_max = IWL3945_UCODE_API_MAX,
2887         .ucode_api_min = IWL3945_UCODE_API_MIN,
2888         .sku = IWL_SKU_G,
2889         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2890         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2891         .ops = &iwl3945_ops,
2892         .mod_params = &iwl3945_mod_params,
2893         .use_isr_legacy = true,
2894         .ht_greenfield_support = false,
2895         .led_compensation = 64,
2896 };
2897
2898 static struct iwl_cfg iwl3945_abg_cfg = {
2899         .name = "3945ABG",
2900         .fw_name_pre = IWL3945_FW_PRE,
2901         .ucode_api_max = IWL3945_UCODE_API_MAX,
2902         .ucode_api_min = IWL3945_UCODE_API_MIN,
2903         .sku = IWL_SKU_A|IWL_SKU_G,
2904         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2905         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2906         .ops = &iwl3945_ops,
2907         .mod_params = &iwl3945_mod_params,
2908         .use_isr_legacy = true,
2909         .ht_greenfield_support = false,
2910         .led_compensation = 64,
2911 };
2912
2913 struct pci_device_id iwl3945_hw_card_ids[] = {
2914         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2915         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2916         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2917         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2918         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2919         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2920         {0}
2921 };
2922
2923 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);