1 /******************************************************************************
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
41 #include "iwl-3945-core.h"
43 #include "iwl-helpers.h"
44 #include "iwl-3945-rs.h"
46 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
66 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
81 /* 1 = enable the iwl3945_disable_events() function */
82 #define IWL_EVT_DISABLE (0)
83 #define IWL_EVT_DISABLE_SIZE (1532/32)
86 * iwl3945_disable_events - Disable selected events in uCode event log
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
94 void iwl3945_disable_events(struct iwl3945_priv *priv)
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
157 ret = iwl3945_grab_nic_access(priv);
159 IWL_WARNING("Can not read from adapter at this time.\n");
163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
170 ret = iwl3945_grab_nic_access(priv);
171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
172 iwl3945_write_targ_mem(priv,
173 disable_ptr + (i * sizeof(u32)),
176 iwl3945_release_nic_access(priv);
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
186 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
190 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
191 if (iwl3945_rates[idx].plcp == plcp)
197 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
198 * @priv: eeprom and antenna fields are used to determine antenna flags
200 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
201 * priv->antenna specifies the antenna diversity mode:
203 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
204 * IWL_ANTENNA_MAIN - Force MAIN antenna
205 * IWL_ANTENNA_AUX - Force AUX antenna
207 __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
209 switch (priv->antenna) {
210 case IWL_ANTENNA_DIVERSITY:
213 case IWL_ANTENNA_MAIN:
214 if (priv->eeprom.antenna_switch_type)
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
218 case IWL_ANTENNA_AUX:
219 if (priv->eeprom.antenna_switch_type)
220 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
224 /* bad antenna selector value */
225 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
226 return 0; /* "diversity" is default if error */
229 #ifdef CONFIG_IWL3945_DEBUG
230 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
232 static const char *iwl3945_get_tx_fail_reason(u32 status)
234 switch (status & TX_STATUS_MSK) {
235 case TX_STATUS_SUCCESS:
237 TX_STATUS_ENTRY(SHORT_LIMIT);
238 TX_STATUS_ENTRY(LONG_LIMIT);
239 TX_STATUS_ENTRY(FIFO_UNDERRUN);
240 TX_STATUS_ENTRY(MGMNT_ABORT);
241 TX_STATUS_ENTRY(NEXT_FRAG);
242 TX_STATUS_ENTRY(LIFE_EXPIRE);
243 TX_STATUS_ENTRY(DEST_PS);
244 TX_STATUS_ENTRY(ABORTED);
245 TX_STATUS_ENTRY(BT_RETRY);
246 TX_STATUS_ENTRY(STA_INVALID);
247 TX_STATUS_ENTRY(FRAG_DROPPED);
248 TX_STATUS_ENTRY(TID_DISABLE);
249 TX_STATUS_ENTRY(FRAME_FLUSHED);
250 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
251 TX_STATUS_ENTRY(TX_LOCKED);
252 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
258 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
266 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
268 * When FW advances 'R' index, all entries between old and new 'R' index
269 * need to be reclaimed. As result, some free space forms. If there is
270 * enough free space (> low mark), wake the stack that feeds us.
272 static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
273 int txq_id, int index)
275 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
276 struct iwl3945_queue *q = &txq->q;
277 struct iwl3945_tx_info *tx_info;
279 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
281 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
282 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
284 tx_info = &txq->txb[txq->q.read_ptr];
285 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
286 tx_info->skb[0] = NULL;
287 iwl3945_hw_txq_free_tfd(priv, txq);
290 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
291 (txq_id != IWL_CMD_QUEUE_NUM) &&
292 priv->mac80211_registered)
293 ieee80211_wake_queue(priv->hw, txq_id);
297 * iwl3945_rx_reply_tx - Handle Tx response
299 static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
300 struct iwl3945_rx_mem_buffer *rxb)
302 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
303 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
304 int txq_id = SEQ_TO_QUEUE(sequence);
305 int index = SEQ_TO_INDEX(sequence);
306 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
307 struct ieee80211_tx_info *info;
308 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
309 u32 status = le32_to_cpu(tx_resp->status);
312 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
313 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
314 "is out of range [0-%d] %d %d\n", txq_id,
315 index, txq->q.n_bd, txq->q.write_ptr,
320 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
321 memset(&info->status, 0, sizeof(info->status));
323 info->status.retry_count = tx_resp->failure_frame;
324 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
325 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
326 IEEE80211_TX_STAT_ACK : 0;
328 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
329 txq_id, iwl3945_get_tx_fail_reason(status), status,
330 tx_resp->rate, tx_resp->failure_frame);
332 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
333 if (info->band == IEEE80211_BAND_5GHZ)
334 rate_idx -= IWL_FIRST_OFDM_RATE;
335 info->tx_rate_idx = rate_idx;
336 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
337 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
340 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
345 /*****************************************************************************
347 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 * RX handler implementations
351 *****************************************************************************/
353 void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
355 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
356 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
357 (int)sizeof(struct iwl3945_notif_statistics),
358 le32_to_cpu(pkt->len));
360 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
362 iwl3945_led_background(priv);
364 priv->last_statistics_time = jiffies;
367 /******************************************************************************
369 * Misc. internal state and helper functions
371 ******************************************************************************/
372 #ifdef CONFIG_IWL3945_DEBUG
375 * iwl3945_report_frame - dump frame to syslog during debug sessions
377 * You may hack this function to show different aspects of received frames,
378 * including selective frame dumps.
379 * group100 parameter selects whether to show 1 out of 100 good frames.
381 static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
382 struct iwl3945_rx_packet *pkt,
383 struct ieee80211_hdr *header, int group100)
386 u32 print_summary = 0;
387 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
403 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
404 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
405 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
406 u8 *data = IWL_RX_DATA(pkt);
409 fc = header->frame_control;
410 seq_ctl = le16_to_cpu(header->seq_ctrl);
413 channel = le16_to_cpu(rx_hdr->channel);
414 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
415 length = le16_to_cpu(rx_hdr->len);
417 /* end-of-frame status and timestamp */
418 status = le32_to_cpu(rx_end->status);
419 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
420 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
421 tsf = le64_to_cpu(rx_end->timestamp);
423 /* signal statistics */
424 rssi = rx_stats->rssi;
426 sig_avg = le16_to_cpu(rx_stats->sig_avg);
427 noise_diff = le16_to_cpu(rx_stats->noise_diff);
429 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
431 /* if data frame is to us and all is good,
432 * (optionally) print summary for only 1 out of every 100 */
433 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
434 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
437 print_summary = 1; /* print each frame */
438 else if (priv->framecnt_to_us < 100) {
439 priv->framecnt_to_us++;
442 priv->framecnt_to_us = 0;
447 /* print summary for all other frames */
457 else if (ieee80211_has_retry(fc))
459 else if (ieee80211_is_assoc_resp(fc))
461 else if (ieee80211_is_reassoc_resp(fc))
463 else if (ieee80211_is_probe_resp(fc)) {
465 print_dump = 1; /* dump frame contents */
466 } else if (ieee80211_is_beacon(fc)) {
468 print_dump = 1; /* dump frame contents */
469 } else if (ieee80211_is_atim(fc))
471 else if (ieee80211_is_auth(fc))
473 else if (ieee80211_is_deauth(fc))
475 else if (ieee80211_is_disassoc(fc))
480 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
484 rate = iwl3945_rates[rate].ieee / 2;
486 /* print frame summary.
487 * MAC addresses show just the last byte (for brevity),
488 * but you can hack it to show more, if you'd like to. */
490 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
491 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
492 title, le16_to_cpu(fc), header->addr1[5],
493 length, rssi, channel, rate);
495 /* src/dst addresses assume managed mode */
496 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
497 "src=0x%02x, rssi=%u, tim=%lu usec, "
498 "phy=0x%02x, chnl=%d\n",
499 title, le16_to_cpu(fc), header->addr1[5],
500 header->addr3[5], rssi,
501 tsf_low - priv->scan_start_tsf,
506 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
509 static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
510 struct iwl3945_rx_packet *pkt,
511 struct ieee80211_hdr *header, int group100)
516 /* This is necessary only for a number of statistics, see the caller. */
517 static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
518 struct ieee80211_hdr *header)
520 /* Filter incoming packets to determine if they are targeted toward
521 * this network, discarding packets coming from ourselves */
522 switch (priv->iw_mode) {
523 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
524 /* packets to our IBSS update information */
525 return !compare_ether_addr(header->addr3, priv->bssid);
526 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
527 /* packets to our IBSS update information */
528 return !compare_ether_addr(header->addr2, priv->bssid);
534 static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
535 struct iwl3945_rx_mem_buffer *rxb,
536 struct ieee80211_rx_status *stats)
538 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
539 #ifdef CONFIG_IWL3945_LEDS
540 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
542 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
543 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
544 short len = le16_to_cpu(rx_hdr->len);
546 /* We received data from the HW, so stop the watchdog */
547 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
548 IWL_DEBUG_DROP("Corruption detected!\n");
552 /* We only process data packets if the interface is open */
553 if (unlikely(!priv->is_open)) {
555 ("Dropping packet while interface is not open.\n");
559 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
560 /* Set the size of the skb to the size of the frame */
561 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
563 if (iwl3945_param_hwcrypto)
564 iwl3945_set_decrypted_flag(priv, rxb->skb,
565 le32_to_cpu(rx_end->status), stats);
567 #ifdef CONFIG_IWL3945_LEDS
568 if (ieee80211_is_data(hdr->frame_control))
569 priv->rxtxpackets += len;
571 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
575 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
577 static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
578 struct iwl3945_rx_mem_buffer *rxb)
580 struct ieee80211_hdr *header;
581 struct ieee80211_rx_status rx_status;
582 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
583 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
584 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
585 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
587 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
588 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
592 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
594 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
595 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
596 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
598 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
599 if (rx_status.band == IEEE80211_BAND_5GHZ)
600 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
602 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
603 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
605 /* set the preamble flag if appropriate */
606 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
607 rx_status.flag |= RX_FLAG_SHORTPRE;
609 if ((unlikely(rx_stats->phy_count > 20))) {
611 ("dsp size out of range [0,20]: "
612 "%d/n", rx_stats->phy_count);
616 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
617 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
618 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
624 /* Convert 3945's rssi indicator to dBm */
625 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
627 /* Set default noise value to -127 */
628 if (priv->last_rx_noise == 0)
629 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
631 /* 3945 provides noise info for OFDM frames only.
632 * sig_avg and noise_diff are measured by the 3945's digital signal
633 * processor (DSP), and indicate linear levels of signal level and
634 * distortion/noise within the packet preamble after
635 * automatic gain control (AGC). sig_avg should stay fairly
636 * constant if the radio's AGC is working well.
637 * Since these values are linear (not dB or dBm), linear
638 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
639 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
640 * to obtain noise level in dBm.
641 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
642 if (rx_stats_noise_diff) {
643 snr = rx_stats_sig_avg / rx_stats_noise_diff;
644 rx_status.noise = rx_status.signal -
645 iwl3945_calc_db_from_ratio(snr);
646 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
649 /* If noise info not available, calculate signal quality indicator (%)
650 * using just the dBm signal level. */
652 rx_status.noise = priv->last_rx_noise;
653 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
657 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
658 rx_status.signal, rx_status.noise, rx_status.qual,
659 rx_stats_sig_avg, rx_stats_noise_diff);
661 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
663 network_packet = iwl3945_is_network_packet(priv, header);
665 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
666 network_packet ? '*' : ' ',
667 le16_to_cpu(rx_hdr->channel),
668 rx_status.signal, rx_status.signal,
669 rx_status.noise, rx_status.rate_idx);
671 #ifdef CONFIG_IWL3945_DEBUG
672 if (iwl3945_debug_level & (IWL_DL_RX))
673 /* Set "1" to report good data frames in groups of 100 */
674 iwl3945_dbg_report_frame(priv, pkt, header, 1);
677 if (network_packet) {
678 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
679 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
680 priv->last_rx_rssi = rx_status.signal;
681 priv->last_rx_noise = rx_status.noise;
684 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
685 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
689 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
690 case IEEE80211_FTYPE_MGMT:
691 case IEEE80211_FTYPE_DATA:
694 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
699 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
700 dma_addr_t addr, u16 len)
704 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
706 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
707 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
709 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
710 IWL_ERROR("Error can not send more than %d chunks\n",
715 tfd->pa[count].addr = cpu_to_le32(addr);
716 tfd->pa[count].len = cpu_to_le32(len);
720 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
721 TFD_CTL_PAD_SET(pad));
727 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
729 * Does NOT advance any indexes
731 int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
733 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
734 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
735 struct pci_dev *dev = priv->pci_dev;
740 if (txq->q.id == IWL_CMD_QUEUE_NUM)
741 /* nothing to cleanup after for host commands */
745 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
746 if (counter > NUM_TFD_CHUNKS) {
747 IWL_ERROR("Too many chunks: %i\n", counter);
748 /* @todo issue fatal error, it is quite serious situation */
752 /* unmap chunks if any */
754 for (i = 1; i < counter; i++) {
755 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
756 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
757 if (txq->txb[txq->q.read_ptr].skb[0]) {
758 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
759 if (txq->txb[txq->q.read_ptr].skb[0]) {
760 /* Can be called from interrupt context */
761 dev_kfree_skb_any(skb);
762 txq->txb[txq->q.read_ptr].skb[0] = NULL;
769 u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
772 int ret = IWL_INVALID_STATION;
774 DECLARE_MAC_BUF(mac);
776 spin_lock_irqsave(&priv->sta_lock, flags);
777 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
778 if ((priv->stations[i].used) &&
780 (priv->stations[i].sta.sta.addr, addr))) {
785 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
786 print_mac(mac, addr), priv->num_stations);
788 spin_unlock_irqrestore(&priv->sta_lock, flags);
793 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
796 void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
797 struct iwl3945_cmd *cmd,
798 struct ieee80211_tx_info *info,
799 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
802 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
803 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
809 __le16 fc = hdr->frame_control;
811 rate = iwl3945_rates[rate_index].plcp;
812 tx_flags = cmd->cmd.tx.tx_flags;
814 /* We need to figure out how to get the sta->supp_rates while
815 * in this running context */
816 rate_mask = IWL_RATES_MASK;
818 spin_lock_irqsave(&priv->sta_lock, flags);
820 priv->stations[sta_id].current_rate.rate_n_flags = rate;
822 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
823 (sta_id != priv->hw_setting.bcast_sta_id) &&
824 (sta_id != IWL_MULTICAST_ID))
825 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
827 spin_unlock_irqrestore(&priv->sta_lock, flags);
829 if (tx_id >= IWL_CMD_QUEUE_NUM)
834 if (ieee80211_is_probe_resp(fc)) {
835 data_retry_limit = 3;
836 if (data_retry_limit < rts_retry_limit)
837 rts_retry_limit = data_retry_limit;
839 data_retry_limit = IWL_DEFAULT_TX_RETRY;
841 if (priv->data_retry_limit != -1)
842 data_retry_limit = priv->data_retry_limit;
844 if (ieee80211_is_mgmt(fc)) {
845 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
846 case cpu_to_le16(IEEE80211_STYPE_AUTH):
847 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
848 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
849 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
850 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
851 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
852 tx_flags |= TX_CMD_FLG_CTS_MSK;
860 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
861 cmd->cmd.tx.data_retry_limit = data_retry_limit;
862 cmd->cmd.tx.rate = rate;
863 cmd->cmd.tx.tx_flags = tx_flags;
866 cmd->cmd.tx.supp_rates[0] =
867 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
870 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
872 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
873 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
874 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
875 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
878 u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
880 unsigned long flags_spin;
881 struct iwl3945_station_entry *station;
883 if (sta_id == IWL_INVALID_STATION)
884 return IWL_INVALID_STATION;
886 spin_lock_irqsave(&priv->sta_lock, flags_spin);
887 station = &priv->stations[sta_id];
889 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
890 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
891 station->current_rate.rate_n_flags = tx_rate;
892 station->sta.mode = STA_CONTROL_MODIFY_MSK;
894 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
896 iwl3945_send_add_station(priv, &station->sta, flags);
897 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
902 static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
907 spin_lock_irqsave(&priv->lock, flags);
908 rc = iwl3945_grab_nic_access(priv);
910 spin_unlock_irqrestore(&priv->lock, flags);
917 rc = pci_read_config_dword(priv->pci_dev,
918 PCI_POWER_SOURCE, &val);
919 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
920 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
921 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
922 ~APMG_PS_CTRL_MSK_PWR_SRC);
923 iwl3945_release_nic_access(priv);
925 iwl3945_poll_bit(priv, CSR_GPIO_IN,
926 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
927 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
929 iwl3945_release_nic_access(priv);
931 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
932 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
933 ~APMG_PS_CTRL_MSK_PWR_SRC);
935 iwl3945_release_nic_access(priv);
936 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
937 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
939 spin_unlock_irqrestore(&priv->lock, flags);
944 static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
949 spin_lock_irqsave(&priv->lock, flags);
950 rc = iwl3945_grab_nic_access(priv);
952 spin_unlock_irqrestore(&priv->lock, flags);
956 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
957 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
958 priv->hw_setting.shared_phys +
959 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
960 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
961 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
962 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
963 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
964 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
965 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
966 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
967 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
968 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
969 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
971 /* fake read to flush all prev I/O */
972 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
974 iwl3945_release_nic_access(priv);
975 spin_unlock_irqrestore(&priv->lock, flags);
980 static int iwl3945_tx_reset(struct iwl3945_priv *priv)
985 spin_lock_irqsave(&priv->lock, flags);
986 rc = iwl3945_grab_nic_access(priv);
988 spin_unlock_irqrestore(&priv->lock, flags);
993 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
996 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
998 /* all 6 fifo are active */
999 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1001 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1002 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1003 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1004 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1006 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
1007 priv->hw_setting.shared_phys);
1009 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
1010 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1011 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1012 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1013 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1014 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1015 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1016 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1018 iwl3945_release_nic_access(priv);
1019 spin_unlock_irqrestore(&priv->lock, flags);
1025 * iwl3945_txq_ctx_reset - Reset TX queue context
1027 * Destroys all DMA structures and initialize them again
1029 static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
1032 int txq_id, slots_num;
1034 iwl3945_hw_txq_ctx_free(priv);
1037 rc = iwl3945_tx_reset(priv);
1042 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1043 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1044 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1045 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1048 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1056 iwl3945_hw_txq_ctx_free(priv);
1060 int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1064 unsigned long flags;
1065 struct iwl3945_rx_queue *rxq = &priv->rxq;
1067 iwl3945_power_init_handle(priv);
1069 spin_lock_irqsave(&priv->lock, flags);
1070 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1071 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1072 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1074 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1075 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1076 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1077 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1079 spin_unlock_irqrestore(&priv->lock, flags);
1080 IWL_DEBUG_INFO("Failed to init the card\n");
1084 rc = iwl3945_grab_nic_access(priv);
1086 spin_unlock_irqrestore(&priv->lock, flags);
1089 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1090 APMG_CLK_VAL_DMA_CLK_RQT |
1091 APMG_CLK_VAL_BSM_CLK_RQT);
1093 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1094 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1095 iwl3945_release_nic_access(priv);
1096 spin_unlock_irqrestore(&priv->lock, flags);
1098 /* Determine HW type */
1099 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1102 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1104 iwl3945_nic_set_pwr_src(priv, 1);
1105 spin_lock_irqsave(&priv->lock, flags);
1107 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1108 IWL_DEBUG_INFO("RTP type \n");
1109 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1110 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1111 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1112 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1114 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1115 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1116 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1119 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1120 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1121 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1122 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1124 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1126 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1127 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1128 priv->eeprom.board_revision);
1129 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1130 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1132 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1133 priv->eeprom.board_revision);
1134 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1135 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1138 if (priv->eeprom.almgor_m_version <= 1) {
1139 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1140 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1141 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1142 priv->eeprom.almgor_m_version);
1144 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1145 priv->eeprom.almgor_m_version);
1146 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1147 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1149 spin_unlock_irqrestore(&priv->lock, flags);
1151 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1152 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1154 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1155 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1157 /* Allocate the RX queue, or reset if it is already allocated */
1159 rc = iwl3945_rx_queue_alloc(priv);
1161 IWL_ERROR("Unable to initialize Rx queue\n");
1165 iwl3945_rx_queue_reset(priv, rxq);
1167 iwl3945_rx_replenish(priv);
1169 iwl3945_rx_init(priv, rxq);
1171 spin_lock_irqsave(&priv->lock, flags);
1173 /* Look at using this instead:
1174 rxq->need_update = 1;
1175 iwl3945_rx_queue_update_write_ptr(priv, rxq);
1178 rc = iwl3945_grab_nic_access(priv);
1180 spin_unlock_irqrestore(&priv->lock, flags);
1183 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1184 iwl3945_release_nic_access(priv);
1186 spin_unlock_irqrestore(&priv->lock, flags);
1188 rc = iwl3945_txq_ctx_reset(priv);
1192 set_bit(STATUS_INIT, &priv->status);
1198 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1200 * Destroy all TX DMA queues and structures
1202 void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
1207 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1208 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1211 void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1214 unsigned long flags;
1216 spin_lock_irqsave(&priv->lock, flags);
1217 if (iwl3945_grab_nic_access(priv)) {
1218 spin_unlock_irqrestore(&priv->lock, flags);
1219 iwl3945_hw_txq_ctx_free(priv);
1224 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
1226 /* reset TFD queues */
1227 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1228 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1229 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
1230 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1234 iwl3945_release_nic_access(priv);
1235 spin_unlock_irqrestore(&priv->lock, flags);
1237 iwl3945_hw_txq_ctx_free(priv);
1240 int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
1244 unsigned long flags;
1246 spin_lock_irqsave(&priv->lock, flags);
1248 /* set stop master bit */
1249 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1251 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
1253 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1254 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1255 IWL_DEBUG_INFO("Card in power save, master is already "
1258 rc = iwl3945_poll_bit(priv, CSR_RESET,
1259 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1260 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1262 spin_unlock_irqrestore(&priv->lock, flags);
1267 spin_unlock_irqrestore(&priv->lock, flags);
1268 IWL_DEBUG_INFO("stop master\n");
1273 int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
1276 unsigned long flags;
1278 iwl3945_hw_nic_stop_master(priv);
1280 spin_lock_irqsave(&priv->lock, flags);
1282 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1284 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1285 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1286 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1288 rc = iwl3945_grab_nic_access(priv);
1290 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
1291 APMG_CLK_VAL_BSM_CLK_RQT);
1295 iwl3945_set_bit(priv, CSR_GP_CNTRL,
1296 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1298 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1299 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
1303 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1304 APMG_CLK_VAL_DMA_CLK_RQT |
1305 APMG_CLK_VAL_BSM_CLK_RQT);
1308 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
1309 APMG_PS_CTRL_VAL_RESET_REQ);
1311 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1312 APMG_PS_CTRL_VAL_RESET_REQ);
1313 iwl3945_release_nic_access(priv);
1316 /* Clear the 'host command active' bit... */
1317 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1319 wake_up_interruptible(&priv->wait_command_queue);
1320 spin_unlock_irqrestore(&priv->lock, flags);
1326 * iwl3945_hw_reg_adjust_power_by_temp
1327 * return index delta into power gain settings table
1329 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1331 return (new_reading - old_reading) * (-11) / 100;
1335 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1337 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1339 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1342 int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
1344 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
1348 * iwl3945_hw_reg_txpower_get_temperature
1349 * get the current temperature by reading from NIC
1351 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1355 temperature = iwl3945_hw_get_temperature(priv);
1357 /* driver's okay range is -260 to +25.
1358 * human readable okay range is 0 to +285 */
1359 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1361 /* handle insane temp reading */
1362 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1363 IWL_ERROR("Error bad temperature value %d\n", temperature);
1365 /* if really really hot(?),
1366 * substitute the 3rd band/group's temp measured at factory */
1367 if (priv->last_temperature > 100)
1368 temperature = priv->eeprom.groups[2].temperature;
1369 else /* else use most recent "sane" value from driver */
1370 temperature = priv->last_temperature;
1373 return temperature; /* raw, not "human readable" */
1376 /* Adjust Txpower only if temperature variance is greater than threshold.
1378 * Both are lower than older versions' 9 degrees */
1379 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1382 * is_temp_calib_needed - determines if new calibration is needed
1384 * records new temperature in tx_mgr->temperature.
1385 * replaces tx_mgr->last_temperature *only* if calib needed
1386 * (assumes caller will actually do the calibration!). */
1387 static int is_temp_calib_needed(struct iwl3945_priv *priv)
1391 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1392 temp_diff = priv->temperature - priv->last_temperature;
1394 /* get absolute value */
1395 if (temp_diff < 0) {
1396 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1397 temp_diff = -temp_diff;
1398 } else if (temp_diff == 0)
1399 IWL_DEBUG_POWER("Same temp,\n");
1401 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1403 /* if we don't need calibration, *don't* update last_temperature */
1404 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1405 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1409 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1411 /* assume that caller will actually do calib ...
1412 * update the "last temperature" value */
1413 priv->last_temperature = priv->temperature;
1417 #define IWL_MAX_GAIN_ENTRIES 78
1418 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1419 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1421 /* radio and DSP power table, each step is 1/2 dB.
1422 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1423 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1425 {251, 127}, /* 2.4 GHz, highest power */
1502 {3, 95} }, /* 2.4 GHz, lowest power */
1504 {251, 127}, /* 5.x GHz, highest power */
1581 {3, 120} } /* 5.x GHz, lowest power */
1584 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1588 if (index >= IWL_MAX_GAIN_ENTRIES)
1589 return IWL_MAX_GAIN_ENTRIES - 1;
1593 /* Kick off thermal recalibration check every 60 seconds */
1594 #define REG_RECALIB_PERIOD (60)
1597 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1599 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1600 * or 6 Mbit (OFDM) rates.
1602 static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
1603 s32 rate_index, const s8 *clip_pwrs,
1604 struct iwl3945_channel_info *ch_info,
1607 struct iwl3945_scan_power_info *scan_power_info;
1611 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1613 /* use this channel group's 6Mbit clipping/saturation pwr,
1614 * but cap at regulatory scan power restriction (set during init
1615 * based on eeprom channel data) for this channel. */
1616 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1618 /* further limit to user's max power preference.
1619 * FIXME: Other spectrum management power limitations do not
1620 * seem to apply?? */
1621 power = min(power, priv->user_txpower_limit);
1622 scan_power_info->requested_power = power;
1624 /* find difference between new scan *power* and current "normal"
1625 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1626 * current "normal" temperature-compensated Tx power *index* for
1627 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1629 power_index = ch_info->power_info[rate_index].power_table_index
1630 - (power - ch_info->power_info
1631 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1633 /* store reference index that we use when adjusting *all* scan
1634 * powers. So we can accommodate user (all channel) or spectrum
1635 * management (single channel) power changes "between" temperature
1636 * feedback compensation procedures.
1637 * don't force fit this reference index into gain table; it may be a
1638 * negative number. This will help avoid errors when we're at
1639 * the lower bounds (highest gains, for warmest temperatures)
1642 /* don't exceed table bounds for "real" setting */
1643 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1645 scan_power_info->power_table_index = power_index;
1646 scan_power_info->tpc.tx_gain =
1647 power_gain_table[band_index][power_index].tx_gain;
1648 scan_power_info->tpc.dsp_atten =
1649 power_gain_table[band_index][power_index].dsp_atten;
1653 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1655 * Configures power settings for all rates for the current channel,
1656 * using values from channel info struct, and send to NIC
1658 int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1661 const struct iwl3945_channel_info *ch_info = NULL;
1662 struct iwl3945_txpowertable_cmd txpower = {
1663 .channel = priv->active_rxon.channel,
1666 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1667 ch_info = iwl3945_get_channel_info(priv,
1669 le16_to_cpu(priv->active_rxon.channel));
1672 ("Failed to get channel info for channel %d [%d]\n",
1673 le16_to_cpu(priv->active_rxon.channel), priv->band);
1677 if (!is_channel_valid(ch_info)) {
1678 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1679 "non-Tx channel.\n");
1683 /* fill cmd with power settings for all rates for current channel */
1684 /* Fill OFDM rate */
1685 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1686 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1688 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1689 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1691 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1692 le16_to_cpu(txpower.channel),
1694 txpower.power[i].tpc.tx_gain,
1695 txpower.power[i].tpc.dsp_atten,
1696 txpower.power[i].rate);
1698 /* Fill CCK rates */
1699 for (rate_idx = IWL_FIRST_CCK_RATE;
1700 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1701 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1702 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1704 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1705 le16_to_cpu(txpower.channel),
1707 txpower.power[i].tpc.tx_gain,
1708 txpower.power[i].tpc.dsp_atten,
1709 txpower.power[i].rate);
1712 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1713 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1718 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1719 * @ch_info: Channel to update. Uses power_info.requested_power.
1721 * Replace requested_power and base_power_index ch_info fields for
1724 * Called if user or spectrum management changes power preferences.
1725 * Takes into account h/w and modulation limitations (clip power).
1727 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1729 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1730 * properly fill out the scan powers, and actual h/w gain settings,
1731 * and send changes to NIC
1733 static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1734 struct iwl3945_channel_info *ch_info)
1736 struct iwl3945_channel_power_info *power_info;
1737 int power_changed = 0;
1739 const s8 *clip_pwrs;
1742 /* Get this chnlgrp's rate-to-max/clip-powers table */
1743 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1745 /* Get this channel's rate-to-current-power settings table */
1746 power_info = ch_info->power_info;
1748 /* update OFDM Txpower settings */
1749 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1750 i++, ++power_info) {
1753 /* limit new power to be no more than h/w capability */
1754 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1755 if (power == power_info->requested_power)
1758 /* find difference between old and new requested powers,
1759 * update base (non-temp-compensated) power index */
1760 delta_idx = (power - power_info->requested_power) * 2;
1761 power_info->base_power_index -= delta_idx;
1763 /* save new requested power value */
1764 power_info->requested_power = power;
1769 /* update CCK Txpower settings, based on OFDM 12M setting ...
1770 * ... all CCK power settings for a given channel are the *same*. */
1771 if (power_changed) {
1773 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1774 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1776 /* do all CCK rates' iwl3945_channel_power_info structures */
1777 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1778 power_info->requested_power = power;
1779 power_info->base_power_index =
1780 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1781 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1790 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1792 * NOTE: Returned power limit may be less (but not more) than requested,
1793 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1794 * (no consideration for h/w clipping limitations).
1796 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
1801 /* if we're using TGd limits, use lower of TGd or EEPROM */
1802 if (ch_info->tgd_data.max_power != 0)
1803 max_power = min(ch_info->tgd_data.max_power,
1804 ch_info->eeprom.max_power_avg);
1806 /* else just use EEPROM limits */
1809 max_power = ch_info->eeprom.max_power_avg;
1811 return min(max_power, ch_info->max_power_avg);
1815 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1817 * Compensate txpower settings of *all* channels for temperature.
1818 * This only accounts for the difference between current temperature
1819 * and the factory calibration temperatures, and bases the new settings
1820 * on the channel's base_power_index.
1822 * If RxOn is "associated", this sends the new Txpower to NIC!
1824 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1826 struct iwl3945_channel_info *ch_info = NULL;
1828 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1834 int temperature = priv->temperature;
1836 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1837 for (i = 0; i < priv->channel_count; i++) {
1838 ch_info = &priv->channel_info[i];
1839 a_band = is_channel_a_band(ch_info);
1841 /* Get this chnlgrp's factory calibration temperature */
1842 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1845 /* get power index adjustment based on curr and factory
1847 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1850 /* set tx power value for all rates, OFDM and CCK */
1851 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1854 ch_info->power_info[rate_index].base_power_index;
1856 /* temperature compensate */
1857 power_idx += delta_index;
1859 /* stay within table range */
1860 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1861 ch_info->power_info[rate_index].
1862 power_table_index = (u8) power_idx;
1863 ch_info->power_info[rate_index].tpc =
1864 power_gain_table[a_band][power_idx];
1867 /* Get this chnlgrp's rate-to-max/clip-powers table */
1868 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1870 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1871 for (scan_tbl_index = 0;
1872 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1873 s32 actual_index = (scan_tbl_index == 0) ?
1874 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1875 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1876 actual_index, clip_pwrs,
1881 /* send Txpower command for current channel to ucode */
1882 return iwl3945_hw_reg_send_txpower(priv);
1885 int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
1887 struct iwl3945_channel_info *ch_info;
1892 if (priv->user_txpower_limit == power) {
1893 IWL_DEBUG_POWER("Requested Tx power same as current "
1894 "limit: %ddBm.\n", power);
1898 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1899 priv->user_txpower_limit = power;
1901 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1903 for (i = 0; i < priv->channel_count; i++) {
1904 ch_info = &priv->channel_info[i];
1905 a_band = is_channel_a_band(ch_info);
1907 /* find minimum power of all user and regulatory constraints
1908 * (does not consider h/w clipping limitations) */
1909 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1910 max_power = min(power, max_power);
1911 if (max_power != ch_info->curr_txpow) {
1912 ch_info->curr_txpow = max_power;
1914 /* this considers the h/w clipping limitations */
1915 iwl3945_hw_reg_set_new_power(priv, ch_info);
1919 /* update txpower settings for all channels,
1920 * send to NIC if associated. */
1921 is_temp_calib_needed(priv);
1922 iwl3945_hw_reg_comp_txpower_temp(priv);
1927 /* will add 3945 channel switch cmd handling later */
1928 int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
1934 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1936 * -- reset periodic timer
1937 * -- see if temp has changed enough to warrant re-calibration ... if so:
1938 * -- correct coeffs for temp (can reset temp timer)
1939 * -- save this temp as "last",
1940 * -- send new set of gain settings to NIC
1941 * NOTE: This should continue working, even when we're not associated,
1942 * so we can keep our internal table of scan powers current. */
1943 void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
1945 /* This will kick in the "brute force"
1946 * iwl3945_hw_reg_comp_txpower_temp() below */
1947 if (!is_temp_calib_needed(priv))
1950 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1951 * This is based *only* on current temperature,
1952 * ignoring any previous power measurements */
1953 iwl3945_hw_reg_comp_txpower_temp(priv);
1956 queue_delayed_work(priv->workqueue,
1957 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1960 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1962 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
1963 thermal_periodic.work);
1965 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1968 mutex_lock(&priv->mutex);
1969 iwl3945_reg_txpower_periodic(priv);
1970 mutex_unlock(&priv->mutex);
1974 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1977 * This function is used when initializing channel-info structs.
1979 * NOTE: These channel groups do *NOT* match the bands above!
1980 * These channel groups are based on factory-tested channels;
1981 * on A-band, EEPROM's "group frequency" entries represent the top
1982 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1984 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1985 const struct iwl3945_channel_info *ch_info)
1987 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1989 u16 group_index = 0; /* based on factory calib frequencies */
1992 /* Find the group index for the channel ... don't use index 1(?) */
1993 if (is_channel_a_band(ch_info)) {
1994 for (group = 1; group < 5; group++) {
1995 grp_channel = ch_grp[group].group_channel;
1996 if (ch_info->channel <= grp_channel) {
1997 group_index = group;
2001 /* group 4 has a few channels *above* its factory cal freq */
2005 group_index = 0; /* 2.4 GHz, group 0 */
2007 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2013 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2015 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2016 * into radio/DSP gain settings table for requested power.
2018 static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
2020 s32 setting_index, s32 *new_index)
2022 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2024 s32 power = 2 * requested_power;
2026 const struct iwl3945_eeprom_txpower_sample *samples;
2031 chnl_grp = &priv->eeprom.groups[setting_index];
2032 samples = chnl_grp->samples;
2033 for (i = 0; i < 5; i++) {
2034 if (power == samples[i].power) {
2035 *new_index = samples[i].gain_index;
2040 if (power > samples[1].power) {
2043 } else if (power > samples[2].power) {
2046 } else if (power > samples[3].power) {
2054 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2055 if (denominator == 0)
2057 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2058 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2059 res = gains0 + (gains1 - gains0) *
2060 ((s32) power - (s32) samples[index0].power) / denominator +
2062 *new_index = res >> 19;
2066 static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2070 const struct iwl3945_eeprom_txpower_group *group;
2072 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2074 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2075 s8 *clip_pwrs; /* table of power levels for each rate */
2076 s8 satur_pwr; /* saturation power for each chnl group */
2077 group = &priv->eeprom.groups[i];
2079 /* sanity check on factory saturation power value */
2080 if (group->saturation_power < 40) {
2081 IWL_WARNING("Error: saturation power is %d, "
2082 "less than minimum expected 40\n",
2083 group->saturation_power);
2088 * Derive requested power levels for each rate, based on
2089 * hardware capabilities (saturation power for band).
2090 * Basic value is 3dB down from saturation, with further
2091 * power reductions for highest 3 data rates. These
2092 * backoffs provide headroom for high rate modulation
2093 * power peaks, without too much distortion (clipping).
2095 /* we'll fill in this array with h/w max power levels */
2096 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2098 /* divide factory saturation power by 2 to find -3dB level */
2099 satur_pwr = (s8) (group->saturation_power >> 1);
2101 /* fill in channel group's nominal powers for each rate */
2102 for (rate_index = 0;
2103 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2104 switch (rate_index) {
2105 case IWL_RATE_36M_INDEX_TABLE:
2106 if (i == 0) /* B/G */
2107 *clip_pwrs = satur_pwr;
2109 *clip_pwrs = satur_pwr - 5;
2111 case IWL_RATE_48M_INDEX_TABLE:
2113 *clip_pwrs = satur_pwr - 7;
2115 *clip_pwrs = satur_pwr - 10;
2117 case IWL_RATE_54M_INDEX_TABLE:
2119 *clip_pwrs = satur_pwr - 9;
2121 *clip_pwrs = satur_pwr - 12;
2124 *clip_pwrs = satur_pwr;
2132 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2134 * Second pass (during init) to set up priv->channel_info
2136 * Set up Tx-power settings in our channel info database for each VALID
2137 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2138 * and current temperature.
2140 * Since this is based on current temperature (at init time), these values may
2141 * not be valid for very long, but it gives us a starting/default point,
2142 * and allows us to active (i.e. using Tx) scan.
2144 * This does *not* write values to NIC, just sets up our internal table.
2146 int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2148 struct iwl3945_channel_info *ch_info = NULL;
2149 struct iwl3945_channel_power_info *pwr_info;
2153 const s8 *clip_pwrs; /* array of power levels for each rate */
2156 u8 pwr_index, base_pwr_index, a_band;
2160 /* save temperature reference,
2161 * so we can determine next time to calibrate */
2162 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2163 priv->last_temperature = temperature;
2165 iwl3945_hw_reg_init_channel_groups(priv);
2167 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2168 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2170 a_band = is_channel_a_band(ch_info);
2171 if (!is_channel_valid(ch_info))
2174 /* find this channel's channel group (*not* "band") index */
2175 ch_info->group_index =
2176 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2178 /* Get this chnlgrp's rate->max/clip-powers table */
2179 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2181 /* calculate power index *adjustment* value according to
2182 * diff between current temperature and factory temperature */
2183 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2184 priv->eeprom.groups[ch_info->group_index].
2187 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2188 ch_info->channel, delta_index, temperature +
2191 /* set tx power value for all OFDM rates */
2192 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2197 /* use channel group's clip-power table,
2198 * but don't exceed channel's max power */
2199 s8 pwr = min(ch_info->max_power_avg,
2200 clip_pwrs[rate_index]);
2202 pwr_info = &ch_info->power_info[rate_index];
2204 /* get base (i.e. at factory-measured temperature)
2205 * power table index for this rate's power */
2206 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2207 ch_info->group_index,
2210 IWL_ERROR("Invalid power index\n");
2213 pwr_info->base_power_index = (u8) power_idx;
2215 /* temperature compensate */
2216 power_idx += delta_index;
2218 /* stay within range of gain table */
2219 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2221 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2222 pwr_info->requested_power = pwr;
2223 pwr_info->power_table_index = (u8) power_idx;
2224 pwr_info->tpc.tx_gain =
2225 power_gain_table[a_band][power_idx].tx_gain;
2226 pwr_info->tpc.dsp_atten =
2227 power_gain_table[a_band][power_idx].dsp_atten;
2230 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2231 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2232 power = pwr_info->requested_power +
2233 IWL_CCK_FROM_OFDM_POWER_DIFF;
2234 pwr_index = pwr_info->power_table_index +
2235 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2236 base_pwr_index = pwr_info->base_power_index +
2237 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2239 /* stay within table range */
2240 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2241 gain = power_gain_table[a_band][pwr_index].tx_gain;
2242 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2244 /* fill each CCK rate's iwl3945_channel_power_info structure
2245 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2246 * NOTE: CCK rates start at end of OFDM rates! */
2247 for (rate_index = 0;
2248 rate_index < IWL_CCK_RATES; rate_index++) {
2249 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2250 pwr_info->requested_power = power;
2251 pwr_info->power_table_index = pwr_index;
2252 pwr_info->base_power_index = base_pwr_index;
2253 pwr_info->tpc.tx_gain = gain;
2254 pwr_info->tpc.dsp_atten = dsp_atten;
2257 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2258 for (scan_tbl_index = 0;
2259 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2260 s32 actual_index = (scan_tbl_index == 0) ?
2261 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2262 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2263 actual_index, clip_pwrs, ch_info, a_band);
2270 int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
2273 unsigned long flags;
2275 spin_lock_irqsave(&priv->lock, flags);
2276 rc = iwl3945_grab_nic_access(priv);
2278 spin_unlock_irqrestore(&priv->lock, flags);
2282 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2283 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2285 IWL_ERROR("Can't stop Rx DMA.\n");
2287 iwl3945_release_nic_access(priv);
2288 spin_unlock_irqrestore(&priv->lock, flags);
2293 int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
2296 unsigned long flags;
2297 int txq_id = txq->q.id;
2299 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2301 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2303 spin_lock_irqsave(&priv->lock, flags);
2304 rc = iwl3945_grab_nic_access(priv);
2306 spin_unlock_irqrestore(&priv->lock, flags);
2309 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2310 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
2312 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
2313 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2314 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2315 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2316 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2317 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2318 iwl3945_release_nic_access(priv);
2320 /* fake read to flush all prev. writes */
2321 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
2322 spin_unlock_irqrestore(&priv->lock, flags);
2327 int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
2329 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2331 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2335 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2337 int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
2339 int rc, i, index, prev_index;
2340 struct iwl3945_rate_scaling_cmd rate_cmd = {
2341 .reserved = {0, 0, 0},
2343 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2345 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2346 index = iwl3945_rates[i].table_rs_index;
2348 table[index].rate_n_flags =
2349 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2350 table[index].try_cnt = priv->retry_rate;
2351 prev_index = iwl3945_get_prev_ieee_rate(i);
2352 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
2355 switch (priv->band) {
2356 case IEEE80211_BAND_5GHZ:
2357 IWL_DEBUG_RATE("Select A mode rate scale\n");
2358 /* If one of the following CCK rates is used,
2359 * have it fall back to the 6M OFDM rate */
2360 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2361 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2363 /* Don't fall back to CCK rates */
2364 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
2366 /* Don't drop out of OFDM rates */
2367 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2368 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2371 case IEEE80211_BAND_2GHZ:
2372 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2373 /* If an OFDM rate is used, have it fall back to the
2375 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2376 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
2378 /* CCK shouldn't fall back to OFDM... */
2379 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2387 /* Update the rate scaling for control frame Tx */
2388 rate_cmd.table_id = 0;
2389 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2394 /* Update the rate scaling for data frame Tx */
2395 rate_cmd.table_id = 1;
2396 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2400 /* Called when initializing driver */
2401 int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
2403 memset((void *)&priv->hw_setting, 0,
2404 sizeof(struct iwl3945_driver_hw_info));
2406 priv->hw_setting.shared_virt =
2407 pci_alloc_consistent(priv->pci_dev,
2408 sizeof(struct iwl3945_shared),
2409 &priv->hw_setting.shared_phys);
2411 if (!priv->hw_setting.shared_virt) {
2412 IWL_ERROR("failed to allocate pci memory\n");
2413 mutex_unlock(&priv->mutex);
2417 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2418 priv->hw_setting.max_pkt_size = 2342;
2419 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
2420 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2421 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
2422 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2423 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2425 priv->hw_setting.tx_ant_num = 2;
2429 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2430 struct iwl3945_frame *frame, u8 rate)
2432 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2433 unsigned int frame_size;
2435 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2436 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2438 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
2439 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2441 frame_size = iwl3945_fill_beacon_frame(priv,
2442 tx_beacon_cmd->frame,
2443 iwl3945_broadcast_addr,
2444 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2446 BUG_ON(frame_size > MAX_MPDU_SIZE);
2447 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2449 tx_beacon_cmd->tx.rate = rate;
2450 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2451 TX_CMD_FLG_TSF_MSK);
2453 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2454 tx_beacon_cmd->tx.supp_rates[0] =
2455 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2457 tx_beacon_cmd->tx.supp_rates[1] =
2458 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2460 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2463 void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
2465 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2466 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2469 void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
2471 INIT_DELAYED_WORK(&priv->thermal_periodic,
2472 iwl3945_bg_reg_txpower_periodic);
2475 void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
2477 cancel_delayed_work(&priv->thermal_periodic);
2480 static struct iwl_3945_cfg iwl3945_bg_cfg = {
2482 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2486 static struct iwl_3945_cfg iwl3945_abg_cfg = {
2488 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2489 .sku = IWL_SKU_A|IWL_SKU_G,
2492 struct pci_device_id iwl3945_hw_card_ids[] = {
2493 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2494 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2495 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2496 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2497 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2498 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2502 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);