1 /******************************************************************************
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
45 #include "iwl-helpers.h"
47 #include "iwl-agn-rs.h"
49 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_##r##M_IEEE, \
52 IWL_RATE_##ip##M_INDEX, \
53 IWL_RATE_##in##M_INDEX, \
54 IWL_RATE_##rp##M_INDEX, \
55 IWL_RATE_##rn##M_INDEX, \
56 IWL_RATE_##pp##M_INDEX, \
57 IWL_RATE_##np##M_INDEX, \
58 IWL_RATE_##r##M_INDEX_TABLE, \
59 IWL_RATE_##ip##M_INDEX_TABLE }
63 * rate, prev rate, next rate, prev tgg rate, next tgg rate
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
69 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
70 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
84 /* 1 = enable the iwl3945_disable_events() function */
85 #define IWL_EVT_DISABLE (0)
86 #define IWL_EVT_DISABLE_SIZE (1532/32)
89 * iwl3945_disable_events - Disable selected events in uCode event log
91 * Disable an event by writing "1"s into "disable"
92 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
93 * Default values of 0 enable uCode events to be logged.
94 * Use for only special debugging. This function is just a placeholder as-is,
95 * you'll need to provide the special bits! ...
96 * ... and set IWL_EVT_DISABLE to 1. */
97 void iwl3945_disable_events(struct iwl_priv *priv)
101 u32 base; /* SRAM address of event log header */
102 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
103 u32 array_size; /* # of u32 entries in array */
104 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
105 0x00000000, /* 31 - 0 Event id numbers */
106 0x00000000, /* 63 - 32 */
107 0x00000000, /* 95 - 64 */
108 0x00000000, /* 127 - 96 */
109 0x00000000, /* 159 - 128 */
110 0x00000000, /* 191 - 160 */
111 0x00000000, /* 223 - 192 */
112 0x00000000, /* 255 - 224 */
113 0x00000000, /* 287 - 256 */
114 0x00000000, /* 319 - 288 */
115 0x00000000, /* 351 - 320 */
116 0x00000000, /* 383 - 352 */
117 0x00000000, /* 415 - 384 */
118 0x00000000, /* 447 - 416 */
119 0x00000000, /* 479 - 448 */
120 0x00000000, /* 511 - 480 */
121 0x00000000, /* 543 - 512 */
122 0x00000000, /* 575 - 544 */
123 0x00000000, /* 607 - 576 */
124 0x00000000, /* 639 - 608 */
125 0x00000000, /* 671 - 640 */
126 0x00000000, /* 703 - 672 */
127 0x00000000, /* 735 - 704 */
128 0x00000000, /* 767 - 736 */
129 0x00000000, /* 799 - 768 */
130 0x00000000, /* 831 - 800 */
131 0x00000000, /* 863 - 832 */
132 0x00000000, /* 895 - 864 */
133 0x00000000, /* 927 - 896 */
134 0x00000000, /* 959 - 928 */
135 0x00000000, /* 991 - 960 */
136 0x00000000, /* 1023 - 992 */
137 0x00000000, /* 1055 - 1024 */
138 0x00000000, /* 1087 - 1056 */
139 0x00000000, /* 1119 - 1088 */
140 0x00000000, /* 1151 - 1120 */
141 0x00000000, /* 1183 - 1152 */
142 0x00000000, /* 1215 - 1184 */
143 0x00000000, /* 1247 - 1216 */
144 0x00000000, /* 1279 - 1248 */
145 0x00000000, /* 1311 - 1280 */
146 0x00000000, /* 1343 - 1312 */
147 0x00000000, /* 1375 - 1344 */
148 0x00000000, /* 1407 - 1376 */
149 0x00000000, /* 1439 - 1408 */
150 0x00000000, /* 1471 - 1440 */
151 0x00000000, /* 1503 - 1472 */
154 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
155 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
156 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
160 ret = iwl_grab_nic_access(priv);
162 IWL_WARN(priv, "Can not read from adapter at this time.\n");
166 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
167 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
168 iwl_release_nic_access(priv);
170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
173 ret = iwl_grab_nic_access(priv);
174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
175 iwl_write_targ_mem(priv,
176 disable_ptr + (i * sizeof(u32)),
179 iwl_release_nic_access(priv);
181 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
182 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
183 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
184 disable_ptr, array_size);
189 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
193 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
194 if (iwl3945_rates[idx].plcp == plcp)
200 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
201 * @priv: eeprom and antenna fields are used to determine antenna flags
203 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
204 * priv->antenna specifies the antenna diversity mode:
206 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
207 * IWL_ANTENNA_MAIN - Force MAIN antenna
208 * IWL_ANTENNA_AUX - Force AUX antenna
210 __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
212 switch (priv->antenna) {
213 case IWL_ANTENNA_DIVERSITY:
216 case IWL_ANTENNA_MAIN:
217 if (priv->eeprom39.antenna_switch_type)
218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
219 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 case IWL_ANTENNA_AUX:
222 if (priv->eeprom39.antenna_switch_type)
223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
224 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
227 /* bad antenna selector value */
228 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
229 return 0; /* "diversity" is default if error */
232 #ifdef CONFIG_IWL3945_DEBUG
233 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
235 static const char *iwl3945_get_tx_fail_reason(u32 status)
237 switch (status & TX_STATUS_MSK) {
238 case TX_STATUS_SUCCESS:
240 TX_STATUS_ENTRY(SHORT_LIMIT);
241 TX_STATUS_ENTRY(LONG_LIMIT);
242 TX_STATUS_ENTRY(FIFO_UNDERRUN);
243 TX_STATUS_ENTRY(MGMNT_ABORT);
244 TX_STATUS_ENTRY(NEXT_FRAG);
245 TX_STATUS_ENTRY(LIFE_EXPIRE);
246 TX_STATUS_ENTRY(DEST_PS);
247 TX_STATUS_ENTRY(ABORTED);
248 TX_STATUS_ENTRY(BT_RETRY);
249 TX_STATUS_ENTRY(STA_INVALID);
250 TX_STATUS_ENTRY(FRAG_DROPPED);
251 TX_STATUS_ENTRY(TID_DISABLE);
252 TX_STATUS_ENTRY(FRAME_FLUSHED);
253 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
254 TX_STATUS_ENTRY(TX_LOCKED);
255 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
261 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
268 * get ieee prev rate from rate scale table.
269 * for A and B mode we need to overright prev
272 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
274 int next_rate = iwl3945_get_prev_ieee_rate(rate);
276 switch (priv->band) {
277 case IEEE80211_BAND_5GHZ:
278 if (rate == IWL_RATE_12M_INDEX)
279 next_rate = IWL_RATE_9M_INDEX;
280 else if (rate == IWL_RATE_6M_INDEX)
281 next_rate = IWL_RATE_6M_INDEX;
283 case IEEE80211_BAND_2GHZ:
284 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
285 iwl3945_is_associated(priv)) {
286 if (rate == IWL_RATE_11M_INDEX)
287 next_rate = IWL_RATE_5M_INDEX;
300 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
302 * When FW advances 'R' index, all entries between old and new 'R' index
303 * need to be reclaimed. As result, some free space forms. If there is
304 * enough free space (> low mark), wake the stack that feeds us.
306 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
307 int txq_id, int index)
309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
310 struct iwl_queue *q = &txq->q;
311 struct iwl_tx_info *tx_info;
313 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
315 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
316 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
318 tx_info = &txq->txb[txq->q.read_ptr];
319 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
320 tx_info->skb[0] = NULL;
321 iwl3945_hw_txq_free_tfd(priv, txq);
324 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
325 (txq_id != IWL_CMD_QUEUE_NUM) &&
326 priv->mac80211_registered)
327 ieee80211_wake_queue(priv->hw, txq_id);
331 * iwl3945_rx_reply_tx - Handle Tx response
333 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
334 struct iwl_rx_mem_buffer *rxb)
336 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
337 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
338 int txq_id = SEQ_TO_QUEUE(sequence);
339 int index = SEQ_TO_INDEX(sequence);
340 struct iwl_tx_queue *txq = &priv->txq[txq_id];
341 struct ieee80211_tx_info *info;
342 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
343 u32 status = le32_to_cpu(tx_resp->status);
347 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
348 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
349 "is out of range [0-%d] %d %d\n", txq_id,
350 index, txq->q.n_bd, txq->q.write_ptr,
355 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
356 ieee80211_tx_info_clear_status(info);
358 /* Fill the MRR chain with some info about on-chip retransmissions */
359 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
360 if (info->band == IEEE80211_BAND_5GHZ)
361 rate_idx -= IWL_FIRST_OFDM_RATE;
363 fail = tx_resp->failure_frame;
365 info->status.rates[0].idx = rate_idx;
366 info->status.rates[0].count = fail + 1; /* add final attempt */
368 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
369 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
370 IEEE80211_TX_STAT_ACK : 0;
372 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
373 txq_id, iwl3945_get_tx_fail_reason(status), status,
374 tx_resp->rate, tx_resp->failure_frame);
376 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
377 iwl3945_tx_queue_reclaim(priv, txq_id, index);
379 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
380 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
385 /*****************************************************************************
387 * Intel PRO/Wireless 3945ABG/BG Network Connection
389 * RX handler implementations
391 *****************************************************************************/
393 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
395 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
396 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
397 (int)sizeof(struct iwl3945_notif_statistics),
398 le32_to_cpu(pkt->len));
400 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
402 iwl3945_led_background(priv);
404 priv->last_statistics_time = jiffies;
407 /******************************************************************************
409 * Misc. internal state and helper functions
411 ******************************************************************************/
412 #ifdef CONFIG_IWL3945_DEBUG
415 * iwl3945_report_frame - dump frame to syslog during debug sessions
417 * You may hack this function to show different aspects of received frames,
418 * including selective frame dumps.
419 * group100 parameter selects whether to show 1 out of 100 good frames.
421 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
422 struct iwl_rx_packet *pkt,
423 struct ieee80211_hdr *header, int group100)
426 u32 print_summary = 0;
427 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
443 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
444 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
445 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
446 u8 *data = IWL_RX_DATA(pkt);
449 fc = header->frame_control;
450 seq_ctl = le16_to_cpu(header->seq_ctrl);
453 channel = le16_to_cpu(rx_hdr->channel);
454 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
455 length = le16_to_cpu(rx_hdr->len);
457 /* end-of-frame status and timestamp */
458 status = le32_to_cpu(rx_end->status);
459 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
460 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
461 tsf = le64_to_cpu(rx_end->timestamp);
463 /* signal statistics */
464 rssi = rx_stats->rssi;
466 sig_avg = le16_to_cpu(rx_stats->sig_avg);
467 noise_diff = le16_to_cpu(rx_stats->noise_diff);
469 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
471 /* if data frame is to us and all is good,
472 * (optionally) print summary for only 1 out of every 100 */
473 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
474 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
477 print_summary = 1; /* print each frame */
478 else if (priv->framecnt_to_us < 100) {
479 priv->framecnt_to_us++;
482 priv->framecnt_to_us = 0;
487 /* print summary for all other frames */
497 else if (ieee80211_has_retry(fc))
499 else if (ieee80211_is_assoc_resp(fc))
501 else if (ieee80211_is_reassoc_resp(fc))
503 else if (ieee80211_is_probe_resp(fc)) {
505 print_dump = 1; /* dump frame contents */
506 } else if (ieee80211_is_beacon(fc)) {
508 print_dump = 1; /* dump frame contents */
509 } else if (ieee80211_is_atim(fc))
511 else if (ieee80211_is_auth(fc))
513 else if (ieee80211_is_deauth(fc))
515 else if (ieee80211_is_disassoc(fc))
520 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
524 rate = iwl3945_rates[rate].ieee / 2;
526 /* print frame summary.
527 * MAC addresses show just the last byte (for brevity),
528 * but you can hack it to show more, if you'd like to. */
530 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
531 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
532 title, le16_to_cpu(fc), header->addr1[5],
533 length, rssi, channel, rate);
535 /* src/dst addresses assume managed mode */
536 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
537 "src=0x%02x, rssi=%u, tim=%lu usec, "
538 "phy=0x%02x, chnl=%d\n",
539 title, le16_to_cpu(fc), header->addr1[5],
540 header->addr3[5], rssi,
541 tsf_low - priv->scan_start_tsf,
546 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
549 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
550 struct iwl_rx_packet *pkt,
551 struct ieee80211_hdr *header, int group100)
556 /* This is necessary only for a number of statistics, see the caller. */
557 static int iwl3945_is_network_packet(struct iwl_priv *priv,
558 struct ieee80211_hdr *header)
560 /* Filter incoming packets to determine if they are targeted toward
561 * this network, discarding packets coming from ourselves */
562 switch (priv->iw_mode) {
563 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
564 /* packets to our IBSS update information */
565 return !compare_ether_addr(header->addr3, priv->bssid);
566 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
567 /* packets to our IBSS update information */
568 return !compare_ether_addr(header->addr2, priv->bssid);
574 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
575 struct iwl_rx_mem_buffer *rxb,
576 struct ieee80211_rx_status *stats)
578 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
579 #ifdef CONFIG_IWL3945_LEDS
580 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
582 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
583 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
584 short len = le16_to_cpu(rx_hdr->len);
586 /* We received data from the HW, so stop the watchdog */
587 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
588 IWL_DEBUG_DROP("Corruption detected!\n");
592 /* We only process data packets if the interface is open */
593 if (unlikely(!priv->is_open)) {
595 ("Dropping packet while interface is not open.\n");
599 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
600 /* Set the size of the skb to the size of the frame */
601 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
603 if (iwl3945_mod_params.sw_crypto)
604 iwl3945_set_decrypted_flag(priv, rxb->skb,
605 le32_to_cpu(rx_end->status), stats);
607 #ifdef CONFIG_IWL3945_LEDS
608 if (ieee80211_is_data(hdr->frame_control))
609 priv->rxtxpackets += len;
611 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
615 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
617 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
618 struct iwl_rx_mem_buffer *rxb)
620 struct ieee80211_hdr *header;
621 struct ieee80211_rx_status rx_status;
622 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
623 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
624 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
625 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
627 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
628 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
632 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
634 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
635 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
636 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
638 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
639 if (rx_status.band == IEEE80211_BAND_5GHZ)
640 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
642 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
643 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
645 /* set the preamble flag if appropriate */
646 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
647 rx_status.flag |= RX_FLAG_SHORTPRE;
649 if ((unlikely(rx_stats->phy_count > 20))) {
651 ("dsp size out of range [0,20]: "
652 "%d/n", rx_stats->phy_count);
656 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
657 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
658 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
664 /* Convert 3945's rssi indicator to dBm */
665 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
667 /* Set default noise value to -127 */
668 if (priv->last_rx_noise == 0)
669 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
671 /* 3945 provides noise info for OFDM frames only.
672 * sig_avg and noise_diff are measured by the 3945's digital signal
673 * processor (DSP), and indicate linear levels of signal level and
674 * distortion/noise within the packet preamble after
675 * automatic gain control (AGC). sig_avg should stay fairly
676 * constant if the radio's AGC is working well.
677 * Since these values are linear (not dB or dBm), linear
678 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
679 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
680 * to obtain noise level in dBm.
681 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
682 if (rx_stats_noise_diff) {
683 snr = rx_stats_sig_avg / rx_stats_noise_diff;
684 rx_status.noise = rx_status.signal -
685 iwl3945_calc_db_from_ratio(snr);
686 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
689 /* If noise info not available, calculate signal quality indicator (%)
690 * using just the dBm signal level. */
692 rx_status.noise = priv->last_rx_noise;
693 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
697 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
698 rx_status.signal, rx_status.noise, rx_status.qual,
699 rx_stats_sig_avg, rx_stats_noise_diff);
701 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
703 network_packet = iwl3945_is_network_packet(priv, header);
705 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
706 network_packet ? '*' : ' ',
707 le16_to_cpu(rx_hdr->channel),
708 rx_status.signal, rx_status.signal,
709 rx_status.noise, rx_status.rate_idx);
711 #ifdef CONFIG_IWL3945_DEBUG
712 if (priv->debug_level & (IWL_DL_RX))
713 /* Set "1" to report good data frames in groups of 100 */
714 iwl3945_dbg_report_frame(priv, pkt, header, 1);
717 if (network_packet) {
718 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
719 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
720 priv->last_rx_rssi = rx_status.signal;
721 priv->last_rx_noise = rx_status.noise;
724 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
727 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
728 dma_addr_t addr, u16 len)
732 struct iwl3945_tfd *tfd = (struct iwl3945_tfd *)ptr;
734 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
735 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
737 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
738 IWL_ERR(priv, "Error can not send more than %d chunks\n",
743 tfd->tbs[count].addr = cpu_to_le32(addr);
744 tfd->tbs[count].len = cpu_to_le32(len);
748 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
749 TFD_CTL_PAD_SET(pad));
755 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
757 * Does NOT advance any indexes
759 int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
761 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)&txq->tfds39[0];
762 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
763 struct pci_dev *dev = priv->pci_dev;
768 if (txq->q.id == IWL_CMD_QUEUE_NUM)
769 /* nothing to cleanup after for host commands */
773 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
774 if (counter > NUM_TFD_CHUNKS) {
775 IWL_ERR(priv, "Too many chunks: %i\n", counter);
776 /* @todo issue fatal error, it is quite serious situation */
780 /* unmap chunks if any */
782 for (i = 1; i < counter; i++) {
783 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
784 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
785 if (txq->txb[txq->q.read_ptr].skb[0]) {
786 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
787 if (txq->txb[txq->q.read_ptr].skb[0]) {
788 /* Can be called from interrupt context */
789 dev_kfree_skb_any(skb);
790 txq->txb[txq->q.read_ptr].skb[0] = NULL;
797 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
799 int i, start = IWL_AP_ID;
800 int ret = IWL_INVALID_STATION;
803 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
804 (priv->iw_mode == NL80211_IFTYPE_AP))
807 if (is_broadcast_ether_addr(addr))
808 return priv->hw_params.bcast_sta_id;
810 spin_lock_irqsave(&priv->sta_lock, flags);
811 for (i = start; i < priv->hw_params.max_stations; i++)
812 if ((priv->stations_39[i].used) &&
814 (priv->stations_39[i].sta.sta.addr, addr))) {
819 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
820 addr, priv->num_stations);
822 spin_unlock_irqrestore(&priv->sta_lock, flags);
827 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
830 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
831 struct ieee80211_tx_info *info,
832 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
834 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
835 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
841 __le16 fc = hdr->frame_control;
842 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
844 rate = iwl3945_rates[rate_index].plcp;
845 tx_flags = tx->tx_flags;
847 /* We need to figure out how to get the sta->supp_rates while
848 * in this running context */
849 rate_mask = IWL_RATES_MASK;
851 if (tx_id >= IWL_CMD_QUEUE_NUM)
856 if (ieee80211_is_probe_resp(fc)) {
857 data_retry_limit = 3;
858 if (data_retry_limit < rts_retry_limit)
859 rts_retry_limit = data_retry_limit;
861 data_retry_limit = IWL_DEFAULT_TX_RETRY;
863 if (priv->data_retry_limit != -1)
864 data_retry_limit = priv->data_retry_limit;
866 if (ieee80211_is_mgmt(fc)) {
867 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
868 case cpu_to_le16(IEEE80211_STYPE_AUTH):
869 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
870 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
871 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
872 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
873 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
874 tx_flags |= TX_CMD_FLG_CTS_MSK;
882 tx->rts_retry_limit = rts_retry_limit;
883 tx->data_retry_limit = data_retry_limit;
885 tx->tx_flags = tx_flags;
889 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
892 tx->supp_rates[1] = (rate_mask & 0xF);
894 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
895 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
896 tx->rate, le32_to_cpu(tx->tx_flags),
897 tx->supp_rates[1], tx->supp_rates[0]);
900 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
902 unsigned long flags_spin;
903 struct iwl3945_station_entry *station;
905 if (sta_id == IWL_INVALID_STATION)
906 return IWL_INVALID_STATION;
908 spin_lock_irqsave(&priv->sta_lock, flags_spin);
909 station = &priv->stations_39[sta_id];
911 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
912 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
913 station->sta.mode = STA_CONTROL_MODIFY_MSK;
915 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
917 iwl3945_send_add_station(priv, &station->sta, flags);
918 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
923 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
928 spin_lock_irqsave(&priv->lock, flags);
929 rc = iwl_grab_nic_access(priv);
931 spin_unlock_irqrestore(&priv->lock, flags);
935 if (src == IWL_PWR_SRC_VAUX) {
938 rc = pci_read_config_dword(priv->pci_dev,
939 PCI_POWER_SOURCE, &val);
940 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
941 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
942 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
943 ~APMG_PS_CTRL_MSK_PWR_SRC);
944 iwl_release_nic_access(priv);
946 iwl_poll_bit(priv, CSR_GPIO_IN,
947 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
948 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
950 iwl_release_nic_access(priv);
952 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
953 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
954 ~APMG_PS_CTRL_MSK_PWR_SRC);
956 iwl_release_nic_access(priv);
957 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
958 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
960 spin_unlock_irqrestore(&priv->lock, flags);
965 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
970 spin_lock_irqsave(&priv->lock, flags);
971 rc = iwl_grab_nic_access(priv);
973 spin_unlock_irqrestore(&priv->lock, flags);
977 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
978 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
979 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
980 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
981 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
982 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
983 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
984 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
985 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
986 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
987 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
988 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
990 /* fake read to flush all prev I/O */
991 iwl_read_direct32(priv, FH39_RSSR_CTRL);
993 iwl_release_nic_access(priv);
994 spin_unlock_irqrestore(&priv->lock, flags);
999 static int iwl3945_tx_reset(struct iwl_priv *priv)
1002 unsigned long flags;
1004 spin_lock_irqsave(&priv->lock, flags);
1005 rc = iwl_grab_nic_access(priv);
1007 spin_unlock_irqrestore(&priv->lock, flags);
1012 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1014 /* RA 0 is active */
1015 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1017 /* all 6 fifo are active */
1018 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1020 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1021 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1022 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1023 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1025 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1028 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1029 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1033 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1034 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1037 iwl_release_nic_access(priv);
1038 spin_unlock_irqrestore(&priv->lock, flags);
1044 * iwl3945_txq_ctx_reset - Reset TX queue context
1046 * Destroys all DMA structures and initialize them again
1048 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1051 int txq_id, slots_num;
1053 iwl3945_hw_txq_ctx_free(priv);
1056 rc = iwl3945_tx_reset(priv);
1061 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1062 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1063 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1064 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1067 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1075 iwl3945_hw_txq_ctx_free(priv);
1079 static int iwl3945_apm_init(struct iwl_priv *priv)
1083 iwl3945_power_init_handle(priv);
1085 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1086 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1088 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1089 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1090 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1092 /* set "initialization complete" bit to move adapter
1093 * D0U* --> D0A* state */
1094 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1096 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1097 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1099 IWL_DEBUG_INFO("Failed to init the card\n");
1103 ret = iwl_grab_nic_access(priv);
1108 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1109 APMG_CLK_VAL_BSM_CLK_RQT);
1113 /* disable L1-Active */
1114 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1115 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1117 iwl_release_nic_access(priv);
1122 static void iwl3945_nic_config(struct iwl_priv *priv)
1124 unsigned long flags;
1127 spin_lock_irqsave(&priv->lock, flags);
1129 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1130 IWL_DEBUG_INFO("RTP type \n");
1131 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1132 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1133 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1134 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1136 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1137 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1138 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1141 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
1142 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1143 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1144 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1146 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1148 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
1149 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1150 priv->eeprom39.board_revision);
1151 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1152 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1154 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1155 priv->eeprom39.board_revision);
1156 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1157 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1160 if (priv->eeprom39.almgor_m_version <= 1) {
1161 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1162 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1163 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1164 priv->eeprom39.almgor_m_version);
1166 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1167 priv->eeprom39.almgor_m_version);
1168 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1169 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1171 spin_unlock_irqrestore(&priv->lock, flags);
1173 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1174 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1176 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1177 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1180 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1184 unsigned long flags;
1185 struct iwl_rx_queue *rxq = &priv->rxq;
1187 spin_lock_irqsave(&priv->lock, flags);
1188 priv->cfg->ops->lib->apm_ops.init(priv);
1189 spin_unlock_irqrestore(&priv->lock, flags);
1191 /* Determine HW type */
1192 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1195 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1197 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1201 priv->cfg->ops->lib->apm_ops.config(priv);
1203 /* Allocate the RX queue, or reset if it is already allocated */
1205 rc = iwl_rx_queue_alloc(priv);
1207 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1211 iwl_rx_queue_reset(priv, rxq);
1213 iwl3945_rx_replenish(priv);
1215 iwl3945_rx_init(priv, rxq);
1217 spin_lock_irqsave(&priv->lock, flags);
1219 /* Look at using this instead:
1220 rxq->need_update = 1;
1221 iwl3945_rx_queue_update_write_ptr(priv, rxq);
1224 rc = iwl_grab_nic_access(priv);
1226 spin_unlock_irqrestore(&priv->lock, flags);
1229 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1230 iwl_release_nic_access(priv);
1232 spin_unlock_irqrestore(&priv->lock, flags);
1234 rc = iwl3945_txq_ctx_reset(priv);
1238 set_bit(STATUS_INIT, &priv->status);
1244 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1246 * Destroy all TX DMA queues and structures
1248 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1253 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1254 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1257 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1260 unsigned long flags;
1262 spin_lock_irqsave(&priv->lock, flags);
1263 if (iwl_grab_nic_access(priv)) {
1264 spin_unlock_irqrestore(&priv->lock, flags);
1265 iwl3945_hw_txq_ctx_free(priv);
1270 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1272 /* reset TFD queues */
1273 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1274 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1275 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1276 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1280 iwl_release_nic_access(priv);
1281 spin_unlock_irqrestore(&priv->lock, flags);
1283 iwl3945_hw_txq_ctx_free(priv);
1286 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1289 unsigned long flags;
1291 spin_lock_irqsave(&priv->lock, flags);
1293 /* set stop master bit */
1294 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1296 iwl_poll_direct_bit(priv, CSR_RESET,
1297 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1303 spin_unlock_irqrestore(&priv->lock, flags);
1304 IWL_DEBUG_INFO("stop master\n");
1309 static void iwl3945_apm_stop(struct iwl_priv *priv)
1311 unsigned long flags;
1313 iwl3945_apm_stop_master(priv);
1315 spin_lock_irqsave(&priv->lock, flags);
1317 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1320 /* clear "init complete" move adapter D0A* --> D0U state */
1321 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1322 spin_unlock_irqrestore(&priv->lock, flags);
1325 static int iwl3945_apm_reset(struct iwl_priv *priv)
1328 unsigned long flags;
1330 iwl3945_apm_stop_master(priv);
1332 spin_lock_irqsave(&priv->lock, flags);
1334 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1336 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1337 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1339 rc = iwl_grab_nic_access(priv);
1341 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1342 APMG_CLK_VAL_BSM_CLK_RQT);
1346 iwl_set_bit(priv, CSR_GP_CNTRL,
1347 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1349 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1350 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1354 iwl_write_prph(priv, APMG_CLK_EN_REG,
1355 APMG_CLK_VAL_DMA_CLK_RQT |
1356 APMG_CLK_VAL_BSM_CLK_RQT);
1359 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1360 APMG_PS_CTRL_VAL_RESET_REQ);
1362 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1363 APMG_PS_CTRL_VAL_RESET_REQ);
1364 iwl_release_nic_access(priv);
1367 /* Clear the 'host command active' bit... */
1368 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1370 wake_up_interruptible(&priv->wait_command_queue);
1371 spin_unlock_irqrestore(&priv->lock, flags);
1377 * iwl3945_hw_reg_adjust_power_by_temp
1378 * return index delta into power gain settings table
1380 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1382 return (new_reading - old_reading) * (-11) / 100;
1386 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1388 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1390 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1393 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1395 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1399 * iwl3945_hw_reg_txpower_get_temperature
1400 * get the current temperature by reading from NIC
1402 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1406 temperature = iwl3945_hw_get_temperature(priv);
1408 /* driver's okay range is -260 to +25.
1409 * human readable okay range is 0 to +285 */
1410 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1412 /* handle insane temp reading */
1413 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1414 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1416 /* if really really hot(?),
1417 * substitute the 3rd band/group's temp measured at factory */
1418 if (priv->last_temperature > 100)
1419 temperature = priv->eeprom39.groups[2].temperature;
1420 else /* else use most recent "sane" value from driver */
1421 temperature = priv->last_temperature;
1424 return temperature; /* raw, not "human readable" */
1427 /* Adjust Txpower only if temperature variance is greater than threshold.
1429 * Both are lower than older versions' 9 degrees */
1430 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1433 * is_temp_calib_needed - determines if new calibration is needed
1435 * records new temperature in tx_mgr->temperature.
1436 * replaces tx_mgr->last_temperature *only* if calib needed
1437 * (assumes caller will actually do the calibration!). */
1438 static int is_temp_calib_needed(struct iwl_priv *priv)
1442 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1443 temp_diff = priv->temperature - priv->last_temperature;
1445 /* get absolute value */
1446 if (temp_diff < 0) {
1447 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1448 temp_diff = -temp_diff;
1449 } else if (temp_diff == 0)
1450 IWL_DEBUG_POWER("Same temp,\n");
1452 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1454 /* if we don't need calibration, *don't* update last_temperature */
1455 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1456 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1460 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1462 /* assume that caller will actually do calib ...
1463 * update the "last temperature" value */
1464 priv->last_temperature = priv->temperature;
1468 #define IWL_MAX_GAIN_ENTRIES 78
1469 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1470 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1472 /* radio and DSP power table, each step is 1/2 dB.
1473 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1474 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1476 {251, 127}, /* 2.4 GHz, highest power */
1553 {3, 95} }, /* 2.4 GHz, lowest power */
1555 {251, 127}, /* 5.x GHz, highest power */
1632 {3, 120} } /* 5.x GHz, lowest power */
1635 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1639 if (index >= IWL_MAX_GAIN_ENTRIES)
1640 return IWL_MAX_GAIN_ENTRIES - 1;
1644 /* Kick off thermal recalibration check every 60 seconds */
1645 #define REG_RECALIB_PERIOD (60)
1648 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1650 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1651 * or 6 Mbit (OFDM) rates.
1653 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1654 s32 rate_index, const s8 *clip_pwrs,
1655 struct iwl_channel_info *ch_info,
1658 struct iwl3945_scan_power_info *scan_power_info;
1662 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1664 /* use this channel group's 6Mbit clipping/saturation pwr,
1665 * but cap at regulatory scan power restriction (set during init
1666 * based on eeprom channel data) for this channel. */
1667 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1669 /* further limit to user's max power preference.
1670 * FIXME: Other spectrum management power limitations do not
1671 * seem to apply?? */
1672 power = min(power, priv->user_txpower_limit);
1673 scan_power_info->requested_power = power;
1675 /* find difference between new scan *power* and current "normal"
1676 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1677 * current "normal" temperature-compensated Tx power *index* for
1678 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1680 power_index = ch_info->power_info[rate_index].power_table_index
1681 - (power - ch_info->power_info
1682 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1684 /* store reference index that we use when adjusting *all* scan
1685 * powers. So we can accommodate user (all channel) or spectrum
1686 * management (single channel) power changes "between" temperature
1687 * feedback compensation procedures.
1688 * don't force fit this reference index into gain table; it may be a
1689 * negative number. This will help avoid errors when we're at
1690 * the lower bounds (highest gains, for warmest temperatures)
1693 /* don't exceed table bounds for "real" setting */
1694 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1696 scan_power_info->power_table_index = power_index;
1697 scan_power_info->tpc.tx_gain =
1698 power_gain_table[band_index][power_index].tx_gain;
1699 scan_power_info->tpc.dsp_atten =
1700 power_gain_table[band_index][power_index].dsp_atten;
1704 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1706 * Configures power settings for all rates for the current channel,
1707 * using values from channel info struct, and send to NIC
1709 int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
1712 const struct iwl_channel_info *ch_info = NULL;
1713 struct iwl3945_txpowertable_cmd txpower = {
1714 .channel = priv->active39_rxon.channel,
1717 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1718 ch_info = iwl3945_get_channel_info(priv,
1720 le16_to_cpu(priv->active39_rxon.channel));
1723 "Failed to get channel info for channel %d [%d]\n",
1724 le16_to_cpu(priv->active39_rxon.channel), priv->band);
1728 if (!is_channel_valid(ch_info)) {
1729 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1730 "non-Tx channel.\n");
1734 /* fill cmd with power settings for all rates for current channel */
1735 /* Fill OFDM rate */
1736 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1737 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1739 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1740 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1742 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1743 le16_to_cpu(txpower.channel),
1745 txpower.power[i].tpc.tx_gain,
1746 txpower.power[i].tpc.dsp_atten,
1747 txpower.power[i].rate);
1749 /* Fill CCK rates */
1750 for (rate_idx = IWL_FIRST_CCK_RATE;
1751 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1752 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1753 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1755 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1756 le16_to_cpu(txpower.channel),
1758 txpower.power[i].tpc.tx_gain,
1759 txpower.power[i].tpc.dsp_atten,
1760 txpower.power[i].rate);
1763 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1764 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1769 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1770 * @ch_info: Channel to update. Uses power_info.requested_power.
1772 * Replace requested_power and base_power_index ch_info fields for
1775 * Called if user or spectrum management changes power preferences.
1776 * Takes into account h/w and modulation limitations (clip power).
1778 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1780 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1781 * properly fill out the scan powers, and actual h/w gain settings,
1782 * and send changes to NIC
1784 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1785 struct iwl_channel_info *ch_info)
1787 struct iwl3945_channel_power_info *power_info;
1788 int power_changed = 0;
1790 const s8 *clip_pwrs;
1793 /* Get this chnlgrp's rate-to-max/clip-powers table */
1794 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1796 /* Get this channel's rate-to-current-power settings table */
1797 power_info = ch_info->power_info;
1799 /* update OFDM Txpower settings */
1800 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1801 i++, ++power_info) {
1804 /* limit new power to be no more than h/w capability */
1805 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1806 if (power == power_info->requested_power)
1809 /* find difference between old and new requested powers,
1810 * update base (non-temp-compensated) power index */
1811 delta_idx = (power - power_info->requested_power) * 2;
1812 power_info->base_power_index -= delta_idx;
1814 /* save new requested power value */
1815 power_info->requested_power = power;
1820 /* update CCK Txpower settings, based on OFDM 12M setting ...
1821 * ... all CCK power settings for a given channel are the *same*. */
1822 if (power_changed) {
1824 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1825 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1827 /* do all CCK rates' iwl3945_channel_power_info structures */
1828 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1829 power_info->requested_power = power;
1830 power_info->base_power_index =
1831 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1832 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1841 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1843 * NOTE: Returned power limit may be less (but not more) than requested,
1844 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1845 * (no consideration for h/w clipping limitations).
1847 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1852 /* if we're using TGd limits, use lower of TGd or EEPROM */
1853 if (ch_info->tgd_data.max_power != 0)
1854 max_power = min(ch_info->tgd_data.max_power,
1855 ch_info->eeprom.max_power_avg);
1857 /* else just use EEPROM limits */
1860 max_power = ch_info->eeprom.max_power_avg;
1862 return min(max_power, ch_info->max_power_avg);
1866 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1868 * Compensate txpower settings of *all* channels for temperature.
1869 * This only accounts for the difference between current temperature
1870 * and the factory calibration temperatures, and bases the new settings
1871 * on the channel's base_power_index.
1873 * If RxOn is "associated", this sends the new Txpower to NIC!
1875 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1877 struct iwl_channel_info *ch_info = NULL;
1879 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1885 int temperature = priv->temperature;
1887 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1888 for (i = 0; i < priv->channel_count; i++) {
1889 ch_info = &priv->channel_info[i];
1890 a_band = is_channel_a_band(ch_info);
1892 /* Get this chnlgrp's factory calibration temperature */
1893 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
1896 /* get power index adjustment based on current and factory
1898 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1901 /* set tx power value for all rates, OFDM and CCK */
1902 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1905 ch_info->power_info[rate_index].base_power_index;
1907 /* temperature compensate */
1908 power_idx += delta_index;
1910 /* stay within table range */
1911 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1912 ch_info->power_info[rate_index].
1913 power_table_index = (u8) power_idx;
1914 ch_info->power_info[rate_index].tpc =
1915 power_gain_table[a_band][power_idx];
1918 /* Get this chnlgrp's rate-to-max/clip-powers table */
1919 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1921 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1922 for (scan_tbl_index = 0;
1923 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1924 s32 actual_index = (scan_tbl_index == 0) ?
1925 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1926 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1927 actual_index, clip_pwrs,
1932 /* send Txpower command for current channel to ucode */
1933 return iwl3945_hw_reg_send_txpower(priv);
1936 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1938 struct iwl_channel_info *ch_info;
1943 if (priv->user_txpower_limit == power) {
1944 IWL_DEBUG_POWER("Requested Tx power same as current "
1945 "limit: %ddBm.\n", power);
1949 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1950 priv->user_txpower_limit = power;
1952 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1954 for (i = 0; i < priv->channel_count; i++) {
1955 ch_info = &priv->channel_info[i];
1956 a_band = is_channel_a_band(ch_info);
1958 /* find minimum power of all user and regulatory constraints
1959 * (does not consider h/w clipping limitations) */
1960 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1961 max_power = min(power, max_power);
1962 if (max_power != ch_info->curr_txpow) {
1963 ch_info->curr_txpow = max_power;
1965 /* this considers the h/w clipping limitations */
1966 iwl3945_hw_reg_set_new_power(priv, ch_info);
1970 /* update txpower settings for all channels,
1971 * send to NIC if associated. */
1972 is_temp_calib_needed(priv);
1973 iwl3945_hw_reg_comp_txpower_temp(priv);
1978 /* will add 3945 channel switch cmd handling later */
1979 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1985 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1987 * -- reset periodic timer
1988 * -- see if temp has changed enough to warrant re-calibration ... if so:
1989 * -- correct coeffs for temp (can reset temp timer)
1990 * -- save this temp as "last",
1991 * -- send new set of gain settings to NIC
1992 * NOTE: This should continue working, even when we're not associated,
1993 * so we can keep our internal table of scan powers current. */
1994 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1996 /* This will kick in the "brute force"
1997 * iwl3945_hw_reg_comp_txpower_temp() below */
1998 if (!is_temp_calib_needed(priv))
2001 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2002 * This is based *only* on current temperature,
2003 * ignoring any previous power measurements */
2004 iwl3945_hw_reg_comp_txpower_temp(priv);
2007 queue_delayed_work(priv->workqueue,
2008 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2011 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2013 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2014 thermal_periodic.work);
2016 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2019 mutex_lock(&priv->mutex);
2020 iwl3945_reg_txpower_periodic(priv);
2021 mutex_unlock(&priv->mutex);
2025 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2028 * This function is used when initializing channel-info structs.
2030 * NOTE: These channel groups do *NOT* match the bands above!
2031 * These channel groups are based on factory-tested channels;
2032 * on A-band, EEPROM's "group frequency" entries represent the top
2033 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2035 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2036 const struct iwl_channel_info *ch_info)
2038 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
2040 u16 group_index = 0; /* based on factory calib frequencies */
2043 /* Find the group index for the channel ... don't use index 1(?) */
2044 if (is_channel_a_band(ch_info)) {
2045 for (group = 1; group < 5; group++) {
2046 grp_channel = ch_grp[group].group_channel;
2047 if (ch_info->channel <= grp_channel) {
2048 group_index = group;
2052 /* group 4 has a few channels *above* its factory cal freq */
2056 group_index = 0; /* 2.4 GHz, group 0 */
2058 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2064 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2066 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2067 * into radio/DSP gain settings table for requested power.
2069 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2071 s32 setting_index, s32 *new_index)
2073 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2075 s32 power = 2 * requested_power;
2077 const struct iwl3945_eeprom_txpower_sample *samples;
2082 chnl_grp = &priv->eeprom39.groups[setting_index];
2083 samples = chnl_grp->samples;
2084 for (i = 0; i < 5; i++) {
2085 if (power == samples[i].power) {
2086 *new_index = samples[i].gain_index;
2091 if (power > samples[1].power) {
2094 } else if (power > samples[2].power) {
2097 } else if (power > samples[3].power) {
2105 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2106 if (denominator == 0)
2108 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2109 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2110 res = gains0 + (gains1 - gains0) *
2111 ((s32) power - (s32) samples[index0].power) / denominator +
2113 *new_index = res >> 19;
2117 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2121 const struct iwl3945_eeprom_txpower_group *group;
2123 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2125 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2126 s8 *clip_pwrs; /* table of power levels for each rate */
2127 s8 satur_pwr; /* saturation power for each chnl group */
2128 group = &priv->eeprom39.groups[i];
2130 /* sanity check on factory saturation power value */
2131 if (group->saturation_power < 40) {
2132 IWL_WARN(priv, "Error: saturation power is %d, "
2133 "less than minimum expected 40\n",
2134 group->saturation_power);
2139 * Derive requested power levels for each rate, based on
2140 * hardware capabilities (saturation power for band).
2141 * Basic value is 3dB down from saturation, with further
2142 * power reductions for highest 3 data rates. These
2143 * backoffs provide headroom for high rate modulation
2144 * power peaks, without too much distortion (clipping).
2146 /* we'll fill in this array with h/w max power levels */
2147 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2149 /* divide factory saturation power by 2 to find -3dB level */
2150 satur_pwr = (s8) (group->saturation_power >> 1);
2152 /* fill in channel group's nominal powers for each rate */
2153 for (rate_index = 0;
2154 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2155 switch (rate_index) {
2156 case IWL_RATE_36M_INDEX_TABLE:
2157 if (i == 0) /* B/G */
2158 *clip_pwrs = satur_pwr;
2160 *clip_pwrs = satur_pwr - 5;
2162 case IWL_RATE_48M_INDEX_TABLE:
2164 *clip_pwrs = satur_pwr - 7;
2166 *clip_pwrs = satur_pwr - 10;
2168 case IWL_RATE_54M_INDEX_TABLE:
2170 *clip_pwrs = satur_pwr - 9;
2172 *clip_pwrs = satur_pwr - 12;
2175 *clip_pwrs = satur_pwr;
2183 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2185 * Second pass (during init) to set up priv->channel_info
2187 * Set up Tx-power settings in our channel info database for each VALID
2188 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2189 * and current temperature.
2191 * Since this is based on current temperature (at init time), these values may
2192 * not be valid for very long, but it gives us a starting/default point,
2193 * and allows us to active (i.e. using Tx) scan.
2195 * This does *not* write values to NIC, just sets up our internal table.
2197 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2199 struct iwl_channel_info *ch_info = NULL;
2200 struct iwl3945_channel_power_info *pwr_info;
2204 const s8 *clip_pwrs; /* array of power levels for each rate */
2207 u8 pwr_index, base_pwr_index, a_band;
2211 /* save temperature reference,
2212 * so we can determine next time to calibrate */
2213 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2214 priv->last_temperature = temperature;
2216 iwl3945_hw_reg_init_channel_groups(priv);
2218 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2219 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2221 a_band = is_channel_a_band(ch_info);
2222 if (!is_channel_valid(ch_info))
2225 /* find this channel's channel group (*not* "band") index */
2226 ch_info->group_index =
2227 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2229 /* Get this chnlgrp's rate->max/clip-powers table */
2230 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2232 /* calculate power index *adjustment* value according to
2233 * diff between current temperature and factory temperature */
2234 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2235 priv->eeprom39.groups[ch_info->group_index].
2238 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2239 ch_info->channel, delta_index, temperature +
2242 /* set tx power value for all OFDM rates */
2243 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2245 s32 uninitialized_var(power_idx);
2248 /* use channel group's clip-power table,
2249 * but don't exceed channel's max power */
2250 s8 pwr = min(ch_info->max_power_avg,
2251 clip_pwrs[rate_index]);
2253 pwr_info = &ch_info->power_info[rate_index];
2255 /* get base (i.e. at factory-measured temperature)
2256 * power table index for this rate's power */
2257 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2258 ch_info->group_index,
2261 IWL_ERR(priv, "Invalid power index\n");
2264 pwr_info->base_power_index = (u8) power_idx;
2266 /* temperature compensate */
2267 power_idx += delta_index;
2269 /* stay within range of gain table */
2270 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2272 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2273 pwr_info->requested_power = pwr;
2274 pwr_info->power_table_index = (u8) power_idx;
2275 pwr_info->tpc.tx_gain =
2276 power_gain_table[a_band][power_idx].tx_gain;
2277 pwr_info->tpc.dsp_atten =
2278 power_gain_table[a_band][power_idx].dsp_atten;
2281 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2282 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2283 power = pwr_info->requested_power +
2284 IWL_CCK_FROM_OFDM_POWER_DIFF;
2285 pwr_index = pwr_info->power_table_index +
2286 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2287 base_pwr_index = pwr_info->base_power_index +
2288 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2290 /* stay within table range */
2291 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2292 gain = power_gain_table[a_band][pwr_index].tx_gain;
2293 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2295 /* fill each CCK rate's iwl3945_channel_power_info structure
2296 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2297 * NOTE: CCK rates start at end of OFDM rates! */
2298 for (rate_index = 0;
2299 rate_index < IWL_CCK_RATES; rate_index++) {
2300 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2301 pwr_info->requested_power = power;
2302 pwr_info->power_table_index = pwr_index;
2303 pwr_info->base_power_index = base_pwr_index;
2304 pwr_info->tpc.tx_gain = gain;
2305 pwr_info->tpc.dsp_atten = dsp_atten;
2308 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2309 for (scan_tbl_index = 0;
2310 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2311 s32 actual_index = (scan_tbl_index == 0) ?
2312 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2313 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2314 actual_index, clip_pwrs, ch_info, a_band);
2321 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2324 unsigned long flags;
2326 spin_lock_irqsave(&priv->lock, flags);
2327 rc = iwl_grab_nic_access(priv);
2329 spin_unlock_irqrestore(&priv->lock, flags);
2333 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2334 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2335 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2337 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2339 iwl_release_nic_access(priv);
2340 spin_unlock_irqrestore(&priv->lock, flags);
2345 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2348 unsigned long flags;
2349 int txq_id = txq->q.id;
2351 struct iwl3945_shared *shared_data = priv->shared_virt;
2353 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2355 spin_lock_irqsave(&priv->lock, flags);
2356 rc = iwl_grab_nic_access(priv);
2358 spin_unlock_irqrestore(&priv->lock, flags);
2361 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2362 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2364 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2365 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2366 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2367 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2368 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2369 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2370 iwl_release_nic_access(priv);
2372 /* fake read to flush all prev. writes */
2373 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2374 spin_unlock_irqrestore(&priv->lock, flags);
2382 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2386 return (u16) sizeof(struct iwl3945_rxon_cmd);
2393 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2395 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2397 int rc, i, index, prev_index;
2398 struct iwl3945_rate_scaling_cmd rate_cmd = {
2399 .reserved = {0, 0, 0},
2401 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2403 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2404 index = iwl3945_rates[i].table_rs_index;
2406 table[index].rate_n_flags =
2407 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2408 table[index].try_cnt = priv->retry_rate;
2409 prev_index = iwl3945_get_prev_ieee_rate(i);
2410 table[index].next_rate_index =
2411 iwl3945_rates[prev_index].table_rs_index;
2414 switch (priv->band) {
2415 case IEEE80211_BAND_5GHZ:
2416 IWL_DEBUG_RATE("Select A mode rate scale\n");
2417 /* If one of the following CCK rates is used,
2418 * have it fall back to the 6M OFDM rate */
2419 for (i = IWL_RATE_1M_INDEX_TABLE;
2420 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2421 table[i].next_rate_index =
2422 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2424 /* Don't fall back to CCK rates */
2425 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2426 IWL_RATE_9M_INDEX_TABLE;
2428 /* Don't drop out of OFDM rates */
2429 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2430 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2433 case IEEE80211_BAND_2GHZ:
2434 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2435 /* If an OFDM rate is used, have it fall back to the
2438 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2439 iwl3945_is_associated(priv)) {
2441 index = IWL_FIRST_CCK_RATE;
2442 for (i = IWL_RATE_6M_INDEX_TABLE;
2443 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2444 table[i].next_rate_index =
2445 iwl3945_rates[index].table_rs_index;
2447 index = IWL_RATE_11M_INDEX_TABLE;
2448 /* CCK shouldn't fall back to OFDM... */
2449 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2458 /* Update the rate scaling for control frame Tx */
2459 rate_cmd.table_id = 0;
2460 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2465 /* Update the rate scaling for data frame Tx */
2466 rate_cmd.table_id = 1;
2467 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2471 /* Called when initializing driver */
2472 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2474 memset((void *)&priv->hw_params, 0,
2475 sizeof(struct iwl_hw_params));
2478 pci_alloc_consistent(priv->pci_dev,
2479 sizeof(struct iwl3945_shared),
2480 &priv->shared_phys);
2482 if (!priv->shared_virt) {
2483 IWL_ERR(priv, "failed to allocate pci memory\n");
2484 mutex_unlock(&priv->mutex);
2488 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE;
2489 priv->hw_params.max_pkt_size = 2342;
2490 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2491 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2492 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2493 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2498 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2499 struct iwl3945_frame *frame, u8 rate)
2501 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2502 unsigned int frame_size;
2504 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2505 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2507 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2508 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2510 frame_size = iwl3945_fill_beacon_frame(priv,
2511 tx_beacon_cmd->frame,
2512 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2514 BUG_ON(frame_size > MAX_MPDU_SIZE);
2515 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2517 tx_beacon_cmd->tx.rate = rate;
2518 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2519 TX_CMD_FLG_TSF_MSK);
2521 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2522 tx_beacon_cmd->tx.supp_rates[0] =
2523 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2525 tx_beacon_cmd->tx.supp_rates[1] =
2526 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2528 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2531 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2533 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2534 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2537 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2539 INIT_DELAYED_WORK(&priv->thermal_periodic,
2540 iwl3945_bg_reg_txpower_periodic);
2543 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2545 cancel_delayed_work(&priv->thermal_periodic);
2548 /* check contents of special bootstrap uCode SRAM */
2549 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2551 __le32 *image = priv->ucode_boot.v_addr;
2552 u32 len = priv->ucode_boot.len;
2556 IWL_DEBUG_INFO("Begin verify bsm\n");
2558 /* verify BSM SRAM contents */
2559 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2560 for (reg = BSM_SRAM_LOWER_BOUND;
2561 reg < BSM_SRAM_LOWER_BOUND + len;
2562 reg += sizeof(u32), image++) {
2563 val = iwl_read_prph(priv, reg);
2564 if (val != le32_to_cpu(*image)) {
2565 IWL_ERR(priv, "BSM uCode verification failed at "
2566 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2567 BSM_SRAM_LOWER_BOUND,
2568 reg - BSM_SRAM_LOWER_BOUND, len,
2569 val, le32_to_cpu(*image));
2574 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2580 * iwl3945_load_bsm - Load bootstrap instructions
2584 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2585 * in special SRAM that does not power down during RFKILL. When powering back
2586 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2587 * the bootstrap program into the on-board processor, and starts it.
2589 * The bootstrap program loads (via DMA) instructions and data for a new
2590 * program from host DRAM locations indicated by the host driver in the
2591 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2594 * When initializing the NIC, the host driver points the BSM to the
2595 * "initialize" uCode image. This uCode sets up some internal data, then
2596 * notifies host via "initialize alive" that it is complete.
2598 * The host then replaces the BSM_DRAM_* pointer values to point to the
2599 * normal runtime uCode instructions and a backup uCode data cache buffer
2600 * (filled initially with starting data values for the on-board processor),
2601 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2602 * which begins normal operation.
2604 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2605 * the backup data cache in DRAM before SRAM is powered down.
2607 * When powering back up, the BSM loads the bootstrap program. This reloads
2608 * the runtime uCode instructions and the backup data cache into SRAM,
2609 * and re-launches the runtime uCode from where it left off.
2611 static int iwl3945_load_bsm(struct iwl_priv *priv)
2613 __le32 *image = priv->ucode_boot.v_addr;
2614 u32 len = priv->ucode_boot.len;
2624 IWL_DEBUG_INFO("Begin load bsm\n");
2626 /* make sure bootstrap program is no larger than BSM's SRAM size */
2627 if (len > IWL39_MAX_BSM_SIZE)
2630 /* Tell bootstrap uCode where to find the "Initialize" uCode
2631 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2632 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2633 * after the "initialize" uCode has run, to point to
2634 * runtime/protocol instructions and backup data cache. */
2635 pinst = priv->ucode_init.p_addr;
2636 pdata = priv->ucode_init_data.p_addr;
2637 inst_len = priv->ucode_init.len;
2638 data_len = priv->ucode_init_data.len;
2640 rc = iwl_grab_nic_access(priv);
2644 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2645 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2646 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2647 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2649 /* Fill BSM memory with bootstrap instructions */
2650 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2651 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2652 reg_offset += sizeof(u32), image++)
2653 _iwl_write_prph(priv, reg_offset,
2654 le32_to_cpu(*image));
2656 rc = iwl3945_verify_bsm(priv);
2658 iwl_release_nic_access(priv);
2662 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2663 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2664 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2665 IWL39_RTC_INST_LOWER_BOUND);
2666 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2668 /* Load bootstrap code into instruction SRAM now,
2669 * to prepare to load "initialize" uCode */
2670 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2671 BSM_WR_CTRL_REG_BIT_START);
2673 /* Wait for load of bootstrap uCode to finish */
2674 for (i = 0; i < 100; i++) {
2675 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2676 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2681 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2683 IWL_ERR(priv, "BSM write did not complete!\n");
2687 /* Enable future boot loads whenever power management unit triggers it
2688 * (e.g. when powering back up after power-save shutdown) */
2689 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2690 BSM_WR_CTRL_REG_BIT_START_EN);
2692 iwl_release_nic_access(priv);
2697 static struct iwl_lib_ops iwl3945_lib = {
2698 .load_ucode = iwl3945_load_bsm,
2700 .init = iwl3945_apm_init,
2701 .reset = iwl3945_apm_reset,
2702 .stop = iwl3945_apm_stop,
2703 .config = iwl3945_nic_config,
2704 .set_pwr_src = iwl3945_set_pwr_src,
2708 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2709 .get_hcmd_size = iwl3945_get_hcmd_size,
2712 static struct iwl_ops iwl3945_ops = {
2713 .lib = &iwl3945_lib,
2714 .utils = &iwl3945_hcmd_utils,
2717 static struct iwl_cfg iwl3945_bg_cfg = {
2719 .fw_name_pre = IWL3945_FW_PRE,
2720 .ucode_api_max = IWL3945_UCODE_API_MAX,
2721 .ucode_api_min = IWL3945_UCODE_API_MIN,
2723 .ops = &iwl3945_ops,
2724 .mod_params = &iwl3945_mod_params
2727 static struct iwl_cfg iwl3945_abg_cfg = {
2729 .fw_name_pre = IWL3945_FW_PRE,
2730 .ucode_api_max = IWL3945_UCODE_API_MAX,
2731 .ucode_api_min = IWL3945_UCODE_API_MIN,
2732 .sku = IWL_SKU_A|IWL_SKU_G,
2733 .ops = &iwl3945_ops,
2734 .mod_params = &iwl3945_mod_params
2737 struct pci_device_id iwl3945_hw_card_ids[] = {
2738 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2739 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2740 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2741 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2742 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2743 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2747 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);