1 /******************************************************************************
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
39 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
46 #include "iwl-6000-hw.h"
48 /* Highest firmware API version supported */
49 #define IWL5000_UCODE_API_MAX 2
50 #define IWL5150_UCODE_API_MAX 2
52 /* Lowest firmware API version supported */
53 #define IWL5000_UCODE_API_MIN 1
54 #define IWL5150_UCODE_API_MIN 1
56 #define IWL5000_FW_PRE "iwlwifi-5000-"
57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60 #define IWL5150_FW_PRE "iwlwifi-5150-"
61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
64 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
74 /* FIXME: same implementation as 4965 */
75 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
79 spin_lock_irqsave(&priv->lock, flags);
81 /* set stop master bit */
82 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
84 iwl_poll_direct_bit(priv, CSR_RESET,
85 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
87 spin_unlock_irqrestore(&priv->lock, flags);
88 IWL_DEBUG_INFO(priv, "stop master\n");
94 int iwl5000_apm_init(struct iwl_priv *priv)
98 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
106 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
112 if (priv->cfg->need_pll_cfg)
113 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
119 /* wait for clock stabilization */
120 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
123 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
132 /* disable L1-Active */
133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
139 /* FIXME: this is identical to 4965 */
140 void iwl5000_apm_stop(struct iwl_priv *priv)
144 iwl5000_apm_stop_master(priv);
146 spin_lock_irqsave(&priv->lock, flags);
148 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
152 /* clear "init complete" move adapter D0A* --> D0U state */
153 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
155 spin_unlock_irqrestore(&priv->lock, flags);
159 int iwl5000_apm_reset(struct iwl_priv *priv)
163 iwl5000_apm_stop_master(priv);
165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
170 /* FIXME: put here L1A -L0S w/a */
172 if (priv->cfg->need_pll_cfg)
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
179 /* wait for clock stabilization */
180 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
192 /* disable L1-Active */
193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
201 /* NIC configuration for 5000 series */
202 void iwl5000_nic_config(struct iwl_priv *priv)
208 spin_lock_irqsave(&priv->lock, flags);
210 lctl = iwl_pcie_link_ctl(priv);
213 /* L1-ASPM is enabled by BIOS */
214 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
215 /* L1-APSM enabled: disable L0S */
216 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
218 /* L1-ASPM disabled: enable L0S */
219 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
221 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
223 /* write radio config values to register */
224 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
225 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
226 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
227 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
228 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
230 /* set CSR_HW_CONFIG_REG for uCode use */
231 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
232 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
233 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
235 /* W/A : NIC is stuck in a reset state after Early PCIe power off
236 * (PCIe power is lost before PERST# is asserted),
237 * causing ME FW to lose ownership and not being able to obtain it back.
239 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
240 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
241 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
244 spin_unlock_irqrestore(&priv->lock, flags);
251 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
255 if ((address & INDIRECT_ADDRESS) == 0)
258 switch (address & INDIRECT_TYPE_MSK) {
260 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
262 case INDIRECT_GENERAL:
263 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
265 case INDIRECT_REGULATORY:
266 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
268 case INDIRECT_CALIBRATION:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
271 case INDIRECT_PROCESS_ADJST:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
274 case INDIRECT_OTHERS:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
278 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
279 address & INDIRECT_TYPE_MSK);
283 /* translate the offset from words to byte */
284 return (address & ADDRESS_MSK) + (offset << 1);
287 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
289 struct iwl_eeprom_calib_hdr {
295 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
296 EEPROM_5000_CALIB_ALL);
301 static void iwl5000_gain_computation(struct iwl_priv *priv,
302 u32 average_noise[NUM_RX_CHAINS],
303 u16 min_average_noise_antenna_i,
304 u32 min_average_noise,
309 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
312 * Find Gain Code for the chains based on "default chain"
314 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
315 if ((data->disconn_array[i])) {
316 data->delta_gain_code[i] = 0;
319 delta_g = (1000 * ((s32)average_noise[0] -
320 (s32)average_noise[i])) / 1500;
321 /* bound gain by 2 bits value max, 3rd bit is sign */
322 data->delta_gain_code[i] =
323 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
326 /* set negative sign */
327 data->delta_gain_code[i] |= (1 << 2);
330 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
331 data->delta_gain_code[1], data->delta_gain_code[2]);
333 if (!data->radio_write) {
334 struct iwl_calib_chain_noise_gain_cmd cmd;
336 memset(&cmd, 0, sizeof(cmd));
338 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
339 cmd.hdr.first_group = 0;
340 cmd.hdr.groups_num = 1;
341 cmd.hdr.data_valid = 1;
342 cmd.delta_gain_1 = data->delta_gain_code[1];
343 cmd.delta_gain_2 = data->delta_gain_code[2];
344 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
345 sizeof(cmd), &cmd, NULL);
347 data->radio_write = 1;
348 data->state = IWL_CHAIN_NOISE_CALIBRATED;
351 data->chain_noise_a = 0;
352 data->chain_noise_b = 0;
353 data->chain_noise_c = 0;
354 data->chain_signal_a = 0;
355 data->chain_signal_b = 0;
356 data->chain_signal_c = 0;
357 data->beacon_count = 0;
360 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
362 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
365 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
366 struct iwl_calib_chain_noise_reset_cmd cmd;
367 memset(&cmd, 0, sizeof(cmd));
369 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
370 cmd.hdr.first_group = 0;
371 cmd.hdr.groups_num = 1;
372 cmd.hdr.data_valid = 1;
373 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
377 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
378 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
379 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
383 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
386 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
387 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
388 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
390 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
393 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
395 .max_nrg_cck = 0, /* not used, set to 0 */
396 .auto_corr_min_ofdm = 90,
397 .auto_corr_min_ofdm_mrc = 170,
398 .auto_corr_min_ofdm_x1 = 120,
399 .auto_corr_min_ofdm_mrc_x1 = 240,
401 .auto_corr_max_ofdm = 120,
402 .auto_corr_max_ofdm_mrc = 210,
403 .auto_corr_max_ofdm_x1 = 155,
404 .auto_corr_max_ofdm_mrc_x1 = 290,
406 .auto_corr_min_cck = 125,
407 .auto_corr_max_cck = 200,
408 .auto_corr_min_cck_mrc = 170,
409 .auto_corr_max_cck_mrc = 400,
414 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
416 .max_nrg_cck = 0, /* not used, set to 0 */
417 .auto_corr_min_ofdm = 90,
418 .auto_corr_min_ofdm_mrc = 170,
419 .auto_corr_min_ofdm_x1 = 105,
420 .auto_corr_min_ofdm_mrc_x1 = 220,
422 .auto_corr_max_ofdm = 120,
423 .auto_corr_max_ofdm_mrc = 210,
424 /* max = min for performance bug in 5150 DSP */
425 .auto_corr_max_ofdm_x1 = 105,
426 .auto_corr_max_ofdm_mrc_x1 = 220,
428 .auto_corr_min_cck = 125,
429 .auto_corr_max_cck = 200,
430 .auto_corr_min_cck_mrc = 170,
431 .auto_corr_max_cck_mrc = 400,
436 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
439 u32 address = eeprom_indirect_address(priv, offset);
440 BUG_ON(address >= priv->cfg->eeprom_size);
441 return &priv->eeprom[address];
444 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
446 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
447 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
448 iwl_temp_calib_to_offset(priv);
450 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
453 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
456 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
462 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
464 struct iwl_calib_xtal_freq_cmd cmd;
465 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
467 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
468 cmd.hdr.first_group = 0;
469 cmd.hdr.groups_num = 1;
470 cmd.hdr.data_valid = 1;
471 cmd.cap_pin1 = (u8)xtal_calib[0];
472 cmd.cap_pin2 = (u8)xtal_calib[1];
473 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
474 (u8 *)&cmd, sizeof(cmd));
477 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
479 struct iwl_calib_cfg_cmd calib_cfg_cmd;
480 struct iwl_host_cmd cmd = {
481 .id = CALIBRATION_CFG_CMD,
482 .len = sizeof(struct iwl_calib_cfg_cmd),
483 .data = &calib_cfg_cmd,
486 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
487 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
488 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
489 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
490 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
492 return iwl_send_cmd(priv, &cmd);
495 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
496 struct iwl_rx_mem_buffer *rxb)
498 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
499 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
500 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
503 /* reduce the size of the length field itself */
506 /* Define the order in which the results will be sent to the runtime
507 * uCode. iwl_send_calib_results sends them in a row according to their
508 * index. We sort them here */
509 switch (hdr->op_code) {
510 case IWL_PHY_CALIBRATE_DC_CMD:
511 index = IWL_CALIB_DC;
513 case IWL_PHY_CALIBRATE_LO_CMD:
514 index = IWL_CALIB_LO;
516 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
517 index = IWL_CALIB_TX_IQ;
519 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
520 index = IWL_CALIB_TX_IQ_PERD;
522 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
523 index = IWL_CALIB_BASE_BAND;
526 IWL_ERR(priv, "Unknown calibration notification %d\n",
530 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
533 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
534 struct iwl_rx_mem_buffer *rxb)
536 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
537 queue_work(priv->workqueue, &priv->restart);
543 static int iwl5000_load_section(struct iwl_priv *priv,
544 struct fw_desc *image,
547 dma_addr_t phy_addr = image->p_addr;
548 u32 byte_cnt = image->len;
550 iwl_write_direct32(priv,
551 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
552 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
554 iwl_write_direct32(priv,
555 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
557 iwl_write_direct32(priv,
558 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
559 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
561 iwl_write_direct32(priv,
562 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
563 (iwl_get_dma_hi_addr(phy_addr)
564 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
566 iwl_write_direct32(priv,
567 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
568 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
569 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
570 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
572 iwl_write_direct32(priv,
573 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
574 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
575 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
576 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
581 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
582 struct fw_desc *inst_image,
583 struct fw_desc *data_image)
587 ret = iwl5000_load_section(priv, inst_image,
588 IWL50_RTC_INST_LOWER_BOUND);
592 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
593 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
594 priv->ucode_write_complete, 5 * HZ);
595 if (ret == -ERESTARTSYS) {
596 IWL_ERR(priv, "Could not load the INST uCode section due "
601 IWL_ERR(priv, "Could not load the INST uCode section\n");
605 priv->ucode_write_complete = 0;
607 ret = iwl5000_load_section(
608 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
612 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
614 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
615 priv->ucode_write_complete, 5 * HZ);
616 if (ret == -ERESTARTSYS) {
617 IWL_ERR(priv, "Could not load the INST uCode section due "
621 IWL_ERR(priv, "Could not load the DATA uCode section\n");
626 priv->ucode_write_complete = 0;
631 int iwl5000_load_ucode(struct iwl_priv *priv)
635 /* check whether init ucode should be loaded, or rather runtime ucode */
636 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
637 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
638 ret = iwl5000_load_given_ucode(priv,
639 &priv->ucode_init, &priv->ucode_init_data);
641 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
642 priv->ucode_type = UCODE_INIT;
645 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
646 "Loading runtime ucode...\n");
647 ret = iwl5000_load_given_ucode(priv,
648 &priv->ucode_code, &priv->ucode_data);
650 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
651 priv->ucode_type = UCODE_RT;
658 void iwl5000_init_alive_start(struct iwl_priv *priv)
662 /* Check alive response for "valid" sign from uCode */
663 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
664 /* We had an error bringing up the hardware, so take it
665 * all the way back down so we can try again */
666 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
670 /* initialize uCode was loaded... verify inst image.
671 * This is a paranoid check, because we would not have gotten the
672 * "initialize" alive if code weren't properly loaded. */
673 if (iwl_verify_ucode(priv)) {
674 /* Runtime instruction load was bad;
675 * take it all the way back down so we can try again */
676 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
680 iwl_clear_stations_table(priv);
681 ret = priv->cfg->ops->lib->alive_notify(priv);
684 "Could not complete ALIVE transition: %d\n", ret);
688 iwl5000_send_calib_cfg(priv);
692 /* real restart (first load init_ucode) */
693 queue_work(priv->workqueue, &priv->restart);
696 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
697 int txq_id, u32 index)
699 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
700 (index & 0xff) | (txq_id << 8));
701 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
704 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
705 struct iwl_tx_queue *txq,
706 int tx_fifo_id, int scd_retry)
708 int txq_id = txq->q.id;
709 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
711 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
712 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
713 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
714 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
715 IWL50_SCD_QUEUE_STTS_REG_MSK);
717 txq->sched_retry = scd_retry;
719 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
720 active ? "Activate" : "Deactivate",
721 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
724 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
726 struct iwl_wimax_coex_cmd coex_cmd;
728 memset(&coex_cmd, 0, sizeof(coex_cmd));
730 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
731 sizeof(coex_cmd), &coex_cmd);
734 int iwl5000_alive_notify(struct iwl_priv *priv)
741 spin_lock_irqsave(&priv->lock, flags);
743 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
744 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
745 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
747 iwl_write_targ_mem(priv, a, 0);
748 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
750 iwl_write_targ_mem(priv, a, 0);
751 for (; a < priv->scd_base_addr +
752 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
753 iwl_write_targ_mem(priv, a, 0);
755 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
756 priv->scd_bc_tbls.dma >> 10);
758 /* Enable DMA channel */
759 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
760 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
761 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
762 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
764 /* Update FH chicken bits */
765 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
766 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
767 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
769 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
770 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
771 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
773 /* initiate the queues */
774 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
775 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
776 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
777 iwl_write_targ_mem(priv, priv->scd_base_addr +
778 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
779 iwl_write_targ_mem(priv, priv->scd_base_addr +
780 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
783 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
784 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
786 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
787 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
790 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
791 IWL_MASK(0, priv->hw_params.max_txq_num));
793 /* Activate all Tx DMA/FIFO channels */
794 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
796 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
798 /* map qos queues to fifos one-to-one */
799 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
800 int ac = iwl5000_default_queue_to_tx_fifo[i];
801 iwl_txq_ctx_activate(priv, i);
802 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
804 /* TODO - need to initialize those FIFOs inside the loop above,
805 * not only mark them as active */
806 iwl_txq_ctx_activate(priv, 4);
807 iwl_txq_ctx_activate(priv, 7);
808 iwl_txq_ctx_activate(priv, 8);
809 iwl_txq_ctx_activate(priv, 9);
811 spin_unlock_irqrestore(&priv->lock, flags);
814 iwl5000_send_wimax_coex(priv);
816 iwl5000_set_Xtal_calib(priv);
817 iwl_send_calib_results(priv);
822 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
824 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
825 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
827 "invalid queues_num, should be between %d and %d\n",
828 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
832 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
833 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
834 priv->hw_params.scd_bc_tbls_size =
835 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
836 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
837 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
838 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
840 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
841 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
843 priv->hw_params.max_bsm_size = 0;
844 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
845 BIT(IEEE80211_BAND_5GHZ);
846 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
848 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
849 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
850 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
851 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
853 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
854 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
856 /* Set initial sensitivity parameters */
857 /* Set initial calibration set */
858 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
859 case CSR_HW_REV_TYPE_5150:
860 priv->hw_params.sens = &iwl5150_sensitivity;
861 priv->hw_params.calib_init_cfg =
864 BIT(IWL_CALIB_TX_IQ) |
865 BIT(IWL_CALIB_BASE_BAND);
869 priv->hw_params.sens = &iwl5000_sensitivity;
870 priv->hw_params.calib_init_cfg =
871 BIT(IWL_CALIB_XTAL) |
873 BIT(IWL_CALIB_TX_IQ) |
874 BIT(IWL_CALIB_TX_IQ_PERD) |
875 BIT(IWL_CALIB_BASE_BAND);
883 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
885 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
886 struct iwl_tx_queue *txq,
889 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
890 int write_ptr = txq->q.write_ptr;
891 int txq_id = txq->q.id;
894 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
897 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
899 if (txq_id != IWL_CMD_QUEUE_NUM) {
900 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
901 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
903 switch (sec_ctl & TX_CMD_SEC_MSK) {
907 case TX_CMD_SEC_TKIP:
911 len += WEP_IV_LEN + WEP_ICV_LEN;
916 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
918 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
920 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
922 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
925 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
926 struct iwl_tx_queue *txq)
928 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
929 int txq_id = txq->q.id;
930 int read_ptr = txq->q.read_ptr;
934 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
936 if (txq_id != IWL_CMD_QUEUE_NUM)
937 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
939 bc_ent = cpu_to_le16(1 | (sta_id << 12));
940 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
942 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
944 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
947 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
954 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
956 tbl_dw_addr = priv->scd_base_addr +
957 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
959 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
962 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
964 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
966 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
970 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
972 /* Simply stop the queue, but don't change any configuration;
973 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
975 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
976 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
977 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
980 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
981 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
986 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
987 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
989 "queue number out of range: %d, must be %d to %d\n",
990 txq_id, IWL50_FIRST_AMPDU_QUEUE,
991 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
995 ra_tid = BUILD_RAxTID(sta_id, tid);
997 /* Modify device's station table to Tx this TID */
998 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1000 spin_lock_irqsave(&priv->lock, flags);
1002 /* Stop this Tx queue before configuring it */
1003 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1005 /* Map receiver-address / traffic-ID to this queue */
1006 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1008 /* Set this queue as a chain-building queue */
1009 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1011 /* enable aggregations for the queue */
1012 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1014 /* Place first TFD at index corresponding to start sequence number.
1015 * Assumes that ssn_idx is valid (!= 0xFFF) */
1016 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1017 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1018 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1020 /* Set up Tx window size and frame limit for this queue */
1021 iwl_write_targ_mem(priv, priv->scd_base_addr +
1022 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1025 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1026 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1027 ((SCD_FRAME_LIMIT <<
1028 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1029 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1031 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1033 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1034 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1036 spin_unlock_irqrestore(&priv->lock, flags);
1041 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1042 u16 ssn_idx, u8 tx_fifo)
1044 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1045 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1047 "queue number out of range: %d, must be %d to %d\n",
1048 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1049 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1053 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1055 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1057 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1058 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1059 /* supposes that ssn_idx is valid (!= 0xFFF) */
1060 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1062 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1063 iwl_txq_ctx_deactivate(priv, txq_id);
1064 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1069 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1071 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1072 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1073 memcpy(addsta, cmd, size);
1074 /* resrved in 5000 */
1075 addsta->rate_n_flags = cpu_to_le16(0);
1081 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1082 * must be called under priv->lock and mac access
1084 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1086 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1090 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1092 return le32_to_cpup((__le32 *)&tx_resp->status +
1093 tx_resp->frame_count) & MAX_SN;
1096 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1097 struct iwl_ht_agg *agg,
1098 struct iwl5000_tx_resp *tx_resp,
1099 int txq_id, u16 start_idx)
1102 struct agg_tx_status *frame_status = &tx_resp->status;
1103 struct ieee80211_tx_info *info = NULL;
1104 struct ieee80211_hdr *hdr = NULL;
1105 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1109 if (agg->wait_for_ba)
1110 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1112 agg->frame_count = tx_resp->frame_count;
1113 agg->start_idx = start_idx;
1114 agg->rate_n_flags = rate_n_flags;
1117 /* # frames attempted by Tx command */
1118 if (agg->frame_count == 1) {
1119 /* Only one frame was attempted; no block-ack will arrive */
1120 status = le16_to_cpu(frame_status[0].status);
1123 /* FIXME: code repetition */
1124 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1125 agg->frame_count, agg->start_idx, idx);
1127 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1128 info->status.rates[0].count = tx_resp->failure_frame + 1;
1129 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1130 info->flags |= iwl_is_tx_success(status) ?
1131 IEEE80211_TX_STAT_ACK : 0;
1132 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1134 /* FIXME: code repetition end */
1136 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1137 status & 0xff, tx_resp->failure_frame);
1138 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1140 agg->wait_for_ba = 0;
1142 /* Two or more frames were attempted; expect block-ack */
1144 int start = agg->start_idx;
1146 /* Construct bit-map of pending frames within Tx window */
1147 for (i = 0; i < agg->frame_count; i++) {
1149 status = le16_to_cpu(frame_status[i].status);
1150 seq = le16_to_cpu(frame_status[i].sequence);
1151 idx = SEQ_TO_INDEX(seq);
1152 txq_id = SEQ_TO_QUEUE(seq);
1154 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1155 AGG_TX_STATE_ABORT_MSK))
1158 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1159 agg->frame_count, txq_id, idx);
1161 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1164 "BUG_ON idx doesn't point to valid skb"
1165 " idx=%d, txq_id=%d\n", idx, txq_id);
1169 sc = le16_to_cpu(hdr->seq_ctrl);
1170 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1172 "BUG_ON idx doesn't match seq control"
1173 " idx=%d, seq_idx=%d, seq=%d\n",
1179 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1180 i, idx, SEQ_TO_SN(sc));
1184 sh = (start - idx) + 0xff;
1185 bitmap = bitmap << sh;
1188 } else if (sh < -64)
1189 sh = 0xff - (start - idx);
1193 bitmap = bitmap << sh;
1196 bitmap |= 1ULL << sh;
1197 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1198 start, (unsigned long long)bitmap);
1201 agg->bitmap = bitmap;
1202 agg->start_idx = start;
1203 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1204 agg->frame_count, agg->start_idx,
1205 (unsigned long long)agg->bitmap);
1208 agg->wait_for_ba = 1;
1213 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1214 struct iwl_rx_mem_buffer *rxb)
1216 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1217 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1218 int txq_id = SEQ_TO_QUEUE(sequence);
1219 int index = SEQ_TO_INDEX(sequence);
1220 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1221 struct ieee80211_tx_info *info;
1222 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1223 u32 status = le16_to_cpu(tx_resp->status.status);
1228 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1229 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1230 "is out of range [0-%d] %d %d\n", txq_id,
1231 index, txq->q.n_bd, txq->q.write_ptr,
1236 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1237 memset(&info->status, 0, sizeof(info->status));
1239 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1240 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1242 if (txq->sched_retry) {
1243 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1244 struct iwl_ht_agg *agg = NULL;
1246 agg = &priv->stations[sta_id].tid[tid].agg;
1248 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1250 /* check if BAR is needed */
1251 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1252 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1254 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1255 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1256 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1257 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1258 scd_ssn , index, txq_id, txq->swq_id);
1260 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1261 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1263 if (priv->mac80211_registered &&
1264 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1265 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1266 if (agg->state == IWL_AGG_OFF)
1267 iwl_wake_queue(priv, txq_id);
1269 iwl_wake_queue(priv, txq->swq_id);
1273 BUG_ON(txq_id != txq->swq_id);
1275 info->status.rates[0].count = tx_resp->failure_frame + 1;
1276 info->flags |= iwl_is_tx_success(status) ?
1277 IEEE80211_TX_STAT_ACK : 0;
1278 iwl_hwrate_to_tx_control(priv,
1279 le32_to_cpu(tx_resp->rate_n_flags),
1282 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1283 "0x%x retries %d\n",
1285 iwl_get_tx_fail_reason(status), status,
1286 le32_to_cpu(tx_resp->rate_n_flags),
1287 tx_resp->failure_frame);
1289 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1290 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1291 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1293 if (priv->mac80211_registered &&
1294 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1295 iwl_wake_queue(priv, txq_id);
1298 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1299 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1301 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1302 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1305 /* Currently 5000 is the superset of everything */
1306 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1311 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1313 /* in 5000 the tx power calibration is done in uCode */
1314 priv->disable_tx_power_cal = 1;
1317 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1319 /* init calibration handlers */
1320 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1321 iwl5000_rx_calib_result;
1322 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1323 iwl5000_rx_calib_complete;
1324 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1328 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1330 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1331 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1334 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1337 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1338 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1339 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1341 if ((rxon1->flags == rxon2->flags) &&
1342 (rxon1->filter_flags == rxon2->filter_flags) &&
1343 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1344 (rxon1->ofdm_ht_single_stream_basic_rates ==
1345 rxon2->ofdm_ht_single_stream_basic_rates) &&
1346 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1347 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1348 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1349 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1350 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1351 (rxon1->rx_chain == rxon2->rx_chain) &&
1352 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1353 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1357 rxon_assoc.flags = priv->staging_rxon.flags;
1358 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1359 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1360 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1361 rxon_assoc.reserved1 = 0;
1362 rxon_assoc.reserved2 = 0;
1363 rxon_assoc.reserved3 = 0;
1364 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1365 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1366 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1367 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1368 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1369 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1370 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1371 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1373 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1374 sizeof(rxon_assoc), &rxon_assoc, NULL);
1380 int iwl5000_send_tx_power(struct iwl_priv *priv)
1382 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1385 /* half dBm need to multiply */
1386 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1387 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1388 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1390 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1391 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1393 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1395 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1396 sizeof(tx_power_cmd), &tx_power_cmd,
1400 void iwl5000_temperature(struct iwl_priv *priv)
1402 /* store temperature from statistics (in Celsius) */
1403 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1404 iwl_tt_handler(priv);
1407 static void iwl5150_temperature(struct iwl_priv *priv)
1410 s32 offset = iwl_temp_calib_to_offset(priv);
1412 vt = le32_to_cpu(priv->statistics.general.temperature);
1413 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1414 /* now vt hold the temperature in Kelvin */
1415 priv->temperature = KELVIN_TO_CELSIUS(vt);
1416 iwl_tt_handler(priv);
1419 /* Calc max signal level (dBm) among 3 possible receivers */
1420 int iwl5000_calc_rssi(struct iwl_priv *priv,
1421 struct iwl_rx_phy_res *rx_resp)
1423 /* data from PHY/DSP regarding signal strength, etc.,
1424 * contents are always there, not configurable by host
1426 struct iwl5000_non_cfg_phy *ncphy =
1427 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1428 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1431 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1432 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1434 /* Find max rssi among 3 possible receivers.
1435 * These values are measured by the digital signal processor (DSP).
1436 * They should stay fairly constant even as the signal strength varies,
1437 * if the radio's automatic gain control (AGC) is working right.
1438 * AGC value (see below) will provide the "interesting" info.
1440 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1441 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1442 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1443 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1444 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1446 max_rssi = max_t(u32, rssi_a, rssi_b);
1447 max_rssi = max_t(u32, max_rssi, rssi_c);
1449 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1450 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1452 /* dBm = max_rssi dB - agc dB - constant.
1453 * Higher AGC (higher radio gain) means lower signal. */
1454 return max_rssi - agc - IWL49_RSSI_OFFSET;
1457 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1459 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1460 .valid = cpu_to_le32(valid_tx_ant),
1463 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1464 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1465 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1466 sizeof(struct iwl_tx_ant_config_cmd),
1469 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1475 #define IWL5000_UCODE_GET(item) \
1476 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1480 return le32_to_cpu(ucode->u.v1.item); \
1481 return le32_to_cpu(ucode->u.v2.item); \
1484 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1487 return UCODE_HEADER_SIZE(1);
1488 return UCODE_HEADER_SIZE(2);
1491 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1496 return le32_to_cpu(ucode->u.v2.build);
1499 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1503 return (u8 *) ucode->u.v1.data;
1504 return (u8 *) ucode->u.v2.data;
1507 IWL5000_UCODE_GET(inst_size);
1508 IWL5000_UCODE_GET(data_size);
1509 IWL5000_UCODE_GET(init_size);
1510 IWL5000_UCODE_GET(init_data_size);
1511 IWL5000_UCODE_GET(boot_size);
1513 struct iwl_hcmd_ops iwl5000_hcmd = {
1514 .rxon_assoc = iwl5000_send_rxon_assoc,
1515 .commit_rxon = iwl_commit_rxon,
1516 .set_rxon_chain = iwl_set_rxon_chain,
1517 .set_tx_ant = iwl5000_send_tx_ant_config,
1520 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1521 .get_hcmd_size = iwl5000_get_hcmd_size,
1522 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1523 .gain_computation = iwl5000_gain_computation,
1524 .chain_noise_reset = iwl5000_chain_noise_reset,
1525 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1526 .calc_rssi = iwl5000_calc_rssi,
1529 struct iwl_ucode_ops iwl5000_ucode = {
1530 .get_header_size = iwl5000_ucode_get_header_size,
1531 .get_build = iwl5000_ucode_get_build,
1532 .get_inst_size = iwl5000_ucode_get_inst_size,
1533 .get_data_size = iwl5000_ucode_get_data_size,
1534 .get_init_size = iwl5000_ucode_get_init_size,
1535 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1536 .get_boot_size = iwl5000_ucode_get_boot_size,
1537 .get_data = iwl5000_ucode_get_data,
1540 struct iwl_lib_ops iwl5000_lib = {
1541 .set_hw_params = iwl5000_hw_set_hw_params,
1542 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1543 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1544 .txq_set_sched = iwl5000_txq_set_sched,
1545 .txq_agg_enable = iwl5000_txq_agg_enable,
1546 .txq_agg_disable = iwl5000_txq_agg_disable,
1547 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1548 .txq_free_tfd = iwl_hw_txq_free_tfd,
1549 .txq_init = iwl_hw_tx_queue_init,
1550 .rx_handler_setup = iwl5000_rx_handler_setup,
1551 .setup_deferred_work = iwl5000_setup_deferred_work,
1552 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1553 .dump_nic_event_log = iwl_dump_nic_event_log,
1554 .dump_nic_error_log = iwl_dump_nic_error_log,
1555 .load_ucode = iwl5000_load_ucode,
1556 .init_alive_start = iwl5000_init_alive_start,
1557 .alive_notify = iwl5000_alive_notify,
1558 .send_tx_power = iwl5000_send_tx_power,
1559 .update_chain_flags = iwl_update_chain_flags,
1561 .init = iwl5000_apm_init,
1562 .reset = iwl5000_apm_reset,
1563 .stop = iwl5000_apm_stop,
1564 .config = iwl5000_nic_config,
1565 .set_pwr_src = iwl_set_pwr_src,
1568 .regulatory_bands = {
1569 EEPROM_5000_REG_BAND_1_CHANNELS,
1570 EEPROM_5000_REG_BAND_2_CHANNELS,
1571 EEPROM_5000_REG_BAND_3_CHANNELS,
1572 EEPROM_5000_REG_BAND_4_CHANNELS,
1573 EEPROM_5000_REG_BAND_5_CHANNELS,
1574 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1575 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1577 .verify_signature = iwlcore_eeprom_verify_signature,
1578 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1579 .release_semaphore = iwlcore_eeprom_release_semaphore,
1580 .calib_version = iwl5000_eeprom_calib_version,
1581 .query_addr = iwl5000_eeprom_query_addr,
1583 .post_associate = iwl_post_associate,
1585 .config_ap = iwl_config_ap,
1587 .temperature = iwl5000_temperature,
1588 .set_ct_kill = iwl5000_set_ct_threshold,
1592 static struct iwl_lib_ops iwl5150_lib = {
1593 .set_hw_params = iwl5000_hw_set_hw_params,
1594 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1595 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1596 .txq_set_sched = iwl5000_txq_set_sched,
1597 .txq_agg_enable = iwl5000_txq_agg_enable,
1598 .txq_agg_disable = iwl5000_txq_agg_disable,
1599 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1600 .txq_free_tfd = iwl_hw_txq_free_tfd,
1601 .txq_init = iwl_hw_tx_queue_init,
1602 .rx_handler_setup = iwl5000_rx_handler_setup,
1603 .setup_deferred_work = iwl5000_setup_deferred_work,
1604 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1605 .dump_nic_event_log = iwl_dump_nic_event_log,
1606 .dump_nic_error_log = iwl_dump_nic_error_log,
1607 .load_ucode = iwl5000_load_ucode,
1608 .init_alive_start = iwl5000_init_alive_start,
1609 .alive_notify = iwl5000_alive_notify,
1610 .send_tx_power = iwl5000_send_tx_power,
1611 .update_chain_flags = iwl_update_chain_flags,
1613 .init = iwl5000_apm_init,
1614 .reset = iwl5000_apm_reset,
1615 .stop = iwl5000_apm_stop,
1616 .config = iwl5000_nic_config,
1617 .set_pwr_src = iwl_set_pwr_src,
1620 .regulatory_bands = {
1621 EEPROM_5000_REG_BAND_1_CHANNELS,
1622 EEPROM_5000_REG_BAND_2_CHANNELS,
1623 EEPROM_5000_REG_BAND_3_CHANNELS,
1624 EEPROM_5000_REG_BAND_4_CHANNELS,
1625 EEPROM_5000_REG_BAND_5_CHANNELS,
1626 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1627 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1629 .verify_signature = iwlcore_eeprom_verify_signature,
1630 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1631 .release_semaphore = iwlcore_eeprom_release_semaphore,
1632 .calib_version = iwl5000_eeprom_calib_version,
1633 .query_addr = iwl5000_eeprom_query_addr,
1635 .post_associate = iwl_post_associate,
1637 .config_ap = iwl_config_ap,
1639 .temperature = iwl5150_temperature,
1640 .set_ct_kill = iwl5150_set_ct_threshold,
1644 struct iwl_ops iwl5000_ops = {
1645 .ucode = &iwl5000_ucode,
1646 .lib = &iwl5000_lib,
1647 .hcmd = &iwl5000_hcmd,
1648 .utils = &iwl5000_hcmd_utils,
1651 static struct iwl_ops iwl5150_ops = {
1652 .ucode = &iwl5000_ucode,
1653 .lib = &iwl5150_lib,
1654 .hcmd = &iwl5000_hcmd,
1655 .utils = &iwl5000_hcmd_utils,
1658 struct iwl_mod_params iwl50_mod_params = {
1659 .num_of_queues = IWL50_NUM_QUEUES,
1660 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1663 /* the rest are 0 by default */
1667 struct iwl_cfg iwl5300_agn_cfg = {
1669 .fw_name_pre = IWL5000_FW_PRE,
1670 .ucode_api_max = IWL5000_UCODE_API_MAX,
1671 .ucode_api_min = IWL5000_UCODE_API_MIN,
1672 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1673 .ops = &iwl5000_ops,
1674 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1675 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1676 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1677 .mod_params = &iwl50_mod_params,
1678 .valid_tx_ant = ANT_ABC,
1679 .valid_rx_ant = ANT_ABC,
1680 .need_pll_cfg = true,
1681 .ht_greenfield_support = true,
1682 .led_compensation = 51,
1683 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1686 struct iwl_cfg iwl5100_bg_cfg = {
1688 .fw_name_pre = IWL5000_FW_PRE,
1689 .ucode_api_max = IWL5000_UCODE_API_MAX,
1690 .ucode_api_min = IWL5000_UCODE_API_MIN,
1692 .ops = &iwl5000_ops,
1693 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1694 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1695 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1696 .mod_params = &iwl50_mod_params,
1697 .valid_tx_ant = ANT_B,
1698 .valid_rx_ant = ANT_AB,
1699 .need_pll_cfg = true,
1700 .ht_greenfield_support = true,
1701 .led_compensation = 51,
1702 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1705 struct iwl_cfg iwl5100_abg_cfg = {
1707 .fw_name_pre = IWL5000_FW_PRE,
1708 .ucode_api_max = IWL5000_UCODE_API_MAX,
1709 .ucode_api_min = IWL5000_UCODE_API_MIN,
1710 .sku = IWL_SKU_A|IWL_SKU_G,
1711 .ops = &iwl5000_ops,
1712 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1713 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1714 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1715 .mod_params = &iwl50_mod_params,
1716 .valid_tx_ant = ANT_B,
1717 .valid_rx_ant = ANT_AB,
1718 .need_pll_cfg = true,
1719 .ht_greenfield_support = true,
1720 .led_compensation = 51,
1721 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1724 struct iwl_cfg iwl5100_agn_cfg = {
1726 .fw_name_pre = IWL5000_FW_PRE,
1727 .ucode_api_max = IWL5000_UCODE_API_MAX,
1728 .ucode_api_min = IWL5000_UCODE_API_MIN,
1729 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1730 .ops = &iwl5000_ops,
1731 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1732 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1733 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1734 .mod_params = &iwl50_mod_params,
1735 .valid_tx_ant = ANT_B,
1736 .valid_rx_ant = ANT_AB,
1737 .need_pll_cfg = true,
1738 .ht_greenfield_support = true,
1739 .led_compensation = 51,
1740 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1743 struct iwl_cfg iwl5350_agn_cfg = {
1745 .fw_name_pre = IWL5000_FW_PRE,
1746 .ucode_api_max = IWL5000_UCODE_API_MAX,
1747 .ucode_api_min = IWL5000_UCODE_API_MIN,
1748 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1749 .ops = &iwl5000_ops,
1750 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1751 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1752 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1753 .mod_params = &iwl50_mod_params,
1754 .valid_tx_ant = ANT_ABC,
1755 .valid_rx_ant = ANT_ABC,
1756 .need_pll_cfg = true,
1757 .ht_greenfield_support = true,
1758 .led_compensation = 51,
1759 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1762 struct iwl_cfg iwl5150_agn_cfg = {
1764 .fw_name_pre = IWL5150_FW_PRE,
1765 .ucode_api_max = IWL5150_UCODE_API_MAX,
1766 .ucode_api_min = IWL5150_UCODE_API_MIN,
1767 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1768 .ops = &iwl5150_ops,
1769 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1770 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1771 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1772 .mod_params = &iwl50_mod_params,
1773 .valid_tx_ant = ANT_A,
1774 .valid_rx_ant = ANT_AB,
1775 .need_pll_cfg = true,
1776 .ht_greenfield_support = true,
1777 .led_compensation = 51,
1778 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1781 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1782 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1784 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1785 MODULE_PARM_DESC(swcrypto50,
1786 "using software crypto engine (default 0 [hardware])\n");
1787 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1788 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1789 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1790 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1791 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1793 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1794 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1795 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");