drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-5000-hw.h"
  47 #include "iwl-6000-hw.h"
  48
  49 /* Highest firmware API version supported */
  50 #define IWL5000_UCODE_API_MAX 2
  51 #define IWL5150_UCODE_API_MAX 2
  52
  53 /* Lowest firmware API version supported */
  54 #define IWL5000_UCODE_API_MIN 1
  55 #define IWL5150_UCODE_API_MIN 1
  56
  57 #define IWL5000_FW_PRE "iwlwifi-5000-"
  58 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  59 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  60
  61 #define IWL5150_FW_PRE "iwlwifi-5150-"
  62 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  63 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  64
  65 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  66         IWL_TX_FIFO_AC3,
  67         IWL_TX_FIFO_AC2,
  68         IWL_TX_FIFO_AC1,
  69         IWL_TX_FIFO_AC0,
  70         IWL50_CMD_FIFO_NUM,
  71         IWL_TX_FIFO_HCCA_1,
  72         IWL_TX_FIFO_HCCA_2
  73 };
  74
  75 /* FIXME: same implementation as 4965 */
  76 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  77 {
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&priv->lock, flags);
  81
  82         /* set stop master bit */
  83         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  84
  85         iwl_poll_direct_bit(priv, CSR_RESET,
  86                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  87
  88         spin_unlock_irqrestore(&priv->lock, flags);
  89         IWL_DEBUG_INFO(priv, "stop master\n");
  90
  91         return 0;
  92 }
  93
  94
  95 int iwl5000_apm_init(struct iwl_priv *priv)
  96 {
  97         int ret = 0;
  98
  99         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 100                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 101
 102         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 103         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 104                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 105
 106         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 107         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 108
 109         /* enable HAP INTA to move device L1a -> L0s */
 110         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 111                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 112
 113         if (priv->cfg->need_pll_cfg)
 114                 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 115
 116         /* set "initialization complete" bit to move adapter
 117          * D0U* --> D0A* state */
 118         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 119
 120         /* wait for clock stabilization */
 121         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 122                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 123         if (ret < 0) {
 124                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 125                 return ret;
 126         }
 127
 128         /* enable DMA */
 129         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 130
 131         udelay(20);
 132
 133         /* disable L1-Active */
 134         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 135                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 136
 137         return ret;
 138 }
 139
 140 /* FIXME: this is identical to 4965 */
 141 void iwl5000_apm_stop(struct iwl_priv *priv)
 142 {
 143         unsigned long flags;
 144
 145         iwl5000_apm_stop_master(priv);
 146
 147         spin_lock_irqsave(&priv->lock, flags);
 148
 149         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 150
 151         udelay(10);
 152
 153         /* clear "init complete"  move adapter D0A* --> D0U state */
 154         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 155
 156         spin_unlock_irqrestore(&priv->lock, flags);
 157 }
 158
 159
 160 int iwl5000_apm_reset(struct iwl_priv *priv)
 161 {
 162         int ret = 0;
 163
 164         iwl5000_apm_stop_master(priv);
 165
 166         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 167
 168         udelay(10);
 169
 170
 171         /* FIXME: put here L1A -L0S w/a */
 172
 173         if (priv->cfg->need_pll_cfg)
 174                 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 175
 176         /* set "initialization complete" bit to move adapter
 177          * D0U* --> D0A* state */
 178         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 179
 180         /* wait for clock stabilization */
 181         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 182                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 183         if (ret < 0) {
 184                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 185                 goto out;
 186         }
 187
 188         /* enable DMA */
 189         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 190
 191         udelay(20);
 192
 193         /* disable L1-Active */
 194         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 195                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 196 out:
 197
 198         return ret;
 199 }
 200
 201
 202 /* NIC configuration for 5000 series and up */
 203 void iwl5000_nic_config(struct iwl_priv *priv)
 204 {
 205         unsigned long flags;
 206         u16 radio_cfg;
 207         u16 lctl;
 208
 209         spin_lock_irqsave(&priv->lock, flags);
 210
 211         lctl = iwl_pcie_link_ctl(priv);
 212
 213         /* HW bug W/A */
 214         /* L1-ASPM is enabled by BIOS */
 215         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 216                 /* L1-APSM enabled: disable L0S  */
 217                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 218         else
 219                 /* L1-ASPM disabled: enable L0S */
 220                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221
 222         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 223
 224         /* write radio config values to register */
 225         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 226                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 227                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 228                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 229                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 230
 231         /* set CSR_HW_CONFIG_REG for uCode use */
 232         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 233                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 234                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 235
 236         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 237          * (PCIe power is lost before PERST# is asserted),
 238          * causing ME FW to lose ownership and not being able to obtain it back.
 239          */
 240         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 241                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 242                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 243
 244
 245         spin_unlock_irqrestore(&priv->lock, flags);
 246 }
 247
 248
 249 /*
 250  * EEPROM
 251  */
 252 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 253 {
 254         u16 offset = 0;
 255
 256         if ((address & INDIRECT_ADDRESS) == 0)
 257                 return address;
 258
 259         switch (address & INDIRECT_TYPE_MSK) {
 260         case INDIRECT_HOST:
 261                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 262                 break;
 263         case INDIRECT_GENERAL:
 264                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 265                 break;
 266         case INDIRECT_REGULATORY:
 267                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 268                 break;
 269         case INDIRECT_CALIBRATION:
 270                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 271                 break;
 272         case INDIRECT_PROCESS_ADJST:
 273                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 274                 break;
 275         case INDIRECT_OTHERS:
 276                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 277                 break;
 278         default:
 279                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 280                 address & INDIRECT_TYPE_MSK);
 281                 break;
 282         }
 283
 284         /* translate the offset from words to byte */
 285         return (address & ADDRESS_MSK) + (offset << 1);
 286 }
 287
 288 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 289 {
 290         struct iwl_eeprom_calib_hdr {
 291                 u8 version;
 292                 u8 pa_type;
 293                 u16 voltage;
 294         } *hdr;
 295
 296         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 297                                                         EEPROM_5000_CALIB_ALL);
 298         return hdr->version;
 299
 300 }
 301
 302 static void iwl5000_gain_computation(struct iwl_priv *priv,
 303                 u32 average_noise[NUM_RX_CHAINS],
 304                 u16 min_average_noise_antenna_i,
 305                 u32 min_average_noise)
 306 {
 307         int i;
 308         s32 delta_g;
 309         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 310
 311         /* Find Gain Code for the antennas B and C */
 312         for (i = 1; i < NUM_RX_CHAINS; i++) {
 313                 if ((data->disconn_array[i])) {
 314                         data->delta_gain_code[i] = 0;
 315                         continue;
 316                 }
 317                 delta_g = (1000 * ((s32)average_noise[0] -
 318                         (s32)average_noise[i])) / 1500;
 319                 /* bound gain by 2 bits value max, 3rd bit is sign */
 320                 data->delta_gain_code[i] =
 321                         min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 322
 323                 if (delta_g < 0)
 324                         /* set negative sign */
 325                         data->delta_gain_code[i] |= (1 << 2);
 326         }
 327
 328         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 329                         data->delta_gain_code[1], data->delta_gain_code[2]);
 330
 331         if (!data->radio_write) {
 332                 struct iwl_calib_chain_noise_gain_cmd cmd;
 333
 334                 memset(&cmd, 0, sizeof(cmd));
 335
 336                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 337                 cmd.hdr.first_group = 0;
 338                 cmd.hdr.groups_num = 1;
 339                 cmd.hdr.data_valid = 1;
 340                 cmd.delta_gain_1 = data->delta_gain_code[1];
 341                 cmd.delta_gain_2 = data->delta_gain_code[2];
 342                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 343                         sizeof(cmd), &cmd, NULL);
 344
 345                 data->radio_write = 1;
 346                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 347         }
 348
 349         data->chain_noise_a = 0;
 350         data->chain_noise_b = 0;
 351         data->chain_noise_c = 0;
 352         data->chain_signal_a = 0;
 353         data->chain_signal_b = 0;
 354         data->chain_signal_c = 0;
 355         data->beacon_count = 0;
 356 }
 357
 358 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 359 {
 360         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 361         int ret;
 362
 363         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 364                 struct iwl_calib_chain_noise_reset_cmd cmd;
 365                 memset(&cmd, 0, sizeof(cmd));
 366
 367                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 368                 cmd.hdr.first_group = 0;
 369                 cmd.hdr.groups_num = 1;
 370                 cmd.hdr.data_valid = 1;
 371                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 372                                         sizeof(cmd), &cmd);
 373                 if (ret)
 374                         IWL_ERR(priv,
 375                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 376                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 377                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 378         }
 379 }
 380
 381 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 382                         __le32 *tx_flags)
 383 {
 384         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 385             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 386                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 387         else
 388                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 389 }
 390
 391 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 392         .min_nrg_cck = 95,
 393         .max_nrg_cck = 0, /* not used, set to 0 */
 394         .auto_corr_min_ofdm = 90,
 395         .auto_corr_min_ofdm_mrc = 170,
 396         .auto_corr_min_ofdm_x1 = 120,
 397         .auto_corr_min_ofdm_mrc_x1 = 240,
 398
 399         .auto_corr_max_ofdm = 120,
 400         .auto_corr_max_ofdm_mrc = 210,
 401         .auto_corr_max_ofdm_x1 = 155,
 402         .auto_corr_max_ofdm_mrc_x1 = 290,
 403
 404         .auto_corr_min_cck = 125,
 405         .auto_corr_max_cck = 200,
 406         .auto_corr_min_cck_mrc = 170,
 407         .auto_corr_max_cck_mrc = 400,
 408         .nrg_th_cck = 95,
 409         .nrg_th_ofdm = 95,
 410 };
 411
 412 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 413         .min_nrg_cck = 95,
 414         .max_nrg_cck = 0, /* not used, set to 0 */
 415         .auto_corr_min_ofdm = 90,
 416         .auto_corr_min_ofdm_mrc = 170,
 417         .auto_corr_min_ofdm_x1 = 105,
 418         .auto_corr_min_ofdm_mrc_x1 = 220,
 419
 420         .auto_corr_max_ofdm = 120,
 421         .auto_corr_max_ofdm_mrc = 210,
 422         /* max = min for performance bug in 5150 DSP */
 423         .auto_corr_max_ofdm_x1 = 105,
 424         .auto_corr_max_ofdm_mrc_x1 = 220,
 425
 426         .auto_corr_min_cck = 125,
 427         .auto_corr_max_cck = 200,
 428         .auto_corr_min_cck_mrc = 170,
 429         .auto_corr_max_cck_mrc = 400,
 430         .nrg_th_cck = 95,
 431         .nrg_th_ofdm = 95,
 432 };
 433
 434 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 435                                            size_t offset)
 436 {
 437         u32 address = eeprom_indirect_address(priv, offset);
 438         BUG_ON(address >= priv->cfg->eeprom_size);
 439         return &priv->eeprom[address];
 440 }
 441
 442 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 443 {
 444         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 445         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 446                         iwl_temp_calib_to_offset(priv);
 447
 448         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 449 }
 450
 451 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 452 {
 453         /* want Celsius */
 454         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 455 }
 456
 457 /*
 458  *  Calibration
 459  */
 460 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 461 {
 462         struct iwl_calib_xtal_freq_cmd cmd;
 463         __le16 *xtal_calib =
 464                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 465
 466         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 467         cmd.hdr.first_group = 0;
 468         cmd.hdr.groups_num = 1;
 469         cmd.hdr.data_valid = 1;
 470         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 471         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 472         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 473                              (u8 *)&cmd, sizeof(cmd));
 474 }
 475
 476 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 477 {
 478         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 479         struct iwl_host_cmd cmd = {
 480                 .id = CALIBRATION_CFG_CMD,
 481                 .len = sizeof(struct iwl_calib_cfg_cmd),
 482                 .data = &calib_cfg_cmd,
 483         };
 484
 485         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 486         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 487         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 488         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 489         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 490
 491         return iwl_send_cmd(priv, &cmd);
 492 }
 493
 494 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 495                              struct iwl_rx_mem_buffer *rxb)
 496 {
 497         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 498         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 499         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 500         int index;
 501
 502         /* reduce the size of the length field itself */
 503         len -= 4;
 504
 505         /* Define the order in which the results will be sent to the runtime
 506          * uCode. iwl_send_calib_results sends them in a row according to their
 507          * index. We sort them here */
 508         switch (hdr->op_code) {
 509         case IWL_PHY_CALIBRATE_DC_CMD:
 510                 index = IWL_CALIB_DC;
 511                 break;
 512         case IWL_PHY_CALIBRATE_LO_CMD:
 513                 index = IWL_CALIB_LO;
 514                 break;
 515         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 516                 index = IWL_CALIB_TX_IQ;
 517                 break;
 518         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 519                 index = IWL_CALIB_TX_IQ_PERD;
 520                 break;
 521         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 522                 index = IWL_CALIB_BASE_BAND;
 523                 break;
 524         default:
 525                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 526                           hdr->op_code);
 527                 return;
 528         }
 529         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 530 }
 531
 532 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 533                                struct iwl_rx_mem_buffer *rxb)
 534 {
 535         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 536         queue_work(priv->workqueue, &priv->restart);
 537 }
 538
 539 /*
 540  * ucode
 541  */
 542 static int iwl5000_load_section(struct iwl_priv *priv,
 543                                 struct fw_desc *image,
 544                                 u32 dst_addr)
 545 {
 546         dma_addr_t phy_addr = image->p_addr;
 547         u32 byte_cnt = image->len;
 548
 549         iwl_write_direct32(priv,
 550                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 551                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 552
 553         iwl_write_direct32(priv,
 554                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 555
 556         iwl_write_direct32(priv,
 557                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 558                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 559
 560         iwl_write_direct32(priv,
 561                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 562                 (iwl_get_dma_hi_addr(phy_addr)
 563                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 564
 565         iwl_write_direct32(priv,
 566                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 567                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 568                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 569                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 570
 571         iwl_write_direct32(priv,
 572                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 573                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 574                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 575                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 576
 577         return 0;
 578 }
 579
 580 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 581                 struct fw_desc *inst_image,
 582                 struct fw_desc *data_image)
 583 {
 584         int ret = 0;
 585
 586         ret = iwl5000_load_section(priv, inst_image,
 587                                    IWL50_RTC_INST_LOWER_BOUND);
 588         if (ret)
 589                 return ret;
 590
 591         IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
 592         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 593                                         priv->ucode_write_complete, 5 * HZ);
 594         if (ret == -ERESTARTSYS) {
 595                 IWL_ERR(priv, "Could not load the INST uCode section due "
 596                         "to interrupt\n");
 597                 return ret;
 598         }
 599         if (!ret) {
 600                 IWL_ERR(priv, "Could not load the INST uCode section\n");
 601                 return -ETIMEDOUT;
 602         }
 603
 604         priv->ucode_write_complete = 0;
 605
 606         ret = iwl5000_load_section(
 607                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
 608         if (ret)
 609                 return ret;
 610
 611         IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
 612
 613         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 614                                 priv->ucode_write_complete, 5 * HZ);
 615         if (ret == -ERESTARTSYS) {
 616                 IWL_ERR(priv, "Could not load the INST uCode section due "
 617                         "to interrupt\n");
 618                 return ret;
 619         } else if (!ret) {
 620                 IWL_ERR(priv, "Could not load the DATA uCode section\n");
 621                 return -ETIMEDOUT;
 622         } else
 623                 ret = 0;
 624
 625         priv->ucode_write_complete = 0;
 626
 627         return ret;
 628 }
 629
 630 int iwl5000_load_ucode(struct iwl_priv *priv)
 631 {
 632         int ret = 0;
 633
 634         /* check whether init ucode should be loaded, or rather runtime ucode */
 635         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 636                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 637                 ret = iwl5000_load_given_ucode(priv,
 638                         &priv->ucode_init, &priv->ucode_init_data);
 639                 if (!ret) {
 640                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 641                         priv->ucode_type = UCODE_INIT;
 642                 }
 643         } else {
 644                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 645                         "Loading runtime ucode...\n");
 646                 ret = iwl5000_load_given_ucode(priv,
 647                         &priv->ucode_code, &priv->ucode_data);
 648                 if (!ret) {
 649                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 650                         priv->ucode_type = UCODE_RT;
 651                 }
 652         }
 653
 654         return ret;
 655 }
 656
 657 void iwl5000_init_alive_start(struct iwl_priv *priv)
 658 {
 659         int ret = 0;
 660
 661         /* Check alive response for "valid" sign from uCode */
 662         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 663                 /* We had an error bringing up the hardware, so take it
 664                  * all the way back down so we can try again */
 665                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 666                 goto restart;
 667         }
 668
 669         /* initialize uCode was loaded... verify inst image.
 670          * This is a paranoid check, because we would not have gotten the
 671          * "initialize" alive if code weren't properly loaded.  */
 672         if (iwl_verify_ucode(priv)) {
 673                 /* Runtime instruction load was bad;
 674                  * take it all the way back down so we can try again */
 675                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 676                 goto restart;
 677         }
 678
 679         iwl_clear_stations_table(priv);
 680         ret = priv->cfg->ops->lib->alive_notify(priv);
 681         if (ret) {
 682                 IWL_WARN(priv,
 683                         "Could not complete ALIVE transition: %d\n", ret);
 684                 goto restart;
 685         }
 686
 687         iwl5000_send_calib_cfg(priv);
 688         return;
 689
 690 restart:
 691         /* real restart (first load init_ucode) */
 692         queue_work(priv->workqueue, &priv->restart);
 693 }
 694
 695 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 696                                 int txq_id, u32 index)
 697 {
 698         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 699                         (index & 0xff) | (txq_id << 8));
 700         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 701 }
 702
 703 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 704                                         struct iwl_tx_queue *txq,
 705                                         int tx_fifo_id, int scd_retry)
 706 {
 707         int txq_id = txq->q.id;
 708         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 709
 710         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 711                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 712                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 713                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 714                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 715
 716         txq->sched_retry = scd_retry;
 717
 718         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 719                        active ? "Activate" : "Deactivate",
 720                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 721 }
 722
 723 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 724 {
 725         struct iwl_wimax_coex_cmd coex_cmd;
 726
 727         memset(&coex_cmd, 0, sizeof(coex_cmd));
 728
 729         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 730                                 sizeof(coex_cmd), &coex_cmd);
 731 }
 732
 733 int iwl5000_alive_notify(struct iwl_priv *priv)
 734 {
 735         u32 a;
 736         unsigned long flags;
 737         int i, chan;
 738         u32 reg_val;
 739
 740         spin_lock_irqsave(&priv->lock, flags);
 741
 742         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 743         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 744         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 745                 a += 4)
 746                 iwl_write_targ_mem(priv, a, 0);
 747         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 748                 a += 4)
 749                 iwl_write_targ_mem(priv, a, 0);
 750         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 751                 iwl_write_targ_mem(priv, a, 0);
 752
 753         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 754                        priv->scd_bc_tbls.dma >> 10);
 755
 756         /* Enable DMA channel */
 757         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 758                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 759                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 760                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 761
 762         /* Update FH chicken bits */
 763         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 764         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 765                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 766
 767         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 768                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 769         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 770
 771         /* initiate the queues */
 772         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 773                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 774                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 775                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 776                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 777                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 778                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 779                                 sizeof(u32),
 780                                 ((SCD_WIN_SIZE <<
 781                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 782                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 783                                 ((SCD_FRAME_LIMIT <<
 784                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 785                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 786         }
 787
 788         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 789                         IWL_MASK(0, priv->hw_params.max_txq_num));
 790
 791         /* Activate all Tx DMA/FIFO channels */
 792         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 793
 794         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 795
 796         /* make sure all queue are not stopped */
 797         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 798         for (i = 0; i < 4; i++)
 799                 atomic_set(&priv->queue_stop_count[i], 0);
 800
 801         /* reset to 0 to enable all the queue first */
 802         priv->txq_ctx_active_msk = 0;
 803         /* map qos queues to fifos one-to-one */
 804         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 805                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 806                 iwl_txq_ctx_activate(priv, i);
 807                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 808         }
 809         /* TODO - need to initialize those FIFOs inside the loop above,
 810          * not only mark them as active */
 811         iwl_txq_ctx_activate(priv, 4);
 812         iwl_txq_ctx_activate(priv, 7);
 813         iwl_txq_ctx_activate(priv, 8);
 814         iwl_txq_ctx_activate(priv, 9);
 815
 816         spin_unlock_irqrestore(&priv->lock, flags);
 817
 818
 819         iwl5000_send_wimax_coex(priv);
 820
 821         iwl5000_set_Xtal_calib(priv);
 822         iwl_send_calib_results(priv);
 823
 824         return 0;
 825 }
 826
 827 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 828 {
 829         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 830             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 831                 IWL_ERR(priv,
 832                         "invalid queues_num, should be between %d and %d\n",
 833                         IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 834                 return -EINVAL;
 835         }
 836
 837         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 838         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 839         priv->hw_params.scd_bc_tbls_size =
 840                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 841         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 842         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 843         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 844
 845         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 846         case CSR_HW_REV_TYPE_6x00:
 847         case CSR_HW_REV_TYPE_6x50:
 848                 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
 849                 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
 850                 break;
 851         default:
 852                 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 853                 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 854         }
 855
 856         priv->hw_params.max_bsm_size = 0;
 857         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 858                                         BIT(IEEE80211_BAND_5GHZ);
 859         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 860
 861         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 862         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 863         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 864         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 865
 866         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 867                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 868
 869         /* Set initial sensitivity parameters */
 870         /* Set initial calibration set */
 871         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 872         case CSR_HW_REV_TYPE_5150:
 873                 priv->hw_params.sens = &iwl5150_sensitivity;
 874                 priv->hw_params.calib_init_cfg =
 875                         BIT(IWL_CALIB_DC)               |
 876                         BIT(IWL_CALIB_LO)               |
 877                         BIT(IWL_CALIB_TX_IQ)            |
 878                         BIT(IWL_CALIB_BASE_BAND);
 879
 880                 break;
 881         default:
 882                 priv->hw_params.sens = &iwl5000_sensitivity;
 883                 priv->hw_params.calib_init_cfg =
 884                         BIT(IWL_CALIB_XTAL)             |
 885                         BIT(IWL_CALIB_LO)               |
 886                         BIT(IWL_CALIB_TX_IQ)            |
 887                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 888                         BIT(IWL_CALIB_BASE_BAND);
 889                 break;
 890         }
 891
 892         return 0;
 893 }
 894
 895 /**
 896  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 897  */
 898 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 899                                             struct iwl_tx_queue *txq,
 900                                             u16 byte_cnt)
 901 {
 902         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 903         int write_ptr = txq->q.write_ptr;
 904         int txq_id = txq->q.id;
 905         u8 sec_ctl = 0;
 906         u8 sta_id = 0;
 907         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 908         __le16 bc_ent;
 909
 910         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 911
 912         if (txq_id != IWL_CMD_QUEUE_NUM) {
 913                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 914                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 915
 916                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 917                 case TX_CMD_SEC_CCM:
 918                         len += CCMP_MIC_LEN;
 919                         break;
 920                 case TX_CMD_SEC_TKIP:
 921                         len += TKIP_ICV_LEN;
 922                         break;
 923                 case TX_CMD_SEC_WEP:
 924                         len += WEP_IV_LEN + WEP_ICV_LEN;
 925                         break;
 926                 }
 927         }
 928
 929         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 930
 931         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 932
 933         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 934                 scd_bc_tbl[txq_id].
 935                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 936 }
 937
 938 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 939                                            struct iwl_tx_queue *txq)
 940 {
 941         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 942         int txq_id = txq->q.id;
 943         int read_ptr = txq->q.read_ptr;
 944         u8 sta_id = 0;
 945         __le16 bc_ent;
 946
 947         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 948
 949         if (txq_id != IWL_CMD_QUEUE_NUM)
 950                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 951
 952         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 953         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 954
 955         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 956                 scd_bc_tbl[txq_id].
 957                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 958 }
 959
 960 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 961                                         u16 txq_id)
 962 {
 963         u32 tbl_dw_addr;
 964         u32 tbl_dw;
 965         u16 scd_q2ratid;
 966
 967         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 968
 969         tbl_dw_addr = priv->scd_base_addr +
 970                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 971
 972         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 973
 974         if (txq_id & 0x1)
 975                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 976         else
 977                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 978
 979         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 980
 981         return 0;
 982 }
 983 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 984 {
 985         /* Simply stop the queue, but don't change any configuration;
 986          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 987         iwl_write_prph(priv,
 988                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 989                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 990                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 991 }
 992
 993 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 994                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 995 {
 996         unsigned long flags;
 997         u16 ra_tid;
 998
 999         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1000             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1001                 IWL_WARN(priv,
1002                         "queue number out of range: %d, must be %d to %d\n",
1003                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1004                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1005                 return -EINVAL;
1006         }
1007
1008         ra_tid = BUILD_RAxTID(sta_id, tid);
1009
1010         /* Modify device's station table to Tx this TID */
1011         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1012
1013         spin_lock_irqsave(&priv->lock, flags);
1014
1015         /* Stop this Tx queue before configuring it */
1016         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1017
1018         /* Map receiver-address / traffic-ID to this queue */
1019         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1020
1021         /* Set this queue as a chain-building queue */
1022         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1023
1024         /* enable aggregations for the queue */
1025         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1026
1027         /* Place first TFD at index corresponding to start sequence number.
1028          * Assumes that ssn_idx is valid (!= 0xFFF) */
1029         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1030         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1031         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1032
1033         /* Set up Tx window size and frame limit for this queue */
1034         iwl_write_targ_mem(priv, priv->scd_base_addr +
1035                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1036                         sizeof(u32),
1037                         ((SCD_WIN_SIZE <<
1038                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1039                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1040                         ((SCD_FRAME_LIMIT <<
1041                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1042                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1043
1044         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1045
1046         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1047         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1048
1049         spin_unlock_irqrestore(&priv->lock, flags);
1050
1051         return 0;
1052 }
1053
1054 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1055                                    u16 ssn_idx, u8 tx_fifo)
1056 {
1057         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1058             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1059                 IWL_ERR(priv,
1060                         "queue number out of range: %d, must be %d to %d\n",
1061                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1062                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1063                 return -EINVAL;
1064         }
1065
1066         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1067
1068         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1069
1070         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1071         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1072         /* supposes that ssn_idx is valid (!= 0xFFF) */
1073         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1074
1075         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1076         iwl_txq_ctx_deactivate(priv, txq_id);
1077         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1078
1079         return 0;
1080 }
1081
1082 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1083 {
1084         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1085         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1086         memcpy(addsta, cmd, size);
1087         /* resrved in 5000 */
1088         addsta->rate_n_flags = cpu_to_le16(0);
1089         return size;
1090 }
1091
1092
1093 /*
1094  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1095  * must be called under priv->lock and mac access
1096  */
1097 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1098 {
1099         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1100 }
1101
1102
1103 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1104 {
1105         return le32_to_cpup((__le32 *)&tx_resp->status +
1106                             tx_resp->frame_count) & MAX_SN;
1107 }
1108
1109 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1110                                       struct iwl_ht_agg *agg,
1111                                       struct iwl5000_tx_resp *tx_resp,
1112                                       int txq_id, u16 start_idx)
1113 {
1114         u16 status;
1115         struct agg_tx_status *frame_status = &tx_resp->status;
1116         struct ieee80211_tx_info *info = NULL;
1117         struct ieee80211_hdr *hdr = NULL;
1118         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1119         int i, sh, idx;
1120         u16 seq;
1121
1122         if (agg->wait_for_ba)
1123                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1124
1125         agg->frame_count = tx_resp->frame_count;
1126         agg->start_idx = start_idx;
1127         agg->rate_n_flags = rate_n_flags;
1128         agg->bitmap = 0;
1129
1130         /* # frames attempted by Tx command */
1131         if (agg->frame_count == 1) {
1132                 /* Only one frame was attempted; no block-ack will arrive */
1133                 status = le16_to_cpu(frame_status[0].status);
1134                 idx = start_idx;
1135
1136                 /* FIXME: code repetition */
1137                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1138                                    agg->frame_count, agg->start_idx, idx);
1139
1140                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1141                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1142                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1143                 info->flags |= iwl_is_tx_success(status) ?
1144                                         IEEE80211_TX_STAT_ACK : 0;
1145                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1146
1147                 /* FIXME: code repetition end */
1148
1149                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1150                                     status & 0xff, tx_resp->failure_frame);
1151                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1152
1153                 agg->wait_for_ba = 0;
1154         } else {
1155                 /* Two or more frames were attempted; expect block-ack */
1156                 u64 bitmap = 0;
1157                 int start = agg->start_idx;
1158
1159                 /* Construct bit-map of pending frames within Tx window */
1160                 for (i = 0; i < agg->frame_count; i++) {
1161                         u16 sc;
1162                         status = le16_to_cpu(frame_status[i].status);
1163                         seq  = le16_to_cpu(frame_status[i].sequence);
1164                         idx = SEQ_TO_INDEX(seq);
1165                         txq_id = SEQ_TO_QUEUE(seq);
1166
1167                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1168                                       AGG_TX_STATE_ABORT_MSK))
1169                                 continue;
1170
1171                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1172                                            agg->frame_count, txq_id, idx);
1173
1174                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1175                         if (!hdr) {
1176                                 IWL_ERR(priv,
1177                                         "BUG_ON idx doesn't point to valid skb"
1178                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1179                                 return -1;
1180                         }
1181
1182                         sc = le16_to_cpu(hdr->seq_ctrl);
1183                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1184                                 IWL_ERR(priv,
1185                                         "BUG_ON idx doesn't match seq control"
1186                                         " idx=%d, seq_idx=%d, seq=%d\n",
1187                                           idx, SEQ_TO_SN(sc),
1188                                           hdr->seq_ctrl);
1189                                 return -1;
1190                         }
1191
1192                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1193                                            i, idx, SEQ_TO_SN(sc));
1194
1195                         sh = idx - start;
1196                         if (sh > 64) {
1197                                 sh = (start - idx) + 0xff;
1198                                 bitmap = bitmap << sh;
1199                                 sh = 0;
1200                                 start = idx;
1201                         } else if (sh < -64)
1202                                 sh  = 0xff - (start - idx);
1203                         else if (sh < 0) {
1204                                 sh = start - idx;
1205                                 start = idx;
1206                                 bitmap = bitmap << sh;
1207                                 sh = 0;
1208                         }
1209                         bitmap |= 1ULL << sh;
1210                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1211                                            start, (unsigned long long)bitmap);
1212                 }
1213
1214                 agg->bitmap = bitmap;
1215                 agg->start_idx = start;
1216                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1217                                    agg->frame_count, agg->start_idx,
1218                                    (unsigned long long)agg->bitmap);
1219
1220                 if (bitmap)
1221                         agg->wait_for_ba = 1;
1222         }
1223         return 0;
1224 }
1225
1226 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1227                                 struct iwl_rx_mem_buffer *rxb)
1228 {
1229         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1230         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1231         int txq_id = SEQ_TO_QUEUE(sequence);
1232         int index = SEQ_TO_INDEX(sequence);
1233         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1234         struct ieee80211_tx_info *info;
1235         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1236         u32  status = le16_to_cpu(tx_resp->status.status);
1237         int tid;
1238         int sta_id;
1239         int freed;
1240
1241         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1242                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1243                           "is out of range [0-%d] %d %d\n", txq_id,
1244                           index, txq->q.n_bd, txq->q.write_ptr,
1245                           txq->q.read_ptr);
1246                 return;
1247         }
1248
1249         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1250         memset(&info->status, 0, sizeof(info->status));
1251
1252         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1253         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1254
1255         if (txq->sched_retry) {
1256                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1257                 struct iwl_ht_agg *agg = NULL;
1258
1259                 agg = &priv->stations[sta_id].tid[tid].agg;
1260
1261                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1262
1263                 /* check if BAR is needed */
1264                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1265                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1266
1267                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1268                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1269                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1270                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1271                                         scd_ssn , index, txq_id, txq->swq_id);
1272
1273                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1274                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1275
1276                         if (priv->mac80211_registered &&
1277                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1278                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1279                                 if (agg->state == IWL_AGG_OFF)
1280                                         iwl_wake_queue(priv, txq_id);
1281                                 else
1282                                         iwl_wake_queue(priv, txq->swq_id);
1283                         }
1284                 }
1285         } else {
1286                 BUG_ON(txq_id != txq->swq_id);
1287
1288                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1289                 info->flags |= iwl_is_tx_success(status) ?
1290                                         IEEE80211_TX_STAT_ACK : 0;
1291                 iwl_hwrate_to_tx_control(priv,
1292                                         le32_to_cpu(tx_resp->rate_n_flags),
1293                                         info);
1294
1295                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1296                                    "0x%x retries %d\n",
1297                                    txq_id,
1298                                    iwl_get_tx_fail_reason(status), status,
1299                                    le32_to_cpu(tx_resp->rate_n_flags),
1300                                    tx_resp->failure_frame);
1301
1302                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1303                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1304
1305                 if (priv->mac80211_registered &&
1306                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1307                         iwl_wake_queue(priv, txq_id);
1308         }
1309
1310         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1311
1312         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1313                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1314 }
1315
1316 /* Currently 5000 is the superset of everything */
1317 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1318 {
1319         return len;
1320 }
1321
1322 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1323 {
1324         /* in 5000 the tx power calibration is done in uCode */
1325         priv->disable_tx_power_cal = 1;
1326 }
1327
1328 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1329 {
1330         /* init calibration handlers */
1331         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1332                                         iwl5000_rx_calib_result;
1333         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1334                                         iwl5000_rx_calib_complete;
1335         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1336 }
1337
1338
1339 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1340 {
1341         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1342                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1343 }
1344
1345 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1346 {
1347         int ret = 0;
1348         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1349         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1350         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1351
1352         if ((rxon1->flags == rxon2->flags) &&
1353             (rxon1->filter_flags == rxon2->filter_flags) &&
1354             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1355             (rxon1->ofdm_ht_single_stream_basic_rates ==
1356              rxon2->ofdm_ht_single_stream_basic_rates) &&
1357             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1358              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1359             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1360              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1361             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1362             (rxon1->rx_chain == rxon2->rx_chain) &&
1363             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1364                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1365                 return 0;
1366         }
1367
1368         rxon_assoc.flags = priv->staging_rxon.flags;
1369         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1370         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1371         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1372         rxon_assoc.reserved1 = 0;
1373         rxon_assoc.reserved2 = 0;
1374         rxon_assoc.reserved3 = 0;
1375         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1376             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1377         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1378             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1379         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1380         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1381                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1382         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1383
1384         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1385                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1386         if (ret)
1387                 return ret;
1388
1389         return ret;
1390 }
1391 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1392 {
1393         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1394         u8 tx_ant_cfg_cmd;
1395
1396         /* half dBm need to multiply */
1397         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1398         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1399         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1400
1401         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1402                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1403         else
1404                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1405
1406         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1407                                        sizeof(tx_power_cmd), &tx_power_cmd,
1408                                        NULL);
1409 }
1410
1411 void iwl5000_temperature(struct iwl_priv *priv)
1412 {
1413         /* store temperature from statistics (in Celsius) */
1414         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1415         iwl_tt_handler(priv);
1416 }
1417
1418 static void iwl5150_temperature(struct iwl_priv *priv)
1419 {
1420         u32 vt = 0;
1421         s32 offset =  iwl_temp_calib_to_offset(priv);
1422
1423         vt = le32_to_cpu(priv->statistics.general.temperature);
1424         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1425         /* now vt hold the temperature in Kelvin */
1426         priv->temperature = KELVIN_TO_CELSIUS(vt);
1427         iwl_tt_handler(priv);
1428 }
1429
1430 /* Calc max signal level (dBm) among 3 possible receivers */
1431 int iwl5000_calc_rssi(struct iwl_priv *priv,
1432                              struct iwl_rx_phy_res *rx_resp)
1433 {
1434         /* data from PHY/DSP regarding signal strength, etc.,
1435          *   contents are always there, not configurable by host
1436          */
1437         struct iwl5000_non_cfg_phy *ncphy =
1438                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1439         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1440         u8 agc;
1441
1442         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1443         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1444
1445         /* Find max rssi among 3 possible receivers.
1446          * These values are measured by the digital signal processor (DSP).
1447          * They should stay fairly constant even as the signal strength varies,
1448          *   if the radio's automatic gain control (AGC) is working right.
1449          * AGC value (see below) will provide the "interesting" info.
1450          */
1451         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1452         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1453         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1454         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1455         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1456
1457         max_rssi = max_t(u32, rssi_a, rssi_b);
1458         max_rssi = max_t(u32, max_rssi, rssi_c);
1459
1460         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1461                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1462
1463         /* dBm = max_rssi dB - agc dB - constant.
1464          * Higher AGC (higher radio gain) means lower signal. */
1465         return max_rssi - agc - IWL49_RSSI_OFFSET;
1466 }
1467
1468 #define IWL5000_UCODE_GET(item)                                         \
1469 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1470                                     u32 api_ver)                        \
1471 {                                                                       \
1472         if (api_ver <= 2)                                               \
1473                 return le32_to_cpu(ucode->u.v1.item);                   \
1474         return le32_to_cpu(ucode->u.v2.item);                           \
1475 }
1476
1477 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1478 {
1479         if (api_ver <= 2)
1480                 return UCODE_HEADER_SIZE(1);
1481         return UCODE_HEADER_SIZE(2);
1482 }
1483
1484 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1485                                    u32 api_ver)
1486 {
1487         if (api_ver <= 2)
1488                 return 0;
1489         return le32_to_cpu(ucode->u.v2.build);
1490 }
1491
1492 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1493                                   u32 api_ver)
1494 {
1495         if (api_ver <= 2)
1496                 return (u8 *) ucode->u.v1.data;
1497         return (u8 *) ucode->u.v2.data;
1498 }
1499
1500 IWL5000_UCODE_GET(inst_size);
1501 IWL5000_UCODE_GET(data_size);
1502 IWL5000_UCODE_GET(init_size);
1503 IWL5000_UCODE_GET(init_data_size);
1504 IWL5000_UCODE_GET(boot_size);
1505
1506 struct iwl_hcmd_ops iwl5000_hcmd = {
1507         .rxon_assoc = iwl5000_send_rxon_assoc,
1508         .commit_rxon = iwl_commit_rxon,
1509         .set_rxon_chain = iwl_set_rxon_chain,
1510 };
1511
1512 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1513         .get_hcmd_size = iwl5000_get_hcmd_size,
1514         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1515         .gain_computation = iwl5000_gain_computation,
1516         .chain_noise_reset = iwl5000_chain_noise_reset,
1517         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1518         .calc_rssi = iwl5000_calc_rssi,
1519 };
1520
1521 struct iwl_ucode_ops iwl5000_ucode = {
1522         .get_header_size = iwl5000_ucode_get_header_size,
1523         .get_build = iwl5000_ucode_get_build,
1524         .get_inst_size = iwl5000_ucode_get_inst_size,
1525         .get_data_size = iwl5000_ucode_get_data_size,
1526         .get_init_size = iwl5000_ucode_get_init_size,
1527         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1528         .get_boot_size = iwl5000_ucode_get_boot_size,
1529         .get_data = iwl5000_ucode_get_data,
1530 };
1531
1532 struct iwl_lib_ops iwl5000_lib = {
1533         .set_hw_params = iwl5000_hw_set_hw_params,
1534         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1535         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1536         .txq_set_sched = iwl5000_txq_set_sched,
1537         .txq_agg_enable = iwl5000_txq_agg_enable,
1538         .txq_agg_disable = iwl5000_txq_agg_disable,
1539         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1540         .txq_free_tfd = iwl_hw_txq_free_tfd,
1541         .txq_init = iwl_hw_tx_queue_init,
1542         .rx_handler_setup = iwl5000_rx_handler_setup,
1543         .setup_deferred_work = iwl5000_setup_deferred_work,
1544         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1545         .dump_nic_event_log = iwl_dump_nic_event_log,
1546         .dump_nic_error_log = iwl_dump_nic_error_log,
1547         .load_ucode = iwl5000_load_ucode,
1548         .init_alive_start = iwl5000_init_alive_start,
1549         .alive_notify = iwl5000_alive_notify,
1550         .send_tx_power = iwl5000_send_tx_power,
1551         .update_chain_flags = iwl_update_chain_flags,
1552         .apm_ops = {
1553                 .init = iwl5000_apm_init,
1554                 .reset = iwl5000_apm_reset,
1555                 .stop = iwl5000_apm_stop,
1556                 .config = iwl5000_nic_config,
1557                 .set_pwr_src = iwl_set_pwr_src,
1558         },
1559         .eeprom_ops = {
1560                 .regulatory_bands = {
1561                         EEPROM_5000_REG_BAND_1_CHANNELS,
1562                         EEPROM_5000_REG_BAND_2_CHANNELS,
1563                         EEPROM_5000_REG_BAND_3_CHANNELS,
1564                         EEPROM_5000_REG_BAND_4_CHANNELS,
1565                         EEPROM_5000_REG_BAND_5_CHANNELS,
1566                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1567                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1568                 },
1569                 .verify_signature  = iwlcore_eeprom_verify_signature,
1570                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1571                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1572                 .calib_version  = iwl5000_eeprom_calib_version,
1573                 .query_addr = iwl5000_eeprom_query_addr,
1574         },
1575         .post_associate = iwl_post_associate,
1576         .isr = iwl_isr_ict,
1577         .config_ap = iwl_config_ap,
1578         .temp_ops = {
1579                 .temperature = iwl5000_temperature,
1580                 .set_ct_kill = iwl5000_set_ct_threshold,
1581          },
1582 };
1583
1584 static struct iwl_lib_ops iwl5150_lib = {
1585         .set_hw_params = iwl5000_hw_set_hw_params,
1586         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1587         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1588         .txq_set_sched = iwl5000_txq_set_sched,
1589         .txq_agg_enable = iwl5000_txq_agg_enable,
1590         .txq_agg_disable = iwl5000_txq_agg_disable,
1591         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1592         .txq_free_tfd = iwl_hw_txq_free_tfd,
1593         .txq_init = iwl_hw_tx_queue_init,
1594         .rx_handler_setup = iwl5000_rx_handler_setup,
1595         .setup_deferred_work = iwl5000_setup_deferred_work,
1596         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1597         .dump_nic_event_log = iwl_dump_nic_event_log,
1598         .dump_nic_error_log = iwl_dump_nic_error_log,
1599         .load_ucode = iwl5000_load_ucode,
1600         .init_alive_start = iwl5000_init_alive_start,
1601         .alive_notify = iwl5000_alive_notify,
1602         .send_tx_power = iwl5000_send_tx_power,
1603         .update_chain_flags = iwl_update_chain_flags,
1604         .apm_ops = {
1605                 .init = iwl5000_apm_init,
1606                 .reset = iwl5000_apm_reset,
1607                 .stop = iwl5000_apm_stop,
1608                 .config = iwl5000_nic_config,
1609                 .set_pwr_src = iwl_set_pwr_src,
1610         },
1611         .eeprom_ops = {
1612                 .regulatory_bands = {
1613                         EEPROM_5000_REG_BAND_1_CHANNELS,
1614                         EEPROM_5000_REG_BAND_2_CHANNELS,
1615                         EEPROM_5000_REG_BAND_3_CHANNELS,
1616                         EEPROM_5000_REG_BAND_4_CHANNELS,
1617                         EEPROM_5000_REG_BAND_5_CHANNELS,
1618                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1619                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1620                 },
1621                 .verify_signature  = iwlcore_eeprom_verify_signature,
1622                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1623                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1624                 .calib_version  = iwl5000_eeprom_calib_version,
1625                 .query_addr = iwl5000_eeprom_query_addr,
1626         },
1627         .post_associate = iwl_post_associate,
1628         .isr = iwl_isr_ict,
1629         .config_ap = iwl_config_ap,
1630         .temp_ops = {
1631                 .temperature = iwl5150_temperature,
1632                 .set_ct_kill = iwl5150_set_ct_threshold,
1633          },
1634 };
1635
1636 struct iwl_ops iwl5000_ops = {
1637         .ucode = &iwl5000_ucode,
1638         .lib = &iwl5000_lib,
1639         .hcmd = &iwl5000_hcmd,
1640         .utils = &iwl5000_hcmd_utils,
1641 };
1642
1643 static struct iwl_ops iwl5150_ops = {
1644         .ucode = &iwl5000_ucode,
1645         .lib = &iwl5150_lib,
1646         .hcmd = &iwl5000_hcmd,
1647         .utils = &iwl5000_hcmd_utils,
1648 };
1649
1650 struct iwl_mod_params iwl50_mod_params = {
1651         .num_of_queues = IWL50_NUM_QUEUES,
1652         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1653         .amsdu_size_8K = 1,
1654         .restart_fw = 1,
1655         /* the rest are 0 by default */
1656 };
1657
1658
1659 struct iwl_cfg iwl5300_agn_cfg = {
1660         .name = "5300AGN",
1661         .fw_name_pre = IWL5000_FW_PRE,
1662         .ucode_api_max = IWL5000_UCODE_API_MAX,
1663         .ucode_api_min = IWL5000_UCODE_API_MIN,
1664         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1665         .ops = &iwl5000_ops,
1666         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1667         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1668         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1669         .mod_params = &iwl50_mod_params,
1670         .valid_tx_ant = ANT_ABC,
1671         .valid_rx_ant = ANT_ABC,
1672         .need_pll_cfg = true,
1673         .ht_greenfield_support = true,
1674         .use_rts_for_ht = true, /* use rts/cts protection */
1675 };
1676
1677 struct iwl_cfg iwl5100_bgn_cfg = {
1678         .name = "5100BGN",
1679         .fw_name_pre = IWL5000_FW_PRE,
1680         .ucode_api_max = IWL5000_UCODE_API_MAX,
1681         .ucode_api_min = IWL5000_UCODE_API_MIN,
1682         .sku = IWL_SKU_G|IWL_SKU_N,
1683         .ops = &iwl5000_ops,
1684         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1685         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1686         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1687         .mod_params = &iwl50_mod_params,
1688         .valid_tx_ant = ANT_B,
1689         .valid_rx_ant = ANT_AB,
1690         .need_pll_cfg = true,
1691         .ht_greenfield_support = true,
1692 };
1693
1694 struct iwl_cfg iwl5100_abg_cfg = {
1695         .name = "5100ABG",
1696         .fw_name_pre = IWL5000_FW_PRE,
1697         .ucode_api_max = IWL5000_UCODE_API_MAX,
1698         .ucode_api_min = IWL5000_UCODE_API_MIN,
1699         .sku = IWL_SKU_A|IWL_SKU_G,
1700         .ops = &iwl5000_ops,
1701         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1702         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1703         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1704         .mod_params = &iwl50_mod_params,
1705         .valid_tx_ant = ANT_B,
1706         .valid_rx_ant = ANT_AB,
1707         .need_pll_cfg = true,
1708 };
1709
1710 struct iwl_cfg iwl5100_agn_cfg = {
1711         .name = "5100AGN",
1712         .fw_name_pre = IWL5000_FW_PRE,
1713         .ucode_api_max = IWL5000_UCODE_API_MAX,
1714         .ucode_api_min = IWL5000_UCODE_API_MIN,
1715         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1716         .ops = &iwl5000_ops,
1717         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1718         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1719         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1720         .mod_params = &iwl50_mod_params,
1721         .valid_tx_ant = ANT_B,
1722         .valid_rx_ant = ANT_AB,
1723         .need_pll_cfg = true,
1724         .ht_greenfield_support = true,
1725         .use_rts_for_ht = true, /* use rts/cts protection */
1726 };
1727
1728 struct iwl_cfg iwl5350_agn_cfg = {
1729         .name = "5350AGN",
1730         .fw_name_pre = IWL5000_FW_PRE,
1731         .ucode_api_max = IWL5000_UCODE_API_MAX,
1732         .ucode_api_min = IWL5000_UCODE_API_MIN,
1733         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1734         .ops = &iwl5000_ops,
1735         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1736         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1737         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1738         .mod_params = &iwl50_mod_params,
1739         .valid_tx_ant = ANT_ABC,
1740         .valid_rx_ant = ANT_ABC,
1741         .need_pll_cfg = true,
1742         .ht_greenfield_support = true,
1743         .use_rts_for_ht = true, /* use rts/cts protection */
1744 };
1745
1746 struct iwl_cfg iwl5150_agn_cfg = {
1747         .name = "5150AGN",
1748         .fw_name_pre = IWL5150_FW_PRE,
1749         .ucode_api_max = IWL5150_UCODE_API_MAX,
1750         .ucode_api_min = IWL5150_UCODE_API_MIN,
1751         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1752         .ops = &iwl5150_ops,
1753         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1754         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1755         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1756         .mod_params = &iwl50_mod_params,
1757         .valid_tx_ant = ANT_A,
1758         .valid_rx_ant = ANT_AB,
1759         .need_pll_cfg = true,
1760         .ht_greenfield_support = true,
1761         .use_rts_for_ht = true, /* use rts/cts protection */
1762 };
1763
1764 struct iwl_cfg iwl5150_abg_cfg = {
1765         .name = "5150ABG",
1766         .fw_name_pre = IWL5150_FW_PRE,
1767         .ucode_api_max = IWL5150_UCODE_API_MAX,
1768         .ucode_api_min = IWL5150_UCODE_API_MIN,
1769         .sku = IWL_SKU_A|IWL_SKU_G,
1770         .ops = &iwl5150_ops,
1771         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1772         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1773         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1774         .mod_params = &iwl50_mod_params,
1775         .valid_tx_ant = ANT_A,
1776         .valid_rx_ant = ANT_AB,
1777         .need_pll_cfg = true,
1778 };
1779
1780 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1781 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1782
1783 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1784 MODULE_PARM_DESC(swcrypto50,
1785                   "using software crypto engine (default 0 [hardware])\n");
1786 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1787 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1788 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1789 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1790 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1791 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1792 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1793 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");