drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 #define IWL5000_UCODE_API  "-1"
  48 #define IWL5150_UCODE_API  "-1"
  49
  50 #define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
  51 #define IWL5150_MODULE_FIRMWARE "iwlwifi-5150" IWL5150_UCODE_API ".ucode"
  52
  53 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  54         IWL_TX_FIFO_AC3,
  55         IWL_TX_FIFO_AC2,
  56         IWL_TX_FIFO_AC1,
  57         IWL_TX_FIFO_AC0,
  58         IWL50_CMD_FIFO_NUM,
  59         IWL_TX_FIFO_HCCA_1,
  60         IWL_TX_FIFO_HCCA_2
  61 };
  62
  63 /* FIXME: same implementation as 4965 */
  64 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  65 {
  66         int ret = 0;
  67         unsigned long flags;
  68
  69         spin_lock_irqsave(&priv->lock, flags);
  70
  71         /* set stop master bit */
  72         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  73
  74         ret = iwl_poll_bit(priv, CSR_RESET,
  75                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
  76                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  77         if (ret < 0)
  78                 goto out;
  79
  80 out:
  81         spin_unlock_irqrestore(&priv->lock, flags);
  82         IWL_DEBUG_INFO("stop master\n");
  83
  84         return ret;
  85 }
  86
  87
  88 static int iwl5000_apm_init(struct iwl_priv *priv)
  89 {
  90         int ret = 0;
  91
  92         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  93                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  94
  95         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  96         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  97                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  98
  99         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 100         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 101
 102         /* enable HAP INTA to move device L1a -> L0s */
 103         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 104                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 105
 106         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 107
 108         /* set "initialization complete" bit to move adapter
 109          * D0U* --> D0A* state */
 110         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 111
 112         /* wait for clock stabilization */
 113         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 114                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 115                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 116         if (ret < 0) {
 117                 IWL_DEBUG_INFO("Failed to init the card\n");
 118                 return ret;
 119         }
 120
 121         ret = iwl_grab_nic_access(priv);
 122         if (ret)
 123                 return ret;
 124
 125         /* enable DMA */
 126         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 127
 128         udelay(20);
 129
 130         /* disable L1-Active */
 131         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 132                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 133
 134         iwl_release_nic_access(priv);
 135
 136         return ret;
 137 }
 138
 139 /* FIXME: this is identical to 4965 */
 140 static void iwl5000_apm_stop(struct iwl_priv *priv)
 141 {
 142         unsigned long flags;
 143
 144         iwl5000_apm_stop_master(priv);
 145
 146         spin_lock_irqsave(&priv->lock, flags);
 147
 148         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 149
 150         udelay(10);
 151
 152         /* clear "init complete"  move adapter D0A* --> D0U state */
 153         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 154
 155         spin_unlock_irqrestore(&priv->lock, flags);
 156 }
 157
 158
 159 static int iwl5000_apm_reset(struct iwl_priv *priv)
 160 {
 161         int ret = 0;
 162         unsigned long flags;
 163
 164         iwl5000_apm_stop_master(priv);
 165
 166         spin_lock_irqsave(&priv->lock, flags);
 167
 168         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 169
 170         udelay(10);
 171
 172
 173         /* FIXME: put here L1A -L0S w/a */
 174
 175         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 176
 177         /* set "initialization complete" bit to move adapter
 178          * D0U* --> D0A* state */
 179         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 180
 181         /* wait for clock stabilization */
 182         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 183                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 184                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 185         if (ret < 0) {
 186                 IWL_DEBUG_INFO("Failed to init the card\n");
 187                 goto out;
 188         }
 189
 190         ret = iwl_grab_nic_access(priv);
 191         if (ret)
 192                 goto out;
 193
 194         /* enable DMA */
 195         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 196
 197         udelay(20);
 198
 199         /* disable L1-Active */
 200         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 201                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 202
 203         iwl_release_nic_access(priv);
 204
 205 out:
 206         spin_unlock_irqrestore(&priv->lock, flags);
 207
 208         return ret;
 209 }
 210
 211
 212 static void iwl5000_nic_config(struct iwl_priv *priv)
 213 {
 214         unsigned long flags;
 215         u16 radio_cfg;
 216         u16 link;
 217
 218         spin_lock_irqsave(&priv->lock, flags);
 219
 220         pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
 221
 222         /* L1 is enabled by BIOS */
 223         if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 224                 /* disable L0S disabled L1A enabled */
 225                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 226         else
 227                 /* L0S enabled L1A disabled */
 228                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 229
 230         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 231
 232         /* write radio config values to register */
 233         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 234                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 235                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 236                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 237                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 238
 239         /* set CSR_HW_CONFIG_REG for uCode use */
 240         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 241                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 242                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 243
 244         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 245          * (PCIe power is lost before PERST# is asserted),
 246          * causing ME FW to lose ownership and not being able to obtain it back.
 247          */
 248         iwl_grab_nic_access(priv);
 249         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 250                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 251                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 252         iwl_release_nic_access(priv);
 253
 254         spin_unlock_irqrestore(&priv->lock, flags);
 255 }
 256
 257
 258
 259 /*
 260  * EEPROM
 261  */
 262 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 263 {
 264         u16 offset = 0;
 265
 266         if ((address & INDIRECT_ADDRESS) == 0)
 267                 return address;
 268
 269         switch (address & INDIRECT_TYPE_MSK) {
 270         case INDIRECT_HOST:
 271                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 272                 break;
 273         case INDIRECT_GENERAL:
 274                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 275                 break;
 276         case INDIRECT_REGULATORY:
 277                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 278                 break;
 279         case INDIRECT_CALIBRATION:
 280                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 281                 break;
 282         case INDIRECT_PROCESS_ADJST:
 283                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 284                 break;
 285         case INDIRECT_OTHERS:
 286                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 287                 break;
 288         default:
 289                 IWL_ERROR("illegal indirect type: 0x%X\n",
 290                 address & INDIRECT_TYPE_MSK);
 291                 break;
 292         }
 293
 294         /* translate the offset from words to byte */
 295         return (address & ADDRESS_MSK) + (offset << 1);
 296 }
 297
 298 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 299 {
 300         struct iwl_eeprom_calib_hdr {
 301                 u8 version;
 302                 u8 pa_type;
 303                 u16 voltage;
 304         } *hdr;
 305
 306         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 307                                                         EEPROM_5000_CALIB_ALL);
 308         return hdr->version;
 309
 310 }
 311
 312 static void iwl5000_gain_computation(struct iwl_priv *priv,
 313                 u32 average_noise[NUM_RX_CHAINS],
 314                 u16 min_average_noise_antenna_i,
 315                 u32 min_average_noise)
 316 {
 317         int i;
 318         s32 delta_g;
 319         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 320
 321         /* Find Gain Code for the antennas B and C */
 322         for (i = 1; i < NUM_RX_CHAINS; i++) {
 323                 if ((data->disconn_array[i])) {
 324                         data->delta_gain_code[i] = 0;
 325                         continue;
 326                 }
 327                 delta_g = (1000 * ((s32)average_noise[0] -
 328                         (s32)average_noise[i])) / 1500;
 329                 /* bound gain by 2 bits value max, 3rd bit is sign */
 330                 data->delta_gain_code[i] =
 331                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 332
 333                 if (delta_g < 0)
 334                         /* set negative sign */
 335                         data->delta_gain_code[i] |= (1 << 2);
 336         }
 337
 338         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 339                         data->delta_gain_code[1], data->delta_gain_code[2]);
 340
 341         if (!data->radio_write) {
 342                 struct iwl_calib_chain_noise_gain_cmd cmd;
 343
 344                 memset(&cmd, 0, sizeof(cmd));
 345
 346                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 347                 cmd.hdr.first_group = 0;
 348                 cmd.hdr.groups_num = 1;
 349                 cmd.hdr.data_valid = 1;
 350                 cmd.delta_gain_1 = data->delta_gain_code[1];
 351                 cmd.delta_gain_2 = data->delta_gain_code[2];
 352                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 353                         sizeof(cmd), &cmd, NULL);
 354
 355                 data->radio_write = 1;
 356                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 357         }
 358
 359         data->chain_noise_a = 0;
 360         data->chain_noise_b = 0;
 361         data->chain_noise_c = 0;
 362         data->chain_signal_a = 0;
 363         data->chain_signal_b = 0;
 364         data->chain_signal_c = 0;
 365         data->beacon_count = 0;
 366 }
 367
 368 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 369 {
 370         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 371         int ret;
 372
 373         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 374                 struct iwl_calib_chain_noise_reset_cmd cmd;
 375                 memset(&cmd, 0, sizeof(cmd));
 376
 377                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 378                 cmd.hdr.first_group = 0;
 379                 cmd.hdr.groups_num = 1;
 380                 cmd.hdr.data_valid = 1;
 381                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 382                                         sizeof(cmd), &cmd);
 383                 if (ret)
 384                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 385                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 386                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 387         }
 388 }
 389
 390 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 391                         __le32 *tx_flags)
 392 {
 393         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 394             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 395                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 396         else
 397                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 398 }
 399
 400 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 401         .min_nrg_cck = 95,
 402         .max_nrg_cck = 0,
 403         .auto_corr_min_ofdm = 90,
 404         .auto_corr_min_ofdm_mrc = 170,
 405         .auto_corr_min_ofdm_x1 = 120,
 406         .auto_corr_min_ofdm_mrc_x1 = 240,
 407
 408         .auto_corr_max_ofdm = 120,
 409         .auto_corr_max_ofdm_mrc = 210,
 410         .auto_corr_max_ofdm_x1 = 155,
 411         .auto_corr_max_ofdm_mrc_x1 = 290,
 412
 413         .auto_corr_min_cck = 125,
 414         .auto_corr_max_cck = 200,
 415         .auto_corr_min_cck_mrc = 170,
 416         .auto_corr_max_cck_mrc = 400,
 417         .nrg_th_cck = 95,
 418         .nrg_th_ofdm = 95,
 419 };
 420
 421 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 422                                            size_t offset)
 423 {
 424         u32 address = eeprom_indirect_address(priv, offset);
 425         BUG_ON(address >= priv->cfg->eeprom_size);
 426         return &priv->eeprom[address];
 427 }
 428
 429 static s32 iwl5150_get_ct_threshold(struct iwl_priv *priv)
 430 {
 431         const s32 volt2temp_coef = -5;
 432         u16 *temp_calib = (u16 *)iwl_eeprom_query_addr(priv,
 433                                                 EEPROM_5000_TEMPERATURE);
 434         /* offset =  temperate -  voltage / coef */
 435         s32 offset = temp_calib[0] - temp_calib[1] / volt2temp_coef;
 436         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - offset;
 437         return threshold * volt2temp_coef;
 438 }
 439
 440 /*
 441  *  Calibration
 442  */
 443 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 444 {
 445         struct iwl_calib_xtal_freq_cmd cmd;
 446         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 447
 448         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 449         cmd.hdr.first_group = 0;
 450         cmd.hdr.groups_num = 1;
 451         cmd.hdr.data_valid = 1;
 452         cmd.cap_pin1 = (u8)xtal_calib[0];
 453         cmd.cap_pin2 = (u8)xtal_calib[1];
 454         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 455                              (u8 *)&cmd, sizeof(cmd));
 456 }
 457
 458 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 459 {
 460         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 461         struct iwl_host_cmd cmd = {
 462                 .id = CALIBRATION_CFG_CMD,
 463                 .len = sizeof(struct iwl_calib_cfg_cmd),
 464                 .data = &calib_cfg_cmd,
 465         };
 466
 467         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 468         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 469         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 470         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 471         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 472
 473         return iwl_send_cmd(priv, &cmd);
 474 }
 475
 476 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 477                              struct iwl_rx_mem_buffer *rxb)
 478 {
 479         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 480         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 481         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 482         int index;
 483
 484         /* reduce the size of the length field itself */
 485         len -= 4;
 486
 487         /* Define the order in which the results will be sent to the runtime
 488          * uCode. iwl_send_calib_results sends them in a row according to their
 489          * index. We sort them here */
 490         switch (hdr->op_code) {
 491         case IWL_PHY_CALIBRATE_DC_CMD:
 492                 index = IWL_CALIB_DC;
 493                 break;
 494         case IWL_PHY_CALIBRATE_LO_CMD:
 495                 index = IWL_CALIB_LO;
 496                 break;
 497         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 498                 index = IWL_CALIB_TX_IQ;
 499                 break;
 500         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 501                 index = IWL_CALIB_TX_IQ_PERD;
 502                 break;
 503         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 504                 index = IWL_CALIB_BASE_BAND;
 505                 break;
 506         default:
 507                 IWL_ERROR("Unknown calibration notification %d\n",
 508                           hdr->op_code);
 509                 return;
 510         }
 511         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 512 }
 513
 514 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 515                                struct iwl_rx_mem_buffer *rxb)
 516 {
 517         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 518         queue_work(priv->workqueue, &priv->restart);
 519 }
 520
 521 /*
 522  * ucode
 523  */
 524 static int iwl5000_load_section(struct iwl_priv *priv,
 525                                 struct fw_desc *image,
 526                                 u32 dst_addr)
 527 {
 528         int ret = 0;
 529         unsigned long flags;
 530
 531         dma_addr_t phy_addr = image->p_addr;
 532         u32 byte_cnt = image->len;
 533
 534         spin_lock_irqsave(&priv->lock, flags);
 535         ret = iwl_grab_nic_access(priv);
 536         if (ret) {
 537                 spin_unlock_irqrestore(&priv->lock, flags);
 538                 return ret;
 539         }
 540
 541         iwl_write_direct32(priv,
 542                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 543                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 544
 545         iwl_write_direct32(priv,
 546                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 547
 548         iwl_write_direct32(priv,
 549                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 550                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 551
 552         iwl_write_direct32(priv,
 553                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 554                 (iwl_get_dma_hi_addr(phy_addr)
 555                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 556
 557         iwl_write_direct32(priv,
 558                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 559                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 560                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 561                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 562
 563         iwl_write_direct32(priv,
 564                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 565                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 566                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 567                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 568
 569         iwl_release_nic_access(priv);
 570         spin_unlock_irqrestore(&priv->lock, flags);
 571         return 0;
 572 }
 573
 574 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 575                 struct fw_desc *inst_image,
 576                 struct fw_desc *data_image)
 577 {
 578         int ret = 0;
 579
 580         ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
 581         if (ret)
 582                 return ret;
 583
 584         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 585         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 586                                         priv->ucode_write_complete, 5 * HZ);
 587         if (ret == -ERESTARTSYS) {
 588                 IWL_ERROR("Could not load the INST uCode section due "
 589                         "to interrupt\n");
 590                 return ret;
 591         }
 592         if (!ret) {
 593                 IWL_ERROR("Could not load the INST uCode section\n");
 594                 return -ETIMEDOUT;
 595         }
 596
 597         priv->ucode_write_complete = 0;
 598
 599         ret = iwl5000_load_section(
 600                 priv, data_image, RTC_DATA_LOWER_BOUND);
 601         if (ret)
 602                 return ret;
 603
 604         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 605
 606         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 607                                 priv->ucode_write_complete, 5 * HZ);
 608         if (ret == -ERESTARTSYS) {
 609                 IWL_ERROR("Could not load the INST uCode section due "
 610                         "to interrupt\n");
 611                 return ret;
 612         } else if (!ret) {
 613                 IWL_ERROR("Could not load the DATA uCode section\n");
 614                 return -ETIMEDOUT;
 615         } else
 616                 ret = 0;
 617
 618         priv->ucode_write_complete = 0;
 619
 620         return ret;
 621 }
 622
 623 static int iwl5000_load_ucode(struct iwl_priv *priv)
 624 {
 625         int ret = 0;
 626
 627         /* check whether init ucode should be loaded, or rather runtime ucode */
 628         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 629                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 630                 ret = iwl5000_load_given_ucode(priv,
 631                         &priv->ucode_init, &priv->ucode_init_data);
 632                 if (!ret) {
 633                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 634                         priv->ucode_type = UCODE_INIT;
 635                 }
 636         } else {
 637                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 638                         "Loading runtime ucode...\n");
 639                 ret = iwl5000_load_given_ucode(priv,
 640                         &priv->ucode_code, &priv->ucode_data);
 641                 if (!ret) {
 642                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 643                         priv->ucode_type = UCODE_RT;
 644                 }
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 651 {
 652         int ret = 0;
 653
 654         /* Check alive response for "valid" sign from uCode */
 655         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 656                 /* We had an error bringing up the hardware, so take it
 657                  * all the way back down so we can try again */
 658                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 659                 goto restart;
 660         }
 661
 662         /* initialize uCode was loaded... verify inst image.
 663          * This is a paranoid check, because we would not have gotten the
 664          * "initialize" alive if code weren't properly loaded.  */
 665         if (iwl_verify_ucode(priv)) {
 666                 /* Runtime instruction load was bad;
 667                  * take it all the way back down so we can try again */
 668                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 669                 goto restart;
 670         }
 671
 672         iwl_clear_stations_table(priv);
 673         ret = priv->cfg->ops->lib->alive_notify(priv);
 674         if (ret) {
 675                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 676                 goto restart;
 677         }
 678
 679         iwl5000_send_calib_cfg(priv);
 680         return;
 681
 682 restart:
 683         /* real restart (first load init_ucode) */
 684         queue_work(priv->workqueue, &priv->restart);
 685 }
 686
 687 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 688                                 int txq_id, u32 index)
 689 {
 690         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 691                         (index & 0xff) | (txq_id << 8));
 692         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 693 }
 694
 695 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 696                                         struct iwl_tx_queue *txq,
 697                                         int tx_fifo_id, int scd_retry)
 698 {
 699         int txq_id = txq->q.id;
 700         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 701
 702         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 703                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 704                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 705                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 706                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 707
 708         txq->sched_retry = scd_retry;
 709
 710         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 711                        active ? "Activate" : "Deactivate",
 712                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 713 }
 714
 715 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 716 {
 717         struct iwl_wimax_coex_cmd coex_cmd;
 718
 719         memset(&coex_cmd, 0, sizeof(coex_cmd));
 720
 721         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 722                                 sizeof(coex_cmd), &coex_cmd);
 723 }
 724
 725 static int iwl5000_alive_notify(struct iwl_priv *priv)
 726 {
 727         u32 a;
 728         unsigned long flags;
 729         int ret;
 730         int i, chan;
 731         u32 reg_val;
 732
 733         spin_lock_irqsave(&priv->lock, flags);
 734
 735         ret = iwl_grab_nic_access(priv);
 736         if (ret) {
 737                 spin_unlock_irqrestore(&priv->lock, flags);
 738                 return ret;
 739         }
 740
 741         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 742         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 743         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 744                 a += 4)
 745                 iwl_write_targ_mem(priv, a, 0);
 746         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 747                 a += 4)
 748                 iwl_write_targ_mem(priv, a, 0);
 749         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 750                 iwl_write_targ_mem(priv, a, 0);
 751
 752         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 753                        priv->scd_bc_tbls.dma >> 10);
 754
 755         /* Enable DMA channel */
 756         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 757                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 758                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 759                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 760
 761         /* Update FH chicken bits */
 762         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 763         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 764                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 765
 766         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 767                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 768         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 769
 770         /* initiate the queues */
 771         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 772                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 773                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 774                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 775                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 776                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 777                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 778                                 sizeof(u32),
 779                                 ((SCD_WIN_SIZE <<
 780                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 781                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 782                                 ((SCD_FRAME_LIMIT <<
 783                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 784                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 785         }
 786
 787         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 788                         IWL_MASK(0, priv->hw_params.max_txq_num));
 789
 790         /* Activate all Tx DMA/FIFO channels */
 791         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 792
 793         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 794
 795         /* map qos queues to fifos one-to-one */
 796         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 797                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 798                 iwl_txq_ctx_activate(priv, i);
 799                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 800         }
 801         /* TODO - need to initialize those FIFOs inside the loop above,
 802          * not only mark them as active */
 803         iwl_txq_ctx_activate(priv, 4);
 804         iwl_txq_ctx_activate(priv, 7);
 805         iwl_txq_ctx_activate(priv, 8);
 806         iwl_txq_ctx_activate(priv, 9);
 807
 808         iwl_release_nic_access(priv);
 809         spin_unlock_irqrestore(&priv->lock, flags);
 810
 811
 812         iwl5000_send_wimax_coex(priv);
 813
 814         iwl5000_set_Xtal_calib(priv);
 815         iwl_send_calib_results(priv);
 816
 817         return 0;
 818 }
 819
 820 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 821 {
 822         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 823             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 824                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 825                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 826                 return -EINVAL;
 827         }
 828
 829         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 830         priv->hw_params.scd_bc_tbls_size =
 831                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 832         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 833         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 834         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 835         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 836         priv->hw_params.max_bsm_size = 0;
 837         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 838                                         BIT(IEEE80211_BAND_5GHZ);
 839         priv->hw_params.sens = &iwl5000_sensitivity;
 840
 841         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 842         case CSR_HW_REV_TYPE_5100:
 843                 priv->hw_params.tx_chains_num = 1;
 844                 priv->hw_params.rx_chains_num = 2;
 845                 priv->hw_params.valid_tx_ant = ANT_B;
 846                 priv->hw_params.valid_rx_ant = ANT_AB;
 847                 break;
 848         case CSR_HW_REV_TYPE_5150:
 849                 priv->hw_params.tx_chains_num = 1;
 850                 priv->hw_params.rx_chains_num = 2;
 851                 priv->hw_params.valid_tx_ant = ANT_A;
 852                 priv->hw_params.valid_rx_ant = ANT_AB;
 853                 break;
 854         case CSR_HW_REV_TYPE_5300:
 855         case CSR_HW_REV_TYPE_5350:
 856                 priv->hw_params.tx_chains_num = 3;
 857                 priv->hw_params.rx_chains_num = 3;
 858                 priv->hw_params.valid_tx_ant = ANT_ABC;
 859                 priv->hw_params.valid_rx_ant = ANT_ABC;
 860                 break;
 861         }
 862
 863         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 864         case CSR_HW_REV_TYPE_5100:
 865         case CSR_HW_REV_TYPE_5300:
 866         case CSR_HW_REV_TYPE_5350:
 867                 /* 5X00 and 5350 wants in Celsius */
 868                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 869                 break;
 870         case CSR_HW_REV_TYPE_5150:
 871                 /* 5150 wants in Kelvin */
 872                 priv->hw_params.ct_kill_threshold =
 873                                 iwl5150_get_ct_threshold(priv);
 874                 break;
 875         }
 876
 877         /* Set initial calibration set */
 878         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 879         case CSR_HW_REV_TYPE_5100:
 880         case CSR_HW_REV_TYPE_5300:
 881         case CSR_HW_REV_TYPE_5350:
 882                 priv->hw_params.calib_init_cfg =
 883                         BIT(IWL_CALIB_XTAL)             |
 884                         BIT(IWL_CALIB_LO)               |
 885                         BIT(IWL_CALIB_TX_IQ)            |
 886                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 887                         BIT(IWL_CALIB_BASE_BAND);
 888                 break;
 889         case CSR_HW_REV_TYPE_5150:
 890                 priv->hw_params.calib_init_cfg =
 891                         BIT(IWL_CALIB_DC);
 892
 893                 break;
 894         }
 895
 896
 897         return 0;
 898 }
 899
 900 /**
 901  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 902  */
 903 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 904                                             struct iwl_tx_queue *txq,
 905                                             u16 byte_cnt)
 906 {
 907         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 908         int write_ptr = txq->q.write_ptr;
 909         int txq_id = txq->q.id;
 910         u8 sec_ctl = 0;
 911         u8 sta_id = 0;
 912         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 913         __le16 bc_ent;
 914
 915         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 916
 917         if (txq_id != IWL_CMD_QUEUE_NUM) {
 918                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 919                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 920
 921                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 922                 case TX_CMD_SEC_CCM:
 923                         len += CCMP_MIC_LEN;
 924                         break;
 925                 case TX_CMD_SEC_TKIP:
 926                         len += TKIP_ICV_LEN;
 927                         break;
 928                 case TX_CMD_SEC_WEP:
 929                         len += WEP_IV_LEN + WEP_ICV_LEN;
 930                         break;
 931                 }
 932         }
 933
 934         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 935
 936         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 937
 938         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 939                 scd_bc_tbl[txq_id].
 940                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 941 }
 942
 943 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 944                                            struct iwl_tx_queue *txq)
 945 {
 946         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 947         int txq_id = txq->q.id;
 948         int read_ptr = txq->q.read_ptr;
 949         u8 sta_id = 0;
 950         __le16 bc_ent;
 951
 952         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 953
 954         if (txq_id != IWL_CMD_QUEUE_NUM)
 955                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 956
 957         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 958         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 959
 960         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 961                 scd_bc_tbl[txq_id].
 962                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 963 }
 964
 965 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 966                                         u16 txq_id)
 967 {
 968         u32 tbl_dw_addr;
 969         u32 tbl_dw;
 970         u16 scd_q2ratid;
 971
 972         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 973
 974         tbl_dw_addr = priv->scd_base_addr +
 975                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 976
 977         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 978
 979         if (txq_id & 0x1)
 980                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 981         else
 982                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 983
 984         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 985
 986         return 0;
 987 }
 988 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 989 {
 990         /* Simply stop the queue, but don't change any configuration;
 991          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 992         iwl_write_prph(priv,
 993                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 994                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 995                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 996 }
 997
 998 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 999                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1000 {
1001         unsigned long flags;
1002         int ret;
1003         u16 ra_tid;
1004
1005         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1006             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1007                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1008                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1009                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1010                 return -EINVAL;
1011         }
1012
1013         ra_tid = BUILD_RAxTID(sta_id, tid);
1014
1015         /* Modify device's station table to Tx this TID */
1016         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1017
1018         spin_lock_irqsave(&priv->lock, flags);
1019         ret = iwl_grab_nic_access(priv);
1020         if (ret) {
1021                 spin_unlock_irqrestore(&priv->lock, flags);
1022                 return ret;
1023         }
1024
1025         /* Stop this Tx queue before configuring it */
1026         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1027
1028         /* Map receiver-address / traffic-ID to this queue */
1029         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1030
1031         /* Set this queue as a chain-building queue */
1032         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1033
1034         /* enable aggregations for the queue */
1035         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1036
1037         /* Place first TFD at index corresponding to start sequence number.
1038          * Assumes that ssn_idx is valid (!= 0xFFF) */
1039         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1040         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1041         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1042
1043         /* Set up Tx window size and frame limit for this queue */
1044         iwl_write_targ_mem(priv, priv->scd_base_addr +
1045                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1046                         sizeof(u32),
1047                         ((SCD_WIN_SIZE <<
1048                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1049                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1050                         ((SCD_FRAME_LIMIT <<
1051                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1052                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1053
1054         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1055
1056         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1057         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1058
1059         iwl_release_nic_access(priv);
1060         spin_unlock_irqrestore(&priv->lock, flags);
1061
1062         return 0;
1063 }
1064
1065 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1066                                    u16 ssn_idx, u8 tx_fifo)
1067 {
1068         int ret;
1069
1070         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1071             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1072                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1073                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1074                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1075                 return -EINVAL;
1076         }
1077
1078         ret = iwl_grab_nic_access(priv);
1079         if (ret)
1080                 return ret;
1081
1082         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1083
1084         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1085
1086         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1087         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1088         /* supposes that ssn_idx is valid (!= 0xFFF) */
1089         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1090
1091         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1092         iwl_txq_ctx_deactivate(priv, txq_id);
1093         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1094
1095         iwl_release_nic_access(priv);
1096
1097         return 0;
1098 }
1099
1100 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1101 {
1102         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1103         memcpy(data, cmd, size);
1104         return size;
1105 }
1106
1107
1108 /*
1109  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1110  * must be called under priv->lock and mac access
1111  */
1112 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1113 {
1114         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1115 }
1116
1117
1118 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1119 {
1120         return le32_to_cpup((__le32 *)&tx_resp->status +
1121                             tx_resp->frame_count) & MAX_SN;
1122 }
1123
1124 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1125                                       struct iwl_ht_agg *agg,
1126                                       struct iwl5000_tx_resp *tx_resp,
1127                                       int txq_id, u16 start_idx)
1128 {
1129         u16 status;
1130         struct agg_tx_status *frame_status = &tx_resp->status;
1131         struct ieee80211_tx_info *info = NULL;
1132         struct ieee80211_hdr *hdr = NULL;
1133         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1134         int i, sh, idx;
1135         u16 seq;
1136
1137         if (agg->wait_for_ba)
1138                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1139
1140         agg->frame_count = tx_resp->frame_count;
1141         agg->start_idx = start_idx;
1142         agg->rate_n_flags = rate_n_flags;
1143         agg->bitmap = 0;
1144
1145         /* # frames attempted by Tx command */
1146         if (agg->frame_count == 1) {
1147                 /* Only one frame was attempted; no block-ack will arrive */
1148                 status = le16_to_cpu(frame_status[0].status);
1149                 idx = start_idx;
1150
1151                 /* FIXME: code repetition */
1152                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1153                                    agg->frame_count, agg->start_idx, idx);
1154
1155                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1156                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1157                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1158                 info->flags |= iwl_is_tx_success(status) ?
1159                                         IEEE80211_TX_STAT_ACK : 0;
1160                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1161
1162                 /* FIXME: code repetition end */
1163
1164                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1165                                     status & 0xff, tx_resp->failure_frame);
1166                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1167
1168                 agg->wait_for_ba = 0;
1169         } else {
1170                 /* Two or more frames were attempted; expect block-ack */
1171                 u64 bitmap = 0;
1172                 int start = agg->start_idx;
1173
1174                 /* Construct bit-map of pending frames within Tx window */
1175                 for (i = 0; i < agg->frame_count; i++) {
1176                         u16 sc;
1177                         status = le16_to_cpu(frame_status[i].status);
1178                         seq  = le16_to_cpu(frame_status[i].sequence);
1179                         idx = SEQ_TO_INDEX(seq);
1180                         txq_id = SEQ_TO_QUEUE(seq);
1181
1182                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1183                                       AGG_TX_STATE_ABORT_MSK))
1184                                 continue;
1185
1186                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1187                                            agg->frame_count, txq_id, idx);
1188
1189                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1190
1191                         sc = le16_to_cpu(hdr->seq_ctrl);
1192                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1193                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1194                                           " idx=%d, seq_idx=%d, seq=%d\n",
1195                                           idx, SEQ_TO_SN(sc),
1196                                           hdr->seq_ctrl);
1197                                 return -1;
1198                         }
1199
1200                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1201                                            i, idx, SEQ_TO_SN(sc));
1202
1203                         sh = idx - start;
1204                         if (sh > 64) {
1205                                 sh = (start - idx) + 0xff;
1206                                 bitmap = bitmap << sh;
1207                                 sh = 0;
1208                                 start = idx;
1209                         } else if (sh < -64)
1210                                 sh  = 0xff - (start - idx);
1211                         else if (sh < 0) {
1212                                 sh = start - idx;
1213                                 start = idx;
1214                                 bitmap = bitmap << sh;
1215                                 sh = 0;
1216                         }
1217                         bitmap |= 1ULL << sh;
1218                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1219                                            start, (unsigned long long)bitmap);
1220                 }
1221
1222                 agg->bitmap = bitmap;
1223                 agg->start_idx = start;
1224                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1225                                    agg->frame_count, agg->start_idx,
1226                                    (unsigned long long)agg->bitmap);
1227
1228                 if (bitmap)
1229                         agg->wait_for_ba = 1;
1230         }
1231         return 0;
1232 }
1233
1234 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1235                                 struct iwl_rx_mem_buffer *rxb)
1236 {
1237         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1238         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1239         int txq_id = SEQ_TO_QUEUE(sequence);
1240         int index = SEQ_TO_INDEX(sequence);
1241         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1242         struct ieee80211_tx_info *info;
1243         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1244         u32  status = le16_to_cpu(tx_resp->status.status);
1245         int tid;
1246         int sta_id;
1247         int freed;
1248
1249         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1250                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1251                           "is out of range [0-%d] %d %d\n", txq_id,
1252                           index, txq->q.n_bd, txq->q.write_ptr,
1253                           txq->q.read_ptr);
1254                 return;
1255         }
1256
1257         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1258         memset(&info->status, 0, sizeof(info->status));
1259
1260         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1261         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1262
1263         if (txq->sched_retry) {
1264                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1265                 struct iwl_ht_agg *agg = NULL;
1266
1267                 agg = &priv->stations[sta_id].tid[tid].agg;
1268
1269                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1270
1271                 /* check if BAR is needed */
1272                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1273                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1274
1275                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1276                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1277                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1278                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1279                                         scd_ssn , index, txq_id, txq->swq_id);
1280
1281                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1282                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1283
1284                         if (priv->mac80211_registered &&
1285                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1286                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1287                                 if (agg->state == IWL_AGG_OFF)
1288                                         ieee80211_wake_queue(priv->hw, txq_id);
1289                                 else
1290                                         ieee80211_wake_queue(priv->hw,
1291                                                              txq->swq_id);
1292                         }
1293                 }
1294         } else {
1295                 BUG_ON(txq_id != txq->swq_id);
1296
1297                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1298                 info->flags |= iwl_is_tx_success(status) ?
1299                                         IEEE80211_TX_STAT_ACK : 0;
1300                 iwl_hwrate_to_tx_control(priv,
1301                                         le32_to_cpu(tx_resp->rate_n_flags),
1302                                         info);
1303
1304                 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1305                                    "0x%x retries %d\n",
1306                                    txq_id,
1307                                    iwl_get_tx_fail_reason(status), status,
1308                                    le32_to_cpu(tx_resp->rate_n_flags),
1309                                    tx_resp->failure_frame);
1310
1311                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1312                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1313                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1314
1315                 if (priv->mac80211_registered &&
1316                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1317                         ieee80211_wake_queue(priv->hw, txq_id);
1318         }
1319
1320         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1321                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1322
1323         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1324                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1325 }
1326
1327 /* Currently 5000 is the superset of everything */
1328 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1329 {
1330         return len;
1331 }
1332
1333 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1334 {
1335         /* in 5000 the tx power calibration is done in uCode */
1336         priv->disable_tx_power_cal = 1;
1337 }
1338
1339 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1340 {
1341         /* init calibration handlers */
1342         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1343                                         iwl5000_rx_calib_result;
1344         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1345                                         iwl5000_rx_calib_complete;
1346         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1347 }
1348
1349
1350 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1351 {
1352         return (addr >= RTC_DATA_LOWER_BOUND) &&
1353                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1354 }
1355
1356 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1357 {
1358         int ret = 0;
1359         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1360         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1361         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1362
1363         if ((rxon1->flags == rxon2->flags) &&
1364             (rxon1->filter_flags == rxon2->filter_flags) &&
1365             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1366             (rxon1->ofdm_ht_single_stream_basic_rates ==
1367              rxon2->ofdm_ht_single_stream_basic_rates) &&
1368             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1369              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1370             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1371              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1372             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1373             (rxon1->rx_chain == rxon2->rx_chain) &&
1374             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1375                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1376                 return 0;
1377         }
1378
1379         rxon_assoc.flags = priv->staging_rxon.flags;
1380         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1381         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1382         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1383         rxon_assoc.reserved1 = 0;
1384         rxon_assoc.reserved2 = 0;
1385         rxon_assoc.reserved3 = 0;
1386         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1387             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1388         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1389             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1390         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1391         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1392                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1393         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1394
1395         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1396                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1397         if (ret)
1398                 return ret;
1399
1400         return ret;
1401 }
1402 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1403 {
1404         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1405
1406         /* half dBm need to multiply */
1407         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1408         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1409         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1410         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1411                                        sizeof(tx_power_cmd), &tx_power_cmd,
1412                                        NULL);
1413 }
1414
1415 static void iwl5000_temperature(struct iwl_priv *priv)
1416 {
1417         /* store temperature from statistics (in Celsius) */
1418         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1419 }
1420
1421 /* Calc max signal level (dBm) among 3 possible receivers */
1422 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1423                              struct iwl_rx_phy_res *rx_resp)
1424 {
1425         /* data from PHY/DSP regarding signal strength, etc.,
1426          *   contents are always there, not configurable by host
1427          */
1428         struct iwl5000_non_cfg_phy *ncphy =
1429                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1430         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1431         u8 agc;
1432
1433         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1434         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1435
1436         /* Find max rssi among 3 possible receivers.
1437          * These values are measured by the digital signal processor (DSP).
1438          * They should stay fairly constant even as the signal strength varies,
1439          *   if the radio's automatic gain control (AGC) is working right.
1440          * AGC value (see below) will provide the "interesting" info.
1441          */
1442         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1443         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1444         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1445         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1446         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1447
1448         max_rssi = max_t(u32, rssi_a, rssi_b);
1449         max_rssi = max_t(u32, max_rssi, rssi_c);
1450
1451         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1452                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1453
1454         /* dBm = max_rssi dB - agc dB - constant.
1455          * Higher AGC (higher radio gain) means lower signal. */
1456         return max_rssi - agc - IWL_RSSI_OFFSET;
1457 }
1458
1459 static struct iwl_hcmd_ops iwl5000_hcmd = {
1460         .rxon_assoc = iwl5000_send_rxon_assoc,
1461 };
1462
1463 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1464         .get_hcmd_size = iwl5000_get_hcmd_size,
1465         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1466         .gain_computation = iwl5000_gain_computation,
1467         .chain_noise_reset = iwl5000_chain_noise_reset,
1468         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1469         .calc_rssi = iwl5000_calc_rssi,
1470 };
1471
1472 static struct iwl_lib_ops iwl5000_lib = {
1473         .set_hw_params = iwl5000_hw_set_hw_params,
1474         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1475         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1476         .txq_set_sched = iwl5000_txq_set_sched,
1477         .txq_agg_enable = iwl5000_txq_agg_enable,
1478         .txq_agg_disable = iwl5000_txq_agg_disable,
1479         .rx_handler_setup = iwl5000_rx_handler_setup,
1480         .setup_deferred_work = iwl5000_setup_deferred_work,
1481         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1482         .load_ucode = iwl5000_load_ucode,
1483         .init_alive_start = iwl5000_init_alive_start,
1484         .alive_notify = iwl5000_alive_notify,
1485         .send_tx_power = iwl5000_send_tx_power,
1486         .temperature = iwl5000_temperature,
1487         .update_chain_flags = iwl_update_chain_flags,
1488         .apm_ops = {
1489                 .init = iwl5000_apm_init,
1490                 .reset = iwl5000_apm_reset,
1491                 .stop = iwl5000_apm_stop,
1492                 .config = iwl5000_nic_config,
1493                 .set_pwr_src = iwl_set_pwr_src,
1494         },
1495         .eeprom_ops = {
1496                 .regulatory_bands = {
1497                         EEPROM_5000_REG_BAND_1_CHANNELS,
1498                         EEPROM_5000_REG_BAND_2_CHANNELS,
1499                         EEPROM_5000_REG_BAND_3_CHANNELS,
1500                         EEPROM_5000_REG_BAND_4_CHANNELS,
1501                         EEPROM_5000_REG_BAND_5_CHANNELS,
1502                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1503                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1504                 },
1505                 .verify_signature  = iwlcore_eeprom_verify_signature,
1506                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1507                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1508                 .calib_version  = iwl5000_eeprom_calib_version,
1509                 .query_addr = iwl5000_eeprom_query_addr,
1510         },
1511 };
1512
1513 static struct iwl_ops iwl5000_ops = {
1514         .lib = &iwl5000_lib,
1515         .hcmd = &iwl5000_hcmd,
1516         .utils = &iwl5000_hcmd_utils,
1517 };
1518
1519 static struct iwl_mod_params iwl50_mod_params = {
1520         .num_of_queues = IWL50_NUM_QUEUES,
1521         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1522         .enable_qos = 1,
1523         .amsdu_size_8K = 1,
1524         .restart_fw = 1,
1525         /* the rest are 0 by default */
1526 };
1527
1528
1529 struct iwl_cfg iwl5300_agn_cfg = {
1530         .name = "5300AGN",
1531         .fw_name = IWL5000_MODULE_FIRMWARE,
1532         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1533         .ops = &iwl5000_ops,
1534         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1535         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1536         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1537         .mod_params = &iwl50_mod_params,
1538 };
1539
1540 struct iwl_cfg iwl5100_bg_cfg = {
1541         .name = "5100BG",
1542         .fw_name = IWL5000_MODULE_FIRMWARE,
1543         .sku = IWL_SKU_G,
1544         .ops = &iwl5000_ops,
1545         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1546         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1547         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1548         .mod_params = &iwl50_mod_params,
1549 };
1550
1551 struct iwl_cfg iwl5100_abg_cfg = {
1552         .name = "5100ABG",
1553         .fw_name = IWL5000_MODULE_FIRMWARE,
1554         .sku = IWL_SKU_A|IWL_SKU_G,
1555         .ops = &iwl5000_ops,
1556         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1557         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1558         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1559         .mod_params = &iwl50_mod_params,
1560 };
1561
1562 struct iwl_cfg iwl5100_agn_cfg = {
1563         .name = "5100AGN",
1564         .fw_name = IWL5000_MODULE_FIRMWARE,
1565         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1566         .ops = &iwl5000_ops,
1567         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1568         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1569         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1570         .mod_params = &iwl50_mod_params,
1571 };
1572
1573 struct iwl_cfg iwl5350_agn_cfg = {
1574         .name = "5350AGN",
1575         .fw_name = IWL5000_MODULE_FIRMWARE,
1576         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1577         .ops = &iwl5000_ops,
1578         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1579         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1580         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1581         .mod_params = &iwl50_mod_params,
1582 };
1583
1584 struct iwl_cfg iwl5150_agn_cfg = {
1585         .name = "5150AGN",
1586         .fw_name = IWL5150_MODULE_FIRMWARE,
1587         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1588         .ops = &iwl5000_ops,
1589         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1590         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1591         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1592         .mod_params = &iwl50_mod_params,
1593 };
1594
1595 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
1596 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE);
1597
1598 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1599 MODULE_PARM_DESC(disable50,
1600                   "manually disable the 50XX radio (default 0 [radio on])");
1601 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1602 MODULE_PARM_DESC(swcrypto50,
1603                   "using software crypto engine (default 0 [hardware])\n");
1604 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1605 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1606 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1607 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1608 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1609 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1610 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1611 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1612 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1613 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1614 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1615 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");