drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/version.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 #define IWL5000_UCODE_API  "-1"
  48
  49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  50         IWL_TX_FIFO_AC3,
  51         IWL_TX_FIFO_AC2,
  52         IWL_TX_FIFO_AC1,
  53         IWL_TX_FIFO_AC0,
  54         IWL50_CMD_FIFO_NUM,
  55         IWL_TX_FIFO_HCCA_1,
  56         IWL_TX_FIFO_HCCA_2
  57 };
  58
  59 static int iwl5000_apm_init(struct iwl_priv *priv)
  60 {
  61         int ret = 0;
  62
  63         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  64                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  65
  66         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
  67
  68         /* set "initialization complete" bit to move adapter
  69          * D0U* --> D0A* state */
  70         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  71
  72         /* wait for clock stabilization */
  73         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  74                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  75                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  76         if (ret < 0) {
  77                 IWL_DEBUG_INFO("Failed to init the card\n");
  78                 return ret;
  79         }
  80
  81         ret = iwl_grab_nic_access(priv);
  82         if (ret)
  83                 return ret;
  84
  85         /* enable DMA */
  86         iwl_write_prph(priv, APMG_CLK_EN_REG,
  87                         APMG_CLK_VAL_DMA_CLK_RQT);
  88
  89         udelay(20);
  90
  91         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  92                         APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  93
  94         iwl_release_nic_access(priv);
  95
  96         return ret;
  97 }
  98
  99 static void iwl5000_nic_config(struct iwl_priv *priv)
 100 {
 101         unsigned long flags;
 102         u16 radio_cfg;
 103         u8 val_link;
 104
 105         spin_lock_irqsave(&priv->lock, flags);
 106
 107         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
 108
 109         /* disable L1 entry -- workaround for pre-B1 */
 110         pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
 111
 112         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 113
 114         /* write radio config values to register */
 115         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 116                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 117                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 118                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 119                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 120
 121         /* set CSR_HW_CONFIG_REG for uCode use */
 122         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 123                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 124                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 125
 126         spin_unlock_irqrestore(&priv->lock, flags);
 127 }
 128
 129
 130
 131 /*
 132  * EEPROM
 133  */
 134 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 135 {
 136         u16 offset = 0;
 137
 138         if ((address & INDIRECT_ADDRESS) == 0)
 139                 return address;
 140
 141         switch (address & INDIRECT_TYPE_MSK) {
 142         case INDIRECT_HOST:
 143                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 144                 break;
 145         case INDIRECT_GENERAL:
 146                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 147                 break;
 148         case INDIRECT_REGULATORY:
 149                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 150                 break;
 151         case INDIRECT_CALIBRATION:
 152                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 153                 break;
 154         case INDIRECT_PROCESS_ADJST:
 155                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 156                 break;
 157         case INDIRECT_OTHERS:
 158                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 159                 break;
 160         default:
 161                 IWL_ERROR("illegal indirect type: 0x%X\n",
 162                 address & INDIRECT_TYPE_MSK);
 163                 break;
 164         }
 165
 166         /* translate the offset from words to byte */
 167         return (address & ADDRESS_MSK) + (offset << 1);
 168 }
 169
 170 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
 171 {
 172         u16 eeprom_ver;
 173         struct iwl_eeprom_calib_hdr {
 174                 u8 version;
 175                 u8 pa_type;
 176                 u16 voltage;
 177         } *hdr;
 178
 179         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 180
 181         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 182                                                         EEPROM_5000_CALIB_ALL);
 183
 184         if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
 185             hdr->version < EEPROM_5000_TX_POWER_VERSION)
 186                 goto err;
 187
 188         return 0;
 189 err:
 190         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 191                   eeprom_ver, EEPROM_5000_EEPROM_VERSION,
 192                   hdr->version, EEPROM_5000_TX_POWER_VERSION);
 193         return -EINVAL;
 194
 195 }
 196
 197 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
 198
 199 static void iwl5000_gain_computation(struct iwl_priv *priv,
 200                 u32 average_noise[NUM_RX_CHAINS],
 201                 u16 min_average_noise_antenna_i,
 202                 u32 min_average_noise)
 203 {
 204         int i;
 205         s32 delta_g;
 206         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 207
 208         /* Find Gain Code for the antennas B and C */
 209         for (i = 1; i < NUM_RX_CHAINS; i++) {
 210                 if ((data->disconn_array[i])) {
 211                         data->delta_gain_code[i] = 0;
 212                         continue;
 213                 }
 214                 delta_g = (1000 * ((s32)average_noise[0] -
 215                         (s32)average_noise[i])) / 1500;
 216                 /* bound gain by 2 bits value max, 3rd bit is sign */
 217                 data->delta_gain_code[i] =
 218                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 219
 220                 if (delta_g < 0)
 221                         /* set negative sign */
 222                         data->delta_gain_code[i] |= (1 << 2);
 223         }
 224
 225         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 226                         data->delta_gain_code[1], data->delta_gain_code[2]);
 227
 228         if (!data->radio_write) {
 229                 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
 230                 memset(&cmd, 0, sizeof(cmd));
 231
 232                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 233                 cmd.delta_gain_1 = data->delta_gain_code[1];
 234                 cmd.delta_gain_2 = data->delta_gain_code[2];
 235                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 236                         sizeof(cmd), &cmd, NULL);
 237
 238                 data->radio_write = 1;
 239                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 240         }
 241
 242         data->chain_noise_a = 0;
 243         data->chain_noise_b = 0;
 244         data->chain_noise_c = 0;
 245         data->chain_signal_a = 0;
 246         data->chain_signal_b = 0;
 247         data->chain_signal_c = 0;
 248         data->beacon_count = 0;
 249 }
 250
 251
 252 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 253 {
 254         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 255
 256         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 257                 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
 258
 259                 memset(&cmd, 0, sizeof(cmd));
 260                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 261                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 262                         sizeof(cmd), &cmd))
 263                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 264                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 265                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 266         }
 267 }
 268
 269 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 270         .min_nrg_cck = 95,
 271         .max_nrg_cck = 0,
 272         .auto_corr_min_ofdm = 90,
 273         .auto_corr_min_ofdm_mrc = 170,
 274         .auto_corr_min_ofdm_x1 = 120,
 275         .auto_corr_min_ofdm_mrc_x1 = 240,
 276
 277         .auto_corr_max_ofdm = 120,
 278         .auto_corr_max_ofdm_mrc = 210,
 279         .auto_corr_max_ofdm_x1 = 155,
 280         .auto_corr_max_ofdm_mrc_x1 = 290,
 281
 282         .auto_corr_min_cck = 125,
 283         .auto_corr_max_cck = 200,
 284         .auto_corr_min_cck_mrc = 170,
 285         .auto_corr_max_cck_mrc = 400,
 286         .nrg_th_cck = 95,
 287         .nrg_th_ofdm = 95,
 288 };
 289
 290 #endif /* CONFIG_IWL5000_RUN_TIME_CALIB */
 291
 292 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 293                                            size_t offset)
 294 {
 295         u32 address = eeprom_indirect_address(priv, offset);
 296         BUG_ON(address >= priv->cfg->eeprom_size);
 297         return &priv->eeprom[address];
 298 }
 299
 300 /*
 301  * ucode
 302  */
 303 static int iwl5000_load_section(struct iwl_priv *priv,
 304                                 struct fw_desc *image,
 305                                 u32 dst_addr)
 306 {
 307         int ret = 0;
 308         unsigned long flags;
 309
 310         dma_addr_t phy_addr = image->p_addr;
 311         u32 byte_cnt = image->len;
 312
 313         spin_lock_irqsave(&priv->lock, flags);
 314         ret = iwl_grab_nic_access(priv);
 315         if (ret) {
 316                 spin_unlock_irqrestore(&priv->lock, flags);
 317                 return ret;
 318         }
 319
 320         iwl_write_direct32(priv,
 321                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 322                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 323
 324         iwl_write_direct32(priv,
 325                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 326
 327         iwl_write_direct32(priv,
 328                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 329                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 330
 331         /* FIME: write the MSB of the phy_addr in CTRL1
 332          * iwl_write_direct32(priv,
 333                 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
 334                 ((phy_addr & MSB_MSK)
 335                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
 336          */
 337         iwl_write_direct32(priv,
 338                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
 339         iwl_write_direct32(priv,
 340                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 341                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 342                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 343                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 344
 345         iwl_write_direct32(priv,
 346                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 347                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 348                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
 349                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 350
 351         iwl_release_nic_access(priv);
 352         spin_unlock_irqrestore(&priv->lock, flags);
 353         return 0;
 354 }
 355
 356 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 357                 struct fw_desc *inst_image,
 358                 struct fw_desc *data_image)
 359 {
 360         int ret = 0;
 361
 362         ret = iwl5000_load_section(
 363                 priv, inst_image, RTC_INST_LOWER_BOUND);
 364         if (ret)
 365                 return ret;
 366
 367         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 368         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 369                                 priv->ucode_write_complete, 5 * HZ);
 370         if (ret == -ERESTARTSYS) {
 371                 IWL_ERROR("Could not load the INST uCode section due "
 372                         "to interrupt\n");
 373                 return ret;
 374         }
 375         if (!ret) {
 376                 IWL_ERROR("Could not load the INST uCode section\n");
 377                 return -ETIMEDOUT;
 378         }
 379
 380         priv->ucode_write_complete = 0;
 381
 382         ret = iwl5000_load_section(
 383                 priv, data_image, RTC_DATA_LOWER_BOUND);
 384         if (ret)
 385                 return ret;
 386
 387         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 388
 389         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 390                                 priv->ucode_write_complete, 5 * HZ);
 391         if (ret == -ERESTARTSYS) {
 392                 IWL_ERROR("Could not load the INST uCode section due "
 393                         "to interrupt\n");
 394                 return ret;
 395         } else if (!ret) {
 396                 IWL_ERROR("Could not load the DATA uCode section\n");
 397                 return -ETIMEDOUT;
 398         } else
 399                 ret = 0;
 400
 401         priv->ucode_write_complete = 0;
 402
 403         return ret;
 404 }
 405
 406 static int iwl5000_load_ucode(struct iwl_priv *priv)
 407 {
 408         int ret = 0;
 409
 410         /* check whether init ucode should be loaded, or rather runtime ucode */
 411         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 412                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 413                 ret = iwl5000_load_given_ucode(priv,
 414                         &priv->ucode_init, &priv->ucode_init_data);
 415                 if (!ret) {
 416                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 417                         priv->ucode_type = UCODE_INIT;
 418                 }
 419         } else {
 420                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 421                         "Loading runtime ucode...\n");
 422                 ret = iwl5000_load_given_ucode(priv,
 423                         &priv->ucode_code, &priv->ucode_data);
 424                 if (!ret) {
 425                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 426                         priv->ucode_type = UCODE_RT;
 427                 }
 428         }
 429
 430         return ret;
 431 }
 432
 433 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 434 {
 435         int ret = 0;
 436
 437         /* Check alive response for "valid" sign from uCode */
 438         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 439                 /* We had an error bringing up the hardware, so take it
 440                  * all the way back down so we can try again */
 441                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 442                 goto restart;
 443         }
 444
 445         /* initialize uCode was loaded... verify inst image.
 446          * This is a paranoid check, because we would not have gotten the
 447          * "initialize" alive if code weren't properly loaded.  */
 448         if (iwl_verify_ucode(priv)) {
 449                 /* Runtime instruction load was bad;
 450                  * take it all the way back down so we can try again */
 451                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 452                 goto restart;
 453         }
 454
 455         iwlcore_clear_stations_table(priv);
 456         ret = priv->cfg->ops->lib->alive_notify(priv);
 457         if (ret) {
 458                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 459                 goto restart;
 460         }
 461
 462         return;
 463
 464 restart:
 465         /* real restart (first load init_ucode) */
 466         queue_work(priv->workqueue, &priv->restart);
 467 }
 468
 469 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 470                                 int txq_id, u32 index)
 471 {
 472         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 473                         (index & 0xff) | (txq_id << 8));
 474         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 475 }
 476
 477 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 478                                         struct iwl_tx_queue *txq,
 479                                         int tx_fifo_id, int scd_retry)
 480 {
 481         int txq_id = txq->q.id;
 482         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
 483
 484         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 485                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 486                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 487                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 488                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 489
 490         txq->sched_retry = scd_retry;
 491
 492         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 493                        active ? "Activate" : "Deactivate",
 494                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 495 }
 496
 497 static int iwl5000_alive_notify(struct iwl_priv *priv)
 498 {
 499         u32 a;
 500         int i = 0;
 501         unsigned long flags;
 502         int ret;
 503
 504         spin_lock_irqsave(&priv->lock, flags);
 505
 506         ret = iwl_grab_nic_access(priv);
 507         if (ret) {
 508                 spin_unlock_irqrestore(&priv->lock, flags);
 509                 return ret;
 510         }
 511
 512         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 513         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 514         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 515                 a += 4)
 516                 iwl_write_targ_mem(priv, a, 0);
 517         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 518                 a += 4)
 519                 iwl_write_targ_mem(priv, a, 0);
 520         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 521                 iwl_write_targ_mem(priv, a, 0);
 522
 523         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 524                 (priv->shared_phys +
 525                  offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
 526         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 527                 IWL50_SCD_QUEUECHAIN_SEL_ALL(
 528                         priv->hw_params.max_txq_num));
 529         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 530
 531         /* initiate the queues */
 532         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 533                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 534                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 535                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 536                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 537                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 538                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 539                                 sizeof(u32),
 540                                 ((SCD_WIN_SIZE <<
 541                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 542                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 543                                 ((SCD_FRAME_LIMIT <<
 544                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 545                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 546         }
 547
 548         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 549                                  (1 << priv->hw_params.max_txq_num) - 1);
 550
 551         iwl_write_prph(priv, IWL50_SCD_TXFACT,
 552                                  SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
 553
 554         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 555         /* map qos queues to fifos one-to-one */
 556         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 557                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 558                 iwl_txq_ctx_activate(priv, i);
 559                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 560         }
 561         /* TODO - need to initialize those FIFOs inside the loop above,
 562          * not only mark them as active */
 563         iwl_txq_ctx_activate(priv, 4);
 564         iwl_txq_ctx_activate(priv, 7);
 565         iwl_txq_ctx_activate(priv, 8);
 566         iwl_txq_ctx_activate(priv, 9);
 567
 568         iwl_release_nic_access(priv);
 569         spin_unlock_irqrestore(&priv->lock, flags);
 570
 571         /* Ask for statistics now, the uCode will send notification
 572          * periodically after association */
 573         iwl_send_statistics_request(priv, CMD_ASYNC);
 574
 575         return 0;
 576 }
 577
 578 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 579 {
 580         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 581             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 582                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 583                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 584                 return -EINVAL;
 585         }
 586
 587         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 588         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
 589         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
 590         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
 591         if (priv->cfg->mod_params->amsdu_size_8K)
 592                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
 593         else
 594                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
 595         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
 596         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 597         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 598         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 599         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 600         priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
 601         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 602                                         BIT(IEEE80211_BAND_5GHZ);
 603 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
 604         priv->hw_params.sens = &iwl5000_sensitivity;
 605 #endif
 606
 607         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 608         case CSR_HW_REV_TYPE_5100:
 609         case CSR_HW_REV_TYPE_5150:
 610                 priv->hw_params.tx_chains_num = 1;
 611                 priv->hw_params.rx_chains_num = 2;
 612                 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
 613                 priv->hw_params.valid_tx_ant = ANT_A;
 614                 priv->hw_params.valid_rx_ant = ANT_AB;
 615                 break;
 616         case CSR_HW_REV_TYPE_5300:
 617         case CSR_HW_REV_TYPE_5350:
 618                 priv->hw_params.tx_chains_num = 3;
 619                 priv->hw_params.rx_chains_num = 3;
 620                 priv->hw_params.valid_tx_ant = ANT_ABC;
 621                 priv->hw_params.valid_rx_ant = ANT_ABC;
 622                 break;
 623         }
 624
 625         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 626         case CSR_HW_REV_TYPE_5100:
 627         case CSR_HW_REV_TYPE_5300:
 628                 /* 5X00 wants in Celsius */
 629                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 630                 break;
 631         case CSR_HW_REV_TYPE_5150:
 632         case CSR_HW_REV_TYPE_5350:
 633                 /* 5X50 wants in Kelvin */
 634                 priv->hw_params.ct_kill_threshold =
 635                                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
 636                 break;
 637         }
 638
 639         return 0;
 640 }
 641
 642 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
 643 {
 644         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
 645                                         sizeof(struct iwl5000_shared),
 646                                         &priv->shared_phys);
 647         if (!priv->shared_virt)
 648                 return -ENOMEM;
 649
 650         memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
 651
 652         priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
 653
 654         return 0;
 655 }
 656
 657 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
 658 {
 659         if (priv->shared_virt)
 660                 pci_free_consistent(priv->pci_dev,
 661                                     sizeof(struct iwl5000_shared),
 662                                     priv->shared_virt,
 663                                     priv->shared_phys);
 664 }
 665
 666 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
 667 {
 668         struct iwl5000_shared *s = priv->shared_virt;
 669         return le32_to_cpu(s->rb_closed) & 0xFFF;
 670 }
 671
 672 /**
 673  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 674  */
 675 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 676                                             struct iwl_tx_queue *txq,
 677                                             u16 byte_cnt)
 678 {
 679         struct iwl5000_shared *shared_data = priv->shared_virt;
 680         int txq_id = txq->q.id;
 681         u8 sec_ctl = 0;
 682         u8 sta = 0;
 683         int len;
 684
 685         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 686
 687         if (txq_id != IWL_CMD_QUEUE_NUM) {
 688                 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
 689                 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
 690
 691                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 692                 case TX_CMD_SEC_CCM:
 693                         len += CCMP_MIC_LEN;
 694                         break;
 695                 case TX_CMD_SEC_TKIP:
 696                         len += TKIP_ICV_LEN;
 697                         break;
 698                 case TX_CMD_SEC_WEP:
 699                         len += WEP_IV_LEN + WEP_ICV_LEN;
 700                         break;
 701                 }
 702         }
 703
 704         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 705                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
 706
 707         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 708                        tfd_offset[txq->q.write_ptr], sta_id, sta);
 709
 710         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
 711                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 712                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 713                         byte_cnt, len);
 714                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
 715                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
 716                         sta_id, sta);
 717         }
 718 }
 719
 720 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 721 {
 722         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 723         memcpy(data, cmd, size);
 724         return size;
 725 }
 726
 727
 728 static int iwl5000_disable_tx_fifo(struct iwl_priv *priv)
 729 {
 730         unsigned long flags;
 731         int ret;
 732
 733         spin_lock_irqsave(&priv->lock, flags);
 734
 735         ret = iwl_grab_nic_access(priv);
 736         if (unlikely(ret)) {
 737                 IWL_ERROR("Tx fifo reset failed");
 738                 spin_unlock_irqrestore(&priv->lock, flags);
 739                 return ret;
 740         }
 741
 742         iwl_write_prph(priv, IWL50_SCD_TXFACT, 0);
 743         iwl_release_nic_access(priv);
 744         spin_unlock_irqrestore(&priv->lock, flags);
 745
 746         return 0;
 747 }
 748
 749 /* Currently 5000 is the supperset of everything */
 750 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
 751 {
 752         return len;
 753 }
 754
 755 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
 756 {
 757 }
 758
 759 static struct iwl_hcmd_ops iwl5000_hcmd = {
 760 };
 761
 762 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
 763         .get_hcmd_size = iwl5000_get_hcmd_size,
 764         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
 765 #ifdef CONFIG_IWL5000_RUN_TIME_CALIB
 766         .gain_computation = iwl5000_gain_computation,
 767         .chain_noise_reset = iwl5000_chain_noise_reset,
 768 #endif
 769 };
 770
 771 static struct iwl_lib_ops iwl5000_lib = {
 772         .set_hw_params = iwl5000_hw_set_hw_params,
 773         .alloc_shared_mem = iwl5000_alloc_shared_mem,
 774         .free_shared_mem = iwl5000_free_shared_mem,
 775         .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
 776         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
 777         .disable_tx_fifo = iwl5000_disable_tx_fifo,
 778         .rx_handler_setup = iwl5000_rx_handler_setup,
 779         .load_ucode = iwl5000_load_ucode,
 780         .init_alive_start = iwl5000_init_alive_start,
 781         .alive_notify = iwl5000_alive_notify,
 782         .apm_ops = {
 783                 .init = iwl5000_apm_init,
 784                 .config = iwl5000_nic_config,
 785                 .set_pwr_src = iwl4965_set_pwr_src,
 786         },
 787         .eeprom_ops = {
 788                 .regulatory_bands = {
 789                         EEPROM_5000_REG_BAND_1_CHANNELS,
 790                         EEPROM_5000_REG_BAND_2_CHANNELS,
 791                         EEPROM_5000_REG_BAND_3_CHANNELS,
 792                         EEPROM_5000_REG_BAND_4_CHANNELS,
 793                         EEPROM_5000_REG_BAND_5_CHANNELS,
 794                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
 795                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
 796                 },
 797                 .verify_signature  = iwlcore_eeprom_verify_signature,
 798                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
 799                 .release_semaphore = iwlcore_eeprom_release_semaphore,
 800                 .check_version  = iwl5000_eeprom_check_version,
 801                 .query_addr = iwl5000_eeprom_query_addr,
 802         },
 803 };
 804
 805 static struct iwl_ops iwl5000_ops = {
 806         .lib = &iwl5000_lib,
 807         .hcmd = &iwl5000_hcmd,
 808         .utils = &iwl5000_hcmd_utils,
 809 };
 810
 811 static struct iwl_mod_params iwl50_mod_params = {
 812         .num_of_queues = IWL50_NUM_QUEUES,
 813         .enable_qos = 1,
 814         .amsdu_size_8K = 1,
 815         .restart_fw = 1,
 816         /* the rest are 0 by default */
 817 };
 818
 819
 820 struct iwl_cfg iwl5300_agn_cfg = {
 821         .name = "5300AGN",
 822         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
 823         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 824         .ops = &iwl5000_ops,
 825         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 826         .mod_params = &iwl50_mod_params,
 827 };
 828
 829 struct iwl_cfg iwl5100_agn_cfg = {
 830         .name = "5100AGN",
 831         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
 832         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 833         .ops = &iwl5000_ops,
 834         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 835         .mod_params = &iwl50_mod_params,
 836 };
 837
 838 struct iwl_cfg iwl5350_agn_cfg = {
 839         .name = "5350AGN",
 840         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
 841         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 842         .ops = &iwl5000_ops,
 843         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 844         .mod_params = &iwl50_mod_params,
 845 };
 846
 847 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
 848 MODULE_PARM_DESC(disable50,
 849                   "manually disable the 50XX radio (default 0 [radio on])");
 850 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
 851 MODULE_PARM_DESC(swcrypto50,
 852                   "using software crypto engine (default 0 [hardware])\n");
 853 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
 854 MODULE_PARM_DESC(debug50, "50XX debug output mask");
 855 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
 856 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
 857 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
 858 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
 859 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
 860 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
 861 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
 862 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");