1 /******************************************************************************
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
39 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
47 #define IWL5000_UCODE_API "-1"
48 #define IWL5150_UCODE_API "-1"
50 #define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
51 #define IWL5150_MODULE_FIRMWARE "iwlwifi-5150" IWL5150_UCODE_API ".ucode"
53 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
63 /* FIXME: same implementation as 4965 */
64 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
69 spin_lock_irqsave(&priv->lock, flags);
71 /* set stop master bit */
72 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
74 ret = iwl_poll_bit(priv, CSR_RESET,
75 CSR_RESET_REG_FLAG_MASTER_DISABLED,
76 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
81 spin_unlock_irqrestore(&priv->lock, flags);
82 IWL_DEBUG_INFO("stop master\n");
88 static int iwl5000_apm_init(struct iwl_priv *priv)
92 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
93 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
95 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
96 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
97 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
99 /* Set FH wait threshold to maximum (HW error during stress W/A) */
100 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
102 /* enable HAP INTA to move device L1a -> L0s */
103 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
104 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
106 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
108 /* set "initialization complete" bit to move adapter
109 * D0U* --> D0A* state */
110 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
112 /* wait for clock stabilization */
113 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
114 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
115 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
117 IWL_DEBUG_INFO("Failed to init the card\n");
121 ret = iwl_grab_nic_access(priv);
126 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
130 /* disable L1-Active */
131 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
132 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
134 iwl_release_nic_access(priv);
139 /* FIXME: this is identical to 4965 */
140 static void iwl5000_apm_stop(struct iwl_priv *priv)
144 iwl5000_apm_stop_master(priv);
146 spin_lock_irqsave(&priv->lock, flags);
148 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
152 /* clear "init complete" move adapter D0A* --> D0U state */
153 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
155 spin_unlock_irqrestore(&priv->lock, flags);
159 static int iwl5000_apm_reset(struct iwl_priv *priv)
164 iwl5000_apm_stop_master(priv);
166 spin_lock_irqsave(&priv->lock, flags);
168 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
173 /* FIXME: put here L1A -L0S w/a */
175 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
177 /* set "initialization complete" bit to move adapter
178 * D0U* --> D0A* state */
179 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
181 /* wait for clock stabilization */
182 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
183 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
184 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
186 IWL_DEBUG_INFO("Failed to init the card\n");
190 ret = iwl_grab_nic_access(priv);
195 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
199 /* disable L1-Active */
200 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
201 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
203 iwl_release_nic_access(priv);
206 spin_unlock_irqrestore(&priv->lock, flags);
212 static void iwl5000_nic_config(struct iwl_priv *priv)
218 spin_lock_irqsave(&priv->lock, flags);
220 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
222 /* L1 is enabled by BIOS */
223 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
224 /* disable L0S disabled L1A enabled */
225 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
227 /* L0S enabled L1A disabled */
228 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
230 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
232 /* write radio config values to register */
233 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
234 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
235 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
236 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
237 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
239 /* set CSR_HW_CONFIG_REG for uCode use */
240 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
241 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
242 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
244 /* W/A : NIC is stuck in a reset state after Early PCIe power off
245 * (PCIe power is lost before PERST# is asserted),
246 * causing ME FW to lose ownership and not being able to obtain it back.
248 iwl_grab_nic_access(priv);
249 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
250 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
251 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
252 iwl_release_nic_access(priv);
254 spin_unlock_irqrestore(&priv->lock, flags);
262 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
266 if ((address & INDIRECT_ADDRESS) == 0)
269 switch (address & INDIRECT_TYPE_MSK) {
271 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
273 case INDIRECT_GENERAL:
274 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
276 case INDIRECT_REGULATORY:
277 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
279 case INDIRECT_CALIBRATION:
280 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
282 case INDIRECT_PROCESS_ADJST:
283 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
285 case INDIRECT_OTHERS:
286 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
289 IWL_ERROR("illegal indirect type: 0x%X\n",
290 address & INDIRECT_TYPE_MSK);
294 /* translate the offset from words to byte */
295 return (address & ADDRESS_MSK) + (offset << 1);
298 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
300 struct iwl_eeprom_calib_hdr {
306 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
307 EEPROM_5000_CALIB_ALL);
312 static void iwl5000_gain_computation(struct iwl_priv *priv,
313 u32 average_noise[NUM_RX_CHAINS],
314 u16 min_average_noise_antenna_i,
315 u32 min_average_noise)
319 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
321 /* Find Gain Code for the antennas B and C */
322 for (i = 1; i < NUM_RX_CHAINS; i++) {
323 if ((data->disconn_array[i])) {
324 data->delta_gain_code[i] = 0;
327 delta_g = (1000 * ((s32)average_noise[0] -
328 (s32)average_noise[i])) / 1500;
329 /* bound gain by 2 bits value max, 3rd bit is sign */
330 data->delta_gain_code[i] =
331 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
334 /* set negative sign */
335 data->delta_gain_code[i] |= (1 << 2);
338 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
339 data->delta_gain_code[1], data->delta_gain_code[2]);
341 if (!data->radio_write) {
342 struct iwl_calib_chain_noise_gain_cmd cmd;
344 memset(&cmd, 0, sizeof(cmd));
346 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
347 cmd.hdr.first_group = 0;
348 cmd.hdr.groups_num = 1;
349 cmd.hdr.data_valid = 1;
350 cmd.delta_gain_1 = data->delta_gain_code[1];
351 cmd.delta_gain_2 = data->delta_gain_code[2];
352 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
353 sizeof(cmd), &cmd, NULL);
355 data->radio_write = 1;
356 data->state = IWL_CHAIN_NOISE_CALIBRATED;
359 data->chain_noise_a = 0;
360 data->chain_noise_b = 0;
361 data->chain_noise_c = 0;
362 data->chain_signal_a = 0;
363 data->chain_signal_b = 0;
364 data->chain_signal_c = 0;
365 data->beacon_count = 0;
368 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
370 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
373 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
374 struct iwl_calib_chain_noise_reset_cmd cmd;
375 memset(&cmd, 0, sizeof(cmd));
377 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
378 cmd.hdr.first_group = 0;
379 cmd.hdr.groups_num = 1;
380 cmd.hdr.data_valid = 1;
381 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
384 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
385 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
386 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
390 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
393 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
394 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
395 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
397 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
400 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
403 .auto_corr_min_ofdm = 90,
404 .auto_corr_min_ofdm_mrc = 170,
405 .auto_corr_min_ofdm_x1 = 120,
406 .auto_corr_min_ofdm_mrc_x1 = 240,
408 .auto_corr_max_ofdm = 120,
409 .auto_corr_max_ofdm_mrc = 210,
410 .auto_corr_max_ofdm_x1 = 155,
411 .auto_corr_max_ofdm_mrc_x1 = 290,
413 .auto_corr_min_cck = 125,
414 .auto_corr_max_cck = 200,
415 .auto_corr_min_cck_mrc = 170,
416 .auto_corr_max_cck_mrc = 400,
421 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
424 u32 address = eeprom_indirect_address(priv, offset);
425 BUG_ON(address >= priv->cfg->eeprom_size);
426 return &priv->eeprom[address];
432 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
434 struct iwl_calib_xtal_freq_cmd cmd;
435 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
437 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
438 cmd.hdr.first_group = 0;
439 cmd.hdr.groups_num = 1;
440 cmd.hdr.data_valid = 1;
441 cmd.cap_pin1 = (u8)xtal_calib[0];
442 cmd.cap_pin2 = (u8)xtal_calib[1];
443 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
444 (u8 *)&cmd, sizeof(cmd));
447 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
449 struct iwl_calib_cfg_cmd calib_cfg_cmd;
450 struct iwl_host_cmd cmd = {
451 .id = CALIBRATION_CFG_CMD,
452 .len = sizeof(struct iwl_calib_cfg_cmd),
453 .data = &calib_cfg_cmd,
456 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
457 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
458 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
459 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
460 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
462 return iwl_send_cmd(priv, &cmd);
465 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
466 struct iwl_rx_mem_buffer *rxb)
468 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
469 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
470 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
473 /* reduce the size of the length field itself */
476 /* Define the order in which the results will be sent to the runtime
477 * uCode. iwl_send_calib_results sends them in a row according to their
478 * index. We sort them here */
479 switch (hdr->op_code) {
480 case IWL_PHY_CALIBRATE_LO_CMD:
481 index = IWL_CALIB_LO;
483 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
484 index = IWL_CALIB_TX_IQ;
486 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
487 index = IWL_CALIB_TX_IQ_PERD;
489 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
490 index = IWL_CALIB_BASE_BAND;
493 IWL_ERROR("Unknown calibration notification %d\n",
497 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
500 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
501 struct iwl_rx_mem_buffer *rxb)
503 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
504 queue_work(priv->workqueue, &priv->restart);
510 static int iwl5000_load_section(struct iwl_priv *priv,
511 struct fw_desc *image,
517 dma_addr_t phy_addr = image->p_addr;
518 u32 byte_cnt = image->len;
520 spin_lock_irqsave(&priv->lock, flags);
521 ret = iwl_grab_nic_access(priv);
523 spin_unlock_irqrestore(&priv->lock, flags);
527 iwl_write_direct32(priv,
528 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
529 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
531 iwl_write_direct32(priv,
532 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
534 iwl_write_direct32(priv,
535 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
536 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
538 iwl_write_direct32(priv,
539 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
540 (iwl_get_dma_hi_addr(phy_addr)
541 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
543 iwl_write_direct32(priv,
544 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
545 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
546 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
547 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
549 iwl_write_direct32(priv,
550 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
551 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
552 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
553 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
555 iwl_release_nic_access(priv);
556 spin_unlock_irqrestore(&priv->lock, flags);
560 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
561 struct fw_desc *inst_image,
562 struct fw_desc *data_image)
566 ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
570 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
571 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
572 priv->ucode_write_complete, 5 * HZ);
573 if (ret == -ERESTARTSYS) {
574 IWL_ERROR("Could not load the INST uCode section due "
579 IWL_ERROR("Could not load the INST uCode section\n");
583 priv->ucode_write_complete = 0;
585 ret = iwl5000_load_section(
586 priv, data_image, RTC_DATA_LOWER_BOUND);
590 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
592 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
593 priv->ucode_write_complete, 5 * HZ);
594 if (ret == -ERESTARTSYS) {
595 IWL_ERROR("Could not load the INST uCode section due "
599 IWL_ERROR("Could not load the DATA uCode section\n");
604 priv->ucode_write_complete = 0;
609 static int iwl5000_load_ucode(struct iwl_priv *priv)
613 /* check whether init ucode should be loaded, or rather runtime ucode */
614 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
615 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
616 ret = iwl5000_load_given_ucode(priv,
617 &priv->ucode_init, &priv->ucode_init_data);
619 IWL_DEBUG_INFO("Init ucode load complete.\n");
620 priv->ucode_type = UCODE_INIT;
623 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
624 "Loading runtime ucode...\n");
625 ret = iwl5000_load_given_ucode(priv,
626 &priv->ucode_code, &priv->ucode_data);
628 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
629 priv->ucode_type = UCODE_RT;
636 static void iwl5000_init_alive_start(struct iwl_priv *priv)
640 /* Check alive response for "valid" sign from uCode */
641 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
642 /* We had an error bringing up the hardware, so take it
643 * all the way back down so we can try again */
644 IWL_DEBUG_INFO("Initialize Alive failed.\n");
648 /* initialize uCode was loaded... verify inst image.
649 * This is a paranoid check, because we would not have gotten the
650 * "initialize" alive if code weren't properly loaded. */
651 if (iwl_verify_ucode(priv)) {
652 /* Runtime instruction load was bad;
653 * take it all the way back down so we can try again */
654 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
658 iwl_clear_stations_table(priv);
659 ret = priv->cfg->ops->lib->alive_notify(priv);
661 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
665 iwl5000_send_calib_cfg(priv);
669 /* real restart (first load init_ucode) */
670 queue_work(priv->workqueue, &priv->restart);
673 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
674 int txq_id, u32 index)
676 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
677 (index & 0xff) | (txq_id << 8));
678 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
681 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
682 struct iwl_tx_queue *txq,
683 int tx_fifo_id, int scd_retry)
685 int txq_id = txq->q.id;
686 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
688 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
689 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
690 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
691 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
692 IWL50_SCD_QUEUE_STTS_REG_MSK);
694 txq->sched_retry = scd_retry;
696 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
697 active ? "Activate" : "Deactivate",
698 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
701 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
703 struct iwl_wimax_coex_cmd coex_cmd;
705 memset(&coex_cmd, 0, sizeof(coex_cmd));
707 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
708 sizeof(coex_cmd), &coex_cmd);
711 static int iwl5000_alive_notify(struct iwl_priv *priv)
719 spin_lock_irqsave(&priv->lock, flags);
721 ret = iwl_grab_nic_access(priv);
723 spin_unlock_irqrestore(&priv->lock, flags);
727 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
728 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
729 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
731 iwl_write_targ_mem(priv, a, 0);
732 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
734 iwl_write_targ_mem(priv, a, 0);
735 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
736 iwl_write_targ_mem(priv, a, 0);
738 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
739 priv->scd_bc_tbls.dma >> 10);
741 /* Enable DMA channel */
742 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
743 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
744 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
745 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
747 /* Update FH chicken bits */
748 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
749 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
750 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
752 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
753 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
754 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
756 /* initiate the queues */
757 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
758 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
759 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
760 iwl_write_targ_mem(priv, priv->scd_base_addr +
761 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
762 iwl_write_targ_mem(priv, priv->scd_base_addr +
763 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
766 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
767 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
769 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
770 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
773 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
774 IWL_MASK(0, priv->hw_params.max_txq_num));
776 /* Activate all Tx DMA/FIFO channels */
777 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
779 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
781 /* map qos queues to fifos one-to-one */
782 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
783 int ac = iwl5000_default_queue_to_tx_fifo[i];
784 iwl_txq_ctx_activate(priv, i);
785 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
787 /* TODO - need to initialize those FIFOs inside the loop above,
788 * not only mark them as active */
789 iwl_txq_ctx_activate(priv, 4);
790 iwl_txq_ctx_activate(priv, 7);
791 iwl_txq_ctx_activate(priv, 8);
792 iwl_txq_ctx_activate(priv, 9);
794 iwl_release_nic_access(priv);
795 spin_unlock_irqrestore(&priv->lock, flags);
798 iwl5000_send_wimax_coex(priv);
800 iwl5000_set_Xtal_calib(priv);
801 iwl_send_calib_results(priv);
806 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
808 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
809 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
810 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
811 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
815 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
816 priv->hw_params.scd_bc_tbls_size =
817 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
818 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
819 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
820 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
821 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
822 priv->hw_params.max_bsm_size = 0;
823 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
824 BIT(IEEE80211_BAND_5GHZ);
825 priv->hw_params.sens = &iwl5000_sensitivity;
827 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
828 case CSR_HW_REV_TYPE_5100:
829 priv->hw_params.tx_chains_num = 1;
830 priv->hw_params.rx_chains_num = 2;
831 priv->hw_params.valid_tx_ant = ANT_B;
832 priv->hw_params.valid_rx_ant = ANT_AB;
834 case CSR_HW_REV_TYPE_5150:
835 priv->hw_params.tx_chains_num = 1;
836 priv->hw_params.rx_chains_num = 2;
837 priv->hw_params.valid_tx_ant = ANT_A;
838 priv->hw_params.valid_rx_ant = ANT_AB;
840 case CSR_HW_REV_TYPE_5300:
841 case CSR_HW_REV_TYPE_5350:
842 priv->hw_params.tx_chains_num = 3;
843 priv->hw_params.rx_chains_num = 3;
844 priv->hw_params.valid_tx_ant = ANT_ABC;
845 priv->hw_params.valid_rx_ant = ANT_ABC;
849 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
850 case CSR_HW_REV_TYPE_5100:
851 case CSR_HW_REV_TYPE_5300:
852 case CSR_HW_REV_TYPE_5350:
853 /* 5X00 and 5350 wants in Celsius */
854 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
856 case CSR_HW_REV_TYPE_5150:
857 /* 5150 wants in Kelvin */
858 priv->hw_params.ct_kill_threshold =
859 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
863 /* Set initial calibration set */
864 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
865 case CSR_HW_REV_TYPE_5100:
866 case CSR_HW_REV_TYPE_5300:
867 case CSR_HW_REV_TYPE_5350:
868 priv->hw_params.calib_init_cfg =
869 BIT(IWL_CALIB_XTAL) |
871 BIT(IWL_CALIB_TX_IQ) |
872 BIT(IWL_CALIB_TX_IQ_PERD) |
873 BIT(IWL_CALIB_BASE_BAND);
875 case CSR_HW_REV_TYPE_5150:
876 priv->hw_params.calib_init_cfg = 0;
885 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
887 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
888 struct iwl_tx_queue *txq,
891 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
892 int write_ptr = txq->q.write_ptr;
893 int txq_id = txq->q.id;
896 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
899 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
901 if (txq_id != IWL_CMD_QUEUE_NUM) {
902 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
903 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
905 switch (sec_ctl & TX_CMD_SEC_MSK) {
909 case TX_CMD_SEC_TKIP:
913 len += WEP_IV_LEN + WEP_ICV_LEN;
918 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
920 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
922 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
924 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
927 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
928 struct iwl_tx_queue *txq)
930 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
931 int txq_id = txq->q.id;
932 int read_ptr = txq->q.read_ptr;
936 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
938 if (txq_id != IWL_CMD_QUEUE_NUM)
939 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
941 bc_ent = cpu_to_le16(1 | (sta_id << 12));
942 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
944 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
946 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
949 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
956 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
958 tbl_dw_addr = priv->scd_base_addr +
959 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
961 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
964 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
966 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
968 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
972 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
974 /* Simply stop the queue, but don't change any configuration;
975 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
977 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
978 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
979 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
982 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
983 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
989 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
990 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
991 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
992 txq_id, IWL50_FIRST_AMPDU_QUEUE,
993 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
997 ra_tid = BUILD_RAxTID(sta_id, tid);
999 /* Modify device's station table to Tx this TID */
1000 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1002 spin_lock_irqsave(&priv->lock, flags);
1003 ret = iwl_grab_nic_access(priv);
1005 spin_unlock_irqrestore(&priv->lock, flags);
1009 /* Stop this Tx queue before configuring it */
1010 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1012 /* Map receiver-address / traffic-ID to this queue */
1013 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1015 /* Set this queue as a chain-building queue */
1016 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1018 /* enable aggregations for the queue */
1019 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1021 /* Place first TFD at index corresponding to start sequence number.
1022 * Assumes that ssn_idx is valid (!= 0xFFF) */
1023 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1024 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1025 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1027 /* Set up Tx window size and frame limit for this queue */
1028 iwl_write_targ_mem(priv, priv->scd_base_addr +
1029 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1032 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1033 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1034 ((SCD_FRAME_LIMIT <<
1035 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1036 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1038 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1040 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1041 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1043 iwl_release_nic_access(priv);
1044 spin_unlock_irqrestore(&priv->lock, flags);
1049 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1050 u16 ssn_idx, u8 tx_fifo)
1054 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1055 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1056 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1057 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1058 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1062 ret = iwl_grab_nic_access(priv);
1066 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1068 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1070 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1071 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1072 /* supposes that ssn_idx is valid (!= 0xFFF) */
1073 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1075 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1076 iwl_txq_ctx_deactivate(priv, txq_id);
1077 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1079 iwl_release_nic_access(priv);
1084 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1086 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1087 memcpy(data, cmd, size);
1093 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1094 * must be called under priv->lock and mac access
1096 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1098 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1102 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1104 return le32_to_cpup((__le32 *)&tx_resp->status +
1105 tx_resp->frame_count) & MAX_SN;
1108 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1109 struct iwl_ht_agg *agg,
1110 struct iwl5000_tx_resp *tx_resp,
1111 int txq_id, u16 start_idx)
1114 struct agg_tx_status *frame_status = &tx_resp->status;
1115 struct ieee80211_tx_info *info = NULL;
1116 struct ieee80211_hdr *hdr = NULL;
1117 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1121 if (agg->wait_for_ba)
1122 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1124 agg->frame_count = tx_resp->frame_count;
1125 agg->start_idx = start_idx;
1126 agg->rate_n_flags = rate_n_flags;
1129 /* # frames attempted by Tx command */
1130 if (agg->frame_count == 1) {
1131 /* Only one frame was attempted; no block-ack will arrive */
1132 status = le16_to_cpu(frame_status[0].status);
1135 /* FIXME: code repetition */
1136 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1137 agg->frame_count, agg->start_idx, idx);
1139 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1140 info->status.rates[0].count = tx_resp->failure_frame + 1;
1141 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1142 info->flags |= iwl_is_tx_success(status) ?
1143 IEEE80211_TX_STAT_ACK : 0;
1144 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1146 /* FIXME: code repetition end */
1148 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1149 status & 0xff, tx_resp->failure_frame);
1150 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1152 agg->wait_for_ba = 0;
1154 /* Two or more frames were attempted; expect block-ack */
1156 int start = agg->start_idx;
1158 /* Construct bit-map of pending frames within Tx window */
1159 for (i = 0; i < agg->frame_count; i++) {
1161 status = le16_to_cpu(frame_status[i].status);
1162 seq = le16_to_cpu(frame_status[i].sequence);
1163 idx = SEQ_TO_INDEX(seq);
1164 txq_id = SEQ_TO_QUEUE(seq);
1166 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1167 AGG_TX_STATE_ABORT_MSK))
1170 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1171 agg->frame_count, txq_id, idx);
1173 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1175 sc = le16_to_cpu(hdr->seq_ctrl);
1176 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1177 IWL_ERROR("BUG_ON idx doesn't match seq control"
1178 " idx=%d, seq_idx=%d, seq=%d\n",
1184 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1185 i, idx, SEQ_TO_SN(sc));
1189 sh = (start - idx) + 0xff;
1190 bitmap = bitmap << sh;
1193 } else if (sh < -64)
1194 sh = 0xff - (start - idx);
1198 bitmap = bitmap << sh;
1201 bitmap |= 1ULL << sh;
1202 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1203 start, (unsigned long long)bitmap);
1206 agg->bitmap = bitmap;
1207 agg->start_idx = start;
1208 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1209 agg->frame_count, agg->start_idx,
1210 (unsigned long long)agg->bitmap);
1213 agg->wait_for_ba = 1;
1218 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1219 struct iwl_rx_mem_buffer *rxb)
1221 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1222 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1223 int txq_id = SEQ_TO_QUEUE(sequence);
1224 int index = SEQ_TO_INDEX(sequence);
1225 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1226 struct ieee80211_tx_info *info;
1227 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1228 u32 status = le16_to_cpu(tx_resp->status.status);
1233 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1234 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1235 "is out of range [0-%d] %d %d\n", txq_id,
1236 index, txq->q.n_bd, txq->q.write_ptr,
1241 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1242 memset(&info->status, 0, sizeof(info->status));
1244 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1245 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1247 if (txq->sched_retry) {
1248 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1249 struct iwl_ht_agg *agg = NULL;
1251 agg = &priv->stations[sta_id].tid[tid].agg;
1253 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1255 /* check if BAR is needed */
1256 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1257 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1259 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1260 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1261 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1262 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1263 scd_ssn , index, txq_id, txq->swq_id);
1265 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1266 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1268 if (priv->mac80211_registered &&
1269 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1270 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1271 if (agg->state == IWL_AGG_OFF)
1272 ieee80211_wake_queue(priv->hw, txq_id);
1274 ieee80211_wake_queue(priv->hw,
1279 BUG_ON(txq_id != txq->swq_id);
1281 info->status.rates[0].count = tx_resp->failure_frame + 1;
1282 info->flags |= iwl_is_tx_success(status) ?
1283 IEEE80211_TX_STAT_ACK : 0;
1284 iwl_hwrate_to_tx_control(priv,
1285 le32_to_cpu(tx_resp->rate_n_flags),
1288 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1289 "0x%x retries %d\n",
1291 iwl_get_tx_fail_reason(status), status,
1292 le32_to_cpu(tx_resp->rate_n_flags),
1293 tx_resp->failure_frame);
1295 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1296 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1297 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1299 if (priv->mac80211_registered &&
1300 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1301 ieee80211_wake_queue(priv->hw, txq_id);
1304 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1305 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1307 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1308 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1311 /* Currently 5000 is the superset of everything */
1312 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1317 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1319 /* in 5000 the tx power calibration is done in uCode */
1320 priv->disable_tx_power_cal = 1;
1323 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1325 /* init calibration handlers */
1326 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1327 iwl5000_rx_calib_result;
1328 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1329 iwl5000_rx_calib_complete;
1330 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1334 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1336 return (addr >= RTC_DATA_LOWER_BOUND) &&
1337 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1340 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1343 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1344 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1345 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1347 if ((rxon1->flags == rxon2->flags) &&
1348 (rxon1->filter_flags == rxon2->filter_flags) &&
1349 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1350 (rxon1->ofdm_ht_single_stream_basic_rates ==
1351 rxon2->ofdm_ht_single_stream_basic_rates) &&
1352 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1353 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1354 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1355 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1356 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1357 (rxon1->rx_chain == rxon2->rx_chain) &&
1358 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1359 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1363 rxon_assoc.flags = priv->staging_rxon.flags;
1364 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1365 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1366 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1367 rxon_assoc.reserved1 = 0;
1368 rxon_assoc.reserved2 = 0;
1369 rxon_assoc.reserved3 = 0;
1370 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1371 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1372 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1373 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1374 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1375 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1376 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1377 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1379 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1380 sizeof(rxon_assoc), &rxon_assoc, NULL);
1386 static int iwl5000_send_tx_power(struct iwl_priv *priv)
1388 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1390 /* half dBm need to multiply */
1391 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1392 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1393 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1394 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1395 sizeof(tx_power_cmd), &tx_power_cmd,
1399 static void iwl5000_temperature(struct iwl_priv *priv)
1401 /* store temperature from statistics (in Celsius) */
1402 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1405 /* Calc max signal level (dBm) among 3 possible receivers */
1406 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1407 struct iwl_rx_phy_res *rx_resp)
1409 /* data from PHY/DSP regarding signal strength, etc.,
1410 * contents are always there, not configurable by host
1412 struct iwl5000_non_cfg_phy *ncphy =
1413 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1414 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1417 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1418 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1420 /* Find max rssi among 3 possible receivers.
1421 * These values are measured by the digital signal processor (DSP).
1422 * They should stay fairly constant even as the signal strength varies,
1423 * if the radio's automatic gain control (AGC) is working right.
1424 * AGC value (see below) will provide the "interesting" info.
1426 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1427 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1428 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1429 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1430 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1432 max_rssi = max_t(u32, rssi_a, rssi_b);
1433 max_rssi = max_t(u32, max_rssi, rssi_c);
1435 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1436 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1438 /* dBm = max_rssi dB - agc dB - constant.
1439 * Higher AGC (higher radio gain) means lower signal. */
1440 return max_rssi - agc - IWL_RSSI_OFFSET;
1443 static struct iwl_hcmd_ops iwl5000_hcmd = {
1444 .rxon_assoc = iwl5000_send_rxon_assoc,
1447 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1448 .get_hcmd_size = iwl5000_get_hcmd_size,
1449 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1450 .gain_computation = iwl5000_gain_computation,
1451 .chain_noise_reset = iwl5000_chain_noise_reset,
1452 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1453 .calc_rssi = iwl5000_calc_rssi,
1456 static struct iwl_lib_ops iwl5000_lib = {
1457 .set_hw_params = iwl5000_hw_set_hw_params,
1458 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1459 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1460 .txq_set_sched = iwl5000_txq_set_sched,
1461 .txq_agg_enable = iwl5000_txq_agg_enable,
1462 .txq_agg_disable = iwl5000_txq_agg_disable,
1463 .rx_handler_setup = iwl5000_rx_handler_setup,
1464 .setup_deferred_work = iwl5000_setup_deferred_work,
1465 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1466 .load_ucode = iwl5000_load_ucode,
1467 .init_alive_start = iwl5000_init_alive_start,
1468 .alive_notify = iwl5000_alive_notify,
1469 .send_tx_power = iwl5000_send_tx_power,
1470 .temperature = iwl5000_temperature,
1471 .update_chain_flags = iwl_update_chain_flags,
1473 .init = iwl5000_apm_init,
1474 .reset = iwl5000_apm_reset,
1475 .stop = iwl5000_apm_stop,
1476 .config = iwl5000_nic_config,
1477 .set_pwr_src = iwl_set_pwr_src,
1480 .regulatory_bands = {
1481 EEPROM_5000_REG_BAND_1_CHANNELS,
1482 EEPROM_5000_REG_BAND_2_CHANNELS,
1483 EEPROM_5000_REG_BAND_3_CHANNELS,
1484 EEPROM_5000_REG_BAND_4_CHANNELS,
1485 EEPROM_5000_REG_BAND_5_CHANNELS,
1486 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1487 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1489 .verify_signature = iwlcore_eeprom_verify_signature,
1490 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1491 .release_semaphore = iwlcore_eeprom_release_semaphore,
1492 .calib_version = iwl5000_eeprom_calib_version,
1493 .query_addr = iwl5000_eeprom_query_addr,
1497 static struct iwl_ops iwl5000_ops = {
1498 .lib = &iwl5000_lib,
1499 .hcmd = &iwl5000_hcmd,
1500 .utils = &iwl5000_hcmd_utils,
1503 static struct iwl_mod_params iwl50_mod_params = {
1504 .num_of_queues = IWL50_NUM_QUEUES,
1505 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1509 /* the rest are 0 by default */
1513 struct iwl_cfg iwl5300_agn_cfg = {
1515 .fw_name = IWL5000_MODULE_FIRMWARE,
1516 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1517 .ops = &iwl5000_ops,
1518 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1519 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1520 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1521 .mod_params = &iwl50_mod_params,
1524 struct iwl_cfg iwl5100_bg_cfg = {
1526 .fw_name = IWL5000_MODULE_FIRMWARE,
1528 .ops = &iwl5000_ops,
1529 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1530 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1531 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1532 .mod_params = &iwl50_mod_params,
1535 struct iwl_cfg iwl5100_abg_cfg = {
1537 .fw_name = IWL5000_MODULE_FIRMWARE,
1538 .sku = IWL_SKU_A|IWL_SKU_G,
1539 .ops = &iwl5000_ops,
1540 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1541 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1542 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1543 .mod_params = &iwl50_mod_params,
1546 struct iwl_cfg iwl5100_agn_cfg = {
1548 .fw_name = IWL5000_MODULE_FIRMWARE,
1549 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1550 .ops = &iwl5000_ops,
1551 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1552 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1553 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1554 .mod_params = &iwl50_mod_params,
1557 struct iwl_cfg iwl5350_agn_cfg = {
1559 .fw_name = IWL5000_MODULE_FIRMWARE,
1560 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1561 .ops = &iwl5000_ops,
1562 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1563 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1564 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1565 .mod_params = &iwl50_mod_params,
1568 struct iwl_cfg iwl5150_agn_cfg = {
1570 .fw_name = IWL5150_MODULE_FIRMWARE,
1571 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1572 .ops = &iwl5000_ops,
1573 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1574 .mod_params = &iwl50_mod_params,
1577 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
1578 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE);
1580 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1581 MODULE_PARM_DESC(disable50,
1582 "manually disable the 50XX radio (default 0 [radio on])");
1583 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1584 MODULE_PARM_DESC(swcrypto50,
1585 "using software crypto engine (default 0 [hardware])\n");
1586 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1587 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1588 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1589 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1590 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1591 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1592 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1593 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1594 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1595 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1596 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1597 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");