drivers/net/wireless/iwlwifi/iwl-agn-lib.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-sta.h"
  42
  43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  44 {
  45         return le32_to_cpup((__le32 *)&tx_resp->status +
  46                             tx_resp->frame_count) & MAX_SN;
  47 }
  48
  49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  50 {
  51         status &= TX_STATUS_MSK;
  52
  53         switch (status) {
  54         case TX_STATUS_POSTPONE_DELAY:
  55                 priv->_agn.reply_tx_stats.pp_delay++;
  56                 break;
  57         case TX_STATUS_POSTPONE_FEW_BYTES:
  58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
  59                 break;
  60         case TX_STATUS_POSTPONE_BT_PRIO:
  61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
  62                 break;
  63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
  64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
  65                 break;
  66         case TX_STATUS_POSTPONE_CALC_TTAK:
  67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
  68                 break;
  69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
  71                 break;
  72         case TX_STATUS_FAIL_SHORT_LIMIT:
  73                 priv->_agn.reply_tx_stats.short_limit++;
  74                 break;
  75         case TX_STATUS_FAIL_LONG_LIMIT:
  76                 priv->_agn.reply_tx_stats.long_limit++;
  77                 break;
  78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
  79                 priv->_agn.reply_tx_stats.fifo_underrun++;
  80                 break;
  81         case TX_STATUS_FAIL_DRAIN_FLOW:
  82                 priv->_agn.reply_tx_stats.drain_flow++;
  83                 break;
  84         case TX_STATUS_FAIL_RFKILL_FLUSH:
  85                 priv->_agn.reply_tx_stats.rfkill_flush++;
  86                 break;
  87         case TX_STATUS_FAIL_LIFE_EXPIRE:
  88                 priv->_agn.reply_tx_stats.life_expire++;
  89                 break;
  90         case TX_STATUS_FAIL_DEST_PS:
  91                 priv->_agn.reply_tx_stats.dest_ps++;
  92                 break;
  93         case TX_STATUS_FAIL_HOST_ABORTED:
  94                 priv->_agn.reply_tx_stats.host_abort++;
  95                 break;
  96         case TX_STATUS_FAIL_BT_RETRY:
  97                 priv->_agn.reply_tx_stats.bt_retry++;
  98                 break;
  99         case TX_STATUS_FAIL_STA_INVALID:
 100                 priv->_agn.reply_tx_stats.sta_invalid++;
 101                 break;
 102         case TX_STATUS_FAIL_FRAG_DROPPED:
 103                 priv->_agn.reply_tx_stats.frag_drop++;
 104                 break;
 105         case TX_STATUS_FAIL_TID_DISABLE:
 106                 priv->_agn.reply_tx_stats.tid_disable++;
 107                 break;
 108         case TX_STATUS_FAIL_FIFO_FLUSHED:
 109                 priv->_agn.reply_tx_stats.fifo_flush++;
 110                 break;
 111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
 112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
 113                 break;
 114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
 115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
 116                 break;
 117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
 118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
 119                 break;
 120         default:
 121                 priv->_agn.reply_tx_stats.unknown++;
 122                 break;
 123         }
 124 }
 125
 126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
 127 {
 128         status &= AGG_TX_STATUS_MSK;
 129
 130         switch (status) {
 131         case AGG_TX_STATE_UNDERRUN_MSK:
 132                 priv->_agn.reply_agg_tx_stats.underrun++;
 133                 break;
 134         case AGG_TX_STATE_BT_PRIO_MSK:
 135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
 136                 break;
 137         case AGG_TX_STATE_FEW_BYTES_MSK:
 138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
 139                 break;
 140         case AGG_TX_STATE_ABORT_MSK:
 141                 priv->_agn.reply_agg_tx_stats.abort++;
 142                 break;
 143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
 144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
 145                 break;
 146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
 147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
 148                 break;
 149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
 150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
 151                 break;
 152         case AGG_TX_STATE_SCD_QUERY_MSK:
 153                 priv->_agn.reply_agg_tx_stats.scd_query++;
 154                 break;
 155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
 156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
 157                 break;
 158         case AGG_TX_STATE_RESPONSE_MSK:
 159                 priv->_agn.reply_agg_tx_stats.response++;
 160                 break;
 161         case AGG_TX_STATE_DUMP_TX_MSK:
 162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
 163                 break;
 164         case AGG_TX_STATE_DELAY_TX_MSK:
 165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
 166                 break;
 167         default:
 168                 priv->_agn.reply_agg_tx_stats.unknown++;
 169                 break;
 170         }
 171 }
 172
 173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
 174                                  struct ieee80211_tx_info *info,
 175                                  struct iwlagn_tx_resp *tx_resp,
 176                                  int txq_id, bool is_agg)
 177 {
 178         u16  status = le16_to_cpu(tx_resp->status.status);
 179
 180         info->status.rates[0].count = tx_resp->failure_frame + 1;
 181         if (is_agg)
 182                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 183         info->flags |= iwl_tx_status_to_mac80211(status);
 184         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
 185                                     info);
 186         if (!iwl_is_tx_success(status))
 187                 iwlagn_count_tx_err_status(priv, status);
 188
 189         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 190                            "0x%x retries %d\n",
 191                            txq_id,
 192                            iwl_get_tx_fail_reason(status), status,
 193                            le32_to_cpu(tx_resp->rate_n_flags),
 194                            tx_resp->failure_frame);
 195 }
 196
 197 #ifdef CONFIG_IWLWIFI_DEBUG
 198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
 199
 200 const char *iwl_get_agg_tx_fail_reason(u16 status)
 201 {
 202         status &= AGG_TX_STATUS_MSK;
 203         switch (status) {
 204         case AGG_TX_STATE_TRANSMITTED:
 205                 return "SUCCESS";
 206                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
 207                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
 208                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
 209                 AGG_TX_STATE_FAIL(ABORT_MSK);
 210                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
 211                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
 212                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
 213                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
 214                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
 215                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
 216                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
 217                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
 218         }
 219
 220         return "UNKNOWN";
 221 }
 222 #endif /* CONFIG_IWLWIFI_DEBUG */
 223
 224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
 225                                       struct iwl_ht_agg *agg,
 226                                       struct iwlagn_tx_resp *tx_resp,
 227                                       int txq_id, u16 start_idx)
 228 {
 229         u16 status;
 230         struct agg_tx_status *frame_status = &tx_resp->status;
 231         struct ieee80211_hdr *hdr = NULL;
 232         int i, sh, idx;
 233         u16 seq;
 234
 235         if (agg->wait_for_ba)
 236                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 237
 238         agg->frame_count = tx_resp->frame_count;
 239         agg->start_idx = start_idx;
 240         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 241         agg->bitmap = 0;
 242
 243         /* # frames attempted by Tx command */
 244         if (agg->frame_count == 1) {
 245                 /* Only one frame was attempted; no block-ack will arrive */
 246                 idx = start_idx;
 247
 248                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 249                                    agg->frame_count, agg->start_idx, idx);
 250                 iwlagn_set_tx_status(priv,
 251                                      IEEE80211_SKB_CB(
 252                                         priv->txq[txq_id].txb[idx].skb),
 253                                      tx_resp, txq_id, true);
 254                 agg->wait_for_ba = 0;
 255         } else {
 256                 /* Two or more frames were attempted; expect block-ack */
 257                 u64 bitmap = 0;
 258
 259                 /*
 260                  * Start is the lowest frame sent. It may not be the first
 261                  * frame in the batch; we figure this out dynamically during
 262                  * the following loop.
 263                  */
 264                 int start = agg->start_idx;
 265
 266                 /* Construct bit-map of pending frames within Tx window */
 267                 for (i = 0; i < agg->frame_count; i++) {
 268                         u16 sc;
 269                         status = le16_to_cpu(frame_status[i].status);
 270                         seq  = le16_to_cpu(frame_status[i].sequence);
 271                         idx = SEQ_TO_INDEX(seq);
 272                         txq_id = SEQ_TO_QUEUE(seq);
 273
 274                         if (status & AGG_TX_STATUS_MSK)
 275                                 iwlagn_count_agg_tx_err_status(priv, status);
 276
 277                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 278                                       AGG_TX_STATE_ABORT_MSK))
 279                                 continue;
 280
 281                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 282                                            agg->frame_count, txq_id, idx);
 283                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
 284                                            "try-count (0x%08x)\n",
 285                                            iwl_get_agg_tx_fail_reason(status),
 286                                            status & AGG_TX_STATUS_MSK,
 287                                            status & AGG_TX_TRY_MSK);
 288
 289                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 290                         if (!hdr) {
 291                                 IWL_ERR(priv,
 292                                         "BUG_ON idx doesn't point to valid skb"
 293                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 294                                 return -1;
 295                         }
 296
 297                         sc = le16_to_cpu(hdr->seq_ctrl);
 298                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 299                                 IWL_ERR(priv,
 300                                         "BUG_ON idx doesn't match seq control"
 301                                         " idx=%d, seq_idx=%d, seq=%d\n",
 302                                           idx, SEQ_TO_SN(sc),
 303                                           hdr->seq_ctrl);
 304                                 return -1;
 305                         }
 306
 307                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 308                                            i, idx, SEQ_TO_SN(sc));
 309
 310                         /*
 311                          * sh -> how many frames ahead of the starting frame is
 312                          * the current one?
 313                          *
 314                          * Note that all frames sent in the batch must be in a
 315                          * 64-frame window, so this number should be in [0,63].
 316                          * If outside of this window, then we've found a new
 317                          * "first" frame in the batch and need to change start.
 318                          */
 319                         sh = idx - start;
 320
 321                         /*
 322                          * If >= 64, out of window. start must be at the front
 323                          * of the circular buffer, idx must be near the end of
 324                          * the buffer, and idx is the new "first" frame. Shift
 325                          * the indices around.
 326                          */
 327                         if (sh >= 64) {
 328                                 /* Shift bitmap by start - idx, wrapped */
 329                                 sh = 0x100 - idx + start;
 330                                 bitmap = bitmap << sh;
 331                                 /* Now idx is the new start so sh = 0 */
 332                                 sh = 0;
 333                                 start = idx;
 334                         /*
 335                          * If <= -64 then wraps the 256-pkt circular buffer
 336                          * (e.g., start = 255 and idx = 0, sh should be 1)
 337                          */
 338                         } else if (sh <= -64) {
 339                                 sh  = 0x100 - start + idx;
 340                         /*
 341                          * If < 0 but > -64, out of window. idx is before start
 342                          * but not wrapped. Shift the indices around.
 343                          */
 344                         } else if (sh < 0) {
 345                                 /* Shift by how far start is ahead of idx */
 346                                 sh = start - idx;
 347                                 bitmap = bitmap << sh;
 348                                 /* Now idx is the new start so sh = 0 */
 349                                 start = idx;
 350                                 sh = 0;
 351                         }
 352                         /* Sequence number start + sh was sent in this batch */
 353                         bitmap |= 1ULL << sh;
 354                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 355                                            start, (unsigned long long)bitmap);
 356                 }
 357
 358                 /*
 359                  * Store the bitmap and possibly the new start, if we wrapped
 360                  * the buffer above
 361                  */
 362                 agg->bitmap = bitmap;
 363                 agg->start_idx = start;
 364                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 365                                    agg->frame_count, agg->start_idx,
 366                                    (unsigned long long)agg->bitmap);
 367
 368                 if (bitmap)
 369                         agg->wait_for_ba = 1;
 370         }
 371         return 0;
 372 }
 373
 374 void iwl_check_abort_status(struct iwl_priv *priv,
 375                             u8 frame_count, u32 status)
 376 {
 377         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
 378                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
 379                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 380                         queue_work(priv->workqueue, &priv->tx_flush);
 381         }
 382 }
 383
 384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 385                                 struct iwl_rx_mem_buffer *rxb)
 386 {
 387         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 388         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 389         int txq_id = SEQ_TO_QUEUE(sequence);
 390         int index = SEQ_TO_INDEX(sequence);
 391         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 392         struct ieee80211_tx_info *info;
 393         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 394         u32  status = le16_to_cpu(tx_resp->status.status);
 395         int tid;
 396         int sta_id;
 397         int freed;
 398         unsigned long flags;
 399
 400         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 401                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 402                           "is out of range [0-%d] %d %d\n", txq_id,
 403                           index, txq->q.n_bd, txq->q.write_ptr,
 404                           txq->q.read_ptr);
 405                 return;
 406         }
 407
 408         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 409         memset(&info->status, 0, sizeof(info->status));
 410
 411         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
 412                 IWLAGN_TX_RES_TID_POS;
 413         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
 414                 IWLAGN_TX_RES_RA_POS;
 415
 416         spin_lock_irqsave(&priv->sta_lock, flags);
 417         if (txq->sched_retry) {
 418                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
 419                 struct iwl_ht_agg *agg;
 420
 421                 agg = &priv->stations[sta_id].tid[tid].agg;
 422                 /*
 423                  * If the BT kill count is non-zero, we'll get this
 424                  * notification again.
 425                  */
 426                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
 427                     priv->cfg->bt_params &&
 428                     priv->cfg->bt_params->advanced_bt_coexist) {
 429                         IWL_WARN(priv, "receive reply tx with bt_kill\n");
 430                 }
 431                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 432
 433                 /* check if BAR is needed */
 434                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 435                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 436
 437                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 438                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 439                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 440                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 441                                         scd_ssn , index, txq_id, txq->swq_id);
 442
 443                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 444                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 445
 446                         if (priv->mac80211_registered &&
 447                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 448                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
 449                                 iwl_wake_queue(priv, txq);
 450                 }
 451         } else {
 452                 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
 453                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 454                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 455
 456                 if (priv->mac80211_registered &&
 457                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
 458                         iwl_wake_queue(priv, txq);
 459         }
 460
 461         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
 462
 463         iwl_check_abort_status(priv, tx_resp->frame_count, status);
 464         spin_unlock_irqrestore(&priv->sta_lock, flags);
 465 }
 466
 467 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
 468 {
 469         /* init calibration handlers */
 470         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 471                                         iwlagn_rx_calib_result;
 472         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
 473                                         iwlagn_rx_calib_complete;
 474         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
 475 }
 476
 477 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
 478 {
 479         /* in agn, the tx power calibration is done in uCode */
 480         priv->disable_tx_power_cal = 1;
 481 }
 482
 483 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
 484 {
 485         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
 486                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
 487 }
 488
 489 int iwlagn_send_tx_power(struct iwl_priv *priv)
 490 {
 491         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
 492         u8 tx_ant_cfg_cmd;
 493
 494         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
 495                       "TX Power requested while scanning!\n"))
 496                 return -EAGAIN;
 497
 498         /* half dBm need to multiply */
 499         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 500
 501         if (priv->tx_power_lmt_in_half_dbm &&
 502             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 503                 /*
 504                  * For the newer devices which using enhanced/extend tx power
 505                  * table in EEPROM, the format is in half dBm. driver need to
 506                  * convert to dBm format before report to mac80211.
 507                  * By doing so, there is a possibility of 1/2 dBm resolution
 508                  * lost. driver will perform "round-up" operation before
 509                  * reporting, but it will cause 1/2 dBm tx power over the
 510                  * regulatory limit. Perform the checking here, if the
 511                  * "tx_power_user_lmt" is higher than EEPROM value (in
 512                  * half-dBm format), lower the tx power based on EEPROM
 513                  */
 514                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 515         }
 516         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
 517         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
 518
 519         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 520                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 521         else
 522                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 523
 524         return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
 525                                 &tx_power_cmd);
 526 }
 527
 528 void iwlagn_temperature(struct iwl_priv *priv)
 529 {
 530         /* store temperature from statistics (in Celsius) */
 531         priv->temperature =
 532                 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
 533         iwl_tt_handler(priv);
 534 }
 535
 536 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
 537 {
 538         struct iwl_eeprom_calib_hdr {
 539                 u8 version;
 540                 u8 pa_type;
 541                 u16 voltage;
 542         } *hdr;
 543
 544         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 545                                                         EEPROM_CALIB_ALL);
 546         return hdr->version;
 547
 548 }
 549
 550 /*
 551  * EEPROM
 552  */
 553 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 554 {
 555         u16 offset = 0;
 556
 557         if ((address & INDIRECT_ADDRESS) == 0)
 558                 return address;
 559
 560         switch (address & INDIRECT_TYPE_MSK) {
 561         case INDIRECT_HOST:
 562                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
 563                 break;
 564         case INDIRECT_GENERAL:
 565                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
 566                 break;
 567         case INDIRECT_REGULATORY:
 568                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
 569                 break;
 570         case INDIRECT_CALIBRATION:
 571                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
 572                 break;
 573         case INDIRECT_PROCESS_ADJST:
 574                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
 575                 break;
 576         case INDIRECT_OTHERS:
 577                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
 578                 break;
 579         default:
 580                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 581                 address & INDIRECT_TYPE_MSK);
 582                 break;
 583         }
 584
 585         /* translate the offset from words to byte */
 586         return (address & ADDRESS_MSK) + (offset << 1);
 587 }
 588
 589 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
 590                                            size_t offset)
 591 {
 592         u32 address = eeprom_indirect_address(priv, offset);
 593         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
 594         return &priv->eeprom[address];
 595 }
 596
 597 struct iwl_mod_params iwlagn_mod_params = {
 598         .amsdu_size_8K = 1,
 599         .restart_fw = 1,
 600         /* the rest are 0 by default */
 601 };
 602
 603 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 604 {
 605         unsigned long flags;
 606         int i;
 607         spin_lock_irqsave(&rxq->lock, flags);
 608         INIT_LIST_HEAD(&rxq->rx_free);
 609         INIT_LIST_HEAD(&rxq->rx_used);
 610         /* Fill the rx_used queue with _all_ of the Rx buffers */
 611         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 612                 /* In the reset function, these buffers may have been allocated
 613                  * to an SKB, so we need to unmap and free potential storage */
 614                 if (rxq->pool[i].page != NULL) {
 615                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 616                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 617                                 PCI_DMA_FROMDEVICE);
 618                         __iwl_free_pages(priv, rxq->pool[i].page);
 619                         rxq->pool[i].page = NULL;
 620                 }
 621                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 622         }
 623
 624         for (i = 0; i < RX_QUEUE_SIZE; i++)
 625                 rxq->queue[i] = NULL;
 626
 627         /* Set us so that we have processed and used all buffers, but have
 628          * not restocked the Rx queue with fresh buffers */
 629         rxq->read = rxq->write = 0;
 630         rxq->write_actual = 0;
 631         rxq->free_count = 0;
 632         spin_unlock_irqrestore(&rxq->lock, flags);
 633 }
 634
 635 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 636 {
 637         u32 rb_size;
 638         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 639         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 640
 641         if (!priv->cfg->base_params->use_isr_legacy)
 642                 rb_timeout = RX_RB_TIMEOUT;
 643
 644         if (priv->cfg->mod_params->amsdu_size_8K)
 645                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 646         else
 647                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 648
 649         /* Stop Rx DMA */
 650         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 651
 652         /* Reset driver's Rx queue write index */
 653         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 654
 655         /* Tell device where to find RBD circular buffer in DRAM */
 656         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 657                            (u32)(rxq->bd_dma >> 8));
 658
 659         /* Tell device where in DRAM to update its Rx status */
 660         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 661                            rxq->rb_stts_dma >> 4);
 662
 663         /* Enable Rx DMA
 664          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 665          *      the credit mechanism in 5000 HW RX FIFO
 666          * Direct rx interrupts to hosts
 667          * Rx buffer size 4 or 8k
 668          * RB timeout 0x10
 669          * 256 RBDs
 670          */
 671         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 672                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 673                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 674                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 675                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 676                            rb_size|
 677                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 678                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 679
 680         /* Set interrupt coalescing timer to default (2048 usecs) */
 681         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 682
 683         return 0;
 684 }
 685
 686 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
 687 {
 688 /*
 689  * (for documentation purposes)
 690  * to set power to V_AUX, do:
 691
 692                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 693                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 694                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 695                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 696  */
 697
 698         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 699                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 700                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 701 }
 702
 703 int iwlagn_hw_nic_init(struct iwl_priv *priv)
 704 {
 705         unsigned long flags;
 706         struct iwl_rx_queue *rxq = &priv->rxq;
 707         int ret;
 708
 709         /* nic_init */
 710         spin_lock_irqsave(&priv->lock, flags);
 711         priv->cfg->ops->lib->apm_ops.init(priv);
 712
 713         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 714         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 715
 716         spin_unlock_irqrestore(&priv->lock, flags);
 717
 718         iwlagn_set_pwr_vmain(priv);
 719
 720         priv->cfg->ops->lib->apm_ops.config(priv);
 721
 722         /* Allocate the RX queue, or reset if it is already allocated */
 723         if (!rxq->bd) {
 724                 ret = iwl_rx_queue_alloc(priv);
 725                 if (ret) {
 726                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
 727                         return -ENOMEM;
 728                 }
 729         } else
 730                 iwlagn_rx_queue_reset(priv, rxq);
 731
 732         iwlagn_rx_replenish(priv);
 733
 734         iwlagn_rx_init(priv, rxq);
 735
 736         spin_lock_irqsave(&priv->lock, flags);
 737
 738         rxq->need_update = 1;
 739         iwl_rx_queue_update_write_ptr(priv, rxq);
 740
 741         spin_unlock_irqrestore(&priv->lock, flags);
 742
 743         /* Allocate or reset and init all Tx and Command queues */
 744         if (!priv->txq) {
 745                 ret = iwlagn_txq_ctx_alloc(priv);
 746                 if (ret)
 747                         return ret;
 748         } else
 749                 iwlagn_txq_ctx_reset(priv);
 750
 751         if (priv->cfg->base_params->shadow_reg_enable) {
 752                 /* enable shadow regs in HW */
 753                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
 754                         0x800FFFFF);
 755         }
 756
 757         set_bit(STATUS_INIT, &priv->status);
 758
 759         return 0;
 760 }
 761
 762 /**
 763  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 764  */
 765 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
 766                                           dma_addr_t dma_addr)
 767 {
 768         return cpu_to_le32((u32)(dma_addr >> 8));
 769 }
 770
 771 /**
 772  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 773  *
 774  * If there are slots in the RX queue that need to be restocked,
 775  * and we have free pre-allocated buffers, fill the ranks as much
 776  * as we can, pulling from rx_free.
 777  *
 778  * This moves the 'write' index forward to catch up with 'processed', and
 779  * also updates the memory address in the firmware to reference the new
 780  * target buffer.
 781  */
 782 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
 783 {
 784         struct iwl_rx_queue *rxq = &priv->rxq;
 785         struct list_head *element;
 786         struct iwl_rx_mem_buffer *rxb;
 787         unsigned long flags;
 788
 789         spin_lock_irqsave(&rxq->lock, flags);
 790         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 791                 /* The overwritten rxb must be a used one */
 792                 rxb = rxq->queue[rxq->write];
 793                 BUG_ON(rxb && rxb->page);
 794
 795                 /* Get next free Rx buffer, remove from free list */
 796                 element = rxq->rx_free.next;
 797                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 798                 list_del(element);
 799
 800                 /* Point to Rx buffer via next RBD in circular buffer */
 801                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
 802                                                               rxb->page_dma);
 803                 rxq->queue[rxq->write] = rxb;
 804                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 805                 rxq->free_count--;
 806         }
 807         spin_unlock_irqrestore(&rxq->lock, flags);
 808         /* If the pre-allocated buffer pool is dropping low, schedule to
 809          * refill it */
 810         if (rxq->free_count <= RX_LOW_WATERMARK)
 811                 queue_work(priv->workqueue, &priv->rx_replenish);
 812
 813
 814         /* If we've added more space for the firmware to place data, tell it.
 815          * Increment device's write pointer in multiples of 8. */
 816         if (rxq->write_actual != (rxq->write & ~0x7)) {
 817                 spin_lock_irqsave(&rxq->lock, flags);
 818                 rxq->need_update = 1;
 819                 spin_unlock_irqrestore(&rxq->lock, flags);
 820                 iwl_rx_queue_update_write_ptr(priv, rxq);
 821         }
 822 }
 823
 824 /**
 825  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 826  *
 827  * When moving to rx_free an SKB is allocated for the slot.
 828  *
 829  * Also restock the Rx queue via iwl_rx_queue_restock.
 830  * This is called as a scheduled work item (except for during initialization)
 831  */
 832 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 833 {
 834         struct iwl_rx_queue *rxq = &priv->rxq;
 835         struct list_head *element;
 836         struct iwl_rx_mem_buffer *rxb;
 837         struct page *page;
 838         unsigned long flags;
 839         gfp_t gfp_mask = priority;
 840
 841         while (1) {
 842                 spin_lock_irqsave(&rxq->lock, flags);
 843                 if (list_empty(&rxq->rx_used)) {
 844                         spin_unlock_irqrestore(&rxq->lock, flags);
 845                         return;
 846                 }
 847                 spin_unlock_irqrestore(&rxq->lock, flags);
 848
 849                 if (rxq->free_count > RX_LOW_WATERMARK)
 850                         gfp_mask |= __GFP_NOWARN;
 851
 852                 if (priv->hw_params.rx_page_order > 0)
 853                         gfp_mask |= __GFP_COMP;
 854
 855                 /* Alloc a new receive buffer */
 856                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
 857                 if (!page) {
 858                         if (net_ratelimit())
 859                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
 860                                                "order: %d\n",
 861                                                priv->hw_params.rx_page_order);
 862
 863                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 864                             net_ratelimit())
 865                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
 866                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
 867                                          rxq->free_count);
 868                         /* We don't reschedule replenish work here -- we will
 869                          * call the restock method and if it still needs
 870                          * more buffers it will schedule replenish */
 871                         return;
 872                 }
 873
 874                 spin_lock_irqsave(&rxq->lock, flags);
 875
 876                 if (list_empty(&rxq->rx_used)) {
 877                         spin_unlock_irqrestore(&rxq->lock, flags);
 878                         __free_pages(page, priv->hw_params.rx_page_order);
 879                         return;
 880                 }
 881                 element = rxq->rx_used.next;
 882                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 883                 list_del(element);
 884
 885                 spin_unlock_irqrestore(&rxq->lock, flags);
 886
 887                 BUG_ON(rxb->page);
 888                 rxb->page = page;
 889                 /* Get physical address of the RB */
 890                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
 891                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 892                                 PCI_DMA_FROMDEVICE);
 893                 /* dma address must be no more than 36 bits */
 894                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 895                 /* and also 256 byte aligned! */
 896                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 897
 898                 spin_lock_irqsave(&rxq->lock, flags);
 899
 900                 list_add_tail(&rxb->list, &rxq->rx_free);
 901                 rxq->free_count++;
 902                 priv->alloc_rxb_page++;
 903
 904                 spin_unlock_irqrestore(&rxq->lock, flags);
 905         }
 906 }
 907
 908 void iwlagn_rx_replenish(struct iwl_priv *priv)
 909 {
 910         unsigned long flags;
 911
 912         iwlagn_rx_allocate(priv, GFP_KERNEL);
 913
 914         spin_lock_irqsave(&priv->lock, flags);
 915         iwlagn_rx_queue_restock(priv);
 916         spin_unlock_irqrestore(&priv->lock, flags);
 917 }
 918
 919 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
 920 {
 921         iwlagn_rx_allocate(priv, GFP_ATOMIC);
 922
 923         iwlagn_rx_queue_restock(priv);
 924 }
 925
 926 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 927  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 928  * This free routine walks the list of POOL entries and if SKB is set to
 929  * non NULL it is unmapped and freed
 930  */
 931 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 932 {
 933         int i;
 934         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 935                 if (rxq->pool[i].page != NULL) {
 936                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 937                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 938                                 PCI_DMA_FROMDEVICE);
 939                         __iwl_free_pages(priv, rxq->pool[i].page);
 940                         rxq->pool[i].page = NULL;
 941                 }
 942         }
 943
 944         dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
 945                           rxq->bd_dma);
 946         dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
 947                           rxq->rb_stts, rxq->rb_stts_dma);
 948         rxq->bd = NULL;
 949         rxq->rb_stts  = NULL;
 950 }
 951
 952 int iwlagn_rxq_stop(struct iwl_priv *priv)
 953 {
 954
 955         /* stop Rx DMA */
 956         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 957         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 958                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 959
 960         return 0;
 961 }
 962
 963 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 964 {
 965         int idx = 0;
 966         int band_offset = 0;
 967
 968         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 969         if (rate_n_flags & RATE_MCS_HT_MSK) {
 970                 idx = (rate_n_flags & 0xff);
 971                 return idx;
 972         /* Legacy rate format, search for match in table */
 973         } else {
 974                 if (band == IEEE80211_BAND_5GHZ)
 975                         band_offset = IWL_FIRST_OFDM_RATE;
 976                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
 977                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 978                                 return idx - band_offset;
 979         }
 980
 981         return -1;
 982 }
 983
 984 /* Calc max signal level (dBm) among 3 possible receivers */
 985 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
 986                                 struct iwl_rx_phy_res *rx_resp)
 987 {
 988         return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
 989 }
 990
 991 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
 992 {
 993         u32 decrypt_out = 0;
 994
 995         if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
 996                                         RX_RES_STATUS_STATION_FOUND)
 997                 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
 998                                 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
 999
1000         decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
1001
1002         /* packet was not encrypted */
1003         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1004                                         RX_RES_STATUS_SEC_TYPE_NONE)
1005                 return decrypt_out;
1006
1007         /* packet was encrypted with unknown alg */
1008         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
1009                                         RX_RES_STATUS_SEC_TYPE_ERR)
1010                 return decrypt_out;
1011
1012         /* decryption was not done in HW */
1013         if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
1014                                         RX_MPDU_RES_STATUS_DEC_DONE_MSK)
1015                 return decrypt_out;
1016
1017         switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
1018
1019         case RX_RES_STATUS_SEC_TYPE_CCMP:
1020                 /* alg is CCM: check MIC only */
1021                 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
1022                         /* Bad MIC */
1023                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1024                 else
1025                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1026
1027                 break;
1028
1029         case RX_RES_STATUS_SEC_TYPE_TKIP:
1030                 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1031                         /* Bad TTAK */
1032                         decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1033                         break;
1034                 }
1035                 /* fall through if TTAK OK */
1036         default:
1037                 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1038                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1039                 else
1040                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1041                 break;
1042         }
1043
1044         IWL_DEBUG_RX(priv, "decrypt_in:0x%x  decrypt_out = 0x%x\n",
1045                                         decrypt_in, decrypt_out);
1046
1047         return decrypt_out;
1048 }
1049
1050 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1051                                         struct ieee80211_hdr *hdr,
1052                                         u16 len,
1053                                         u32 ampdu_status,
1054                                         struct iwl_rx_mem_buffer *rxb,
1055                                         struct ieee80211_rx_status *stats)
1056 {
1057         struct sk_buff *skb;
1058         __le16 fc = hdr->frame_control;
1059
1060         /* We only process data packets if the interface is open */
1061         if (unlikely(!priv->is_open)) {
1062                 IWL_DEBUG_DROP_LIMIT(priv,
1063                     "Dropping packet while interface is not open.\n");
1064                 return;
1065         }
1066
1067         /* In case of HW accelerated crypto and bad decryption, drop */
1068         if (!priv->cfg->mod_params->sw_crypto &&
1069             iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1070                 return;
1071
1072         skb = dev_alloc_skb(128);
1073         if (!skb) {
1074                 IWL_ERR(priv, "dev_alloc_skb failed\n");
1075                 return;
1076         }
1077
1078         skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1079
1080         iwl_update_stats(priv, false, fc, len);
1081         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1082
1083         ieee80211_rx(priv->hw, skb);
1084         priv->alloc_rxb_page--;
1085         rxb->page = NULL;
1086 }
1087
1088 /* Called for REPLY_RX (legacy ABG frames), or
1089  * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1090 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1091                                 struct iwl_rx_mem_buffer *rxb)
1092 {
1093         struct ieee80211_hdr *header;
1094         struct ieee80211_rx_status rx_status;
1095         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1096         struct iwl_rx_phy_res *phy_res;
1097         __le32 rx_pkt_status;
1098         struct iwl_rx_mpdu_res_start *amsdu;
1099         u32 len;
1100         u32 ampdu_status;
1101         u32 rate_n_flags;
1102
1103         /**
1104          * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1105          *      REPLY_RX: physical layer info is in this buffer
1106          *      REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1107          *              command and cached in priv->last_phy_res
1108          *
1109          * Here we set up local variables depending on which command is
1110          * received.
1111          */
1112         if (pkt->hdr.cmd == REPLY_RX) {
1113                 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1114                 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1115                                 + phy_res->cfg_phy_cnt);
1116
1117                 len = le16_to_cpu(phy_res->byte_count);
1118                 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1119                                 phy_res->cfg_phy_cnt + len);
1120                 ampdu_status = le32_to_cpu(rx_pkt_status);
1121         } else {
1122                 if (!priv->_agn.last_phy_res_valid) {
1123                         IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1124                         return;
1125                 }
1126                 phy_res = &priv->_agn.last_phy_res;
1127                 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1128                 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1129                 len = le16_to_cpu(amsdu->byte_count);
1130                 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1131                 ampdu_status = iwlagn_translate_rx_status(priv,
1132                                 le32_to_cpu(rx_pkt_status));
1133         }
1134
1135         if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1136                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1137                                 phy_res->cfg_phy_cnt);
1138                 return;
1139         }
1140
1141         if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1142             !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1143                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1144                                 le32_to_cpu(rx_pkt_status));
1145                 return;
1146         }
1147
1148         /* This will be used in several places later */
1149         rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1150
1151         /* rx_status carries information about the packet to mac80211 */
1152         rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1153         rx_status.freq =
1154                 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1155         rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1156                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1157         rx_status.rate_idx =
1158                 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1159         rx_status.flag = 0;
1160
1161         /* TSF isn't reliable. In order to allow smooth user experience,
1162          * this W/A doesn't propagate it to the mac80211 */
1163         /*rx_status.flag |= RX_FLAG_TSFT;*/
1164
1165         priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1166
1167         /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1168         rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1169
1170         iwl_dbg_log_rx_data_frame(priv, len, header);
1171         IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1172                 rx_status.signal, (unsigned long long)rx_status.mactime);
1173
1174         /*
1175          * "antenna number"
1176          *
1177          * It seems that the antenna field in the phy flags value
1178          * is actually a bit field. This is undefined by radiotap,
1179          * it wants an actual antenna number but I always get "7"
1180          * for most legacy frames I receive indicating that the
1181          * same frame was received on all three RX chains.
1182          *
1183          * I think this field should be removed in favor of a
1184          * new 802.11n radiotap field "RX chains" that is defined
1185          * as a bitmask.
1186          */
1187         rx_status.antenna =
1188                 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1189                 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1190
1191         /* set the preamble flag if appropriate */
1192         if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1193                 rx_status.flag |= RX_FLAG_SHORTPRE;
1194
1195         /* Set up the HT phy flags */
1196         if (rate_n_flags & RATE_MCS_HT_MSK)
1197                 rx_status.flag |= RX_FLAG_HT;
1198         if (rate_n_flags & RATE_MCS_HT40_MSK)
1199                 rx_status.flag |= RX_FLAG_40MHZ;
1200         if (rate_n_flags & RATE_MCS_SGI_MSK)
1201                 rx_status.flag |= RX_FLAG_SHORT_GI;
1202
1203         iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1204                                     rxb, &rx_status);
1205 }
1206
1207 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1208  * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1209 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1210                             struct iwl_rx_mem_buffer *rxb)
1211 {
1212         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1213         priv->_agn.last_phy_res_valid = true;
1214         memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1215                sizeof(struct iwl_rx_phy_res));
1216 }
1217
1218 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1219                                            struct ieee80211_vif *vif,
1220                                            enum ieee80211_band band,
1221                                            struct iwl_scan_channel *scan_ch)
1222 {
1223         const struct ieee80211_supported_band *sband;
1224         u16 passive_dwell = 0;
1225         u16 active_dwell = 0;
1226         int added = 0;
1227         u16 channel = 0;
1228
1229         sband = iwl_get_hw_mode(priv, band);
1230         if (!sband) {
1231                 IWL_ERR(priv, "invalid band\n");
1232                 return added;
1233         }
1234
1235         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1236         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1237
1238         if (passive_dwell <= active_dwell)
1239                 passive_dwell = active_dwell + 1;
1240
1241         channel = iwl_get_single_channel_number(priv, band);
1242         if (channel) {
1243                 scan_ch->channel = cpu_to_le16(channel);
1244                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1245                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1246                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1247                 /* Set txpower levels to defaults */
1248                 scan_ch->dsp_atten = 110;
1249                 if (band == IEEE80211_BAND_5GHZ)
1250                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1251                 else
1252                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1253                 added++;
1254         } else
1255                 IWL_ERR(priv, "no valid channel found\n");
1256         return added;
1257 }
1258
1259 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1260                                      struct ieee80211_vif *vif,
1261                                      enum ieee80211_band band,
1262                                      u8 is_active, u8 n_probes,
1263                                      struct iwl_scan_channel *scan_ch)
1264 {
1265         struct ieee80211_channel *chan;
1266         const struct ieee80211_supported_band *sband;
1267         const struct iwl_channel_info *ch_info;
1268         u16 passive_dwell = 0;
1269         u16 active_dwell = 0;
1270         int added, i;
1271         u16 channel;
1272
1273         sband = iwl_get_hw_mode(priv, band);
1274         if (!sband)
1275                 return 0;
1276
1277         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1278         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1279
1280         if (passive_dwell <= active_dwell)
1281                 passive_dwell = active_dwell + 1;
1282
1283         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1284                 chan = priv->scan_request->channels[i];
1285
1286                 if (chan->band != band)
1287                         continue;
1288
1289                 channel = chan->hw_value;
1290                 scan_ch->channel = cpu_to_le16(channel);
1291
1292                 ch_info = iwl_get_channel_info(priv, band, channel);
1293                 if (!is_channel_valid(ch_info)) {
1294                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1295                                         channel);
1296                         continue;
1297                 }
1298
1299                 if (!is_active || is_channel_passive(ch_info) ||
1300                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1301                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1302                 else
1303                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1304
1305                 if (n_probes)
1306                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1307
1308                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1309                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1310
1311                 /* Set txpower levels to defaults */
1312                 scan_ch->dsp_atten = 110;
1313
1314                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1315                  * power level:
1316                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1317                  */
1318                 if (band == IEEE80211_BAND_5GHZ)
1319                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1320                 else
1321                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1322
1323                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1324                                channel, le32_to_cpu(scan_ch->type),
1325                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1326                                 "ACTIVE" : "PASSIVE",
1327                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1328                                active_dwell : passive_dwell);
1329
1330                 scan_ch++;
1331                 added++;
1332         }
1333
1334         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1335         return added;
1336 }
1337
1338 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1339 {
1340         struct iwl_host_cmd cmd = {
1341                 .id = REPLY_SCAN_CMD,
1342                 .len = sizeof(struct iwl_scan_cmd),
1343                 .flags = CMD_SIZE_HUGE,
1344         };
1345         struct iwl_scan_cmd *scan;
1346         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1347         u32 rate_flags = 0;
1348         u16 cmd_len;
1349         u16 rx_chain = 0;
1350         enum ieee80211_band band;
1351         u8 n_probes = 0;
1352         u8 rx_ant = priv->hw_params.valid_rx_ant;
1353         u8 rate;
1354         bool is_active = false;
1355         int  chan_mod;
1356         u8 active_chains;
1357         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1358         int ret;
1359
1360         lockdep_assert_held(&priv->mutex);
1361
1362         if (vif)
1363                 ctx = iwl_rxon_ctx_from_vif(vif);
1364
1365         if (!priv->scan_cmd) {
1366                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1367                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1368                 if (!priv->scan_cmd) {
1369                         IWL_DEBUG_SCAN(priv,
1370                                        "fail to allocate memory for scan\n");
1371                         return -ENOMEM;
1372                 }
1373         }
1374         scan = priv->scan_cmd;
1375         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1376
1377         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1378         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1379
1380         if (iwl_is_any_associated(priv)) {
1381                 u16 interval = 0;
1382                 u32 extra;
1383                 u32 suspend_time = 100;
1384                 u32 scan_suspend_time = 100;
1385                 unsigned long flags;
1386
1387                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1388                 spin_lock_irqsave(&priv->lock, flags);
1389                 if (priv->is_internal_short_scan)
1390                         interval = 0;
1391                 else
1392                         interval = vif->bss_conf.beacon_int;
1393                 spin_unlock_irqrestore(&priv->lock, flags);
1394
1395                 scan->suspend_time = 0;
1396                 scan->max_out_time = cpu_to_le32(200 * 1024);
1397                 if (!interval)
1398                         interval = suspend_time;
1399
1400                 extra = (suspend_time / interval) << 22;
1401                 scan_suspend_time = (extra |
1402                     ((suspend_time % interval) * 1024));
1403                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1404                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1405                                scan_suspend_time, interval);
1406         }
1407
1408         if (priv->is_internal_short_scan) {
1409                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1410         } else if (priv->scan_request->n_ssids) {
1411                 int i, p = 0;
1412                 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1413                 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1414                         /* always does wildcard anyway */
1415                         if (!priv->scan_request->ssids[i].ssid_len)
1416                                 continue;
1417                         scan->direct_scan[p].id = WLAN_EID_SSID;
1418                         scan->direct_scan[p].len =
1419                                 priv->scan_request->ssids[i].ssid_len;
1420                         memcpy(scan->direct_scan[p].ssid,
1421                                priv->scan_request->ssids[i].ssid,
1422                                priv->scan_request->ssids[i].ssid_len);
1423                         n_probes++;
1424                         p++;
1425                 }
1426                 is_active = true;
1427         } else
1428                 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1429
1430         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1431         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1432         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1433
1434         switch (priv->scan_band) {
1435         case IEEE80211_BAND_2GHZ:
1436                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1437                 chan_mod = le32_to_cpu(
1438                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1439                                                 RXON_FLG_CHANNEL_MODE_MSK)
1440                                        >> RXON_FLG_CHANNEL_MODE_POS;
1441                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1442                         rate = IWL_RATE_6M_PLCP;
1443                 } else {
1444                         rate = IWL_RATE_1M_PLCP;
1445                         rate_flags = RATE_MCS_CCK_MSK;
1446                 }
1447                 /*
1448                  * Internal scans are passive, so we can indiscriminately set
1449                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1450                  */
1451                 if (priv->cfg->bt_params &&
1452                     priv->cfg->bt_params->advanced_bt_coexist)
1453                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1454                 break;
1455         case IEEE80211_BAND_5GHZ:
1456                 rate = IWL_RATE_6M_PLCP;
1457                 break;
1458         default:
1459                 IWL_WARN(priv, "Invalid scan band\n");
1460                 return -EIO;
1461         }
1462
1463         /*
1464          * If active scanning is requested but a certain channel is
1465          * marked passive, we can do active scanning if we detect
1466          * transmissions.
1467          *
1468          * There is an issue with some firmware versions that triggers
1469          * a sysassert on a "good CRC threshold" of zero (== disabled),
1470          * on a radar channel even though this means that we should NOT
1471          * send probes.
1472          *
1473          * The "good CRC threshold" is the number of frames that we
1474          * need to receive during our dwell time on a channel before
1475          * sending out probes -- setting this to a huge value will
1476          * mean we never reach it, but at the same time work around
1477          * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1478          * here instead of IWL_GOOD_CRC_TH_DISABLED.
1479          */
1480         scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1481                                         IWL_GOOD_CRC_TH_NEVER;
1482
1483         band = priv->scan_band;
1484
1485         if (priv->cfg->scan_rx_antennas[band])
1486                 rx_ant = priv->cfg->scan_rx_antennas[band];
1487
1488         if (priv->cfg->scan_tx_antennas[band])
1489                 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1490
1491         if (priv->cfg->bt_params &&
1492             priv->cfg->bt_params->advanced_bt_coexist &&
1493             priv->bt_full_concurrent) {
1494                 /* operated as 1x1 in full concurrency mode */
1495                 scan_tx_antennas = first_antenna(
1496                         priv->cfg->scan_tx_antennas[band]);
1497         }
1498
1499         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1500                                                     scan_tx_antennas);
1501         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1502         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1503
1504         /* In power save mode use one chain, otherwise use all chains */
1505         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1506                 /* rx_ant has been set to all valid chains previously */
1507                 active_chains = rx_ant &
1508                                 ((u8)(priv->chain_noise_data.active_chains));
1509                 if (!active_chains)
1510                         active_chains = rx_ant;
1511
1512                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1513                                 priv->chain_noise_data.active_chains);
1514
1515                 rx_ant = first_antenna(active_chains);
1516         }
1517         if (priv->cfg->bt_params &&
1518             priv->cfg->bt_params->advanced_bt_coexist &&
1519             priv->bt_full_concurrent) {
1520                 /* operated as 1x1 in full concurrency mode */
1521                 rx_ant = first_antenna(rx_ant);
1522         }
1523
1524         /* MIMO is not used here, but value is required */
1525         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1526         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1527         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1528         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1529         scan->rx_chain = cpu_to_le16(rx_chain);
1530         if (!priv->is_internal_short_scan) {
1531                 cmd_len = iwl_fill_probe_req(priv,
1532                                         (struct ieee80211_mgmt *)scan->data,
1533                                         vif->addr,
1534                                         priv->scan_request->ie,
1535                                         priv->scan_request->ie_len,
1536                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1537         } else {
1538                 /* use bcast addr, will not be transmitted but must be valid */
1539                 cmd_len = iwl_fill_probe_req(priv,
1540                                         (struct ieee80211_mgmt *)scan->data,
1541                                         iwl_bcast_addr, NULL, 0,
1542                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1543
1544         }
1545         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1546
1547         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1548                                RXON_FILTER_BCON_AWARE_MSK);
1549
1550         if (priv->is_internal_short_scan) {
1551                 scan->channel_count =
1552                         iwl_get_single_channel_for_scan(priv, vif, band,
1553                                 (void *)&scan->data[le16_to_cpu(
1554                                 scan->tx_cmd.len)]);
1555         } else {
1556                 scan->channel_count =
1557                         iwl_get_channels_for_scan(priv, vif, band,
1558                                 is_active, n_probes,
1559                                 (void *)&scan->data[le16_to_cpu(
1560                                 scan->tx_cmd.len)]);
1561         }
1562         if (scan->channel_count == 0) {
1563                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1564                 return -EIO;
1565         }
1566
1567         cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1568             scan->channel_count * sizeof(struct iwl_scan_channel);
1569         cmd.data = scan;
1570         scan->len = cpu_to_le16(cmd.len);
1571
1572         /* set scan bit here for PAN params */
1573         set_bit(STATUS_SCAN_HW, &priv->status);
1574
1575         if (priv->cfg->ops->hcmd->set_pan_params) {
1576                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1577                 if (ret)
1578                         return ret;
1579         }
1580
1581         ret = iwl_send_cmd_sync(priv, &cmd);
1582         if (ret) {
1583                 clear_bit(STATUS_SCAN_HW, &priv->status);
1584                 if (priv->cfg->ops->hcmd->set_pan_params)
1585                         priv->cfg->ops->hcmd->set_pan_params(priv);
1586         }
1587
1588         return ret;
1589 }
1590
1591 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1592                                struct ieee80211_vif *vif, bool add)
1593 {
1594         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1595
1596         if (add)
1597                 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1598                                                 vif->bss_conf.bssid,
1599                                                 &vif_priv->ibss_bssid_sta_id);
1600         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1601                                   vif->bss_conf.bssid);
1602 }
1603
1604 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1605                             int sta_id, int tid, int freed)
1606 {
1607         lockdep_assert_held(&priv->sta_lock);
1608
1609         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1610                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1611         else {
1612                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1613                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1614                         freed);
1615                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1616         }
1617 }
1618
1619 #define IWL_FLUSH_WAIT_MS       2000
1620
1621 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1622 {
1623         struct iwl_tx_queue *txq;
1624         struct iwl_queue *q;
1625         int cnt;
1626         unsigned long now = jiffies;
1627         int ret = 0;
1628
1629         /* waiting for all the tx frames complete might take a while */
1630         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1631                 if (cnt == priv->cmd_queue)
1632                         continue;
1633                 txq = &priv->txq[cnt];
1634                 q = &txq->q;
1635                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1636                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1637                                 msleep(1);
1638
1639                 if (q->read_ptr != q->write_ptr) {
1640                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1641                         ret = -ETIMEDOUT;
1642                         break;
1643                 }
1644         }
1645         return ret;
1646 }
1647
1648 #define IWL_TX_QUEUE_MSK        0xfffff
1649
1650 /**
1651  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1652  *
1653  * pre-requirements:
1654  *  1. acquire mutex before calling
1655  *  2. make sure rf is on and not in exit state
1656  */
1657 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1658 {
1659         struct iwl_txfifo_flush_cmd flush_cmd;
1660         struct iwl_host_cmd cmd = {
1661                 .id = REPLY_TXFIFO_FLUSH,
1662                 .len = sizeof(struct iwl_txfifo_flush_cmd),
1663                 .flags = CMD_SYNC,
1664                 .data = &flush_cmd,
1665         };
1666
1667         might_sleep();
1668
1669         memset(&flush_cmd, 0, sizeof(flush_cmd));
1670         flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1671                                  IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1672         if (priv->cfg->sku & IWL_SKU_N)
1673                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1674
1675         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1676                        flush_cmd.fifo_control);
1677         flush_cmd.flush_control = cpu_to_le16(flush_control);
1678
1679         return iwl_send_cmd(priv, &cmd);
1680 }
1681
1682 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1683 {
1684         mutex_lock(&priv->mutex);
1685         ieee80211_stop_queues(priv->hw);
1686         if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1687                 IWL_ERR(priv, "flush request fail\n");
1688                 goto done;
1689         }
1690         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1691         iwlagn_wait_tx_queue_empty(priv);
1692 done:
1693         ieee80211_wake_queues(priv->hw);
1694         mutex_unlock(&priv->mutex);
1695 }
1696
1697 /*
1698  * BT coex
1699  */
1700 /*
1701  * Macros to access the lookup table.
1702  *
1703  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1704 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1705  *
1706  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1707  *
1708  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1709  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1710  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1711  *
1712  * These macros encode that format.
1713  */
1714 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1715                   wifi_txrx, wifi_sh_ant_req) \
1716         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1717         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1718
1719 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1720         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1721 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1722                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1723         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1724                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1725                                    wifi_sh_ant_req))))
1726 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1727                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1728         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1729                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1730                                wifi_sh_ant_req))
1731 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1732                                   wifi_req, wifi_prio, wifi_txrx, \
1733                                   wifi_sh_ant_req) \
1734         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1735                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1736                                wifi_sh_ant_req))
1737
1738 #define LUT_WLAN_KILL_OP(lut, op, val) \
1739         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1740 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1741                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1742         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1743                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1744 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1745                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1746         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1747                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1748 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1749                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1750         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1751                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1752
1753 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1754         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1755 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1756                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1757         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1758                               wifi_req, wifi_prio, wifi_txrx, \
1759                               wifi_sh_ant_req))))
1760 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1761                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1762         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1763                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1764 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1765                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1766         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1767                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1768
1769 static const __le32 iwlagn_def_3w_lookup[12] = {
1770         cpu_to_le32(0xaaaaaaaa),
1771         cpu_to_le32(0xaaaaaaaa),
1772         cpu_to_le32(0xaeaaaaaa),
1773         cpu_to_le32(0xaaaaaaaa),
1774         cpu_to_le32(0xcc00ff28),
1775         cpu_to_le32(0x0000aaaa),
1776         cpu_to_le32(0xcc00aaaa),
1777         cpu_to_le32(0x0000aaaa),
1778         cpu_to_le32(0xc0004000),
1779         cpu_to_le32(0x00004000),
1780         cpu_to_le32(0xf0005000),
1781         cpu_to_le32(0xf0005000),
1782 };
1783
1784 static const __le32 iwlagn_concurrent_lookup[12] = {
1785         cpu_to_le32(0xaaaaaaaa),
1786         cpu_to_le32(0xaaaaaaaa),
1787         cpu_to_le32(0xaaaaaaaa),
1788         cpu_to_le32(0xaaaaaaaa),
1789         cpu_to_le32(0xaaaaaaaa),
1790         cpu_to_le32(0xaaaaaaaa),
1791         cpu_to_le32(0xaaaaaaaa),
1792         cpu_to_le32(0xaaaaaaaa),
1793         cpu_to_le32(0x00000000),
1794         cpu_to_le32(0x00000000),
1795         cpu_to_le32(0x00000000),
1796         cpu_to_le32(0x00000000),
1797 };
1798
1799 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1800 {
1801         struct iwlagn_bt_cmd bt_cmd = {
1802                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1803                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1804                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1805                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1806         };
1807
1808         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1809                         sizeof(bt_cmd.bt3_lookup_table));
1810
1811         if (priv->cfg->bt_params)
1812                 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1813         else
1814                 bt_cmd.prio_boost = 0;
1815         bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1816         bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1817
1818         bt_cmd.valid = priv->bt_valid;
1819         bt_cmd.tx_prio_boost = 0;
1820         bt_cmd.rx_prio_boost = 0;
1821
1822         /*
1823          * Configure BT coex mode to "no coexistence" when the
1824          * user disabled BT coexistence, we have no interface
1825          * (might be in monitor mode), or the interface is in
1826          * IBSS mode (no proper uCode support for coex then).
1827          */
1828         if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1829                 bt_cmd.flags = 0;
1830         } else {
1831                 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1832                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1833                 if (priv->cfg->bt_params &&
1834                     priv->cfg->bt_params->bt_sco_disable)
1835                         bt_cmd.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1836
1837                 if (priv->bt_ch_announce)
1838                         bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1839                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1840         }
1841         if (priv->bt_full_concurrent)
1842                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1843                         sizeof(iwlagn_concurrent_lookup));
1844         else
1845                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1846                         sizeof(iwlagn_def_3w_lookup));
1847
1848         IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1849                        bt_cmd.flags ? "active" : "disabled",
1850                        priv->bt_full_concurrent ?
1851                        "full concurrency" : "3-wire");
1852
1853         if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1854                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1855
1856         /*
1857          * When we are doing a restart, need to also reconfigure BT
1858          * SCO to the device. If not doing a restart, bt_sco_active
1859          * will always be false, so there's no need to have an extra
1860          * variable to check for it.
1861          */
1862         if (priv->bt_sco_active) {
1863                 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1864
1865                 if (priv->bt_sco_active)
1866                         sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1867                 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1868                                      sizeof(sco_cmd), &sco_cmd))
1869                         IWL_ERR(priv, "failed to send BT SCO command\n");
1870         }
1871 }
1872
1873 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1874 {
1875         struct iwl_priv *priv =
1876                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1877         struct iwl_rxon_context *ctx;
1878         int smps_request = -1;
1879
1880         /*
1881          * Note: bt_traffic_load can be overridden by scan complete and
1882          * coex profile notifications. Ignore that since only bad consequence
1883          * can be not matching debug print with actual state.
1884          */
1885         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1886                        priv->bt_traffic_load);
1887
1888         switch (priv->bt_traffic_load) {
1889         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1890                 if (priv->bt_status)
1891                         smps_request = IEEE80211_SMPS_DYNAMIC;
1892                 else
1893                         smps_request = IEEE80211_SMPS_AUTOMATIC;
1894                 break;
1895         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1896                 smps_request = IEEE80211_SMPS_DYNAMIC;
1897                 break;
1898         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1899         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1900                 smps_request = IEEE80211_SMPS_STATIC;
1901                 break;
1902         default:
1903                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1904                         priv->bt_traffic_load);
1905                 break;
1906         }
1907
1908         mutex_lock(&priv->mutex);
1909
1910         /*
1911          * We can not send command to firmware while scanning. When the scan
1912          * complete we will schedule this work again. We do check with mutex
1913          * locked to prevent new scan request to arrive. We do not check
1914          * STATUS_SCANNING to avoid race when queue_work two times from
1915          * different notifications, but quit and not perform any work at all.
1916          */
1917         if (test_bit(STATUS_SCAN_HW, &priv->status))
1918                 goto out;
1919
1920         if (priv->cfg->ops->lib->update_chain_flags)
1921                 priv->cfg->ops->lib->update_chain_flags(priv);
1922
1923         if (smps_request != -1) {
1924                 for_each_context(priv, ctx) {
1925                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1926                                 ieee80211_request_smps(ctx->vif, smps_request);
1927                 }
1928         }
1929 out:
1930         mutex_unlock(&priv->mutex);
1931 }
1932
1933 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1934                                 struct iwl_bt_uart_msg *uart_msg)
1935 {
1936         IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1937                         "Update Req = 0x%X",
1938                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1939                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1940                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1941                         BT_UART_MSG_FRAME1SSN_POS,
1942                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1943                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1944
1945         IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1946                         "Chl_SeqN = 0x%X, In band = 0x%X",
1947                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1948                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1949                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1950                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1951                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1952                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1953                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1954                         BT_UART_MSG_FRAME2INBAND_POS);
1955
1956         IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1957                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1958                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1959                         BT_UART_MSG_FRAME3SCOESCO_POS,
1960                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1961                         BT_UART_MSG_FRAME3SNIFF_POS,
1962                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1963                         BT_UART_MSG_FRAME3A2DP_POS,
1964                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1965                         BT_UART_MSG_FRAME3ACL_POS,
1966                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1967                         BT_UART_MSG_FRAME3MASTER_POS,
1968                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1969                         BT_UART_MSG_FRAME3OBEX_POS);
1970
1971         IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1972                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1973                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1974
1975         IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1976                         "eSCO Retransmissions = 0x%X",
1977                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1978                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1979                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1980                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1981                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1982                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1983
1984         IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1985                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1986                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1987                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1988                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1989
1990         IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1991                         "0x%X, Connectable = 0x%X",
1992                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1993                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1994                 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1995                         BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1996                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1997                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1998 }
1999
2000 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
2001                                 struct iwl_bt_uart_msg *uart_msg)
2002 {
2003         u8 kill_msk;
2004         static const __le32 bt_kill_ack_msg[2] = {
2005                 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
2006                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2007         static const __le32 bt_kill_cts_msg[2] = {
2008                 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
2009                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
2010
2011         kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
2012                 ? 1 : 0;
2013         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
2014             priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
2015                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
2016                 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
2017                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
2018                 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
2019
2020                 /* schedule to send runtime bt_config */
2021                 queue_work(priv->workqueue, &priv->bt_runtime_config);
2022         }
2023 }
2024
2025 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
2026                                              struct iwl_rx_mem_buffer *rxb)
2027 {
2028         unsigned long flags;
2029         struct iwl_rx_packet *pkt = rxb_addr(rxb);
2030         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
2031         struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
2032         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
2033
2034         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
2035         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
2036         IWL_DEBUG_NOTIF(priv, "    traffic load: %d\n", coex->bt_traffic_load);
2037         IWL_DEBUG_NOTIF(priv, "    CI compliance: %d\n",
2038                         coex->bt_ci_compliance);
2039         iwlagn_print_uartmsg(priv, uart_msg);
2040
2041         priv->last_bt_traffic_load = priv->bt_traffic_load;
2042         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
2043                 if (priv->bt_status != coex->bt_status ||
2044                     priv->last_bt_traffic_load != coex->bt_traffic_load) {
2045                         if (coex->bt_status) {
2046                                 /* BT on */
2047                                 if (!priv->bt_ch_announce)
2048                                         priv->bt_traffic_load =
2049                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
2050                                 else
2051                                         priv->bt_traffic_load =
2052                                                 coex->bt_traffic_load;
2053                         } else {
2054                                 /* BT off */
2055                                 priv->bt_traffic_load =
2056                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2057                         }
2058                         priv->bt_status = coex->bt_status;
2059                         queue_work(priv->workqueue,
2060                                    &priv->bt_traffic_change_work);
2061                 }
2062                 if (priv->bt_sco_active !=
2063                     (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2064                         priv->bt_sco_active = uart_msg->frame3 &
2065                                 BT_UART_MSG_FRAME3SCOESCO_MSK;
2066                         if (priv->bt_sco_active)
2067                                 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2068                         iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2069                                        sizeof(sco_cmd), &sco_cmd, NULL);
2070                 }
2071         }
2072
2073         iwlagn_set_kill_msk(priv, uart_msg);
2074
2075         /* FIXME: based on notification, adjust the prio_boost */
2076
2077         spin_lock_irqsave(&priv->lock, flags);
2078         priv->bt_ci_compliance = coex->bt_ci_compliance;
2079         spin_unlock_irqrestore(&priv->lock, flags);
2080 }
2081
2082 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2083 {
2084         iwlagn_rx_handler_setup(priv);
2085         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2086                 iwlagn_bt_coex_profile_notif;
2087 }
2088
2089 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2090 {
2091         iwlagn_setup_deferred_work(priv);
2092
2093         INIT_WORK(&priv->bt_traffic_change_work,
2094                   iwlagn_bt_traffic_change_work);
2095 }
2096
2097 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2098 {
2099         cancel_work_sync(&priv->bt_traffic_change_work);
2100 }
2101
2102 static bool is_single_rx_stream(struct iwl_priv *priv)
2103 {
2104         return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
2105                priv->current_ht_config.single_chain_sufficient;
2106 }
2107
2108 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
2109 #define IWL_NUM_RX_CHAINS_SINGLE        2
2110 #define IWL_NUM_IDLE_CHAINS_DUAL        2
2111 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
2112
2113 /*
2114  * Determine how many receiver/antenna chains to use.
2115  *
2116  * More provides better reception via diversity.  Fewer saves power
2117  * at the expense of throughput, but only when not in powersave to
2118  * start with.
2119  *
2120  * MIMO (dual stream) requires at least 2, but works better with 3.
2121  * This does not determine *which* chains to use, just how many.
2122  */
2123 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2124 {
2125         if (priv->cfg->bt_params &&
2126             priv->cfg->bt_params->advanced_bt_coexist &&
2127             (priv->bt_full_concurrent ||
2128              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2129                 /*
2130                  * only use chain 'A' in bt high traffic load or
2131                  * full concurrency mode
2132                  */
2133                 return IWL_NUM_RX_CHAINS_SINGLE;
2134         }
2135         /* # of Rx chains to use when expecting MIMO. */
2136         if (is_single_rx_stream(priv))
2137                 return IWL_NUM_RX_CHAINS_SINGLE;
2138         else
2139                 return IWL_NUM_RX_CHAINS_MULTIPLE;
2140 }
2141
2142 /*
2143  * When we are in power saving mode, unless device support spatial
2144  * multiplexing power save, use the active count for rx chain count.
2145  */
2146 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2147 {
2148         /* # Rx chains when idling, depending on SMPS mode */
2149         switch (priv->current_ht_config.smps) {
2150         case IEEE80211_SMPS_STATIC:
2151         case IEEE80211_SMPS_DYNAMIC:
2152                 return IWL_NUM_IDLE_CHAINS_SINGLE;
2153         case IEEE80211_SMPS_OFF:
2154                 return active_cnt;
2155         default:
2156                 WARN(1, "invalid SMPS mode %d",
2157                      priv->current_ht_config.smps);
2158                 return active_cnt;
2159         }
2160 }
2161
2162 /* up to 4 chains */
2163 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2164 {
2165         u8 res;
2166         res = (chain_bitmap & BIT(0)) >> 0;
2167         res += (chain_bitmap & BIT(1)) >> 1;
2168         res += (chain_bitmap & BIT(2)) >> 2;
2169         res += (chain_bitmap & BIT(3)) >> 3;
2170         return res;
2171 }
2172
2173 /**
2174  * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2175  *
2176  * Selects how many and which Rx receivers/antennas/chains to use.
2177  * This should not be used for scan command ... it puts data in wrong place.
2178  */
2179 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2180 {
2181         bool is_single = is_single_rx_stream(priv);
2182         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2183         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2184         u32 active_chains;
2185         u16 rx_chain;
2186
2187         /* Tell uCode which antennas are actually connected.
2188          * Before first association, we assume all antennas are connected.
2189          * Just after first association, iwl_chain_noise_calibration()
2190          *    checks which antennas actually *are* connected. */
2191         if (priv->chain_noise_data.active_chains)
2192                 active_chains = priv->chain_noise_data.active_chains;
2193         else
2194                 active_chains = priv->hw_params.valid_rx_ant;
2195
2196         if (priv->cfg->bt_params &&
2197             priv->cfg->bt_params->advanced_bt_coexist &&
2198             (priv->bt_full_concurrent ||
2199              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2200                 /*
2201                  * only use chain 'A' in bt high traffic load or
2202                  * full concurrency mode
2203                  */
2204                 active_chains = first_antenna(active_chains);
2205         }
2206
2207         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2208
2209         /* How many receivers should we use? */
2210         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2211         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2212
2213
2214         /* correct rx chain count according hw settings
2215          * and chain noise calibration
2216          */
2217         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2218         if (valid_rx_cnt < active_rx_cnt)
2219                 active_rx_cnt = valid_rx_cnt;
2220
2221         if (valid_rx_cnt < idle_rx_cnt)
2222                 idle_rx_cnt = valid_rx_cnt;
2223
2224         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2225         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
2226
2227         ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2228
2229         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2230                 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2231         else
2232                 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2233
2234         IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2235                         ctx->staging.rx_chain,
2236                         active_rx_cnt, idle_rx_cnt);
2237
2238         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2239                 active_rx_cnt < idle_rx_cnt);
2240 }
2241
2242 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2243 {
2244         int i;
2245         u8 ind = ant;
2246
2247         if (priv->band == IEEE80211_BAND_2GHZ &&
2248             priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2249                 return 0;
2250
2251         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2252                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
2253                 if (valid & BIT(ind))
2254                         return ind;
2255         }
2256         return ant;
2257 }
2258
2259 static const char *get_csr_string(int cmd)
2260 {
2261         switch (cmd) {
2262         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2263         IWL_CMD(CSR_INT_COALESCING);
2264         IWL_CMD(CSR_INT);
2265         IWL_CMD(CSR_INT_MASK);
2266         IWL_CMD(CSR_FH_INT_STATUS);
2267         IWL_CMD(CSR_GPIO_IN);
2268         IWL_CMD(CSR_RESET);
2269         IWL_CMD(CSR_GP_CNTRL);
2270         IWL_CMD(CSR_HW_REV);
2271         IWL_CMD(CSR_EEPROM_REG);
2272         IWL_CMD(CSR_EEPROM_GP);
2273         IWL_CMD(CSR_OTP_GP_REG);
2274         IWL_CMD(CSR_GIO_REG);
2275         IWL_CMD(CSR_GP_UCODE_REG);
2276         IWL_CMD(CSR_GP_DRIVER_REG);
2277         IWL_CMD(CSR_UCODE_DRV_GP1);
2278         IWL_CMD(CSR_UCODE_DRV_GP2);
2279         IWL_CMD(CSR_LED_REG);
2280         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2281         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2282         IWL_CMD(CSR_ANA_PLL_CFG);
2283         IWL_CMD(CSR_HW_REV_WA_REG);
2284         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2285         default:
2286                 return "UNKNOWN";
2287         }
2288 }
2289
2290 void iwl_dump_csr(struct iwl_priv *priv)
2291 {
2292         int i;
2293         static const u32 csr_tbl[] = {
2294                 CSR_HW_IF_CONFIG_REG,
2295                 CSR_INT_COALESCING,
2296                 CSR_INT,
2297                 CSR_INT_MASK,
2298                 CSR_FH_INT_STATUS,
2299                 CSR_GPIO_IN,
2300                 CSR_RESET,
2301                 CSR_GP_CNTRL,
2302                 CSR_HW_REV,
2303                 CSR_EEPROM_REG,
2304                 CSR_EEPROM_GP,
2305                 CSR_OTP_GP_REG,
2306                 CSR_GIO_REG,
2307                 CSR_GP_UCODE_REG,
2308                 CSR_GP_DRIVER_REG,
2309                 CSR_UCODE_DRV_GP1,
2310                 CSR_UCODE_DRV_GP2,
2311                 CSR_LED_REG,
2312                 CSR_DRAM_INT_TBL_REG,
2313                 CSR_GIO_CHICKEN_BITS,
2314                 CSR_ANA_PLL_CFG,
2315                 CSR_HW_REV_WA_REG,
2316                 CSR_DBG_HPET_MEM_REG
2317         };
2318         IWL_ERR(priv, "CSR values:\n");
2319         IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2320                 "CSR_INT_PERIODIC_REG)\n");
2321         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2322                 IWL_ERR(priv, "  %25s: 0X%08x\n",
2323                         get_csr_string(csr_tbl[i]),
2324                         iwl_read32(priv, csr_tbl[i]));
2325         }
2326 }
2327
2328 static const char *get_fh_string(int cmd)
2329 {
2330         switch (cmd) {
2331         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2332         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2333         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2334         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2335         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2336         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2337         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2338         IWL_CMD(FH_TSSR_TX_STATUS_REG);
2339         IWL_CMD(FH_TSSR_TX_ERROR_REG);
2340         default:
2341                 return "UNKNOWN";
2342         }
2343 }
2344
2345 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2346 {
2347         int i;
2348 #ifdef CONFIG_IWLWIFI_DEBUG
2349         int pos = 0;
2350         size_t bufsz = 0;
2351 #endif
2352         static const u32 fh_tbl[] = {
2353                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2354                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2355                 FH_RSCSR_CHNL0_WPTR,
2356                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2357                 FH_MEM_RSSR_SHARED_CTRL_REG,
2358                 FH_MEM_RSSR_RX_STATUS_REG,
2359                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2360                 FH_TSSR_TX_STATUS_REG,
2361                 FH_TSSR_TX_ERROR_REG
2362         };
2363 #ifdef CONFIG_IWLWIFI_DEBUG
2364         if (display) {
2365                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2366                 *buf = kmalloc(bufsz, GFP_KERNEL);
2367                 if (!*buf)
2368                         return -ENOMEM;
2369                 pos += scnprintf(*buf + pos, bufsz - pos,
2370                                 "FH register values:\n");
2371                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2372                         pos += scnprintf(*buf + pos, bufsz - pos,
2373                                 "  %34s: 0X%08x\n",
2374                                 get_fh_string(fh_tbl[i]),
2375                                 iwl_read_direct32(priv, fh_tbl[i]));
2376                 }
2377                 return pos;
2378         }
2379 #endif
2380         IWL_ERR(priv, "FH register values:\n");
2381         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
2382                 IWL_ERR(priv, "  %34s: 0X%08x\n",
2383                         get_fh_string(fh_tbl[i]),
2384                         iwl_read_direct32(priv, fh_tbl[i]));
2385         }
2386         return 0;
2387 }